4 * Copyright (C) 2007-2012 Texas Instruments, Inc.
5 * Copyright (C) 2007-2011 Nokia Corporation
7 * Written by Paul Walmsley
8 * Updated to COMMON clk data format by Rajendra Nayak <rnayak@ti.com>
9 * With many device clock fixes by Kevin Hilman and Jouni Högander
10 * DPLL bypass clock support added by Roman Tereshonkov
15 * Virtual clocks are introduced as convenient tools.
16 * They are sources for other clocks and not supposed
17 * to be requested from drivers directly.
20 #include <linux/kernel.h>
21 #include <linux/clk.h>
22 #include <linux/clk-private.h>
23 #include <linux/list.h>
29 #include "clock3xxx.h"
30 #include "clock34xx.h"
31 #include "clock36xx.h"
32 #include "clock3517.h"
34 #include "cm-regbits-34xx.h"
36 #include "prm-regbits-34xx.h"
43 #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
45 /* Maximum DPLL multiplier, divider values for OMAP3 */
46 #define OMAP3_MAX_DPLL_MULT 2047
47 #define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
48 #define OMAP3_MAX_DPLL_DIV 128
50 DEFINE_CLK_FIXED_RATE(dummy_apb_pclk
, CLK_IS_ROOT
, 0x0, 0x0);
52 DEFINE_CLK_FIXED_RATE(mcbsp_clks
, CLK_IS_ROOT
, 0x0, 0x0);
54 DEFINE_CLK_FIXED_RATE(omap_32k_fck
, CLK_IS_ROOT
, 32768, 0x0);
56 DEFINE_CLK_FIXED_RATE(pclk_ck
, CLK_IS_ROOT
, 27000000, 0x0);
58 DEFINE_CLK_FIXED_RATE(rmii_ck
, CLK_IS_ROOT
, 50000000, 0x0);
60 DEFINE_CLK_FIXED_RATE(secure_32k_fck
, CLK_IS_ROOT
, 32768, 0x0);
62 DEFINE_CLK_FIXED_RATE(sys_altclk
, CLK_IS_ROOT
, 0x0, 0x0);
64 DEFINE_CLK_FIXED_RATE(virt_12m_ck
, CLK_IS_ROOT
, 12000000, 0x0);
66 DEFINE_CLK_FIXED_RATE(virt_13m_ck
, CLK_IS_ROOT
, 13000000, 0x0);
68 DEFINE_CLK_FIXED_RATE(virt_16_8m_ck
, CLK_IS_ROOT
, 16800000, 0x0);
70 DEFINE_CLK_FIXED_RATE(virt_19200000_ck
, CLK_IS_ROOT
, 19200000, 0x0);
72 DEFINE_CLK_FIXED_RATE(virt_26000000_ck
, CLK_IS_ROOT
, 26000000, 0x0);
74 DEFINE_CLK_FIXED_RATE(virt_38_4m_ck
, CLK_IS_ROOT
, 38400000, 0x0);
76 static const char *osc_sys_ck_parent_names
[] = {
77 "virt_12m_ck", "virt_13m_ck", "virt_19200000_ck", "virt_26000000_ck",
78 "virt_38_4m_ck", "virt_16_8m_ck",
81 DEFINE_CLK_MUX(osc_sys_ck
, osc_sys_ck_parent_names
, NULL
, 0x0,
82 OMAP3430_PRM_CLKSEL
, OMAP3430_SYS_CLKIN_SEL_SHIFT
,
83 OMAP3430_SYS_CLKIN_SEL_WIDTH
, 0x0, NULL
);
85 DEFINE_CLK_DIVIDER(sys_ck
, "osc_sys_ck", &osc_sys_ck
, 0x0,
86 OMAP3430_PRM_CLKSRC_CTRL
, OMAP_SYSCLKDIV_SHIFT
,
87 OMAP_SYSCLKDIV_WIDTH
, CLK_DIVIDER_ONE_BASED
, NULL
);
89 static struct dpll_data dpll3_dd
= {
90 .mult_div1_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
91 .mult_mask
= OMAP3430_CORE_DPLL_MULT_MASK
,
92 .div1_mask
= OMAP3430_CORE_DPLL_DIV_MASK
,
93 .clk_bypass
= &sys_ck
,
95 .freqsel_mask
= OMAP3430_CORE_DPLL_FREQSEL_MASK
,
96 .control_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
97 .enable_mask
= OMAP3430_EN_CORE_DPLL_MASK
,
98 .auto_recal_bit
= OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT
,
99 .recal_en_bit
= OMAP3430_CORE_DPLL_RECAL_EN_SHIFT
,
100 .recal_st_bit
= OMAP3430_CORE_DPLL_ST_SHIFT
,
101 .autoidle_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_AUTOIDLE
),
102 .autoidle_mask
= OMAP3430_AUTO_CORE_DPLL_MASK
,
103 .idlest_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_IDLEST
),
104 .idlest_mask
= OMAP3430_ST_CORE_CLK_MASK
,
105 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
107 .max_divider
= OMAP3_MAX_DPLL_DIV
,
110 static struct clk dpll3_ck
;
112 static const char *dpll3_ck_parent_names
[] = {
116 static const struct clk_ops dpll3_ck_ops
= {
117 .init
= &omap2_init_clk_clkdm
,
118 .get_parent
= &omap2_init_dpll_parent
,
119 .recalc_rate
= &omap3_dpll_recalc
,
120 .round_rate
= &omap2_dpll_round_rate
,
123 static struct clk_hw_omap dpll3_ck_hw
= {
127 .ops
= &clkhwops_omap3_dpll
,
128 .dpll_data
= &dpll3_dd
,
129 .clkdm_name
= "dpll3_clkdm",
132 DEFINE_STRUCT_CLK(dpll3_ck
, dpll3_ck_parent_names
, dpll3_ck_ops
);
134 DEFINE_CLK_DIVIDER(dpll3_m2_ck
, "dpll3_ck", &dpll3_ck
, 0x0,
135 OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
136 OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT
,
137 OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH
,
138 CLK_DIVIDER_ONE_BASED
, NULL
);
140 static struct clk core_ck
;
142 static const char *core_ck_parent_names
[] = {
146 static const struct clk_ops core_ck_ops
= {};
148 DEFINE_STRUCT_CLK_HW_OMAP(core_ck
, NULL
);
149 DEFINE_STRUCT_CLK(core_ck
, core_ck_parent_names
, core_ck_ops
);
151 DEFINE_CLK_DIVIDER(l3_ick
, "core_ck", &core_ck
, 0x0,
152 OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
153 OMAP3430_CLKSEL_L3_SHIFT
, OMAP3430_CLKSEL_L3_WIDTH
,
154 CLK_DIVIDER_ONE_BASED
, NULL
);
156 DEFINE_CLK_DIVIDER(l4_ick
, "l3_ick", &l3_ick
, 0x0,
157 OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
158 OMAP3430_CLKSEL_L4_SHIFT
, OMAP3430_CLKSEL_L4_WIDTH
,
159 CLK_DIVIDER_ONE_BASED
, NULL
);
161 static struct clk security_l4_ick2
;
163 static const char *security_l4_ick2_parent_names
[] = {
167 DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2
, NULL
);
168 DEFINE_STRUCT_CLK(security_l4_ick2
, security_l4_ick2_parent_names
, core_ck_ops
);
170 static struct clk aes1_ick
;
172 static const char *aes1_ick_parent_names
[] = {
176 static const struct clk_ops aes1_ick_ops
= {
177 .enable
= &omap2_dflt_clk_enable
,
178 .disable
= &omap2_dflt_clk_disable
,
179 .is_enabled
= &omap2_dflt_clk_is_enabled
,
182 static struct clk_hw_omap aes1_ick_hw
= {
186 .ops
= &clkhwops_iclk_wait
,
187 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
188 .enable_bit
= OMAP3430_EN_AES1_SHIFT
,
191 DEFINE_STRUCT_CLK(aes1_ick
, aes1_ick_parent_names
, aes1_ick_ops
);
193 static struct clk core_l4_ick
;
195 static const struct clk_ops core_l4_ick_ops
= {
196 .init
= &omap2_init_clk_clkdm
,
199 DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick
, "core_l4_clkdm");
200 DEFINE_STRUCT_CLK(core_l4_ick
, security_l4_ick2_parent_names
, core_l4_ick_ops
);
202 static struct clk aes2_ick
;
204 static const char *aes2_ick_parent_names
[] = {
208 static const struct clk_ops aes2_ick_ops
= {
209 .init
= &omap2_init_clk_clkdm
,
210 .enable
= &omap2_dflt_clk_enable
,
211 .disable
= &omap2_dflt_clk_disable
,
212 .is_enabled
= &omap2_dflt_clk_is_enabled
,
215 static struct clk_hw_omap aes2_ick_hw
= {
219 .ops
= &clkhwops_iclk_wait
,
220 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
221 .enable_bit
= OMAP3430_EN_AES2_SHIFT
,
222 .clkdm_name
= "core_l4_clkdm",
225 DEFINE_STRUCT_CLK(aes2_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
227 static struct clk dpll1_fck
;
229 static struct dpll_data dpll1_dd
= {
230 .mult_div1_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_CLKSEL1_PLL
),
231 .mult_mask
= OMAP3430_MPU_DPLL_MULT_MASK
,
232 .div1_mask
= OMAP3430_MPU_DPLL_DIV_MASK
,
233 .clk_bypass
= &dpll1_fck
,
235 .freqsel_mask
= OMAP3430_MPU_DPLL_FREQSEL_MASK
,
236 .control_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_CLKEN_PLL
),
237 .enable_mask
= OMAP3430_EN_MPU_DPLL_MASK
,
238 .modes
= (1 << DPLL_LOW_POWER_BYPASS
) | (1 << DPLL_LOCKED
),
239 .auto_recal_bit
= OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT
,
240 .recal_en_bit
= OMAP3430_MPU_DPLL_RECAL_EN_SHIFT
,
241 .recal_st_bit
= OMAP3430_MPU_DPLL_ST_SHIFT
,
242 .autoidle_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_AUTOIDLE_PLL
),
243 .autoidle_mask
= OMAP3430_AUTO_MPU_DPLL_MASK
,
244 .idlest_reg
= OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_IDLEST_PLL
),
245 .idlest_mask
= OMAP3430_ST_MPU_CLK_MASK
,
246 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
248 .max_divider
= OMAP3_MAX_DPLL_DIV
,
251 static struct clk dpll1_ck
;
253 static const struct clk_ops dpll1_ck_ops
= {
254 .init
= &omap2_init_clk_clkdm
,
255 .enable
= &omap3_noncore_dpll_enable
,
256 .disable
= &omap3_noncore_dpll_disable
,
257 .get_parent
= &omap2_init_dpll_parent
,
258 .recalc_rate
= &omap3_dpll_recalc
,
259 .set_rate
= &omap3_noncore_dpll_set_rate
,
260 .round_rate
= &omap2_dpll_round_rate
,
263 static struct clk_hw_omap dpll1_ck_hw
= {
267 .ops
= &clkhwops_omap3_dpll
,
268 .dpll_data
= &dpll1_dd
,
269 .clkdm_name
= "dpll1_clkdm",
272 DEFINE_STRUCT_CLK(dpll1_ck
, dpll3_ck_parent_names
, dpll1_ck_ops
);
274 DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck
, "dpll1_ck", &dpll1_ck
, 0x0, 2, 1);
276 DEFINE_CLK_DIVIDER(dpll1_x2m2_ck
, "dpll1_x2_ck", &dpll1_x2_ck
, 0x0,
277 OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_CLKSEL2_PLL
),
278 OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT
,
279 OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH
,
280 CLK_DIVIDER_ONE_BASED
, NULL
);
282 static struct clk mpu_ck
;
284 static const char *mpu_ck_parent_names
[] = {
288 DEFINE_STRUCT_CLK_HW_OMAP(mpu_ck
, "mpu_clkdm");
289 DEFINE_STRUCT_CLK(mpu_ck
, mpu_ck_parent_names
, core_l4_ick_ops
);
291 DEFINE_CLK_DIVIDER(arm_fck
, "mpu_ck", &mpu_ck
, 0x0,
292 OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_IDLEST_PLL
),
293 OMAP3430_ST_MPU_CLK_SHIFT
, OMAP3430_ST_MPU_CLK_WIDTH
,
296 static struct clk cam_ick
;
298 static struct clk_hw_omap cam_ick_hw
= {
302 .ops
= &clkhwops_iclk
,
303 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_CAM_MOD
, CM_ICLKEN
),
304 .enable_bit
= OMAP3430_EN_CAM_SHIFT
,
305 .clkdm_name
= "cam_clkdm",
308 DEFINE_STRUCT_CLK(cam_ick
, security_l4_ick2_parent_names
, aes2_ick_ops
);
311 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
313 static struct dpll_data dpll4_dd
;
315 static struct dpll_data dpll4_dd_34xx __initdata
= {
316 .mult_div1_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL2
),
317 .mult_mask
= OMAP3430_PERIPH_DPLL_MULT_MASK
,
318 .div1_mask
= OMAP3430_PERIPH_DPLL_DIV_MASK
,
319 .clk_bypass
= &sys_ck
,
321 .freqsel_mask
= OMAP3430_PERIPH_DPLL_FREQSEL_MASK
,
322 .control_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
323 .enable_mask
= OMAP3430_EN_PERIPH_DPLL_MASK
,
324 .modes
= (1 << DPLL_LOW_POWER_STOP
) | (1 << DPLL_LOCKED
),
325 .auto_recal_bit
= OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT
,
326 .recal_en_bit
= OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT
,
327 .recal_st_bit
= OMAP3430_PERIPH_DPLL_ST_SHIFT
,
328 .autoidle_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_AUTOIDLE
),
329 .autoidle_mask
= OMAP3430_AUTO_PERIPH_DPLL_MASK
,
330 .idlest_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_IDLEST
),
331 .idlest_mask
= OMAP3430_ST_PERIPH_CLK_MASK
,
332 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
334 .max_divider
= OMAP3_MAX_DPLL_DIV
,
337 static struct dpll_data dpll4_dd_3630 __initdata
= {
338 .mult_div1_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL2
),
339 .mult_mask
= OMAP3630_PERIPH_DPLL_MULT_MASK
,
340 .div1_mask
= OMAP3430_PERIPH_DPLL_DIV_MASK
,
341 .clk_bypass
= &sys_ck
,
343 .control_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
344 .enable_mask
= OMAP3430_EN_PERIPH_DPLL_MASK
,
345 .modes
= (1 << DPLL_LOW_POWER_STOP
) | (1 << DPLL_LOCKED
),
346 .auto_recal_bit
= OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT
,
347 .recal_en_bit
= OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT
,
348 .recal_st_bit
= OMAP3430_PERIPH_DPLL_ST_SHIFT
,
349 .autoidle_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_AUTOIDLE
),
350 .autoidle_mask
= OMAP3430_AUTO_PERIPH_DPLL_MASK
,
351 .idlest_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_IDLEST
),
352 .idlest_mask
= OMAP3430_ST_PERIPH_CLK_MASK
,
353 .dco_mask
= OMAP3630_PERIPH_DPLL_DCO_SEL_MASK
,
354 .sddiv_mask
= OMAP3630_PERIPH_DPLL_SD_DIV_MASK
,
355 .max_multiplier
= OMAP3630_MAX_JTYPE_DPLL_MULT
,
357 .max_divider
= OMAP3_MAX_DPLL_DIV
,
361 static struct clk dpll4_ck
;
363 static const struct clk_ops dpll4_ck_ops
= {
364 .init
= &omap2_init_clk_clkdm
,
365 .enable
= &omap3_noncore_dpll_enable
,
366 .disable
= &omap3_noncore_dpll_disable
,
367 .get_parent
= &omap2_init_dpll_parent
,
368 .recalc_rate
= &omap3_dpll_recalc
,
369 .set_rate
= &omap3_dpll4_set_rate
,
370 .round_rate
= &omap2_dpll_round_rate
,
373 static struct clk_hw_omap dpll4_ck_hw
= {
377 .dpll_data
= &dpll4_dd
,
378 .ops
= &clkhwops_omap3_dpll
,
379 .clkdm_name
= "dpll4_clkdm",
382 DEFINE_STRUCT_CLK(dpll4_ck
, dpll3_ck_parent_names
, dpll4_ck_ops
);
384 static const struct clk_div_table dpll4_mx_ck_div_table
[] = {
385 { .div
= 1, .val
= 1 },
386 { .div
= 2, .val
= 2 },
387 { .div
= 3, .val
= 3 },
388 { .div
= 4, .val
= 4 },
389 { .div
= 5, .val
= 5 },
390 { .div
= 6, .val
= 6 },
391 { .div
= 7, .val
= 7 },
392 { .div
= 8, .val
= 8 },
393 { .div
= 9, .val
= 9 },
394 { .div
= 10, .val
= 10 },
395 { .div
= 11, .val
= 11 },
396 { .div
= 12, .val
= 12 },
397 { .div
= 13, .val
= 13 },
398 { .div
= 14, .val
= 14 },
399 { .div
= 15, .val
= 15 },
400 { .div
= 16, .val
= 16 },
401 { .div
= 17, .val
= 17 },
402 { .div
= 18, .val
= 18 },
403 { .div
= 19, .val
= 19 },
404 { .div
= 20, .val
= 20 },
405 { .div
= 21, .val
= 21 },
406 { .div
= 22, .val
= 22 },
407 { .div
= 23, .val
= 23 },
408 { .div
= 24, .val
= 24 },
409 { .div
= 25, .val
= 25 },
410 { .div
= 26, .val
= 26 },
411 { .div
= 27, .val
= 27 },
412 { .div
= 28, .val
= 28 },
413 { .div
= 29, .val
= 29 },
414 { .div
= 30, .val
= 30 },
415 { .div
= 31, .val
= 31 },
416 { .div
= 32, .val
= 32 },
420 DEFINE_CLK_DIVIDER(dpll4_m5_ck
, "dpll4_ck", &dpll4_ck
, 0x0,
421 OMAP_CM_REGADDR(OMAP3430_CAM_MOD
, CM_CLKSEL
),
422 OMAP3430_CLKSEL_CAM_SHIFT
, OMAP3630_CLKSEL_CAM_WIDTH
,
423 CLK_DIVIDER_ONE_BASED
, NULL
);
425 static struct clk dpll4_m5x2_ck
;
427 static const char *dpll4_m5x2_ck_parent_names
[] = {
431 static const struct clk_ops dpll4_m5x2_ck_ops
= {
432 .init
= &omap2_init_clk_clkdm
,
433 .enable
= &omap2_dflt_clk_enable
,
434 .disable
= &omap2_dflt_clk_disable
,
435 .is_enabled
= &omap2_dflt_clk_is_enabled
,
436 .recalc_rate
= &omap3_clkoutx2_recalc
,
439 static const struct clk_ops dpll4_m5x2_ck_3630_ops
= {
440 .init
= &omap2_init_clk_clkdm
,
441 .enable
= &omap36xx_pwrdn_clk_enable_with_hsdiv_restore
,
442 .disable
= &omap2_dflt_clk_disable
,
443 .recalc_rate
= &omap3_clkoutx2_recalc
,
446 static struct clk_hw_omap dpll4_m5x2_ck_hw
= {
448 .clk
= &dpll4_m5x2_ck
,
450 .ops
= &clkhwops_wait
,
451 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
452 .enable_bit
= OMAP3430_PWRDN_CAM_SHIFT
,
453 .flags
= INVERT_ENABLE
,
454 .clkdm_name
= "dpll4_clkdm",
457 DEFINE_STRUCT_CLK(dpll4_m5x2_ck
, dpll4_m5x2_ck_parent_names
, dpll4_m5x2_ck_ops
);
459 static struct clk dpll4_m5x2_ck_3630
= {
460 .name
= "dpll4_m5x2_ck",
461 .hw
= &dpll4_m5x2_ck_hw
.hw
,
462 .parent_names
= dpll4_m5x2_ck_parent_names
,
463 .num_parents
= ARRAY_SIZE(dpll4_m5x2_ck_parent_names
),
464 .ops
= &dpll4_m5x2_ck_3630_ops
,
465 .flags
= CLK_SET_RATE_PARENT
,
468 static struct clk cam_mclk
;
470 static const char *cam_mclk_parent_names
[] = {
474 static struct clk_hw_omap cam_mclk_hw
= {
478 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_CAM_MOD
, CM_FCLKEN
),
479 .enable_bit
= OMAP3430_EN_CAM_SHIFT
,
480 .clkdm_name
= "cam_clkdm",
483 static struct clk cam_mclk
= {
485 .hw
= &cam_mclk_hw
.hw
,
486 .parent_names
= cam_mclk_parent_names
,
487 .num_parents
= ARRAY_SIZE(cam_mclk_parent_names
),
488 .ops
= &aes2_ick_ops
,
489 .flags
= CLK_SET_RATE_PARENT
,
492 static const struct clksel_rate clkout2_src_core_rates
[] = {
493 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
497 static const struct clksel_rate clkout2_src_sys_rates
[] = {
498 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
502 static const struct clksel_rate clkout2_src_96m_rates
[] = {
503 { .div
= 1, .val
= 2, .flags
= RATE_IN_3XXX
},
507 DEFINE_CLK_DIVIDER(dpll4_m2_ck
, "dpll4_ck", &dpll4_ck
, 0x0,
508 OMAP_CM_REGADDR(PLL_MOD
, OMAP3430_CM_CLKSEL3
),
509 OMAP3430_DIV_96M_SHIFT
, OMAP3630_DIV_96M_WIDTH
,
510 CLK_DIVIDER_ONE_BASED
, NULL
);
512 static struct clk dpll4_m2x2_ck
;
514 static const char *dpll4_m2x2_ck_parent_names
[] = {
518 static struct clk_hw_omap dpll4_m2x2_ck_hw
= {
520 .clk
= &dpll4_m2x2_ck
,
522 .ops
= &clkhwops_wait
,
523 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
524 .enable_bit
= OMAP3430_PWRDN_96M_SHIFT
,
525 .flags
= INVERT_ENABLE
,
526 .clkdm_name
= "dpll4_clkdm",
529 DEFINE_STRUCT_CLK(dpll4_m2x2_ck
, dpll4_m2x2_ck_parent_names
, dpll4_m5x2_ck_ops
);
531 static struct clk dpll4_m2x2_ck_3630
= {
532 .name
= "dpll4_m2x2_ck",
533 .hw
= &dpll4_m2x2_ck_hw
.hw
,
534 .parent_names
= dpll4_m2x2_ck_parent_names
,
535 .num_parents
= ARRAY_SIZE(dpll4_m2x2_ck_parent_names
),
536 .ops
= &dpll4_m5x2_ck_3630_ops
,
539 static struct clk omap_96m_alwon_fck
;
541 static const char *omap_96m_alwon_fck_parent_names
[] = {
545 DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck
, NULL
);
546 DEFINE_STRUCT_CLK(omap_96m_alwon_fck
, omap_96m_alwon_fck_parent_names
,
549 static struct clk cm_96m_fck
;
551 static const char *cm_96m_fck_parent_names
[] = {
552 "omap_96m_alwon_fck",
555 DEFINE_STRUCT_CLK_HW_OMAP(cm_96m_fck
, NULL
);
556 DEFINE_STRUCT_CLK(cm_96m_fck
, cm_96m_fck_parent_names
, core_ck_ops
);
558 static const struct clksel_rate clkout2_src_54m_rates
[] = {
559 { .div
= 1, .val
= 3, .flags
= RATE_IN_3XXX
},
563 DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck
, "dpll4_ck", &dpll4_ck
, 0x0,
564 OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_CLKSEL
),
565 OMAP3430_CLKSEL_TV_SHIFT
, OMAP3630_CLKSEL_TV_WIDTH
,
566 0, dpll4_mx_ck_div_table
, NULL
);
568 static struct clk dpll4_m3x2_ck
;
570 static const char *dpll4_m3x2_ck_parent_names
[] = {
574 static struct clk_hw_omap dpll4_m3x2_ck_hw
= {
576 .clk
= &dpll4_m3x2_ck
,
578 .ops
= &clkhwops_wait
,
579 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
580 .enable_bit
= OMAP3430_PWRDN_TV_SHIFT
,
581 .flags
= INVERT_ENABLE
,
582 .clkdm_name
= "dpll4_clkdm",
585 DEFINE_STRUCT_CLK(dpll4_m3x2_ck
, dpll4_m3x2_ck_parent_names
, dpll4_m5x2_ck_ops
);
587 static struct clk dpll4_m3x2_ck_3630
= {
588 .name
= "dpll4_m3x2_ck",
589 .hw
= &dpll4_m3x2_ck_hw
.hw
,
590 .parent_names
= dpll4_m3x2_ck_parent_names
,
591 .num_parents
= ARRAY_SIZE(dpll4_m3x2_ck_parent_names
),
592 .ops
= &dpll4_m5x2_ck_3630_ops
,
595 static const char *omap_54m_fck_parent_names
[] = {
596 "dpll4_m3x2_ck", "sys_altclk",
599 DEFINE_CLK_MUX(omap_54m_fck
, omap_54m_fck_parent_names
, NULL
, 0x0,
600 OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
), OMAP3430_SOURCE_54M_SHIFT
,
601 OMAP3430_SOURCE_54M_WIDTH
, 0x0, NULL
);
603 static const struct clksel clkout2_src_clksel
[] = {
604 { .parent
= &core_ck
, .rates
= clkout2_src_core_rates
},
605 { .parent
= &sys_ck
, .rates
= clkout2_src_sys_rates
},
606 { .parent
= &cm_96m_fck
, .rates
= clkout2_src_96m_rates
},
607 { .parent
= &omap_54m_fck
, .rates
= clkout2_src_54m_rates
},
611 static const char *clkout2_src_ck_parent_names
[] = {
612 "core_ck", "sys_ck", "cm_96m_fck", "omap_54m_fck",
615 static const struct clk_ops clkout2_src_ck_ops
= {
616 .init
= &omap2_init_clk_clkdm
,
617 .enable
= &omap2_dflt_clk_enable
,
618 .disable
= &omap2_dflt_clk_disable
,
619 .is_enabled
= &omap2_dflt_clk_is_enabled
,
620 .recalc_rate
= &omap2_clksel_recalc
,
621 .get_parent
= &omap2_clksel_find_parent_index
,
622 .set_parent
= &omap2_clksel_set_parent
,
625 DEFINE_CLK_OMAP_MUX_GATE(clkout2_src_ck
, "core_clkdm",
626 clkout2_src_clksel
, OMAP3430_CM_CLKOUT_CTRL
,
627 OMAP3430_CLKOUT2SOURCE_MASK
,
628 OMAP3430_CM_CLKOUT_CTRL
, OMAP3430_CLKOUT2_EN_SHIFT
,
629 NULL
, clkout2_src_ck_parent_names
, clkout2_src_ck_ops
);
631 static const struct clksel_rate omap_48m_cm96m_rates
[] = {
632 { .div
= 2, .val
= 0, .flags
= RATE_IN_3XXX
},
636 static const struct clksel_rate omap_48m_alt_rates
[] = {
637 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
641 static const struct clksel omap_48m_clksel
[] = {
642 { .parent
= &cm_96m_fck
, .rates
= omap_48m_cm96m_rates
},
643 { .parent
= &sys_altclk
, .rates
= omap_48m_alt_rates
},
647 static const char *omap_48m_fck_parent_names
[] = {
648 "cm_96m_fck", "sys_altclk",
651 static struct clk omap_48m_fck
;
653 static const struct clk_ops omap_48m_fck_ops
= {
654 .recalc_rate
= &omap2_clksel_recalc
,
655 .get_parent
= &omap2_clksel_find_parent_index
,
656 .set_parent
= &omap2_clksel_set_parent
,
659 static struct clk_hw_omap omap_48m_fck_hw
= {
661 .clk
= &omap_48m_fck
,
663 .clksel
= omap_48m_clksel
,
664 .clksel_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
665 .clksel_mask
= OMAP3430_SOURCE_48M_MASK
,
668 DEFINE_STRUCT_CLK(omap_48m_fck
, omap_48m_fck_parent_names
, omap_48m_fck_ops
);
670 DEFINE_CLK_FIXED_FACTOR(omap_12m_fck
, "omap_48m_fck", &omap_48m_fck
, 0x0, 1, 4);
672 static struct clk core_12m_fck
;
674 static const char *core_12m_fck_parent_names
[] = {
678 DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck
, "core_l4_clkdm");
679 DEFINE_STRUCT_CLK(core_12m_fck
, core_12m_fck_parent_names
, core_l4_ick_ops
);
681 static struct clk core_48m_fck
;
683 static const char *core_48m_fck_parent_names
[] = {
687 DEFINE_STRUCT_CLK_HW_OMAP(core_48m_fck
, "core_l4_clkdm");
688 DEFINE_STRUCT_CLK(core_48m_fck
, core_48m_fck_parent_names
, core_l4_ick_ops
);
690 static const char *omap_96m_fck_parent_names
[] = {
691 "cm_96m_fck", "sys_ck",
694 DEFINE_CLK_MUX(omap_96m_fck
, omap_96m_fck_parent_names
, NULL
, 0x0,
695 OMAP_CM_REGADDR(PLL_MOD
, CM_CLKSEL1
),
696 OMAP3430_SOURCE_96M_SHIFT
, OMAP3430_SOURCE_96M_WIDTH
, 0x0, NULL
);
698 static struct clk core_96m_fck
;
700 static const char *core_96m_fck_parent_names
[] = {
704 DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck
, "core_l4_clkdm");
705 DEFINE_STRUCT_CLK(core_96m_fck
, core_96m_fck_parent_names
, core_l4_ick_ops
);
707 static struct clk core_l3_ick
;
709 static const char *core_l3_ick_parent_names
[] = {
713 DEFINE_STRUCT_CLK_HW_OMAP(core_l3_ick
, "core_l3_clkdm");
714 DEFINE_STRUCT_CLK(core_l3_ick
, core_l3_ick_parent_names
, core_l4_ick_ops
);
716 DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck
, "dpll3_m2_ck", &dpll3_m2_ck
, 0x0, 2, 1);
718 static struct clk corex2_fck
;
720 static const char *corex2_fck_parent_names
[] = {
724 DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck
, NULL
);
725 DEFINE_STRUCT_CLK(corex2_fck
, corex2_fck_parent_names
, core_ck_ops
);
727 static struct clk cpefuse_fck
;
729 static struct clk_hw_omap cpefuse_fck_hw
= {
733 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP3430ES2_CM_FCLKEN3
),
734 .enable_bit
= OMAP3430ES2_EN_CPEFUSE_SHIFT
,
735 .clkdm_name
= "core_l4_clkdm",
738 DEFINE_STRUCT_CLK(cpefuse_fck
, dpll3_ck_parent_names
, aes2_ick_ops
);
740 static struct clk csi2_96m_fck
;
742 static const char *csi2_96m_fck_parent_names
[] = {
746 static struct clk_hw_omap csi2_96m_fck_hw
= {
748 .clk
= &csi2_96m_fck
,
750 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_CAM_MOD
, CM_FCLKEN
),
751 .enable_bit
= OMAP3430_EN_CSI2_SHIFT
,
752 .clkdm_name
= "cam_clkdm",
755 DEFINE_STRUCT_CLK(csi2_96m_fck
, csi2_96m_fck_parent_names
, aes2_ick_ops
);
757 static struct clk d2d_26m_fck
;
759 static struct clk_hw_omap d2d_26m_fck_hw
= {
763 .ops
= &clkhwops_wait
,
764 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
765 .enable_bit
= OMAP3430ES1_EN_D2D_SHIFT
,
766 .clkdm_name
= "d2d_clkdm",
769 DEFINE_STRUCT_CLK(d2d_26m_fck
, dpll3_ck_parent_names
, aes2_ick_ops
);
771 static struct clk des1_ick
;
773 static struct clk_hw_omap des1_ick_hw
= {
777 .ops
= &clkhwops_iclk_wait
,
778 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
779 .enable_bit
= OMAP3430_EN_DES1_SHIFT
,
782 DEFINE_STRUCT_CLK(des1_ick
, aes1_ick_parent_names
, aes1_ick_ops
);
784 static struct clk des2_ick
;
786 static struct clk_hw_omap des2_ick_hw
= {
790 .ops
= &clkhwops_iclk_wait
,
791 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
792 .enable_bit
= OMAP3430_EN_DES2_SHIFT
,
793 .clkdm_name
= "core_l4_clkdm",
796 DEFINE_STRUCT_CLK(des2_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
798 DEFINE_CLK_DIVIDER(dpll1_fck
, "core_ck", &core_ck
, 0x0,
799 OMAP_CM_REGADDR(MPU_MOD
, OMAP3430_CM_CLKSEL1_PLL
),
800 OMAP3430_MPU_CLK_SRC_SHIFT
, OMAP3430_MPU_CLK_SRC_WIDTH
,
801 CLK_DIVIDER_ONE_BASED
, NULL
);
803 static struct clk dpll2_fck
;
805 static struct dpll_data dpll2_dd
= {
806 .mult_div1_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKSEL1_PLL
),
807 .mult_mask
= OMAP3430_IVA2_DPLL_MULT_MASK
,
808 .div1_mask
= OMAP3430_IVA2_DPLL_DIV_MASK
,
809 .clk_bypass
= &dpll2_fck
,
811 .freqsel_mask
= OMAP3430_IVA2_DPLL_FREQSEL_MASK
,
812 .control_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKEN_PLL
),
813 .enable_mask
= OMAP3430_EN_IVA2_DPLL_MASK
,
814 .modes
= ((1 << DPLL_LOW_POWER_STOP
) | (1 << DPLL_LOCKED
) |
815 (1 << DPLL_LOW_POWER_BYPASS
)),
816 .auto_recal_bit
= OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT
,
817 .recal_en_bit
= OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT
,
818 .recal_st_bit
= OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT
,
819 .autoidle_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_AUTOIDLE_PLL
),
820 .autoidle_mask
= OMAP3430_AUTO_IVA2_DPLL_MASK
,
821 .idlest_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_IDLEST_PLL
),
822 .idlest_mask
= OMAP3430_ST_IVA2_CLK_MASK
,
823 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
825 .max_divider
= OMAP3_MAX_DPLL_DIV
,
828 static struct clk dpll2_ck
;
830 static struct clk_hw_omap dpll2_ck_hw
= {
834 .ops
= &clkhwops_omap3_dpll
,
835 .dpll_data
= &dpll2_dd
,
836 .clkdm_name
= "dpll2_clkdm",
839 DEFINE_STRUCT_CLK(dpll2_ck
, dpll3_ck_parent_names
, dpll1_ck_ops
);
841 DEFINE_CLK_DIVIDER(dpll2_fck
, "core_ck", &core_ck
, 0x0,
842 OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKSEL1_PLL
),
843 OMAP3430_IVA2_CLK_SRC_SHIFT
, OMAP3430_IVA2_CLK_SRC_WIDTH
,
844 CLK_DIVIDER_ONE_BASED
, NULL
);
846 DEFINE_CLK_DIVIDER(dpll2_m2_ck
, "dpll2_ck", &dpll2_ck
, 0x0,
847 OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKSEL2_PLL
),
848 OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT
,
849 OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH
,
850 CLK_DIVIDER_ONE_BASED
, NULL
);
852 DEFINE_CLK_DIVIDER(dpll3_m3_ck
, "dpll3_ck", &dpll3_ck
, 0x0,
853 OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
854 OMAP3430_DIV_DPLL3_SHIFT
, OMAP3430_DIV_DPLL3_WIDTH
,
855 CLK_DIVIDER_ONE_BASED
, NULL
);
857 static struct clk dpll3_m3x2_ck
;
859 static const char *dpll3_m3x2_ck_parent_names
[] = {
863 static struct clk_hw_omap dpll3_m3x2_ck_hw
= {
865 .clk
= &dpll3_m3x2_ck
,
867 .ops
= &clkhwops_wait
,
868 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
869 .enable_bit
= OMAP3430_PWRDN_EMU_CORE_SHIFT
,
870 .flags
= INVERT_ENABLE
,
871 .clkdm_name
= "dpll3_clkdm",
874 DEFINE_STRUCT_CLK(dpll3_m3x2_ck
, dpll3_m3x2_ck_parent_names
, dpll4_m5x2_ck_ops
);
876 static struct clk dpll3_m3x2_ck_3630
= {
877 .name
= "dpll3_m3x2_ck",
878 .hw
= &dpll3_m3x2_ck_hw
.hw
,
879 .parent_names
= dpll3_m3x2_ck_parent_names
,
880 .num_parents
= ARRAY_SIZE(dpll3_m3x2_ck_parent_names
),
881 .ops
= &dpll4_m5x2_ck_3630_ops
,
884 DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck
, "dpll3_ck", &dpll3_ck
, 0x0, 2, 1);
886 DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck
, "dpll4_ck", &dpll4_ck
, 0x0,
887 OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_CLKSEL
),
888 OMAP3430_CLKSEL_DSS1_SHIFT
, OMAP3630_CLKSEL_DSS1_WIDTH
,
889 0, dpll4_mx_ck_div_table
, NULL
);
891 static struct clk dpll4_m4x2_ck
;
893 static const char *dpll4_m4x2_ck_parent_names
[] = {
897 static struct clk_hw_omap dpll4_m4x2_ck_hw
= {
899 .clk
= &dpll4_m4x2_ck
,
901 .ops
= &clkhwops_wait
,
902 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
903 .enable_bit
= OMAP3430_PWRDN_DSS1_SHIFT
,
904 .flags
= INVERT_ENABLE
,
905 .clkdm_name
= "dpll4_clkdm",
908 DEFINE_STRUCT_CLK_FLAGS(dpll4_m4x2_ck
, dpll4_m4x2_ck_parent_names
,
909 dpll4_m5x2_ck_ops
, CLK_SET_RATE_PARENT
);
911 static struct clk dpll4_m4x2_ck_3630
= {
912 .name
= "dpll4_m4x2_ck",
913 .hw
= &dpll4_m4x2_ck_hw
.hw
,
914 .parent_names
= dpll4_m4x2_ck_parent_names
,
915 .num_parents
= ARRAY_SIZE(dpll4_m4x2_ck_parent_names
),
916 .ops
= &dpll4_m5x2_ck_3630_ops
,
917 .flags
= CLK_SET_RATE_PARENT
,
920 DEFINE_CLK_DIVIDER(dpll4_m6_ck
, "dpll4_ck", &dpll4_ck
, 0x0,
921 OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
922 OMAP3430_DIV_DPLL4_SHIFT
, OMAP3630_DIV_DPLL4_WIDTH
,
923 CLK_DIVIDER_ONE_BASED
, NULL
);
925 static struct clk dpll4_m6x2_ck
;
927 static const char *dpll4_m6x2_ck_parent_names
[] = {
931 static struct clk_hw_omap dpll4_m6x2_ck_hw
= {
933 .clk
= &dpll4_m6x2_ck
,
935 .ops
= &clkhwops_wait
,
936 .enable_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_CLKEN
),
937 .enable_bit
= OMAP3430_PWRDN_EMU_PERIPH_SHIFT
,
938 .flags
= INVERT_ENABLE
,
939 .clkdm_name
= "dpll4_clkdm",
942 DEFINE_STRUCT_CLK(dpll4_m6x2_ck
, dpll4_m6x2_ck_parent_names
, dpll4_m5x2_ck_ops
);
944 static struct clk dpll4_m6x2_ck_3630
= {
945 .name
= "dpll4_m6x2_ck",
946 .hw
= &dpll4_m6x2_ck_hw
.hw
,
947 .parent_names
= dpll4_m6x2_ck_parent_names
,
948 .num_parents
= ARRAY_SIZE(dpll4_m6x2_ck_parent_names
),
949 .ops
= &dpll4_m5x2_ck_3630_ops
,
952 DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck
, "dpll4_ck", &dpll4_ck
, 0x0, 2, 1);
954 static struct dpll_data dpll5_dd
= {
955 .mult_div1_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430ES2_CM_CLKSEL4
),
956 .mult_mask
= OMAP3430ES2_PERIPH2_DPLL_MULT_MASK
,
957 .div1_mask
= OMAP3430ES2_PERIPH2_DPLL_DIV_MASK
,
958 .clk_bypass
= &sys_ck
,
960 .freqsel_mask
= OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK
,
961 .control_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430ES2_CM_CLKEN2
),
962 .enable_mask
= OMAP3430ES2_EN_PERIPH2_DPLL_MASK
,
963 .modes
= (1 << DPLL_LOW_POWER_STOP
) | (1 << DPLL_LOCKED
),
964 .auto_recal_bit
= OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT
,
965 .recal_en_bit
= OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT
,
966 .recal_st_bit
= OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT
,
967 .autoidle_reg
= OMAP_CM_REGADDR(PLL_MOD
, OMAP3430ES2_CM_AUTOIDLE2_PLL
),
968 .autoidle_mask
= OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK
,
969 .idlest_reg
= OMAP_CM_REGADDR(PLL_MOD
, CM_IDLEST2
),
970 .idlest_mask
= OMAP3430ES2_ST_PERIPH2_CLK_MASK
,
971 .max_multiplier
= OMAP3_MAX_DPLL_MULT
,
973 .max_divider
= OMAP3_MAX_DPLL_DIV
,
976 static struct clk dpll5_ck
;
978 static struct clk_hw_omap dpll5_ck_hw
= {
982 .ops
= &clkhwops_omap3_dpll
,
983 .dpll_data
= &dpll5_dd
,
984 .clkdm_name
= "dpll5_clkdm",
987 DEFINE_STRUCT_CLK(dpll5_ck
, dpll3_ck_parent_names
, dpll1_ck_ops
);
989 DEFINE_CLK_DIVIDER(dpll5_m2_ck
, "dpll5_ck", &dpll5_ck
, 0x0,
990 OMAP_CM_REGADDR(PLL_MOD
, OMAP3430ES2_CM_CLKSEL5
),
991 OMAP3430ES2_DIV_120M_SHIFT
, OMAP3430ES2_DIV_120M_WIDTH
,
992 CLK_DIVIDER_ONE_BASED
, NULL
);
994 static struct clk dss1_alwon_fck_3430es1
;
996 static const char *dss1_alwon_fck_3430es1_parent_names
[] = {
1000 static struct clk_hw_omap dss1_alwon_fck_3430es1_hw
= {
1002 .clk
= &dss1_alwon_fck_3430es1
,
1004 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
1005 .enable_bit
= OMAP3430_EN_DSS1_SHIFT
,
1006 .clkdm_name
= "dss_clkdm",
1009 DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es1
,
1010 dss1_alwon_fck_3430es1_parent_names
, aes2_ick_ops
,
1011 CLK_SET_RATE_PARENT
);
1013 static struct clk dss1_alwon_fck_3430es2
;
1015 static struct clk_hw_omap dss1_alwon_fck_3430es2_hw
= {
1017 .clk
= &dss1_alwon_fck_3430es2
,
1019 .ops
= &clkhwops_omap3430es2_dss_usbhost_wait
,
1020 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
1021 .enable_bit
= OMAP3430_EN_DSS1_SHIFT
,
1022 .clkdm_name
= "dss_clkdm",
1025 DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es2
,
1026 dss1_alwon_fck_3430es1_parent_names
, aes2_ick_ops
,
1027 CLK_SET_RATE_PARENT
);
1029 static struct clk dss2_alwon_fck
;
1031 static struct clk_hw_omap dss2_alwon_fck_hw
= {
1033 .clk
= &dss2_alwon_fck
,
1035 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
1036 .enable_bit
= OMAP3430_EN_DSS2_SHIFT
,
1037 .clkdm_name
= "dss_clkdm",
1040 DEFINE_STRUCT_CLK(dss2_alwon_fck
, dpll3_ck_parent_names
, aes2_ick_ops
);
1042 static struct clk dss_96m_fck
;
1044 static struct clk_hw_omap dss_96m_fck_hw
= {
1046 .clk
= &dss_96m_fck
,
1048 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
1049 .enable_bit
= OMAP3430_EN_TV_SHIFT
,
1050 .clkdm_name
= "dss_clkdm",
1053 DEFINE_STRUCT_CLK(dss_96m_fck
, core_96m_fck_parent_names
, aes2_ick_ops
);
1055 static struct clk dss_ick_3430es1
;
1057 static struct clk_hw_omap dss_ick_3430es1_hw
= {
1059 .clk
= &dss_ick_3430es1
,
1061 .ops
= &clkhwops_iclk
,
1062 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_ICLKEN
),
1063 .enable_bit
= OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT
,
1064 .clkdm_name
= "dss_clkdm",
1067 DEFINE_STRUCT_CLK(dss_ick_3430es1
, security_l4_ick2_parent_names
, aes2_ick_ops
);
1069 static struct clk dss_ick_3430es2
;
1071 static struct clk_hw_omap dss_ick_3430es2_hw
= {
1073 .clk
= &dss_ick_3430es2
,
1075 .ops
= &clkhwops_omap3430es2_iclk_dss_usbhost_wait
,
1076 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_ICLKEN
),
1077 .enable_bit
= OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT
,
1078 .clkdm_name
= "dss_clkdm",
1081 DEFINE_STRUCT_CLK(dss_ick_3430es2
, security_l4_ick2_parent_names
, aes2_ick_ops
);
1083 static struct clk dss_tv_fck
;
1085 static const char *dss_tv_fck_parent_names
[] = {
1089 static struct clk_hw_omap dss_tv_fck_hw
= {
1093 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_DSS_MOD
, CM_FCLKEN
),
1094 .enable_bit
= OMAP3430_EN_TV_SHIFT
,
1095 .clkdm_name
= "dss_clkdm",
1098 DEFINE_STRUCT_CLK(dss_tv_fck
, dss_tv_fck_parent_names
, aes2_ick_ops
);
1100 static struct clk emac_fck
;
1102 static const char *emac_fck_parent_names
[] = {
1106 static struct clk_hw_omap emac_fck_hw
= {
1110 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
1111 .enable_bit
= AM35XX_CPGMAC_FCLK_SHIFT
,
1114 DEFINE_STRUCT_CLK(emac_fck
, emac_fck_parent_names
, aes1_ick_ops
);
1116 static struct clk ipss_ick
;
1118 static const char *ipss_ick_parent_names
[] = {
1122 static struct clk_hw_omap ipss_ick_hw
= {
1126 .ops
= &clkhwops_am35xx_ipss_wait
,
1127 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1128 .enable_bit
= AM35XX_EN_IPSS_SHIFT
,
1129 .clkdm_name
= "core_l3_clkdm",
1132 DEFINE_STRUCT_CLK(ipss_ick
, ipss_ick_parent_names
, aes2_ick_ops
);
1134 static struct clk emac_ick
;
1136 static const char *emac_ick_parent_names
[] = {
1140 static struct clk_hw_omap emac_ick_hw
= {
1144 .ops
= &clkhwops_am35xx_ipss_module_wait
,
1145 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
1146 .enable_bit
= AM35XX_CPGMAC_VBUSP_CLK_SHIFT
,
1147 .clkdm_name
= "core_l3_clkdm",
1150 DEFINE_STRUCT_CLK(emac_ick
, emac_ick_parent_names
, aes2_ick_ops
);
1152 static struct clk emu_core_alwon_ck
;
1154 static const char *emu_core_alwon_ck_parent_names
[] = {
1158 DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck
, "dpll3_clkdm");
1159 DEFINE_STRUCT_CLK(emu_core_alwon_ck
, emu_core_alwon_ck_parent_names
,
1162 static struct clk emu_mpu_alwon_ck
;
1164 static const char *emu_mpu_alwon_ck_parent_names
[] = {
1168 DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck
, NULL
);
1169 DEFINE_STRUCT_CLK(emu_mpu_alwon_ck
, emu_mpu_alwon_ck_parent_names
, core_ck_ops
);
1171 static struct clk emu_per_alwon_ck
;
1173 static const char *emu_per_alwon_ck_parent_names
[] = {
1177 DEFINE_STRUCT_CLK_HW_OMAP(emu_per_alwon_ck
, "dpll4_clkdm");
1178 DEFINE_STRUCT_CLK(emu_per_alwon_ck
, emu_per_alwon_ck_parent_names
,
1181 static const char *emu_src_ck_parent_names
[] = {
1182 "sys_ck", "emu_core_alwon_ck", "emu_per_alwon_ck", "emu_mpu_alwon_ck",
1185 static const struct clksel_rate emu_src_sys_rates
[] = {
1186 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
1190 static const struct clksel_rate emu_src_core_rates
[] = {
1191 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
1195 static const struct clksel_rate emu_src_per_rates
[] = {
1196 { .div
= 1, .val
= 2, .flags
= RATE_IN_3XXX
},
1200 static const struct clksel_rate emu_src_mpu_rates
[] = {
1201 { .div
= 1, .val
= 3, .flags
= RATE_IN_3XXX
},
1205 static const struct clksel emu_src_clksel
[] = {
1206 { .parent
= &sys_ck
, .rates
= emu_src_sys_rates
},
1207 { .parent
= &emu_core_alwon_ck
, .rates
= emu_src_core_rates
},
1208 { .parent
= &emu_per_alwon_ck
, .rates
= emu_src_per_rates
},
1209 { .parent
= &emu_mpu_alwon_ck
, .rates
= emu_src_mpu_rates
},
1213 static const struct clk_ops emu_src_ck_ops
= {
1214 .init
= &omap2_init_clk_clkdm
,
1215 .recalc_rate
= &omap2_clksel_recalc
,
1216 .get_parent
= &omap2_clksel_find_parent_index
,
1217 .set_parent
= &omap2_clksel_set_parent
,
1218 .enable
= &omap2_clkops_enable_clkdm
,
1219 .disable
= &omap2_clkops_disable_clkdm
,
1222 static struct clk emu_src_ck
;
1224 static struct clk_hw_omap emu_src_ck_hw
= {
1228 .clksel
= emu_src_clksel
,
1229 .clksel_reg
= OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
1230 .clksel_mask
= OMAP3430_MUX_CTRL_MASK
,
1231 .clkdm_name
= "emu_clkdm",
1234 DEFINE_STRUCT_CLK(emu_src_ck
, emu_src_ck_parent_names
, emu_src_ck_ops
);
1236 DEFINE_CLK_DIVIDER(atclk_fck
, "emu_src_ck", &emu_src_ck
, 0x0,
1237 OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
1238 OMAP3430_CLKSEL_ATCLK_SHIFT
, OMAP3430_CLKSEL_ATCLK_WIDTH
,
1239 CLK_DIVIDER_ONE_BASED
, NULL
);
1241 static struct clk fac_ick
;
1243 static struct clk_hw_omap fac_ick_hw
= {
1247 .ops
= &clkhwops_iclk_wait
,
1248 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1249 .enable_bit
= OMAP3430ES1_EN_FAC_SHIFT
,
1250 .clkdm_name
= "core_l4_clkdm",
1253 DEFINE_STRUCT_CLK(fac_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
1255 static struct clk fshostusb_fck
;
1257 static const char *fshostusb_fck_parent_names
[] = {
1261 static struct clk_hw_omap fshostusb_fck_hw
= {
1263 .clk
= &fshostusb_fck
,
1265 .ops
= &clkhwops_wait
,
1266 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1267 .enable_bit
= OMAP3430ES1_EN_FSHOSTUSB_SHIFT
,
1268 .clkdm_name
= "core_l4_clkdm",
1271 DEFINE_STRUCT_CLK(fshostusb_fck
, fshostusb_fck_parent_names
, aes2_ick_ops
);
1273 static struct clk gfx_l3_ck
;
1275 static struct clk_hw_omap gfx_l3_ck_hw
= {
1279 .ops
= &clkhwops_wait
,
1280 .enable_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_ICLKEN
),
1281 .enable_bit
= OMAP_EN_GFX_SHIFT
,
1282 .clkdm_name
= "gfx_3430es1_clkdm",
1285 DEFINE_STRUCT_CLK(gfx_l3_ck
, core_l3_ick_parent_names
, aes1_ick_ops
);
1287 DEFINE_CLK_DIVIDER(gfx_l3_fck
, "l3_ick", &l3_ick
, 0x0,
1288 OMAP_CM_REGADDR(GFX_MOD
, CM_CLKSEL
),
1289 OMAP_CLKSEL_GFX_SHIFT
, OMAP_CLKSEL_GFX_WIDTH
,
1290 CLK_DIVIDER_ONE_BASED
, NULL
);
1292 static struct clk gfx_cg1_ck
;
1294 static const char *gfx_cg1_ck_parent_names
[] = {
1298 static struct clk_hw_omap gfx_cg1_ck_hw
= {
1302 .ops
= &clkhwops_wait
,
1303 .enable_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_FCLKEN
),
1304 .enable_bit
= OMAP3430ES1_EN_2D_SHIFT
,
1305 .clkdm_name
= "gfx_3430es1_clkdm",
1308 DEFINE_STRUCT_CLK(gfx_cg1_ck
, gfx_cg1_ck_parent_names
, aes2_ick_ops
);
1310 static struct clk gfx_cg2_ck
;
1312 static struct clk_hw_omap gfx_cg2_ck_hw
= {
1316 .ops
= &clkhwops_wait
,
1317 .enable_reg
= OMAP_CM_REGADDR(GFX_MOD
, CM_FCLKEN
),
1318 .enable_bit
= OMAP3430ES1_EN_3D_SHIFT
,
1319 .clkdm_name
= "gfx_3430es1_clkdm",
1322 DEFINE_STRUCT_CLK(gfx_cg2_ck
, gfx_cg1_ck_parent_names
, aes2_ick_ops
);
1324 static struct clk gfx_l3_ick
;
1326 static const char *gfx_l3_ick_parent_names
[] = {
1330 DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick
, "gfx_3430es1_clkdm");
1331 DEFINE_STRUCT_CLK(gfx_l3_ick
, gfx_l3_ick_parent_names
, core_l4_ick_ops
);
1333 static struct clk wkup_32k_fck
;
1335 static const char *wkup_32k_fck_parent_names
[] = {
1339 DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck
, "wkup_clkdm");
1340 DEFINE_STRUCT_CLK(wkup_32k_fck
, wkup_32k_fck_parent_names
, core_l4_ick_ops
);
1342 static struct clk gpio1_dbck
;
1344 static const char *gpio1_dbck_parent_names
[] = {
1348 static struct clk_hw_omap gpio1_dbck_hw
= {
1352 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
1353 .enable_bit
= OMAP3430_EN_GPIO1_SHIFT
,
1354 .clkdm_name
= "wkup_clkdm",
1357 DEFINE_STRUCT_CLK(gpio1_dbck
, gpio1_dbck_parent_names
, aes2_ick_ops
);
1359 static struct clk wkup_l4_ick
;
1361 DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick
, "wkup_clkdm");
1362 DEFINE_STRUCT_CLK(wkup_l4_ick
, dpll3_ck_parent_names
, core_l4_ick_ops
);
1364 static struct clk gpio1_ick
;
1366 static const char *gpio1_ick_parent_names
[] = {
1370 static struct clk_hw_omap gpio1_ick_hw
= {
1374 .ops
= &clkhwops_iclk_wait
,
1375 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
1376 .enable_bit
= OMAP3430_EN_GPIO1_SHIFT
,
1377 .clkdm_name
= "wkup_clkdm",
1380 DEFINE_STRUCT_CLK(gpio1_ick
, gpio1_ick_parent_names
, aes2_ick_ops
);
1382 static struct clk per_32k_alwon_fck
;
1384 DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck
, "per_clkdm");
1385 DEFINE_STRUCT_CLK(per_32k_alwon_fck
, wkup_32k_fck_parent_names
,
1388 static struct clk gpio2_dbck
;
1390 static const char *gpio2_dbck_parent_names
[] = {
1391 "per_32k_alwon_fck",
1394 static struct clk_hw_omap gpio2_dbck_hw
= {
1398 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1399 .enable_bit
= OMAP3430_EN_GPIO2_SHIFT
,
1400 .clkdm_name
= "per_clkdm",
1403 DEFINE_STRUCT_CLK(gpio2_dbck
, gpio2_dbck_parent_names
, aes2_ick_ops
);
1405 static struct clk per_l4_ick
;
1407 DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick
, "per_clkdm");
1408 DEFINE_STRUCT_CLK(per_l4_ick
, security_l4_ick2_parent_names
, core_l4_ick_ops
);
1410 static struct clk gpio2_ick
;
1412 static const char *gpio2_ick_parent_names
[] = {
1416 static struct clk_hw_omap gpio2_ick_hw
= {
1420 .ops
= &clkhwops_iclk_wait
,
1421 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1422 .enable_bit
= OMAP3430_EN_GPIO2_SHIFT
,
1423 .clkdm_name
= "per_clkdm",
1426 DEFINE_STRUCT_CLK(gpio2_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1428 static struct clk gpio3_dbck
;
1430 static struct clk_hw_omap gpio3_dbck_hw
= {
1434 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1435 .enable_bit
= OMAP3430_EN_GPIO3_SHIFT
,
1436 .clkdm_name
= "per_clkdm",
1439 DEFINE_STRUCT_CLK(gpio3_dbck
, gpio2_dbck_parent_names
, aes2_ick_ops
);
1441 static struct clk gpio3_ick
;
1443 static struct clk_hw_omap gpio3_ick_hw
= {
1447 .ops
= &clkhwops_iclk_wait
,
1448 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1449 .enable_bit
= OMAP3430_EN_GPIO3_SHIFT
,
1450 .clkdm_name
= "per_clkdm",
1453 DEFINE_STRUCT_CLK(gpio3_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1455 static struct clk gpio4_dbck
;
1457 static struct clk_hw_omap gpio4_dbck_hw
= {
1461 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1462 .enable_bit
= OMAP3430_EN_GPIO4_SHIFT
,
1463 .clkdm_name
= "per_clkdm",
1466 DEFINE_STRUCT_CLK(gpio4_dbck
, gpio2_dbck_parent_names
, aes2_ick_ops
);
1468 static struct clk gpio4_ick
;
1470 static struct clk_hw_omap gpio4_ick_hw
= {
1474 .ops
= &clkhwops_iclk_wait
,
1475 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1476 .enable_bit
= OMAP3430_EN_GPIO4_SHIFT
,
1477 .clkdm_name
= "per_clkdm",
1480 DEFINE_STRUCT_CLK(gpio4_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1482 static struct clk gpio5_dbck
;
1484 static struct clk_hw_omap gpio5_dbck_hw
= {
1488 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1489 .enable_bit
= OMAP3430_EN_GPIO5_SHIFT
,
1490 .clkdm_name
= "per_clkdm",
1493 DEFINE_STRUCT_CLK(gpio5_dbck
, gpio2_dbck_parent_names
, aes2_ick_ops
);
1495 static struct clk gpio5_ick
;
1497 static struct clk_hw_omap gpio5_ick_hw
= {
1501 .ops
= &clkhwops_iclk_wait
,
1502 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1503 .enable_bit
= OMAP3430_EN_GPIO5_SHIFT
,
1504 .clkdm_name
= "per_clkdm",
1507 DEFINE_STRUCT_CLK(gpio5_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1509 static struct clk gpio6_dbck
;
1511 static struct clk_hw_omap gpio6_dbck_hw
= {
1515 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1516 .enable_bit
= OMAP3430_EN_GPIO6_SHIFT
,
1517 .clkdm_name
= "per_clkdm",
1520 DEFINE_STRUCT_CLK(gpio6_dbck
, gpio2_dbck_parent_names
, aes2_ick_ops
);
1522 static struct clk gpio6_ick
;
1524 static struct clk_hw_omap gpio6_ick_hw
= {
1528 .ops
= &clkhwops_iclk_wait
,
1529 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1530 .enable_bit
= OMAP3430_EN_GPIO6_SHIFT
,
1531 .clkdm_name
= "per_clkdm",
1534 DEFINE_STRUCT_CLK(gpio6_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1536 static struct clk gpmc_fck
;
1538 static struct clk_hw_omap gpmc_fck_hw
= {
1542 .flags
= ENABLE_ON_INIT
,
1543 .clkdm_name
= "core_l3_clkdm",
1546 DEFINE_STRUCT_CLK(gpmc_fck
, ipss_ick_parent_names
, core_l4_ick_ops
);
1548 static const struct clksel omap343x_gpt_clksel
[] = {
1549 { .parent
= &omap_32k_fck
, .rates
= gpt_32k_rates
},
1550 { .parent
= &sys_ck
, .rates
= gpt_sys_rates
},
1554 static const char *gpt10_fck_parent_names
[] = {
1555 "omap_32k_fck", "sys_ck",
1558 DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck
, "core_l4_clkdm", omap343x_gpt_clksel
,
1559 OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1560 OMAP3430_CLKSEL_GPT10_MASK
,
1561 OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1562 OMAP3430_EN_GPT10_SHIFT
, &clkhwops_wait
,
1563 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1565 static struct clk gpt10_ick
;
1567 static struct clk_hw_omap gpt10_ick_hw
= {
1571 .ops
= &clkhwops_iclk_wait
,
1572 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1573 .enable_bit
= OMAP3430_EN_GPT10_SHIFT
,
1574 .clkdm_name
= "core_l4_clkdm",
1577 DEFINE_STRUCT_CLK(gpt10_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
1579 DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck
, "core_l4_clkdm", omap343x_gpt_clksel
,
1580 OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
1581 OMAP3430_CLKSEL_GPT11_MASK
,
1582 OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1583 OMAP3430_EN_GPT11_SHIFT
, &clkhwops_wait
,
1584 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1586 static struct clk gpt11_ick
;
1588 static struct clk_hw_omap gpt11_ick_hw
= {
1592 .ops
= &clkhwops_iclk_wait
,
1593 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1594 .enable_bit
= OMAP3430_EN_GPT11_SHIFT
,
1595 .clkdm_name
= "core_l4_clkdm",
1598 DEFINE_STRUCT_CLK(gpt11_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
1600 static struct clk gpt12_fck
;
1602 static const char *gpt12_fck_parent_names
[] = {
1606 DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck
, "wkup_clkdm");
1607 DEFINE_STRUCT_CLK(gpt12_fck
, gpt12_fck_parent_names
, core_l4_ick_ops
);
1609 static struct clk gpt12_ick
;
1611 static struct clk_hw_omap gpt12_ick_hw
= {
1615 .ops
= &clkhwops_iclk_wait
,
1616 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
1617 .enable_bit
= OMAP3430_EN_GPT12_SHIFT
,
1618 .clkdm_name
= "wkup_clkdm",
1621 DEFINE_STRUCT_CLK(gpt12_ick
, gpio1_ick_parent_names
, aes2_ick_ops
);
1623 DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck
, "wkup_clkdm", omap343x_gpt_clksel
,
1624 OMAP_CM_REGADDR(WKUP_MOD
, CM_CLKSEL
),
1625 OMAP3430_CLKSEL_GPT1_MASK
,
1626 OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
1627 OMAP3430_EN_GPT1_SHIFT
, &clkhwops_wait
,
1628 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1630 static struct clk gpt1_ick
;
1632 static struct clk_hw_omap gpt1_ick_hw
= {
1636 .ops
= &clkhwops_iclk_wait
,
1637 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
1638 .enable_bit
= OMAP3430_EN_GPT1_SHIFT
,
1639 .clkdm_name
= "wkup_clkdm",
1642 DEFINE_STRUCT_CLK(gpt1_ick
, gpio1_ick_parent_names
, aes2_ick_ops
);
1644 DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck
, "per_clkdm", omap343x_gpt_clksel
,
1645 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
1646 OMAP3430_CLKSEL_GPT2_MASK
,
1647 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1648 OMAP3430_EN_GPT2_SHIFT
, &clkhwops_wait
,
1649 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1651 static struct clk gpt2_ick
;
1653 static struct clk_hw_omap gpt2_ick_hw
= {
1657 .ops
= &clkhwops_iclk_wait
,
1658 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1659 .enable_bit
= OMAP3430_EN_GPT2_SHIFT
,
1660 .clkdm_name
= "per_clkdm",
1663 DEFINE_STRUCT_CLK(gpt2_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1665 DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck
, "per_clkdm", omap343x_gpt_clksel
,
1666 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
1667 OMAP3430_CLKSEL_GPT3_MASK
,
1668 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1669 OMAP3430_EN_GPT3_SHIFT
, &clkhwops_wait
,
1670 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1672 static struct clk gpt3_ick
;
1674 static struct clk_hw_omap gpt3_ick_hw
= {
1678 .ops
= &clkhwops_iclk_wait
,
1679 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1680 .enable_bit
= OMAP3430_EN_GPT3_SHIFT
,
1681 .clkdm_name
= "per_clkdm",
1684 DEFINE_STRUCT_CLK(gpt3_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1686 DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck
, "per_clkdm", omap343x_gpt_clksel
,
1687 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
1688 OMAP3430_CLKSEL_GPT4_MASK
,
1689 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1690 OMAP3430_EN_GPT4_SHIFT
, &clkhwops_wait
,
1691 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1693 static struct clk gpt4_ick
;
1695 static struct clk_hw_omap gpt4_ick_hw
= {
1699 .ops
= &clkhwops_iclk_wait
,
1700 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1701 .enable_bit
= OMAP3430_EN_GPT4_SHIFT
,
1702 .clkdm_name
= "per_clkdm",
1705 DEFINE_STRUCT_CLK(gpt4_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1707 DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck
, "per_clkdm", omap343x_gpt_clksel
,
1708 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
1709 OMAP3430_CLKSEL_GPT5_MASK
,
1710 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1711 OMAP3430_EN_GPT5_SHIFT
, &clkhwops_wait
,
1712 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1714 static struct clk gpt5_ick
;
1716 static struct clk_hw_omap gpt5_ick_hw
= {
1720 .ops
= &clkhwops_iclk_wait
,
1721 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1722 .enable_bit
= OMAP3430_EN_GPT5_SHIFT
,
1723 .clkdm_name
= "per_clkdm",
1726 DEFINE_STRUCT_CLK(gpt5_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1728 DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck
, "per_clkdm", omap343x_gpt_clksel
,
1729 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
1730 OMAP3430_CLKSEL_GPT6_MASK
,
1731 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1732 OMAP3430_EN_GPT6_SHIFT
, &clkhwops_wait
,
1733 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1735 static struct clk gpt6_ick
;
1737 static struct clk_hw_omap gpt6_ick_hw
= {
1741 .ops
= &clkhwops_iclk_wait
,
1742 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1743 .enable_bit
= OMAP3430_EN_GPT6_SHIFT
,
1744 .clkdm_name
= "per_clkdm",
1747 DEFINE_STRUCT_CLK(gpt6_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1749 DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck
, "per_clkdm", omap343x_gpt_clksel
,
1750 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
1751 OMAP3430_CLKSEL_GPT7_MASK
,
1752 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1753 OMAP3430_EN_GPT7_SHIFT
, &clkhwops_wait
,
1754 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1756 static struct clk gpt7_ick
;
1758 static struct clk_hw_omap gpt7_ick_hw
= {
1762 .ops
= &clkhwops_iclk_wait
,
1763 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1764 .enable_bit
= OMAP3430_EN_GPT7_SHIFT
,
1765 .clkdm_name
= "per_clkdm",
1768 DEFINE_STRUCT_CLK(gpt7_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1770 DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck
, "per_clkdm", omap343x_gpt_clksel
,
1771 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
1772 OMAP3430_CLKSEL_GPT8_MASK
,
1773 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1774 OMAP3430_EN_GPT8_SHIFT
, &clkhwops_wait
,
1775 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1777 static struct clk gpt8_ick
;
1779 static struct clk_hw_omap gpt8_ick_hw
= {
1783 .ops
= &clkhwops_iclk_wait
,
1784 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1785 .enable_bit
= OMAP3430_EN_GPT8_SHIFT
,
1786 .clkdm_name
= "per_clkdm",
1789 DEFINE_STRUCT_CLK(gpt8_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1791 DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck
, "per_clkdm", omap343x_gpt_clksel
,
1792 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_CLKSEL
),
1793 OMAP3430_CLKSEL_GPT9_MASK
,
1794 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
1795 OMAP3430_EN_GPT9_SHIFT
, &clkhwops_wait
,
1796 gpt10_fck_parent_names
, clkout2_src_ck_ops
);
1798 static struct clk gpt9_ick
;
1800 static struct clk_hw_omap gpt9_ick_hw
= {
1804 .ops
= &clkhwops_iclk_wait
,
1805 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
1806 .enable_bit
= OMAP3430_EN_GPT9_SHIFT
,
1807 .clkdm_name
= "per_clkdm",
1810 DEFINE_STRUCT_CLK(gpt9_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
1812 static struct clk hdq_fck
;
1814 static const char *hdq_fck_parent_names
[] = {
1818 static struct clk_hw_omap hdq_fck_hw
= {
1822 .ops
= &clkhwops_wait
,
1823 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1824 .enable_bit
= OMAP3430_EN_HDQ_SHIFT
,
1825 .clkdm_name
= "core_l4_clkdm",
1828 DEFINE_STRUCT_CLK(hdq_fck
, hdq_fck_parent_names
, aes2_ick_ops
);
1830 static struct clk hdq_ick
;
1832 static struct clk_hw_omap hdq_ick_hw
= {
1836 .ops
= &clkhwops_iclk_wait
,
1837 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1838 .enable_bit
= OMAP3430_EN_HDQ_SHIFT
,
1839 .clkdm_name
= "core_l4_clkdm",
1842 DEFINE_STRUCT_CLK(hdq_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
1844 static struct clk hecc_ck
;
1846 static struct clk_hw_omap hecc_ck_hw
= {
1850 .ops
= &clkhwops_am35xx_ipss_module_wait
,
1851 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
1852 .enable_bit
= AM35XX_HECC_VBUSP_CLK_SHIFT
,
1853 .clkdm_name
= "core_l3_clkdm",
1856 DEFINE_STRUCT_CLK(hecc_ck
, dpll3_ck_parent_names
, aes2_ick_ops
);
1858 static struct clk hsotgusb_fck_am35xx
;
1860 static struct clk_hw_omap hsotgusb_fck_am35xx_hw
= {
1862 .clk
= &hsotgusb_fck_am35xx
,
1864 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
1865 .enable_bit
= AM35XX_USBOTG_FCLK_SHIFT
,
1866 .clkdm_name
= "core_l3_clkdm",
1869 DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx
, dpll3_ck_parent_names
, aes2_ick_ops
);
1871 static struct clk hsotgusb_ick_3430es1
;
1873 static struct clk_hw_omap hsotgusb_ick_3430es1_hw
= {
1875 .clk
= &hsotgusb_ick_3430es1
,
1877 .ops
= &clkhwops_iclk
,
1878 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1879 .enable_bit
= OMAP3430_EN_HSOTGUSB_SHIFT
,
1880 .clkdm_name
= "core_l3_clkdm",
1883 DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1
, ipss_ick_parent_names
, aes2_ick_ops
);
1885 static struct clk hsotgusb_ick_3430es2
;
1887 static struct clk_hw_omap hsotgusb_ick_3430es2_hw
= {
1889 .clk
= &hsotgusb_ick_3430es2
,
1891 .ops
= &clkhwops_omap3430es2_iclk_hsotgusb_wait
,
1892 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1893 .enable_bit
= OMAP3430_EN_HSOTGUSB_SHIFT
,
1894 .clkdm_name
= "core_l3_clkdm",
1897 DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2
, ipss_ick_parent_names
, aes2_ick_ops
);
1899 static struct clk hsotgusb_ick_am35xx
;
1901 static struct clk_hw_omap hsotgusb_ick_am35xx_hw
= {
1903 .clk
= &hsotgusb_ick_am35xx
,
1905 .ops
= &clkhwops_am35xx_ipss_module_wait
,
1906 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
1907 .enable_bit
= AM35XX_USBOTG_VBUSP_CLK_SHIFT
,
1908 .clkdm_name
= "core_l3_clkdm",
1911 DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx
, emac_ick_parent_names
, aes2_ick_ops
);
1913 static struct clk i2c1_fck
;
1915 static struct clk_hw_omap i2c1_fck_hw
= {
1919 .ops
= &clkhwops_wait
,
1920 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1921 .enable_bit
= OMAP3430_EN_I2C1_SHIFT
,
1922 .clkdm_name
= "core_l4_clkdm",
1925 DEFINE_STRUCT_CLK(i2c1_fck
, csi2_96m_fck_parent_names
, aes2_ick_ops
);
1927 static struct clk i2c1_ick
;
1929 static struct clk_hw_omap i2c1_ick_hw
= {
1933 .ops
= &clkhwops_iclk_wait
,
1934 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1935 .enable_bit
= OMAP3430_EN_I2C1_SHIFT
,
1936 .clkdm_name
= "core_l4_clkdm",
1939 DEFINE_STRUCT_CLK(i2c1_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
1941 static struct clk i2c2_fck
;
1943 static struct clk_hw_omap i2c2_fck_hw
= {
1947 .ops
= &clkhwops_wait
,
1948 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1949 .enable_bit
= OMAP3430_EN_I2C2_SHIFT
,
1950 .clkdm_name
= "core_l4_clkdm",
1953 DEFINE_STRUCT_CLK(i2c2_fck
, csi2_96m_fck_parent_names
, aes2_ick_ops
);
1955 static struct clk i2c2_ick
;
1957 static struct clk_hw_omap i2c2_ick_hw
= {
1961 .ops
= &clkhwops_iclk_wait
,
1962 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1963 .enable_bit
= OMAP3430_EN_I2C2_SHIFT
,
1964 .clkdm_name
= "core_l4_clkdm",
1967 DEFINE_STRUCT_CLK(i2c2_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
1969 static struct clk i2c3_fck
;
1971 static struct clk_hw_omap i2c3_fck_hw
= {
1975 .ops
= &clkhwops_wait
,
1976 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
1977 .enable_bit
= OMAP3430_EN_I2C3_SHIFT
,
1978 .clkdm_name
= "core_l4_clkdm",
1981 DEFINE_STRUCT_CLK(i2c3_fck
, csi2_96m_fck_parent_names
, aes2_ick_ops
);
1983 static struct clk i2c3_ick
;
1985 static struct clk_hw_omap i2c3_ick_hw
= {
1989 .ops
= &clkhwops_iclk_wait
,
1990 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
1991 .enable_bit
= OMAP3430_EN_I2C3_SHIFT
,
1992 .clkdm_name
= "core_l4_clkdm",
1995 DEFINE_STRUCT_CLK(i2c3_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
1997 static struct clk icr_ick
;
1999 static struct clk_hw_omap icr_ick_hw
= {
2003 .ops
= &clkhwops_iclk_wait
,
2004 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2005 .enable_bit
= OMAP3430_EN_ICR_SHIFT
,
2006 .clkdm_name
= "core_l4_clkdm",
2009 DEFINE_STRUCT_CLK(icr_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2011 static struct clk iva2_ck
;
2013 static const char *iva2_ck_parent_names
[] = {
2017 static struct clk_hw_omap iva2_ck_hw
= {
2021 .ops
= &clkhwops_wait
,
2022 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD
, CM_FCLKEN
),
2023 .enable_bit
= OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT
,
2024 .clkdm_name
= "iva2_clkdm",
2027 DEFINE_STRUCT_CLK(iva2_ck
, iva2_ck_parent_names
, aes2_ick_ops
);
2029 static struct clk mad2d_ick
;
2031 static struct clk_hw_omap mad2d_ick_hw
= {
2035 .ops
= &clkhwops_iclk_wait
,
2036 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN3
),
2037 .enable_bit
= OMAP3430_EN_MAD2D_SHIFT
,
2038 .clkdm_name
= "d2d_clkdm",
2041 DEFINE_STRUCT_CLK(mad2d_ick
, core_l3_ick_parent_names
, aes2_ick_ops
);
2043 static struct clk mailboxes_ick
;
2045 static struct clk_hw_omap mailboxes_ick_hw
= {
2047 .clk
= &mailboxes_ick
,
2049 .ops
= &clkhwops_iclk_wait
,
2050 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2051 .enable_bit
= OMAP3430_EN_MAILBOXES_SHIFT
,
2052 .clkdm_name
= "core_l4_clkdm",
2055 DEFINE_STRUCT_CLK(mailboxes_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2057 static const struct clksel_rate common_mcbsp_96m_rates
[] = {
2058 { .div
= 1, .val
= 0, .flags
= RATE_IN_3XXX
},
2062 static const struct clksel_rate common_mcbsp_mcbsp_rates
[] = {
2063 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
2067 static const struct clksel mcbsp_15_clksel
[] = {
2068 { .parent
= &core_96m_fck
, .rates
= common_mcbsp_96m_rates
},
2069 { .parent
= &mcbsp_clks
, .rates
= common_mcbsp_mcbsp_rates
},
2073 static const char *mcbsp1_fck_parent_names
[] = {
2074 "core_96m_fck", "mcbsp_clks",
2077 DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck
, "core_l4_clkdm", mcbsp_15_clksel
,
2078 OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0
),
2079 OMAP2_MCBSP1_CLKS_MASK
,
2080 OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2081 OMAP3430_EN_MCBSP1_SHIFT
, &clkhwops_wait
,
2082 mcbsp1_fck_parent_names
, clkout2_src_ck_ops
);
2084 static struct clk mcbsp1_ick
;
2086 static struct clk_hw_omap mcbsp1_ick_hw
= {
2090 .ops
= &clkhwops_iclk_wait
,
2091 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2092 .enable_bit
= OMAP3430_EN_MCBSP1_SHIFT
,
2093 .clkdm_name
= "core_l4_clkdm",
2096 DEFINE_STRUCT_CLK(mcbsp1_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2098 static struct clk per_96m_fck
;
2100 DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck
, "per_clkdm");
2101 DEFINE_STRUCT_CLK(per_96m_fck
, cm_96m_fck_parent_names
, core_l4_ick_ops
);
2103 static const struct clksel mcbsp_234_clksel
[] = {
2104 { .parent
= &per_96m_fck
, .rates
= common_mcbsp_96m_rates
},
2105 { .parent
= &mcbsp_clks
, .rates
= common_mcbsp_mcbsp_rates
},
2109 static const char *mcbsp2_fck_parent_names
[] = {
2110 "per_96m_fck", "mcbsp_clks",
2113 DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck
, "per_clkdm", mcbsp_234_clksel
,
2114 OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0
),
2115 OMAP2_MCBSP2_CLKS_MASK
,
2116 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2117 OMAP3430_EN_MCBSP2_SHIFT
, &clkhwops_wait
,
2118 mcbsp2_fck_parent_names
, clkout2_src_ck_ops
);
2120 static struct clk mcbsp2_ick
;
2122 static struct clk_hw_omap mcbsp2_ick_hw
= {
2126 .ops
= &clkhwops_iclk_wait
,
2127 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2128 .enable_bit
= OMAP3430_EN_MCBSP2_SHIFT
,
2129 .clkdm_name
= "per_clkdm",
2132 DEFINE_STRUCT_CLK(mcbsp2_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
2134 DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck
, "per_clkdm", mcbsp_234_clksel
,
2135 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1
),
2136 OMAP2_MCBSP3_CLKS_MASK
,
2137 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2138 OMAP3430_EN_MCBSP3_SHIFT
, &clkhwops_wait
,
2139 mcbsp2_fck_parent_names
, clkout2_src_ck_ops
);
2141 static struct clk mcbsp3_ick
;
2143 static struct clk_hw_omap mcbsp3_ick_hw
= {
2147 .ops
= &clkhwops_iclk_wait
,
2148 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2149 .enable_bit
= OMAP3430_EN_MCBSP3_SHIFT
,
2150 .clkdm_name
= "per_clkdm",
2153 DEFINE_STRUCT_CLK(mcbsp3_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
2155 DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck
, "per_clkdm", mcbsp_234_clksel
,
2156 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1
),
2157 OMAP2_MCBSP4_CLKS_MASK
,
2158 OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2159 OMAP3430_EN_MCBSP4_SHIFT
, &clkhwops_wait
,
2160 mcbsp2_fck_parent_names
, clkout2_src_ck_ops
);
2162 static struct clk mcbsp4_ick
;
2164 static struct clk_hw_omap mcbsp4_ick_hw
= {
2168 .ops
= &clkhwops_iclk_wait
,
2169 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2170 .enable_bit
= OMAP3430_EN_MCBSP4_SHIFT
,
2171 .clkdm_name
= "per_clkdm",
2174 DEFINE_STRUCT_CLK(mcbsp4_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
2176 DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck
, "core_l4_clkdm", mcbsp_15_clksel
,
2177 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1
),
2178 OMAP2_MCBSP5_CLKS_MASK
,
2179 OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2180 OMAP3430_EN_MCBSP5_SHIFT
, &clkhwops_wait
,
2181 mcbsp1_fck_parent_names
, clkout2_src_ck_ops
);
2183 static struct clk mcbsp5_ick
;
2185 static struct clk_hw_omap mcbsp5_ick_hw
= {
2189 .ops
= &clkhwops_iclk_wait
,
2190 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2191 .enable_bit
= OMAP3430_EN_MCBSP5_SHIFT
,
2192 .clkdm_name
= "core_l4_clkdm",
2195 DEFINE_STRUCT_CLK(mcbsp5_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2197 static struct clk mcspi1_fck
;
2199 static struct clk_hw_omap mcspi1_fck_hw
= {
2203 .ops
= &clkhwops_wait
,
2204 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2205 .enable_bit
= OMAP3430_EN_MCSPI1_SHIFT
,
2206 .clkdm_name
= "core_l4_clkdm",
2209 DEFINE_STRUCT_CLK(mcspi1_fck
, fshostusb_fck_parent_names
, aes2_ick_ops
);
2211 static struct clk mcspi1_ick
;
2213 static struct clk_hw_omap mcspi1_ick_hw
= {
2217 .ops
= &clkhwops_iclk_wait
,
2218 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2219 .enable_bit
= OMAP3430_EN_MCSPI1_SHIFT
,
2220 .clkdm_name
= "core_l4_clkdm",
2223 DEFINE_STRUCT_CLK(mcspi1_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2225 static struct clk mcspi2_fck
;
2227 static struct clk_hw_omap mcspi2_fck_hw
= {
2231 .ops
= &clkhwops_wait
,
2232 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2233 .enable_bit
= OMAP3430_EN_MCSPI2_SHIFT
,
2234 .clkdm_name
= "core_l4_clkdm",
2237 DEFINE_STRUCT_CLK(mcspi2_fck
, fshostusb_fck_parent_names
, aes2_ick_ops
);
2239 static struct clk mcspi2_ick
;
2241 static struct clk_hw_omap mcspi2_ick_hw
= {
2245 .ops
= &clkhwops_iclk_wait
,
2246 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2247 .enable_bit
= OMAP3430_EN_MCSPI2_SHIFT
,
2248 .clkdm_name
= "core_l4_clkdm",
2251 DEFINE_STRUCT_CLK(mcspi2_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2253 static struct clk mcspi3_fck
;
2255 static struct clk_hw_omap mcspi3_fck_hw
= {
2259 .ops
= &clkhwops_wait
,
2260 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2261 .enable_bit
= OMAP3430_EN_MCSPI3_SHIFT
,
2262 .clkdm_name
= "core_l4_clkdm",
2265 DEFINE_STRUCT_CLK(mcspi3_fck
, fshostusb_fck_parent_names
, aes2_ick_ops
);
2267 static struct clk mcspi3_ick
;
2269 static struct clk_hw_omap mcspi3_ick_hw
= {
2273 .ops
= &clkhwops_iclk_wait
,
2274 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2275 .enable_bit
= OMAP3430_EN_MCSPI3_SHIFT
,
2276 .clkdm_name
= "core_l4_clkdm",
2279 DEFINE_STRUCT_CLK(mcspi3_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2281 static struct clk mcspi4_fck
;
2283 static struct clk_hw_omap mcspi4_fck_hw
= {
2287 .ops
= &clkhwops_wait
,
2288 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2289 .enable_bit
= OMAP3430_EN_MCSPI4_SHIFT
,
2290 .clkdm_name
= "core_l4_clkdm",
2293 DEFINE_STRUCT_CLK(mcspi4_fck
, fshostusb_fck_parent_names
, aes2_ick_ops
);
2295 static struct clk mcspi4_ick
;
2297 static struct clk_hw_omap mcspi4_ick_hw
= {
2301 .ops
= &clkhwops_iclk_wait
,
2302 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2303 .enable_bit
= OMAP3430_EN_MCSPI4_SHIFT
,
2304 .clkdm_name
= "core_l4_clkdm",
2307 DEFINE_STRUCT_CLK(mcspi4_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2309 static struct clk mmchs1_fck
;
2311 static struct clk_hw_omap mmchs1_fck_hw
= {
2315 .ops
= &clkhwops_wait
,
2316 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2317 .enable_bit
= OMAP3430_EN_MMC1_SHIFT
,
2318 .clkdm_name
= "core_l4_clkdm",
2321 DEFINE_STRUCT_CLK(mmchs1_fck
, csi2_96m_fck_parent_names
, aes2_ick_ops
);
2323 static struct clk mmchs1_ick
;
2325 static struct clk_hw_omap mmchs1_ick_hw
= {
2329 .ops
= &clkhwops_iclk_wait
,
2330 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2331 .enable_bit
= OMAP3430_EN_MMC1_SHIFT
,
2332 .clkdm_name
= "core_l4_clkdm",
2335 DEFINE_STRUCT_CLK(mmchs1_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2337 static struct clk mmchs2_fck
;
2339 static struct clk_hw_omap mmchs2_fck_hw
= {
2343 .ops
= &clkhwops_wait
,
2344 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2345 .enable_bit
= OMAP3430_EN_MMC2_SHIFT
,
2346 .clkdm_name
= "core_l4_clkdm",
2349 DEFINE_STRUCT_CLK(mmchs2_fck
, csi2_96m_fck_parent_names
, aes2_ick_ops
);
2351 static struct clk mmchs2_ick
;
2353 static struct clk_hw_omap mmchs2_ick_hw
= {
2357 .ops
= &clkhwops_iclk_wait
,
2358 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2359 .enable_bit
= OMAP3430_EN_MMC2_SHIFT
,
2360 .clkdm_name
= "core_l4_clkdm",
2363 DEFINE_STRUCT_CLK(mmchs2_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2365 static struct clk mmchs3_fck
;
2367 static struct clk_hw_omap mmchs3_fck_hw
= {
2371 .ops
= &clkhwops_wait
,
2372 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2373 .enable_bit
= OMAP3430ES2_EN_MMC3_SHIFT
,
2374 .clkdm_name
= "core_l4_clkdm",
2377 DEFINE_STRUCT_CLK(mmchs3_fck
, csi2_96m_fck_parent_names
, aes2_ick_ops
);
2379 static struct clk mmchs3_ick
;
2381 static struct clk_hw_omap mmchs3_ick_hw
= {
2385 .ops
= &clkhwops_iclk_wait
,
2386 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2387 .enable_bit
= OMAP3430ES2_EN_MMC3_SHIFT
,
2388 .clkdm_name
= "core_l4_clkdm",
2391 DEFINE_STRUCT_CLK(mmchs3_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2393 static struct clk modem_fck
;
2395 static struct clk_hw_omap modem_fck_hw
= {
2399 .ops
= &clkhwops_iclk_wait
,
2400 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2401 .enable_bit
= OMAP3430_EN_MODEM_SHIFT
,
2402 .clkdm_name
= "d2d_clkdm",
2405 DEFINE_STRUCT_CLK(modem_fck
, dpll3_ck_parent_names
, aes2_ick_ops
);
2407 static struct clk mspro_fck
;
2409 static struct clk_hw_omap mspro_fck_hw
= {
2413 .ops
= &clkhwops_wait
,
2414 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2415 .enable_bit
= OMAP3430_EN_MSPRO_SHIFT
,
2416 .clkdm_name
= "core_l4_clkdm",
2419 DEFINE_STRUCT_CLK(mspro_fck
, csi2_96m_fck_parent_names
, aes2_ick_ops
);
2421 static struct clk mspro_ick
;
2423 static struct clk_hw_omap mspro_ick_hw
= {
2427 .ops
= &clkhwops_iclk_wait
,
2428 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2429 .enable_bit
= OMAP3430_EN_MSPRO_SHIFT
,
2430 .clkdm_name
= "core_l4_clkdm",
2433 DEFINE_STRUCT_CLK(mspro_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2435 static struct clk omap_192m_alwon_fck
;
2437 DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck
, NULL
);
2438 DEFINE_STRUCT_CLK(omap_192m_alwon_fck
, omap_96m_alwon_fck_parent_names
,
2441 static struct clk omap_32ksync_ick
;
2443 static struct clk_hw_omap omap_32ksync_ick_hw
= {
2445 .clk
= &omap_32ksync_ick
,
2447 .ops
= &clkhwops_iclk_wait
,
2448 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
2449 .enable_bit
= OMAP3430_EN_32KSYNC_SHIFT
,
2450 .clkdm_name
= "wkup_clkdm",
2453 DEFINE_STRUCT_CLK(omap_32ksync_ick
, gpio1_ick_parent_names
, aes2_ick_ops
);
2455 static const struct clksel_rate omap_96m_alwon_fck_rates
[] = {
2456 { .div
= 1, .val
= 1, .flags
= RATE_IN_36XX
},
2457 { .div
= 2, .val
= 2, .flags
= RATE_IN_36XX
},
2461 static const struct clksel omap_96m_alwon_fck_clksel
[] = {
2462 { .parent
= &omap_192m_alwon_fck
, .rates
= omap_96m_alwon_fck_rates
},
2466 static struct clk omap_96m_alwon_fck_3630
;
2468 static const char *omap_96m_alwon_fck_3630_parent_names
[] = {
2469 "omap_192m_alwon_fck",
2472 static const struct clk_ops omap_96m_alwon_fck_3630_ops
= {
2473 .set_rate
= &omap2_clksel_set_rate
,
2474 .recalc_rate
= &omap2_clksel_recalc
,
2475 .round_rate
= &omap2_clksel_round_rate
,
2478 static struct clk_hw_omap omap_96m_alwon_fck_3630_hw
= {
2480 .clk
= &omap_96m_alwon_fck_3630
,
2482 .clksel
= omap_96m_alwon_fck_clksel
,
2483 .clksel_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
2484 .clksel_mask
= OMAP3630_CLKSEL_96M_MASK
,
2487 static struct clk omap_96m_alwon_fck_3630
= {
2488 .name
= "omap_96m_alwon_fck",
2489 .hw
= &omap_96m_alwon_fck_3630_hw
.hw
,
2490 .parent_names
= omap_96m_alwon_fck_3630_parent_names
,
2491 .num_parents
= ARRAY_SIZE(omap_96m_alwon_fck_3630_parent_names
),
2492 .ops
= &omap_96m_alwon_fck_3630_ops
,
2495 static struct clk omapctrl_ick
;
2497 static struct clk_hw_omap omapctrl_ick_hw
= {
2499 .clk
= &omapctrl_ick
,
2501 .ops
= &clkhwops_iclk_wait
,
2502 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2503 .enable_bit
= OMAP3430_EN_OMAPCTRL_SHIFT
,
2504 .flags
= ENABLE_ON_INIT
,
2505 .clkdm_name
= "core_l4_clkdm",
2508 DEFINE_STRUCT_CLK(omapctrl_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2510 DEFINE_CLK_DIVIDER(pclk_fck
, "emu_src_ck", &emu_src_ck
, 0x0,
2511 OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2512 OMAP3430_CLKSEL_PCLK_SHIFT
, OMAP3430_CLKSEL_PCLK_WIDTH
,
2513 CLK_DIVIDER_ONE_BASED
, NULL
);
2515 DEFINE_CLK_DIVIDER(pclkx2_fck
, "emu_src_ck", &emu_src_ck
, 0x0,
2516 OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2517 OMAP3430_CLKSEL_PCLKX2_SHIFT
, OMAP3430_CLKSEL_PCLKX2_WIDTH
,
2518 CLK_DIVIDER_ONE_BASED
, NULL
);
2520 static struct clk per_48m_fck
;
2522 DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck
, "per_clkdm");
2523 DEFINE_STRUCT_CLK(per_48m_fck
, core_48m_fck_parent_names
, core_l4_ick_ops
);
2525 static struct clk security_l3_ick
;
2527 DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick
, NULL
);
2528 DEFINE_STRUCT_CLK(security_l3_ick
, core_l3_ick_parent_names
, core_ck_ops
);
2530 static struct clk pka_ick
;
2532 static const char *pka_ick_parent_names
[] = {
2536 static struct clk_hw_omap pka_ick_hw
= {
2540 .ops
= &clkhwops_iclk_wait
,
2541 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
2542 .enable_bit
= OMAP3430_EN_PKA_SHIFT
,
2545 DEFINE_STRUCT_CLK(pka_ick
, pka_ick_parent_names
, aes1_ick_ops
);
2547 DEFINE_CLK_DIVIDER(rm_ick
, "l4_ick", &l4_ick
, 0x0,
2548 OMAP_CM_REGADDR(WKUP_MOD
, CM_CLKSEL
),
2549 OMAP3430_CLKSEL_RM_SHIFT
, OMAP3430_CLKSEL_RM_WIDTH
,
2550 CLK_DIVIDER_ONE_BASED
, NULL
);
2552 static struct clk rng_ick
;
2554 static struct clk_hw_omap rng_ick_hw
= {
2558 .ops
= &clkhwops_iclk_wait
,
2559 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
2560 .enable_bit
= OMAP3430_EN_RNG_SHIFT
,
2563 DEFINE_STRUCT_CLK(rng_ick
, aes1_ick_parent_names
, aes1_ick_ops
);
2565 static struct clk sad2d_ick
;
2567 static struct clk_hw_omap sad2d_ick_hw
= {
2571 .ops
= &clkhwops_iclk_wait
,
2572 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2573 .enable_bit
= OMAP3430_EN_SAD2D_SHIFT
,
2574 .clkdm_name
= "d2d_clkdm",
2577 DEFINE_STRUCT_CLK(sad2d_ick
, core_l3_ick_parent_names
, aes2_ick_ops
);
2579 static struct clk sdrc_ick
;
2581 static struct clk_hw_omap sdrc_ick_hw
= {
2585 .ops
= &clkhwops_wait
,
2586 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2587 .enable_bit
= OMAP3430_EN_SDRC_SHIFT
,
2588 .flags
= ENABLE_ON_INIT
,
2589 .clkdm_name
= "core_l3_clkdm",
2592 DEFINE_STRUCT_CLK(sdrc_ick
, ipss_ick_parent_names
, aes2_ick_ops
);
2594 static const struct clksel_rate sgx_core_rates
[] = {
2595 { .div
= 2, .val
= 5, .flags
= RATE_IN_36XX
},
2596 { .div
= 3, .val
= 0, .flags
= RATE_IN_3XXX
},
2597 { .div
= 4, .val
= 1, .flags
= RATE_IN_3XXX
},
2598 { .div
= 6, .val
= 2, .flags
= RATE_IN_3XXX
},
2602 static const struct clksel_rate sgx_96m_rates
[] = {
2603 { .div
= 1, .val
= 3, .flags
= RATE_IN_3XXX
},
2607 static const struct clksel_rate sgx_192m_rates
[] = {
2608 { .div
= 1, .val
= 4, .flags
= RATE_IN_36XX
},
2612 static const struct clksel_rate sgx_corex2_rates
[] = {
2613 { .div
= 3, .val
= 6, .flags
= RATE_IN_36XX
},
2614 { .div
= 5, .val
= 7, .flags
= RATE_IN_36XX
},
2618 static const struct clksel sgx_clksel
[] = {
2619 { .parent
= &core_ck
, .rates
= sgx_core_rates
},
2620 { .parent
= &cm_96m_fck
, .rates
= sgx_96m_rates
},
2621 { .parent
= &omap_192m_alwon_fck
, .rates
= sgx_192m_rates
},
2622 { .parent
= &corex2_fck
, .rates
= sgx_corex2_rates
},
2626 static const char *sgx_fck_parent_names
[] = {
2627 "core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck",
2630 static struct clk sgx_fck
;
2632 static const struct clk_ops sgx_fck_ops
= {
2633 .init
= &omap2_init_clk_clkdm
,
2634 .enable
= &omap2_dflt_clk_enable
,
2635 .disable
= &omap2_dflt_clk_disable
,
2636 .is_enabled
= &omap2_dflt_clk_is_enabled
,
2637 .recalc_rate
= &omap2_clksel_recalc
,
2638 .set_rate
= &omap2_clksel_set_rate
,
2639 .round_rate
= &omap2_clksel_round_rate
,
2640 .get_parent
= &omap2_clksel_find_parent_index
,
2641 .set_parent
= &omap2_clksel_set_parent
,
2644 DEFINE_CLK_OMAP_MUX_GATE(sgx_fck
, "sgx_clkdm", sgx_clksel
,
2645 OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD
, CM_CLKSEL
),
2646 OMAP3430ES2_CLKSEL_SGX_MASK
,
2647 OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD
, CM_FCLKEN
),
2648 OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT
,
2649 &clkhwops_wait
, sgx_fck_parent_names
, sgx_fck_ops
);
2651 static struct clk sgx_ick
;
2653 static struct clk_hw_omap sgx_ick_hw
= {
2657 .ops
= &clkhwops_wait
,
2658 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD
, CM_ICLKEN
),
2659 .enable_bit
= OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT
,
2660 .clkdm_name
= "sgx_clkdm",
2663 DEFINE_STRUCT_CLK(sgx_ick
, core_l3_ick_parent_names
, aes2_ick_ops
);
2665 static struct clk sha11_ick
;
2667 static struct clk_hw_omap sha11_ick_hw
= {
2671 .ops
= &clkhwops_iclk_wait
,
2672 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN2
),
2673 .enable_bit
= OMAP3430_EN_SHA11_SHIFT
,
2676 DEFINE_STRUCT_CLK(sha11_ick
, aes1_ick_parent_names
, aes1_ick_ops
);
2678 static struct clk sha12_ick
;
2680 static struct clk_hw_omap sha12_ick_hw
= {
2684 .ops
= &clkhwops_iclk_wait
,
2685 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2686 .enable_bit
= OMAP3430_EN_SHA12_SHIFT
,
2687 .clkdm_name
= "core_l4_clkdm",
2690 DEFINE_STRUCT_CLK(sha12_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2692 static struct clk sr1_fck
;
2694 static struct clk_hw_omap sr1_fck_hw
= {
2698 .ops
= &clkhwops_wait
,
2699 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
2700 .enable_bit
= OMAP3430_EN_SR1_SHIFT
,
2701 .clkdm_name
= "wkup_clkdm",
2704 DEFINE_STRUCT_CLK(sr1_fck
, dpll3_ck_parent_names
, aes2_ick_ops
);
2706 static struct clk sr2_fck
;
2708 static struct clk_hw_omap sr2_fck_hw
= {
2712 .ops
= &clkhwops_wait
,
2713 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
2714 .enable_bit
= OMAP3430_EN_SR2_SHIFT
,
2715 .clkdm_name
= "wkup_clkdm",
2718 DEFINE_STRUCT_CLK(sr2_fck
, dpll3_ck_parent_names
, aes2_ick_ops
);
2720 static struct clk sr_l4_ick
;
2722 DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick
, "core_l4_clkdm");
2723 DEFINE_STRUCT_CLK(sr_l4_ick
, security_l4_ick2_parent_names
, core_l4_ick_ops
);
2725 static struct clk ssi_l4_ick
;
2727 DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick
, "core_l4_clkdm");
2728 DEFINE_STRUCT_CLK(ssi_l4_ick
, security_l4_ick2_parent_names
, core_l4_ick_ops
);
2730 static struct clk ssi_ick_3430es1
;
2732 static const char *ssi_ick_3430es1_parent_names
[] = {
2736 static struct clk_hw_omap ssi_ick_3430es1_hw
= {
2738 .clk
= &ssi_ick_3430es1
,
2740 .ops
= &clkhwops_iclk
,
2741 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2742 .enable_bit
= OMAP3430_EN_SSI_SHIFT
,
2743 .clkdm_name
= "core_l4_clkdm",
2746 DEFINE_STRUCT_CLK(ssi_ick_3430es1
, ssi_ick_3430es1_parent_names
, aes2_ick_ops
);
2748 static struct clk ssi_ick_3430es2
;
2750 static struct clk_hw_omap ssi_ick_3430es2_hw
= {
2752 .clk
= &ssi_ick_3430es2
,
2754 .ops
= &clkhwops_omap3430es2_iclk_ssi_wait
,
2755 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2756 .enable_bit
= OMAP3430_EN_SSI_SHIFT
,
2757 .clkdm_name
= "core_l4_clkdm",
2760 DEFINE_STRUCT_CLK(ssi_ick_3430es2
, ssi_ick_3430es1_parent_names
, aes2_ick_ops
);
2762 static const struct clksel_rate ssi_ssr_corex2_rates
[] = {
2763 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
2764 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
2765 { .div
= 3, .val
= 3, .flags
= RATE_IN_3XXX
},
2766 { .div
= 4, .val
= 4, .flags
= RATE_IN_3XXX
},
2767 { .div
= 6, .val
= 6, .flags
= RATE_IN_3XXX
},
2768 { .div
= 8, .val
= 8, .flags
= RATE_IN_3XXX
},
2772 static const struct clksel ssi_ssr_clksel
[] = {
2773 { .parent
= &corex2_fck
, .rates
= ssi_ssr_corex2_rates
},
2777 static const char *ssi_ssr_fck_3430es1_parent_names
[] = {
2781 static const struct clk_ops ssi_ssr_fck_3430es1_ops
= {
2782 .init
= &omap2_init_clk_clkdm
,
2783 .enable
= &omap2_dflt_clk_enable
,
2784 .disable
= &omap2_dflt_clk_disable
,
2785 .is_enabled
= &omap2_dflt_clk_is_enabled
,
2786 .recalc_rate
= &omap2_clksel_recalc
,
2787 .set_rate
= &omap2_clksel_set_rate
,
2788 .round_rate
= &omap2_clksel_round_rate
,
2791 DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es1
, "core_l4_clkdm",
2792 ssi_ssr_clksel
, OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
2793 OMAP3430_CLKSEL_SSI_MASK
,
2794 OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2795 OMAP3430_EN_SSI_SHIFT
,
2796 NULL
, ssi_ssr_fck_3430es1_parent_names
,
2797 ssi_ssr_fck_3430es1_ops
);
2799 DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es2
, "core_l4_clkdm",
2800 ssi_ssr_clksel
, OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
2801 OMAP3430_CLKSEL_SSI_MASK
,
2802 OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2803 OMAP3430_EN_SSI_SHIFT
,
2804 NULL
, ssi_ssr_fck_3430es1_parent_names
,
2805 ssi_ssr_fck_3430es1_ops
);
2807 DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1
, "ssi_ssr_fck_3430es1",
2808 &ssi_ssr_fck_3430es1
, 0x0, 1, 2);
2810 DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2
, "ssi_ssr_fck_3430es2",
2811 &ssi_ssr_fck_3430es2
, 0x0, 1, 2);
2813 static struct clk sys_clkout1
;
2815 static const char *sys_clkout1_parent_names
[] = {
2819 static struct clk_hw_omap sys_clkout1_hw
= {
2821 .clk
= &sys_clkout1
,
2823 .enable_reg
= OMAP3430_PRM_CLKOUT_CTRL
,
2824 .enable_bit
= OMAP3430_CLKOUT_EN_SHIFT
,
2827 DEFINE_STRUCT_CLK(sys_clkout1
, sys_clkout1_parent_names
, aes1_ick_ops
);
2829 DEFINE_CLK_DIVIDER(sys_clkout2
, "clkout2_src_ck", &clkout2_src_ck
, 0x0,
2830 OMAP3430_CM_CLKOUT_CTRL
, OMAP3430_CLKOUT2_DIV_SHIFT
,
2831 OMAP3430_CLKOUT2_DIV_WIDTH
, CLK_DIVIDER_POWER_OF_TWO
, NULL
);
2833 DEFINE_CLK_MUX(traceclk_src_fck
, emu_src_ck_parent_names
, NULL
, 0x0,
2834 OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2835 OMAP3430_TRACE_MUX_CTRL_SHIFT
, OMAP3430_TRACE_MUX_CTRL_WIDTH
,
2838 DEFINE_CLK_DIVIDER(traceclk_fck
, "traceclk_src_fck", &traceclk_src_fck
, 0x0,
2839 OMAP_CM_REGADDR(OMAP3430_EMU_MOD
, CM_CLKSEL1
),
2840 OMAP3430_CLKSEL_TRACECLK_SHIFT
,
2841 OMAP3430_CLKSEL_TRACECLK_WIDTH
, CLK_DIVIDER_ONE_BASED
, NULL
);
2843 static struct clk ts_fck
;
2845 static struct clk_hw_omap ts_fck_hw
= {
2849 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP3430ES2_CM_FCLKEN3
),
2850 .enable_bit
= OMAP3430ES2_EN_TS_SHIFT
,
2851 .clkdm_name
= "core_l4_clkdm",
2854 DEFINE_STRUCT_CLK(ts_fck
, wkup_32k_fck_parent_names
, aes2_ick_ops
);
2856 static struct clk uart1_fck
;
2858 static struct clk_hw_omap uart1_fck_hw
= {
2862 .ops
= &clkhwops_wait
,
2863 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2864 .enable_bit
= OMAP3430_EN_UART1_SHIFT
,
2865 .clkdm_name
= "core_l4_clkdm",
2868 DEFINE_STRUCT_CLK(uart1_fck
, fshostusb_fck_parent_names
, aes2_ick_ops
);
2870 static struct clk uart1_ick
;
2872 static struct clk_hw_omap uart1_ick_hw
= {
2876 .ops
= &clkhwops_iclk_wait
,
2877 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2878 .enable_bit
= OMAP3430_EN_UART1_SHIFT
,
2879 .clkdm_name
= "core_l4_clkdm",
2882 DEFINE_STRUCT_CLK(uart1_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2884 static struct clk uart2_fck
;
2886 static struct clk_hw_omap uart2_fck_hw
= {
2890 .ops
= &clkhwops_wait
,
2891 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2892 .enable_bit
= OMAP3430_EN_UART2_SHIFT
,
2893 .clkdm_name
= "core_l4_clkdm",
2896 DEFINE_STRUCT_CLK(uart2_fck
, fshostusb_fck_parent_names
, aes2_ick_ops
);
2898 static struct clk uart2_ick
;
2900 static struct clk_hw_omap uart2_ick_hw
= {
2904 .ops
= &clkhwops_iclk_wait
,
2905 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2906 .enable_bit
= OMAP3430_EN_UART2_SHIFT
,
2907 .clkdm_name
= "core_l4_clkdm",
2910 DEFINE_STRUCT_CLK(uart2_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
2912 static struct clk uart3_fck
;
2914 static const char *uart3_fck_parent_names
[] = {
2918 static struct clk_hw_omap uart3_fck_hw
= {
2922 .ops
= &clkhwops_wait
,
2923 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2924 .enable_bit
= OMAP3430_EN_UART3_SHIFT
,
2925 .clkdm_name
= "per_clkdm",
2928 DEFINE_STRUCT_CLK(uart3_fck
, uart3_fck_parent_names
, aes2_ick_ops
);
2930 static struct clk uart3_ick
;
2932 static struct clk_hw_omap uart3_ick_hw
= {
2936 .ops
= &clkhwops_iclk_wait
,
2937 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2938 .enable_bit
= OMAP3430_EN_UART3_SHIFT
,
2939 .clkdm_name
= "per_clkdm",
2942 DEFINE_STRUCT_CLK(uart3_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
2944 static struct clk uart4_fck
;
2946 static struct clk_hw_omap uart4_fck_hw
= {
2950 .ops
= &clkhwops_wait
,
2951 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
2952 .enable_bit
= OMAP3630_EN_UART4_SHIFT
,
2953 .clkdm_name
= "per_clkdm",
2956 DEFINE_STRUCT_CLK(uart4_fck
, uart3_fck_parent_names
, aes2_ick_ops
);
2958 static struct clk uart4_fck_am35xx
;
2960 static struct clk_hw_omap uart4_fck_am35xx_hw
= {
2962 .clk
= &uart4_fck_am35xx
,
2964 .ops
= &clkhwops_wait
,
2965 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_FCLKEN1
),
2966 .enable_bit
= AM35XX_EN_UART4_SHIFT
,
2967 .clkdm_name
= "core_l4_clkdm",
2970 DEFINE_STRUCT_CLK(uart4_fck_am35xx
, fshostusb_fck_parent_names
, aes2_ick_ops
);
2972 static struct clk uart4_ick
;
2974 static struct clk_hw_omap uart4_ick_hw
= {
2978 .ops
= &clkhwops_iclk_wait
,
2979 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
2980 .enable_bit
= OMAP3630_EN_UART4_SHIFT
,
2981 .clkdm_name
= "per_clkdm",
2984 DEFINE_STRUCT_CLK(uart4_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
2986 static struct clk uart4_ick_am35xx
;
2988 static struct clk_hw_omap uart4_ick_am35xx_hw
= {
2990 .clk
= &uart4_ick_am35xx
,
2992 .ops
= &clkhwops_iclk_wait
,
2993 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
2994 .enable_bit
= AM35XX_EN_UART4_SHIFT
,
2995 .clkdm_name
= "core_l4_clkdm",
2998 DEFINE_STRUCT_CLK(uart4_ick_am35xx
, aes2_ick_parent_names
, aes2_ick_ops
);
3000 static const struct clksel_rate div2_rates
[] = {
3001 { .div
= 1, .val
= 1, .flags
= RATE_IN_3XXX
},
3002 { .div
= 2, .val
= 2, .flags
= RATE_IN_3XXX
},
3006 static const struct clksel usb_l4_clksel
[] = {
3007 { .parent
= &l4_ick
, .rates
= div2_rates
},
3011 static const char *usb_l4_ick_parent_names
[] = {
3015 DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick
, "core_l4_clkdm", usb_l4_clksel
,
3016 OMAP_CM_REGADDR(CORE_MOD
, CM_CLKSEL
),
3017 OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK
,
3018 OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN1
),
3019 OMAP3430ES1_EN_FSHOSTUSB_SHIFT
,
3020 &clkhwops_iclk_wait
, usb_l4_ick_parent_names
,
3021 ssi_ssr_fck_3430es1_ops
);
3023 static struct clk usbhost_120m_fck
;
3025 static const char *usbhost_120m_fck_parent_names
[] = {
3029 static struct clk_hw_omap usbhost_120m_fck_hw
= {
3031 .clk
= &usbhost_120m_fck
,
3033 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD
, CM_FCLKEN
),
3034 .enable_bit
= OMAP3430ES2_EN_USBHOST2_SHIFT
,
3035 .clkdm_name
= "usbhost_clkdm",
3038 DEFINE_STRUCT_CLK(usbhost_120m_fck
, usbhost_120m_fck_parent_names
,
3041 static struct clk usbhost_48m_fck
;
3043 static struct clk_hw_omap usbhost_48m_fck_hw
= {
3045 .clk
= &usbhost_48m_fck
,
3047 .ops
= &clkhwops_omap3430es2_dss_usbhost_wait
,
3048 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD
, CM_FCLKEN
),
3049 .enable_bit
= OMAP3430ES2_EN_USBHOST1_SHIFT
,
3050 .clkdm_name
= "usbhost_clkdm",
3053 DEFINE_STRUCT_CLK(usbhost_48m_fck
, core_48m_fck_parent_names
, aes2_ick_ops
);
3055 static struct clk usbhost_ick
;
3057 static struct clk_hw_omap usbhost_ick_hw
= {
3059 .clk
= &usbhost_ick
,
3061 .ops
= &clkhwops_omap3430es2_iclk_dss_usbhost_wait
,
3062 .enable_reg
= OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD
, CM_ICLKEN
),
3063 .enable_bit
= OMAP3430ES2_EN_USBHOST_SHIFT
,
3064 .clkdm_name
= "usbhost_clkdm",
3067 DEFINE_STRUCT_CLK(usbhost_ick
, security_l4_ick2_parent_names
, aes2_ick_ops
);
3069 static struct clk usbtll_fck
;
3071 static struct clk_hw_omap usbtll_fck_hw
= {
3075 .ops
= &clkhwops_wait
,
3076 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, OMAP3430ES2_CM_FCLKEN3
),
3077 .enable_bit
= OMAP3430ES2_EN_USBTLL_SHIFT
,
3078 .clkdm_name
= "core_l4_clkdm",
3081 DEFINE_STRUCT_CLK(usbtll_fck
, usbhost_120m_fck_parent_names
, aes2_ick_ops
);
3083 static struct clk usbtll_ick
;
3085 static struct clk_hw_omap usbtll_ick_hw
= {
3089 .ops
= &clkhwops_iclk_wait
,
3090 .enable_reg
= OMAP_CM_REGADDR(CORE_MOD
, CM_ICLKEN3
),
3091 .enable_bit
= OMAP3430ES2_EN_USBTLL_SHIFT
,
3092 .clkdm_name
= "core_l4_clkdm",
3095 DEFINE_STRUCT_CLK(usbtll_ick
, aes2_ick_parent_names
, aes2_ick_ops
);
3097 static const struct clksel_rate usim_96m_rates
[] = {
3098 { .div
= 2, .val
= 3, .flags
= RATE_IN_3XXX
},
3099 { .div
= 4, .val
= 4, .flags
= RATE_IN_3XXX
},
3100 { .div
= 8, .val
= 5, .flags
= RATE_IN_3XXX
},
3101 { .div
= 10, .val
= 6, .flags
= RATE_IN_3XXX
},
3105 static const struct clksel_rate usim_120m_rates
[] = {
3106 { .div
= 4, .val
= 7, .flags
= RATE_IN_3XXX
},
3107 { .div
= 8, .val
= 8, .flags
= RATE_IN_3XXX
},
3108 { .div
= 16, .val
= 9, .flags
= RATE_IN_3XXX
},
3109 { .div
= 20, .val
= 10, .flags
= RATE_IN_3XXX
},
3113 static const struct clksel usim_clksel
[] = {
3114 { .parent
= &omap_96m_fck
, .rates
= usim_96m_rates
},
3115 { .parent
= &dpll5_m2_ck
, .rates
= usim_120m_rates
},
3116 { .parent
= &sys_ck
, .rates
= div2_rates
},
3120 static const char *usim_fck_parent_names
[] = {
3121 "omap_96m_fck", "dpll5_m2_ck", "sys_ck",
3124 static struct clk usim_fck
;
3126 static const struct clk_ops usim_fck_ops
= {
3127 .enable
= &omap2_dflt_clk_enable
,
3128 .disable
= &omap2_dflt_clk_disable
,
3129 .is_enabled
= &omap2_dflt_clk_is_enabled
,
3130 .recalc_rate
= &omap2_clksel_recalc
,
3131 .get_parent
= &omap2_clksel_find_parent_index
,
3132 .set_parent
= &omap2_clksel_set_parent
,
3135 DEFINE_CLK_OMAP_MUX_GATE(usim_fck
, NULL
, usim_clksel
,
3136 OMAP_CM_REGADDR(WKUP_MOD
, CM_CLKSEL
),
3137 OMAP3430ES2_CLKSEL_USIMOCP_MASK
,
3138 OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
3139 OMAP3430ES2_EN_USIMOCP_SHIFT
, &clkhwops_wait
,
3140 usim_fck_parent_names
, usim_fck_ops
);
3142 static struct clk usim_ick
;
3144 static struct clk_hw_omap usim_ick_hw
= {
3148 .ops
= &clkhwops_iclk_wait
,
3149 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
3150 .enable_bit
= OMAP3430ES2_EN_USIMOCP_SHIFT
,
3151 .clkdm_name
= "wkup_clkdm",
3154 DEFINE_STRUCT_CLK(usim_ick
, gpio1_ick_parent_names
, aes2_ick_ops
);
3156 static struct clk vpfe_fck
;
3158 static const char *vpfe_fck_parent_names
[] = {
3162 static struct clk_hw_omap vpfe_fck_hw
= {
3166 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
3167 .enable_bit
= AM35XX_VPFE_FCLK_SHIFT
,
3170 DEFINE_STRUCT_CLK(vpfe_fck
, vpfe_fck_parent_names
, aes1_ick_ops
);
3172 static struct clk vpfe_ick
;
3174 static struct clk_hw_omap vpfe_ick_hw
= {
3178 .ops
= &clkhwops_am35xx_ipss_module_wait
,
3179 .enable_reg
= OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL
),
3180 .enable_bit
= AM35XX_VPFE_VBUSP_CLK_SHIFT
,
3181 .clkdm_name
= "core_l3_clkdm",
3184 DEFINE_STRUCT_CLK(vpfe_ick
, emac_ick_parent_names
, aes2_ick_ops
);
3186 static struct clk wdt1_fck
;
3188 DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck
, "wkup_clkdm");
3189 DEFINE_STRUCT_CLK(wdt1_fck
, gpt12_fck_parent_names
, core_l4_ick_ops
);
3191 static struct clk wdt1_ick
;
3193 static struct clk_hw_omap wdt1_ick_hw
= {
3197 .ops
= &clkhwops_iclk_wait
,
3198 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
3199 .enable_bit
= OMAP3430_EN_WDT1_SHIFT
,
3200 .clkdm_name
= "wkup_clkdm",
3203 DEFINE_STRUCT_CLK(wdt1_ick
, gpio1_ick_parent_names
, aes2_ick_ops
);
3205 static struct clk wdt2_fck
;
3207 static struct clk_hw_omap wdt2_fck_hw
= {
3211 .ops
= &clkhwops_wait
,
3212 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_FCLKEN
),
3213 .enable_bit
= OMAP3430_EN_WDT2_SHIFT
,
3214 .clkdm_name
= "wkup_clkdm",
3217 DEFINE_STRUCT_CLK(wdt2_fck
, gpio1_dbck_parent_names
, aes2_ick_ops
);
3219 static struct clk wdt2_ick
;
3221 static struct clk_hw_omap wdt2_ick_hw
= {
3225 .ops
= &clkhwops_iclk_wait
,
3226 .enable_reg
= OMAP_CM_REGADDR(WKUP_MOD
, CM_ICLKEN
),
3227 .enable_bit
= OMAP3430_EN_WDT2_SHIFT
,
3228 .clkdm_name
= "wkup_clkdm",
3231 DEFINE_STRUCT_CLK(wdt2_ick
, gpio1_ick_parent_names
, aes2_ick_ops
);
3233 static struct clk wdt3_fck
;
3235 static struct clk_hw_omap wdt3_fck_hw
= {
3239 .ops
= &clkhwops_wait
,
3240 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_FCLKEN
),
3241 .enable_bit
= OMAP3430_EN_WDT3_SHIFT
,
3242 .clkdm_name
= "per_clkdm",
3245 DEFINE_STRUCT_CLK(wdt3_fck
, gpio2_dbck_parent_names
, aes2_ick_ops
);
3247 static struct clk wdt3_ick
;
3249 static struct clk_hw_omap wdt3_ick_hw
= {
3253 .ops
= &clkhwops_iclk_wait
,
3254 .enable_reg
= OMAP_CM_REGADDR(OMAP3430_PER_MOD
, CM_ICLKEN
),
3255 .enable_bit
= OMAP3430_EN_WDT3_SHIFT
,
3256 .clkdm_name
= "per_clkdm",
3259 DEFINE_STRUCT_CLK(wdt3_ick
, gpio2_ick_parent_names
, aes2_ick_ops
);
3262 * clocks specific to omap3430es1
3264 static struct omap_clk omap3430es1_clks
[] = {
3265 CLK(NULL
, "gfx_l3_ck", &gfx_l3_ck
),
3266 CLK(NULL
, "gfx_l3_fck", &gfx_l3_fck
),
3267 CLK(NULL
, "gfx_l3_ick", &gfx_l3_ick
),
3268 CLK(NULL
, "gfx_cg1_ck", &gfx_cg1_ck
),
3269 CLK(NULL
, "gfx_cg2_ck", &gfx_cg2_ck
),
3270 CLK(NULL
, "d2d_26m_fck", &d2d_26m_fck
),
3271 CLK(NULL
, "fshostusb_fck", &fshostusb_fck
),
3272 CLK(NULL
, "ssi_ssr_fck", &ssi_ssr_fck_3430es1
),
3273 CLK(NULL
, "ssi_sst_fck", &ssi_sst_fck_3430es1
),
3274 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1
),
3275 CLK(NULL
, "hsotgusb_ick", &hsotgusb_ick_3430es1
),
3276 CLK(NULL
, "fac_ick", &fac_ick
),
3277 CLK(NULL
, "ssi_ick", &ssi_ick_3430es1
),
3278 CLK(NULL
, "usb_l4_ick", &usb_l4_ick
),
3279 CLK(NULL
, "dss1_alwon_fck", &dss1_alwon_fck_3430es1
),
3280 CLK("omapdss_dss", "ick", &dss_ick_3430es1
),
3281 CLK(NULL
, "dss_ick", &dss_ick_3430es1
),
3285 * clocks specific to am35xx
3287 static struct omap_clk am35xx_clks
[] = {
3288 CLK(NULL
, "ipss_ick", &ipss_ick
),
3289 CLK(NULL
, "rmii_ck", &rmii_ck
),
3290 CLK(NULL
, "pclk_ck", &pclk_ck
),
3291 CLK(NULL
, "emac_ick", &emac_ick
),
3292 CLK(NULL
, "emac_fck", &emac_fck
),
3293 CLK("davinci_emac.0", NULL
, &emac_ick
),
3294 CLK("davinci_mdio.0", NULL
, &emac_fck
),
3295 CLK("vpfe-capture", "master", &vpfe_ick
),
3296 CLK("vpfe-capture", "slave", &vpfe_fck
),
3297 CLK(NULL
, "hsotgusb_ick", &hsotgusb_ick_am35xx
),
3298 CLK(NULL
, "hsotgusb_fck", &hsotgusb_fck_am35xx
),
3299 CLK(NULL
, "hecc_ck", &hecc_ck
),
3300 CLK(NULL
, "uart4_ick", &uart4_ick_am35xx
),
3301 CLK(NULL
, "uart4_fck", &uart4_fck_am35xx
),
3305 * clocks specific to omap36xx
3307 static struct omap_clk omap36xx_clks
[] = {
3308 CLK(NULL
, "omap_192m_alwon_fck", &omap_192m_alwon_fck
),
3309 CLK(NULL
, "uart4_fck", &uart4_fck
),
3313 * clocks common to omap36xx omap34xx
3315 static struct omap_clk omap34xx_omap36xx_clks
[] = {
3316 CLK(NULL
, "aes1_ick", &aes1_ick
),
3317 CLK("omap_rng", "ick", &rng_ick
),
3318 CLK("omap3-rom-rng", "ick", &rng_ick
),
3319 CLK(NULL
, "sha11_ick", &sha11_ick
),
3320 CLK(NULL
, "des1_ick", &des1_ick
),
3321 CLK(NULL
, "cam_mclk", &cam_mclk
),
3322 CLK(NULL
, "cam_ick", &cam_ick
),
3323 CLK(NULL
, "csi2_96m_fck", &csi2_96m_fck
),
3324 CLK(NULL
, "security_l3_ick", &security_l3_ick
),
3325 CLK(NULL
, "pka_ick", &pka_ick
),
3326 CLK(NULL
, "icr_ick", &icr_ick
),
3327 CLK("omap-aes", "ick", &aes2_ick
),
3328 CLK("omap-sham", "ick", &sha12_ick
),
3329 CLK(NULL
, "des2_ick", &des2_ick
),
3330 CLK(NULL
, "mspro_ick", &mspro_ick
),
3331 CLK(NULL
, "mailboxes_ick", &mailboxes_ick
),
3332 CLK(NULL
, "ssi_l4_ick", &ssi_l4_ick
),
3333 CLK(NULL
, "sr1_fck", &sr1_fck
),
3334 CLK(NULL
, "sr2_fck", &sr2_fck
),
3335 CLK(NULL
, "sr_l4_ick", &sr_l4_ick
),
3336 CLK(NULL
, "security_l4_ick2", &security_l4_ick2
),
3337 CLK(NULL
, "wkup_l4_ick", &wkup_l4_ick
),
3338 CLK(NULL
, "dpll2_fck", &dpll2_fck
),
3339 CLK(NULL
, "iva2_ck", &iva2_ck
),
3340 CLK(NULL
, "modem_fck", &modem_fck
),
3341 CLK(NULL
, "sad2d_ick", &sad2d_ick
),
3342 CLK(NULL
, "mad2d_ick", &mad2d_ick
),
3343 CLK(NULL
, "mspro_fck", &mspro_fck
),
3344 CLK(NULL
, "dpll2_ck", &dpll2_ck
),
3345 CLK(NULL
, "dpll2_m2_ck", &dpll2_m2_ck
),
3349 * clocks common to omap36xx and omap3430es2plus
3351 static struct omap_clk omap36xx_omap3430es2plus_clks
[] = {
3352 CLK(NULL
, "ssi_ssr_fck", &ssi_ssr_fck_3430es2
),
3353 CLK(NULL
, "ssi_sst_fck", &ssi_sst_fck_3430es2
),
3354 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2
),
3355 CLK(NULL
, "hsotgusb_ick", &hsotgusb_ick_3430es2
),
3356 CLK(NULL
, "ssi_ick", &ssi_ick_3430es2
),
3357 CLK(NULL
, "usim_fck", &usim_fck
),
3358 CLK(NULL
, "usim_ick", &usim_ick
),
3362 * clocks common to am35xx omap36xx and omap3430es2plus
3364 static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks
[] = {
3365 CLK(NULL
, "virt_16_8m_ck", &virt_16_8m_ck
),
3366 CLK(NULL
, "dpll5_ck", &dpll5_ck
),
3367 CLK(NULL
, "dpll5_m2_ck", &dpll5_m2_ck
),
3368 CLK(NULL
, "sgx_fck", &sgx_fck
),
3369 CLK(NULL
, "sgx_ick", &sgx_ick
),
3370 CLK(NULL
, "cpefuse_fck", &cpefuse_fck
),
3371 CLK(NULL
, "ts_fck", &ts_fck
),
3372 CLK(NULL
, "usbtll_fck", &usbtll_fck
),
3373 CLK(NULL
, "usbtll_ick", &usbtll_ick
),
3374 CLK("omap_hsmmc.2", "ick", &mmchs3_ick
),
3375 CLK(NULL
, "mmchs3_ick", &mmchs3_ick
),
3376 CLK(NULL
, "mmchs3_fck", &mmchs3_fck
),
3377 CLK(NULL
, "dss1_alwon_fck", &dss1_alwon_fck_3430es2
),
3378 CLK("omapdss_dss", "ick", &dss_ick_3430es2
),
3379 CLK(NULL
, "dss_ick", &dss_ick_3430es2
),
3380 CLK(NULL
, "usbhost_120m_fck", &usbhost_120m_fck
),
3381 CLK(NULL
, "usbhost_48m_fck", &usbhost_48m_fck
),
3382 CLK(NULL
, "usbhost_ick", &usbhost_ick
),
3388 static struct omap_clk omap3xxx_clks
[] = {
3389 CLK(NULL
, "apb_pclk", &dummy_apb_pclk
),
3390 CLK(NULL
, "omap_32k_fck", &omap_32k_fck
),
3391 CLK(NULL
, "virt_12m_ck", &virt_12m_ck
),
3392 CLK(NULL
, "virt_13m_ck", &virt_13m_ck
),
3393 CLK(NULL
, "virt_19200000_ck", &virt_19200000_ck
),
3394 CLK(NULL
, "virt_26000000_ck", &virt_26000000_ck
),
3395 CLK(NULL
, "virt_38_4m_ck", &virt_38_4m_ck
),
3396 CLK(NULL
, "osc_sys_ck", &osc_sys_ck
),
3397 CLK("twl", "fck", &osc_sys_ck
),
3398 CLK(NULL
, "sys_ck", &sys_ck
),
3399 CLK(NULL
, "omap_96m_alwon_fck", &omap_96m_alwon_fck
),
3400 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck
),
3401 CLK(NULL
, "sys_altclk", &sys_altclk
),
3402 CLK(NULL
, "mcbsp_clks", &mcbsp_clks
),
3403 CLK(NULL
, "sys_clkout1", &sys_clkout1
),
3404 CLK(NULL
, "dpll1_ck", &dpll1_ck
),
3405 CLK(NULL
, "dpll1_x2_ck", &dpll1_x2_ck
),
3406 CLK(NULL
, "dpll1_x2m2_ck", &dpll1_x2m2_ck
),
3407 CLK(NULL
, "dpll3_ck", &dpll3_ck
),
3408 CLK(NULL
, "core_ck", &core_ck
),
3409 CLK(NULL
, "dpll3_x2_ck", &dpll3_x2_ck
),
3410 CLK(NULL
, "dpll3_m2_ck", &dpll3_m2_ck
),
3411 CLK(NULL
, "dpll3_m2x2_ck", &dpll3_m2x2_ck
),
3412 CLK(NULL
, "dpll3_m3_ck", &dpll3_m3_ck
),
3413 CLK(NULL
, "dpll3_m3x2_ck", &dpll3_m3x2_ck
),
3414 CLK(NULL
, "dpll4_ck", &dpll4_ck
),
3415 CLK(NULL
, "dpll4_x2_ck", &dpll4_x2_ck
),
3416 CLK(NULL
, "omap_96m_fck", &omap_96m_fck
),
3417 CLK(NULL
, "cm_96m_fck", &cm_96m_fck
),
3418 CLK(NULL
, "omap_54m_fck", &omap_54m_fck
),
3419 CLK(NULL
, "omap_48m_fck", &omap_48m_fck
),
3420 CLK(NULL
, "omap_12m_fck", &omap_12m_fck
),
3421 CLK(NULL
, "dpll4_m2_ck", &dpll4_m2_ck
),
3422 CLK(NULL
, "dpll4_m2x2_ck", &dpll4_m2x2_ck
),
3423 CLK(NULL
, "dpll4_m3_ck", &dpll4_m3_ck
),
3424 CLK(NULL
, "dpll4_m3x2_ck", &dpll4_m3x2_ck
),
3425 CLK(NULL
, "dpll4_m4_ck", &dpll4_m4_ck
),
3426 CLK(NULL
, "dpll4_m4x2_ck", &dpll4_m4x2_ck
),
3427 CLK(NULL
, "dpll4_m5_ck", &dpll4_m5_ck
),
3428 CLK(NULL
, "dpll4_m5x2_ck", &dpll4_m5x2_ck
),
3429 CLK(NULL
, "dpll4_m6_ck", &dpll4_m6_ck
),
3430 CLK(NULL
, "dpll4_m6x2_ck", &dpll4_m6x2_ck
),
3431 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck
),
3432 CLK(NULL
, "clkout2_src_ck", &clkout2_src_ck
),
3433 CLK(NULL
, "sys_clkout2", &sys_clkout2
),
3434 CLK(NULL
, "corex2_fck", &corex2_fck
),
3435 CLK(NULL
, "dpll1_fck", &dpll1_fck
),
3436 CLK(NULL
, "mpu_ck", &mpu_ck
),
3437 CLK(NULL
, "arm_fck", &arm_fck
),
3438 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck
),
3439 CLK(NULL
, "l3_ick", &l3_ick
),
3440 CLK(NULL
, "l4_ick", &l4_ick
),
3441 CLK(NULL
, "rm_ick", &rm_ick
),
3442 CLK(NULL
, "gpt10_fck", &gpt10_fck
),
3443 CLK(NULL
, "gpt11_fck", &gpt11_fck
),
3444 CLK(NULL
, "core_96m_fck", &core_96m_fck
),
3445 CLK(NULL
, "mmchs2_fck", &mmchs2_fck
),
3446 CLK(NULL
, "mmchs1_fck", &mmchs1_fck
),
3447 CLK(NULL
, "i2c3_fck", &i2c3_fck
),
3448 CLK(NULL
, "i2c2_fck", &i2c2_fck
),
3449 CLK(NULL
, "i2c1_fck", &i2c1_fck
),
3450 CLK(NULL
, "mcbsp5_fck", &mcbsp5_fck
),
3451 CLK(NULL
, "mcbsp1_fck", &mcbsp1_fck
),
3452 CLK(NULL
, "core_48m_fck", &core_48m_fck
),
3453 CLK(NULL
, "mcspi4_fck", &mcspi4_fck
),
3454 CLK(NULL
, "mcspi3_fck", &mcspi3_fck
),
3455 CLK(NULL
, "mcspi2_fck", &mcspi2_fck
),
3456 CLK(NULL
, "mcspi1_fck", &mcspi1_fck
),
3457 CLK(NULL
, "uart2_fck", &uart2_fck
),
3458 CLK(NULL
, "uart1_fck", &uart1_fck
),
3459 CLK(NULL
, "core_12m_fck", &core_12m_fck
),
3460 CLK("omap_hdq.0", "fck", &hdq_fck
),
3461 CLK(NULL
, "hdq_fck", &hdq_fck
),
3462 CLK(NULL
, "core_l3_ick", &core_l3_ick
),
3463 CLK(NULL
, "sdrc_ick", &sdrc_ick
),
3464 CLK(NULL
, "gpmc_fck", &gpmc_fck
),
3465 CLK(NULL
, "core_l4_ick", &core_l4_ick
),
3466 CLK("omap_hsmmc.1", "ick", &mmchs2_ick
),
3467 CLK("omap_hsmmc.0", "ick", &mmchs1_ick
),
3468 CLK(NULL
, "mmchs2_ick", &mmchs2_ick
),
3469 CLK(NULL
, "mmchs1_ick", &mmchs1_ick
),
3470 CLK("omap_hdq.0", "ick", &hdq_ick
),
3471 CLK(NULL
, "hdq_ick", &hdq_ick
),
3472 CLK("omap2_mcspi.4", "ick", &mcspi4_ick
),
3473 CLK("omap2_mcspi.3", "ick", &mcspi3_ick
),
3474 CLK("omap2_mcspi.2", "ick", &mcspi2_ick
),
3475 CLK("omap2_mcspi.1", "ick", &mcspi1_ick
),
3476 CLK(NULL
, "mcspi4_ick", &mcspi4_ick
),
3477 CLK(NULL
, "mcspi3_ick", &mcspi3_ick
),
3478 CLK(NULL
, "mcspi2_ick", &mcspi2_ick
),
3479 CLK(NULL
, "mcspi1_ick", &mcspi1_ick
),
3480 CLK("omap_i2c.3", "ick", &i2c3_ick
),
3481 CLK("omap_i2c.2", "ick", &i2c2_ick
),
3482 CLK("omap_i2c.1", "ick", &i2c1_ick
),
3483 CLK(NULL
, "i2c3_ick", &i2c3_ick
),
3484 CLK(NULL
, "i2c2_ick", &i2c2_ick
),
3485 CLK(NULL
, "i2c1_ick", &i2c1_ick
),
3486 CLK(NULL
, "uart2_ick", &uart2_ick
),
3487 CLK(NULL
, "uart1_ick", &uart1_ick
),
3488 CLK(NULL
, "gpt11_ick", &gpt11_ick
),
3489 CLK(NULL
, "gpt10_ick", &gpt10_ick
),
3490 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick
),
3491 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick
),
3492 CLK(NULL
, "mcbsp5_ick", &mcbsp5_ick
),
3493 CLK(NULL
, "mcbsp1_ick", &mcbsp1_ick
),
3494 CLK(NULL
, "omapctrl_ick", &omapctrl_ick
),
3495 CLK(NULL
, "dss_tv_fck", &dss_tv_fck
),
3496 CLK(NULL
, "dss_96m_fck", &dss_96m_fck
),
3497 CLK(NULL
, "dss2_alwon_fck", &dss2_alwon_fck
),
3498 CLK(NULL
, "utmi_p1_gfclk", &dummy_ck
),
3499 CLK(NULL
, "utmi_p2_gfclk", &dummy_ck
),
3500 CLK(NULL
, "xclk60mhsp1_ck", &dummy_ck
),
3501 CLK(NULL
, "xclk60mhsp2_ck", &dummy_ck
),
3502 CLK(NULL
, "init_60m_fclk", &dummy_ck
),
3503 CLK(NULL
, "gpt1_fck", &gpt1_fck
),
3504 CLK(NULL
, "aes2_ick", &aes2_ick
),
3505 CLK(NULL
, "wkup_32k_fck", &wkup_32k_fck
),
3506 CLK(NULL
, "gpio1_dbck", &gpio1_dbck
),
3507 CLK(NULL
, "sha12_ick", &sha12_ick
),
3508 CLK(NULL
, "wdt2_fck", &wdt2_fck
),
3509 CLK("omap_wdt", "ick", &wdt2_ick
),
3510 CLK(NULL
, "wdt2_ick", &wdt2_ick
),
3511 CLK(NULL
, "wdt1_ick", &wdt1_ick
),
3512 CLK(NULL
, "gpio1_ick", &gpio1_ick
),
3513 CLK(NULL
, "omap_32ksync_ick", &omap_32ksync_ick
),
3514 CLK(NULL
, "gpt12_ick", &gpt12_ick
),
3515 CLK(NULL
, "gpt1_ick", &gpt1_ick
),
3516 CLK(NULL
, "per_96m_fck", &per_96m_fck
),
3517 CLK(NULL
, "per_48m_fck", &per_48m_fck
),
3518 CLK(NULL
, "uart3_fck", &uart3_fck
),
3519 CLK(NULL
, "gpt2_fck", &gpt2_fck
),
3520 CLK(NULL
, "gpt3_fck", &gpt3_fck
),
3521 CLK(NULL
, "gpt4_fck", &gpt4_fck
),
3522 CLK(NULL
, "gpt5_fck", &gpt5_fck
),
3523 CLK(NULL
, "gpt6_fck", &gpt6_fck
),
3524 CLK(NULL
, "gpt7_fck", &gpt7_fck
),
3525 CLK(NULL
, "gpt8_fck", &gpt8_fck
),
3526 CLK(NULL
, "gpt9_fck", &gpt9_fck
),
3527 CLK(NULL
, "per_32k_alwon_fck", &per_32k_alwon_fck
),
3528 CLK(NULL
, "gpio6_dbck", &gpio6_dbck
),
3529 CLK(NULL
, "gpio5_dbck", &gpio5_dbck
),
3530 CLK(NULL
, "gpio4_dbck", &gpio4_dbck
),
3531 CLK(NULL
, "gpio3_dbck", &gpio3_dbck
),
3532 CLK(NULL
, "gpio2_dbck", &gpio2_dbck
),
3533 CLK(NULL
, "wdt3_fck", &wdt3_fck
),
3534 CLK(NULL
, "per_l4_ick", &per_l4_ick
),
3535 CLK(NULL
, "gpio6_ick", &gpio6_ick
),
3536 CLK(NULL
, "gpio5_ick", &gpio5_ick
),
3537 CLK(NULL
, "gpio4_ick", &gpio4_ick
),
3538 CLK(NULL
, "gpio3_ick", &gpio3_ick
),
3539 CLK(NULL
, "gpio2_ick", &gpio2_ick
),
3540 CLK(NULL
, "wdt3_ick", &wdt3_ick
),
3541 CLK(NULL
, "uart3_ick", &uart3_ick
),
3542 CLK(NULL
, "uart4_ick", &uart4_ick
),
3543 CLK(NULL
, "gpt9_ick", &gpt9_ick
),
3544 CLK(NULL
, "gpt8_ick", &gpt8_ick
),
3545 CLK(NULL
, "gpt7_ick", &gpt7_ick
),
3546 CLK(NULL
, "gpt6_ick", &gpt6_ick
),
3547 CLK(NULL
, "gpt5_ick", &gpt5_ick
),
3548 CLK(NULL
, "gpt4_ick", &gpt4_ick
),
3549 CLK(NULL
, "gpt3_ick", &gpt3_ick
),
3550 CLK(NULL
, "gpt2_ick", &gpt2_ick
),
3551 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick
),
3552 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick
),
3553 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick
),
3554 CLK(NULL
, "mcbsp4_ick", &mcbsp2_ick
),
3555 CLK(NULL
, "mcbsp3_ick", &mcbsp3_ick
),
3556 CLK(NULL
, "mcbsp2_ick", &mcbsp4_ick
),
3557 CLK(NULL
, "mcbsp2_fck", &mcbsp2_fck
),
3558 CLK(NULL
, "mcbsp3_fck", &mcbsp3_fck
),
3559 CLK(NULL
, "mcbsp4_fck", &mcbsp4_fck
),
3560 CLK("etb", "emu_src_ck", &emu_src_ck
),
3561 CLK(NULL
, "emu_src_ck", &emu_src_ck
),
3562 CLK(NULL
, "pclk_fck", &pclk_fck
),
3563 CLK(NULL
, "pclkx2_fck", &pclkx2_fck
),
3564 CLK(NULL
, "atclk_fck", &atclk_fck
),
3565 CLK(NULL
, "traceclk_src_fck", &traceclk_src_fck
),
3566 CLK(NULL
, "traceclk_fck", &traceclk_fck
),
3567 CLK(NULL
, "secure_32k_fck", &secure_32k_fck
),
3568 CLK(NULL
, "gpt12_fck", &gpt12_fck
),
3569 CLK(NULL
, "wdt1_fck", &wdt1_fck
),
3570 CLK(NULL
, "timer_32k_ck", &omap_32k_fck
),
3571 CLK(NULL
, "timer_sys_ck", &sys_ck
),
3572 CLK(NULL
, "cpufreq_ck", &dpll1_ck
),
3575 static const char *enable_init_clks
[] = {
3581 int __init
omap3xxx_clk_init(void)
3583 if (omap3_has_192mhz_clk())
3584 omap_96m_alwon_fck
= omap_96m_alwon_fck_3630
;
3586 if (cpu_is_omap3630()) {
3587 dpll3_m3x2_ck
= dpll3_m3x2_ck_3630
;
3588 dpll4_m2x2_ck
= dpll4_m2x2_ck_3630
;
3589 dpll4_m3x2_ck
= dpll4_m3x2_ck_3630
;
3590 dpll4_m4x2_ck
= dpll4_m4x2_ck_3630
;
3591 dpll4_m5x2_ck
= dpll4_m5x2_ck_3630
;
3592 dpll4_m6x2_ck
= dpll4_m6x2_ck_3630
;
3596 * XXX This type of dynamic rewriting of the clock tree is
3597 * deprecated and should be revised soon.
3599 if (cpu_is_omap3630())
3600 dpll4_dd
= dpll4_dd_3630
;
3602 dpll4_dd
= dpll4_dd_34xx
;
3606 * 3505 must be tested before 3517, since 3517 returns true
3607 * for both AM3517 chips and AM3517 family chips, which
3608 * includes 3505. Unfortunately there's no obvious family
3609 * test for 3517/3505 :-(
3611 if (soc_is_am35xx()) {
3612 cpu_mask
= RATE_IN_34XX
;
3613 omap_clocks_register(am35xx_clks
, ARRAY_SIZE(am35xx_clks
));
3614 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks
,
3615 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks
));
3616 omap_clocks_register(omap3xxx_clks
, ARRAY_SIZE(omap3xxx_clks
));
3617 } else if (cpu_is_omap3630()) {
3618 cpu_mask
= (RATE_IN_34XX
| RATE_IN_36XX
);
3619 omap_clocks_register(omap36xx_clks
, ARRAY_SIZE(omap36xx_clks
));
3620 omap_clocks_register(omap36xx_omap3430es2plus_clks
,
3621 ARRAY_SIZE(omap36xx_omap3430es2plus_clks
));
3622 omap_clocks_register(omap34xx_omap36xx_clks
,
3623 ARRAY_SIZE(omap34xx_omap36xx_clks
));
3624 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks
,
3625 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks
));
3626 omap_clocks_register(omap3xxx_clks
, ARRAY_SIZE(omap3xxx_clks
));
3627 } else if (soc_is_am33xx()) {
3628 cpu_mask
= RATE_IN_AM33XX
;
3629 } else if (cpu_is_ti814x()) {
3630 cpu_mask
= RATE_IN_TI814X
;
3631 } else if (cpu_is_omap34xx()) {
3632 if (omap_rev() == OMAP3430_REV_ES1_0
) {
3633 cpu_mask
= RATE_IN_3430ES1
;
3634 omap_clocks_register(omap3430es1_clks
,
3635 ARRAY_SIZE(omap3430es1_clks
));
3636 omap_clocks_register(omap34xx_omap36xx_clks
,
3637 ARRAY_SIZE(omap34xx_omap36xx_clks
));
3638 omap_clocks_register(omap3xxx_clks
,
3639 ARRAY_SIZE(omap3xxx_clks
));
3642 * Assume that anything that we haven't matched yet
3643 * has 3430ES2-type clocks.
3645 cpu_mask
= RATE_IN_3430ES2PLUS
;
3646 omap_clocks_register(omap34xx_omap36xx_clks
,
3647 ARRAY_SIZE(omap34xx_omap36xx_clks
));
3648 omap_clocks_register(omap36xx_omap3430es2plus_clks
,
3649 ARRAY_SIZE(omap36xx_omap3430es2plus_clks
));
3650 omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks
,
3651 ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks
));
3652 omap_clocks_register(omap3xxx_clks
,
3653 ARRAY_SIZE(omap3xxx_clks
));
3656 WARN(1, "clock: could not identify OMAP3 variant\n");
3659 omap2_clk_disable_autoidle_all();
3661 omap2_clk_enable_init_clocks(enable_init_clks
,
3662 ARRAY_SIZE(enable_init_clks
));
3664 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3665 (clk_get_rate(&osc_sys_ck
) / 1000000),
3666 (clk_get_rate(&osc_sys_ck
) / 100000) % 10,
3667 (clk_get_rate(&core_ck
) / 1000000),
3668 (clk_get_rate(&arm_fck
) / 1000000));
3671 * Lock DPLL5 -- here only until other device init code can
3674 if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0
))
3675 omap3_clk_lock_dpll5();
3677 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3678 sdrc_ick_p
= clk_get(NULL
, "sdrc_ick");
3679 arm_fck_p
= clk_get(NULL
, "arm_fck");