?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Remove all #inclusions of asm/system.h
[linux-2.6.git] / drivers / staging / comedi / drivers / cb_pcidas64.c
blob915157d47805562ef039c683d2279c185a786bc7
1 /*
2 comedi/drivers/cb_pcidas64.c
3 This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
4 64xx, 60xx, and 4020 cards.
5
6 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7 Copyright (C) 2001, 2002 Frank Mori Hess
8
9 Thanks also go to the following people:
10
11 Steve Rosenbluth, for providing the source code for
12 his pci-das6402 driver, and source code for working QNX pci-6402
13 drivers by Greg Laird and Mariusz Bogacz. None of the code was
14 used directly here, but it was useful as an additional source of
15 documentation on how to program the boards.
16
17 John Sims, for much testing and feedback on pcidas-4020 support.
18
19 COMEDI - Linux Control and Measurement Device Interface
20 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
21
22 This program is free software; you can redistribute it and/or modify
23 it under the terms of the GNU General Public License as published by
24 the Free Software Foundation; either version 2 of the License, or
25 (at your option) any later version.
26
27 This program is distributed in the hope that it will be useful,
28 but WITHOUT ANY WARRANTY; without even the implied warranty of
29 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 GNU General Public License for more details.
31
32 You should have received a copy of the GNU General Public License
33 along with this program; if not, write to the Free Software
34 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
35
36 ************************************************************************/
37
38 /*
39
40 Driver: cb_pcidas64
41 Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series with the PLX 9080 PCI controller
42 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
43 Status: works
44 Updated: 2002-10-09
45 Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
46 PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
47 PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
48 PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
49 PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
50 PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
51 PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
52 PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
53 PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
54
55 Configuration options:
56 [0] - PCI bus of device (optional)
57 [1] - PCI slot of device (optional)
58
59 These boards may be autocalibrated with the comedi_calibrate utility.
60
61 To select the bnc trigger input on the 4020 (instead of the dio input),
62 specify a nonzero channel in the chanspec. If you wish to use an external
63 master clock on the 4020, you may do so by setting the scan_begin_src
64 to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
65 to configure the divisor to use for the external clock.
66
67 Some devices are not identified because the PCI device IDs are not yet
68 known. If you have such a board, please file a bug report at
69 https://bugs.comedi.org.
70
71 */
72
73 /*
74
75 TODO:
76 make it return error if user attempts an ai command that uses the
77 external queue, and an ao command simultaneously
78 user counter subdevice
79 there are a number of boards this driver will support when they are
80 fully released, but does not yet since the pci device id numbers
81 are not yet available.
82 support prescaled 100khz clock for slow pacing (not available on 6000 series?)
83 make ao fifo size adjustable like ai fifo
84 */
85
86 #include "../comedidev.h"
87 #include <linux/delay.h>
88 #include <linux/interrupt.h>
89
90 #include "comedi_pci.h"
91 #include "8253.h"
92 #include "8255.h"
93 #include "plx9080.h"
94 #include "comedi_fc.h"
95
96 #undef PCIDAS64_DEBUG /* disable debugging code */
97 /* #define PCIDAS64_DEBUG enable debugging code */
98
99 #ifdef PCIDAS64_DEBUG
100 #define DEBUG_PRINT(format, args...) printk(format , ## args)
101 #else
102 #define DEBUG_PRINT(format, args...)
103 #endif
104
105 #define TIMER_BASE 25 /* 40MHz master clock */
106 #define PRESCALED_TIMER_BASE 10000 /* 100kHz 'prescaled' clock for slow acquisition, maybe I'll support this someday */
107 #define DMA_BUFFER_SIZE 0x1000
108
109 #define PCI_VENDOR_ID_COMPUTERBOARDS 0x1307
110
111 /* maximum value that can be loaded into board's 24-bit counters*/
112 static const int max_counter_value = 0xffffff;
113
114 /* PCI-DAS64xxx base addresses */
115
116 /* indices of base address regions */
117 enum base_address_regions {
118 PLX9080_BADDRINDEX = 0,
119 MAIN_BADDRINDEX = 2,
120 DIO_COUNTER_BADDRINDEX = 3,
121 };
122
123 /* priv(dev)->main_iobase registers */
124 enum write_only_registers {
125 INTR_ENABLE_REG = 0x0, /* interrupt enable register */
126 HW_CONFIG_REG = 0x2, /* hardware config register */
127 DAQ_SYNC_REG = 0xc,
128 DAQ_ATRIG_LOW_4020_REG = 0xc,
129 ADC_CONTROL0_REG = 0x10, /* adc control register 0 */
130 ADC_CONTROL1_REG = 0x12, /* adc control register 1 */
131 CALIBRATION_REG = 0x14,
132 ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16, /* lower 16 bits of adc sample interval counter */
133 ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18, /* upper 8 bits of adc sample interval counter */
134 ADC_DELAY_INTERVAL_LOWER_REG = 0x1a, /* lower 16 bits of delay interval counter */
135 ADC_DELAY_INTERVAL_UPPER_REG = 0x1c, /* upper 8 bits of delay interval counter */
136 ADC_COUNT_LOWER_REG = 0x1e, /* lower 16 bits of hardware conversion/scan counter */
137 ADC_COUNT_UPPER_REG = 0x20, /* upper 8 bits of hardware conversion/scan counter */
138 ADC_START_REG = 0x22, /* software trigger to start acquisition */
139 ADC_CONVERT_REG = 0x24, /* initiates single conversion */
140 ADC_QUEUE_CLEAR_REG = 0x26, /* clears adc queue */
141 ADC_QUEUE_LOAD_REG = 0x28, /* loads adc queue */
142 ADC_BUFFER_CLEAR_REG = 0x2a,
143 ADC_QUEUE_HIGH_REG = 0x2c, /* high channel for internal queue, use adc_chan_bits() inline above */
144 DAC_CONTROL0_REG = 0x50, /* dac control register 0 */
145 DAC_CONTROL1_REG = 0x52, /* dac control register 0 */
146 DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54, /* lower 16 bits of dac sample interval counter */
147 DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56, /* upper 8 bits of dac sample interval counter */
148 DAC_SELECT_REG = 0x60,
149 DAC_START_REG = 0x64,
150 DAC_BUFFER_CLEAR_REG = 0x66, /* clear dac buffer */
151 };
152 static inline unsigned int dac_convert_reg(unsigned int channel)
153 {
154 return 0x70 + (2 * (channel & 0x1));
155 }
156
157 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
158 {
159 return 0x70 + (4 * (channel & 0x1));
160 }
161
162 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
163 {
164 return 0x72 + (4 * (channel & 0x1));
165 }
166
167 enum read_only_registers {
168 HW_STATUS_REG = 0x0, /* hardware status register, reading this apparently clears pending interrupts as well */
169 PIPE1_READ_REG = 0x4,
170 ADC_READ_PNTR_REG = 0x8,
171 LOWER_XFER_REG = 0x10,
172 ADC_WRITE_PNTR_REG = 0xc,
173 PREPOST_REG = 0x14,
174 };
175
176 enum read_write_registers {
177 I8255_4020_REG = 0x48, /* 8255 offset, for 4020 only */
178 ADC_QUEUE_FIFO_REG = 0x100, /* external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
179 ADC_FIFO_REG = 0x200, /* adc data fifo */
180 DAC_FIFO_REG = 0x300, /* dac data fifo, has weird interactions with external channel queue */
181 };
182
183 /* priv(dev)->dio_counter_iobase registers */
184 enum dio_counter_registers {
185 DIO_8255_OFFSET = 0x0,
186 DO_REG = 0x20,
187 DI_REG = 0x28,
188 DIO_DIRECTION_60XX_REG = 0x40,
189 DIO_DATA_60XX_REG = 0x48,
190 };
191
192 /* bit definitions for write-only registers */
193
194 enum intr_enable_contents {
195 ADC_INTR_SRC_MASK = 0x3, /* bits that set adc interrupt source */
196 ADC_INTR_QFULL_BITS = 0x0, /* interrupt fifo quater full */
197 ADC_INTR_EOC_BITS = 0x1, /* interrupt end of conversion */
198 ADC_INTR_EOSCAN_BITS = 0x2, /* interrupt end of scan */
199 ADC_INTR_EOSEQ_BITS = 0x3, /* interrupt end of sequence (probably wont use this it's pretty fancy) */
200 EN_ADC_INTR_SRC_BIT = 0x4, /* enable adc interrupt source */
201 EN_ADC_DONE_INTR_BIT = 0x8, /* enable adc acquisition done interrupt */
202 DAC_INTR_SRC_MASK = 0x30,
203 DAC_INTR_QEMPTY_BITS = 0x0,
204 DAC_INTR_HIGH_CHAN_BITS = 0x10,
205 EN_DAC_INTR_SRC_BIT = 0x40, /* enable dac interrupt source */
206 EN_DAC_DONE_INTR_BIT = 0x80,
207 EN_ADC_ACTIVE_INTR_BIT = 0x200, /* enable adc active interrupt */
208 EN_ADC_STOP_INTR_BIT = 0x400, /* enable adc stop trigger interrupt */
209 EN_DAC_ACTIVE_INTR_BIT = 0x800, /* enable dac active interrupt */
210 EN_DAC_UNDERRUN_BIT = 0x4000, /* enable dac underrun status bit */
211 EN_ADC_OVERRUN_BIT = 0x8000, /* enable adc overrun status bit */
212 };
213
214 enum hw_config_contents {
215 MASTER_CLOCK_4020_MASK = 0x3, /* bits that specify master clock source for 4020 */
216 INTERNAL_CLOCK_4020_BITS = 0x1, /* use 40 MHz internal master clock for 4020 */
217 BNC_CLOCK_4020_BITS = 0x2, /* use BNC input for master clock */
218 EXT_CLOCK_4020_BITS = 0x3, /* use dio input for master clock */
219 EXT_QUEUE_BIT = 0x200, /* use external channel/gain queue (more versatile than internal queue) */
220 SLOW_DAC_BIT = 0x400, /* use 225 nanosec strobe when loading dac instead of 50 nanosec */
221 HW_CONFIG_DUMMY_BITS = 0x2000, /* bit with unknown function yet given as default value in pci-das64 manual */
222 DMA_CH_SELECT_BIT = 0x8000, /* bit selects channels 1/0 for analog input/output, otherwise 0/1 */
223 FIFO_SIZE_REG = 0x4, /* allows adjustment of fifo sizes */
224 DAC_FIFO_SIZE_MASK = 0xff00, /* bits that set dac fifo size */
225 DAC_FIFO_BITS = 0xf800, /* 8k sample ao fifo */
226 };
227 #define DAC_FIFO_SIZE 0x2000
228
229 enum daq_atrig_low_4020_contents {
230 EXT_AGATE_BNC_BIT = 0x8000, /* use trig/ext clk bnc input for analog gate signal */
231 EXT_STOP_TRIG_BNC_BIT = 0x4000, /* use trig/ext clk bnc input for external stop trigger signal */
232 EXT_START_TRIG_BNC_BIT = 0x2000, /* use trig/ext clk bnc input for external start trigger signal */
233 };
234 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
235 {
236 return threshold & 0xfff;
237 }
238
239 enum adc_control0_contents {
240 ADC_GATE_SRC_MASK = 0x3, /* bits that select gate */
241 ADC_SOFT_GATE_BITS = 0x1, /* software gate */
242 ADC_EXT_GATE_BITS = 0x2, /* external digital gate */
243 ADC_ANALOG_GATE_BITS = 0x3, /* analog level gate */
244 ADC_GATE_LEVEL_BIT = 0x4, /* level-sensitive gate (for digital) */
245 ADC_GATE_POLARITY_BIT = 0x8, /* gate active low */
246 ADC_START_TRIG_SOFT_BITS = 0x10,
247 ADC_START_TRIG_EXT_BITS = 0x20,
248 ADC_START_TRIG_ANALOG_BITS = 0x30,
249 ADC_START_TRIG_MASK = 0x30,
250 ADC_START_TRIG_FALLING_BIT = 0x40, /* trig 1 uses falling edge */
251 ADC_EXT_CONV_FALLING_BIT = 0x800, /* external pacing uses falling edge */
252 ADC_SAMPLE_COUNTER_EN_BIT = 0x1000, /* enable hardware scan counter */
253 ADC_DMA_DISABLE_BIT = 0x4000, /* disables dma */
254 ADC_ENABLE_BIT = 0x8000, /* master adc enable */
255 };
256
257 enum adc_control1_contents {
258 ADC_QUEUE_CONFIG_BIT = 0x1, /* should be set for boards with > 16 channels */
259 CONVERT_POLARITY_BIT = 0x10,
260 EOC_POLARITY_BIT = 0x20,
261 ADC_SW_GATE_BIT = 0x40, /* software gate of adc */
262 ADC_DITHER_BIT = 0x200, /* turn on extra noise for dithering */
263 RETRIGGER_BIT = 0x800,
264 ADC_LO_CHANNEL_4020_MASK = 0x300,
265 ADC_HI_CHANNEL_4020_MASK = 0xc00,
266 TWO_CHANNEL_4020_BITS = 0x1000, /* two channel mode for 4020 */
267 FOUR_CHANNEL_4020_BITS = 0x2000, /* four channel mode for 4020 */
268 CHANNEL_MODE_4020_MASK = 0x3000,
269 ADC_MODE_MASK = 0xf000,
270 };
271 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
272 {
273 return (channel & 0x3) << 8;
274 };
275
276 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
277 {
278 return (channel & 0x3) << 10;
279 };
280
281 static inline uint16_t adc_mode_bits(unsigned int mode)
282 {
283 return (mode & 0xf) << 12;
284 };
285
286 enum calibration_contents {
287 SELECT_8800_BIT = 0x1,
288 SELECT_8402_64XX_BIT = 0x2,
289 SELECT_1590_60XX_BIT = 0x2,
290 CAL_EN_64XX_BIT = 0x40, /* calibration enable for 64xx series */
291 SERIAL_DATA_IN_BIT = 0x80,
292 SERIAL_CLOCK_BIT = 0x100,
293 CAL_EN_60XX_BIT = 0x200, /* calibration enable for 60xx series */
294 CAL_GAIN_BIT = 0x800,
295 };
296 /* calibration sources for 6025 are:
297 * 0 : ground
298 * 1 : 10V
299 * 2 : 5V
300 * 3 : 0.5V
301 * 4 : 0.05V
302 * 5 : ground
303 * 6 : dac channel 0
304 * 7 : dac channel 1
305 */
306 static inline uint16_t adc_src_bits(unsigned int source)
307 {
308 return (source & 0xf) << 3;
309 };
310
311 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
312 {
313 return (channel & 0x3) << 8;
314 };
315
316 enum adc_queue_load_contents {
317 UNIP_BIT = 0x800, /* unipolar/bipolar bit */
318 ADC_SE_DIFF_BIT = 0x1000, /* single-ended/ differential bit */
319 ADC_COMMON_BIT = 0x2000, /* non-referenced single-ended (common-mode input) */
320 QUEUE_EOSEQ_BIT = 0x4000, /* queue end of sequence */
321 QUEUE_EOSCAN_BIT = 0x8000, /* queue end of scan */
322 };
323 static inline uint16_t adc_chan_bits(unsigned int channel)
324 {
325 return channel & 0x3f;
326 };
327
328 enum dac_control0_contents {
329 DAC_ENABLE_BIT = 0x8000, /* dac controller enable bit */
330 DAC_CYCLIC_STOP_BIT = 0x4000,
331 DAC_WAVEFORM_MODE_BIT = 0x100,
332 DAC_EXT_UPDATE_FALLING_BIT = 0x80,
333 DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
334 WAVEFORM_TRIG_MASK = 0x30,
335 WAVEFORM_TRIG_DISABLED_BITS = 0x0,
336 WAVEFORM_TRIG_SOFT_BITS = 0x10,
337 WAVEFORM_TRIG_EXT_BITS = 0x20,
338 WAVEFORM_TRIG_ADC1_BITS = 0x30,
339 WAVEFORM_TRIG_FALLING_BIT = 0x8,
340 WAVEFORM_GATE_LEVEL_BIT = 0x4,
341 WAVEFORM_GATE_ENABLE_BIT = 0x2,
342 WAVEFORM_GATE_SELECT_BIT = 0x1,
343 };
344
345 enum dac_control1_contents {
346 DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
347 DAC1_EXT_REF_BIT = 0x200,
348 DAC0_EXT_REF_BIT = 0x100,
349 DAC_OUTPUT_ENABLE_BIT = 0x80, /* dac output enable bit */
350 DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
351 DAC_SW_GATE_BIT = 0x20,
352 DAC1_UNIPOLAR_BIT = 0x8,
353 DAC0_UNIPOLAR_BIT = 0x2,
354 };
355
356 /* bit definitions for read-only registers */
357 enum hw_status_contents {
358 DAC_UNDERRUN_BIT = 0x1,
359 ADC_OVERRUN_BIT = 0x2,
360 DAC_ACTIVE_BIT = 0x4,
361 ADC_ACTIVE_BIT = 0x8,
362 DAC_INTR_PENDING_BIT = 0x10,
363 ADC_INTR_PENDING_BIT = 0x20,
364 DAC_DONE_BIT = 0x40,
365 ADC_DONE_BIT = 0x80,
366 EXT_INTR_PENDING_BIT = 0x100,
367 ADC_STOP_BIT = 0x200,
368 };
369 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
370 {
371 return (hw_status_bits >> 10) & 0x3;
372 };
373
374 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
375 {
376 return (prepost_bits >> 6) & 0x3;
377 }
378
379 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
380 {
381 return (prepost_bits >> 12) & 0x3;
382 }
383
384 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
385 {
386 return (prepost_bits >> 14) & 0x3;
387 }
388
389 /* I2C addresses for 4020 */
390 enum i2c_addresses {
391 RANGE_CAL_I2C_ADDR = 0x20,
392 CALDAC0_I2C_ADDR = 0xc,
393 CALDAC1_I2C_ADDR = 0xd,
394 };
395
396 enum range_cal_i2c_contents {
397 ADC_SRC_4020_MASK = 0x70, /* bits that set what source the adc converter measures */
398 BNC_TRIG_THRESHOLD_0V_BIT = 0x80, /* make bnc trig/ext clock threshold 0V instead of 2.5V */
399 };
400 static inline uint8_t adc_src_4020_bits(unsigned int source)
401 {
402 return (source << 4) & ADC_SRC_4020_MASK;
403 };
404
405 static inline uint8_t attenuate_bit(unsigned int channel)
406 {
407 /* attenuate channel (+-5V input range) */
408 return 1 << (channel & 0x3);
409 };
410
411 /* analog input ranges for 64xx boards */
412 static const struct comedi_lrange ai_ranges_64xx = {
413 8,
414 {
415 BIP_RANGE(10),
416 BIP_RANGE(5),
417 BIP_RANGE(2.5),
418 BIP_RANGE(1.25),
419 UNI_RANGE(10),
420 UNI_RANGE(5),
421 UNI_RANGE(2.5),
422 UNI_RANGE(1.25)
423 }
424 };
425
426 /* analog input ranges for 60xx boards */
427 static const struct comedi_lrange ai_ranges_60xx = {
428 4,
429 {
430 BIP_RANGE(10),
431 BIP_RANGE(5),
432 BIP_RANGE(0.5),
433 BIP_RANGE(0.05),
434 }
435 };
436
437 /* analog input ranges for 6030, etc boards */
438 static const struct comedi_lrange ai_ranges_6030 = {
439 14,
440 {
441 BIP_RANGE(10),
442 BIP_RANGE(5),
443 BIP_RANGE(2),
444 BIP_RANGE(1),
445 BIP_RANGE(0.5),
446 BIP_RANGE(0.2),
447 BIP_RANGE(0.1),
448 UNI_RANGE(10),
449 UNI_RANGE(5),
450 UNI_RANGE(2),
451 UNI_RANGE(1),
452 UNI_RANGE(0.5),
453 UNI_RANGE(0.2),
454 UNI_RANGE(0.1),
455 }
456 };
457
458 /* analog input ranges for 6052, etc boards */
459 static const struct comedi_lrange ai_ranges_6052 = {
460 15,
461 {
462 BIP_RANGE(10),
463 BIP_RANGE(5),
464 BIP_RANGE(2.5),
465 BIP_RANGE(1),
466 BIP_RANGE(0.5),
467 BIP_RANGE(0.25),
468 BIP_RANGE(0.1),
469 BIP_RANGE(0.05),
470 UNI_RANGE(10),
471 UNI_RANGE(5),
472 UNI_RANGE(2),
473 UNI_RANGE(1),
474 UNI_RANGE(0.5),
475 UNI_RANGE(0.2),
476 UNI_RANGE(0.1),
477 }
478 };
479
480 /* analog input ranges for 4020 board */
481 static const struct comedi_lrange ai_ranges_4020 = {
482 2,
483 {
484 BIP_RANGE(5),
485 BIP_RANGE(1),
486 }
487 };
488
489 /* analog output ranges */
490 static const struct comedi_lrange ao_ranges_64xx = {
491 4,
492 {
493 BIP_RANGE(5),
494 BIP_RANGE(10),
495 UNI_RANGE(5),
496 UNI_RANGE(10),
497 }
498 };
499
500 static const int ao_range_code_64xx[] = {
501 0x0,
502 0x1,
503 0x2,
504 0x3,
505 };
506
507 static const struct comedi_lrange ao_ranges_60xx = {
508 1,
509 {
510 BIP_RANGE(10),
511 }
512 };
513
514 static const int ao_range_code_60xx[] = {
515 0x0,
516 };
517
518 static const struct comedi_lrange ao_ranges_6030 = {
519 2,
520 {
521 BIP_RANGE(10),
522 UNI_RANGE(10),
523 }
524 };
525
526 static const int ao_range_code_6030[] = {
527 0x0,
528 0x2,
529 };
530
531 static const struct comedi_lrange ao_ranges_4020 = {
532 2,
533 {
534 BIP_RANGE(5),
535 BIP_RANGE(10),
536 }
537 };
538
539 static const int ao_range_code_4020[] = {
540 0x1,
541 0x0,
542 };
543
544 enum register_layout {
545 LAYOUT_60XX,
546 LAYOUT_64XX,
547 LAYOUT_4020,
548 };
549
550 struct hw_fifo_info {
551 unsigned int num_segments;
552 unsigned int max_segment_length;
553 unsigned int sample_packing_ratio;
554 uint16_t fifo_size_reg_mask;
555 };
556
557 struct pcidas64_board {
558 const char *name;
559 int device_id; /* pci device id */
560 int ai_se_chans; /* number of ai inputs in single-ended mode */
561 int ai_bits; /* analog input resolution */
562 int ai_speed; /* fastest conversion period in ns */
563 const struct comedi_lrange *ai_range_table;
564 int ao_nchan; /* number of analog out channels */
565 int ao_bits; /* analog output resolution */
566 int ao_scan_speed; /* analog output speed (for a scan, not conversion) */
567 const struct comedi_lrange *ao_range_table;
568 const int *ao_range_code;
569 const struct hw_fifo_info *const ai_fifo;
570 enum register_layout layout; /* different board families have slightly different registers */
571 unsigned has_8255:1;
572 };
573
574 static const struct hw_fifo_info ai_fifo_4020 = {
575 .num_segments = 2,
576 .max_segment_length = 0x8000,
577 .sample_packing_ratio = 2,
578 .fifo_size_reg_mask = 0x7f,
579 };
580
581 static const struct hw_fifo_info ai_fifo_64xx = {
582 .num_segments = 4,
583 .max_segment_length = 0x800,
584 .sample_packing_ratio = 1,
585 .fifo_size_reg_mask = 0x3f,
586 };
587
588 static const struct hw_fifo_info ai_fifo_60xx = {
589 .num_segments = 4,
590 .max_segment_length = 0x800,
591 .sample_packing_ratio = 1,
592 .fifo_size_reg_mask = 0x7f,
593 };
594
595 /* maximum number of dma transfers we will chain together into a ring
596 * (and the maximum number of dma buffers we maintain) */
597 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
598 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
599 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
600 static inline unsigned int ai_dma_ring_count(struct pcidas64_board *board)
601 {
602 if (board->layout == LAYOUT_4020)
603 return MAX_AI_DMA_RING_COUNT;
604 else
605 return MIN_AI_DMA_RING_COUNT;
606 }
607
608 static const int bytes_in_sample = 2;
609
610 static const struct pcidas64_board pcidas64_boards[] = {
611 {
612 .name = "pci-das6402/16",
613 .device_id = 0x1d,
614 .ai_se_chans = 64,
615 .ai_bits = 16,
616 .ai_speed = 5000,
617 .ao_nchan = 2,
618 .ao_bits = 16,
619 .ao_scan_speed = 10000,
620 .layout = LAYOUT_64XX,
621 .ai_range_table = &ai_ranges_64xx,
622 .ao_range_table = &ao_ranges_64xx,
623 .ao_range_code = ao_range_code_64xx,
624 .ai_fifo = &ai_fifo_64xx,
625 .has_8255 = 1,
626 },
627 {
628 .name = "pci-das6402/12", /* XXX check */
629 .device_id = 0x1e,
630 .ai_se_chans = 64,
631 .ai_bits = 12,
632 .ai_speed = 5000,
633 .ao_nchan = 2,
634 .ao_bits = 12,
635 .ao_scan_speed = 10000,
636 .layout = LAYOUT_64XX,
637 .ai_range_table = &ai_ranges_64xx,
638 .ao_range_table = &ao_ranges_64xx,
639 .ao_range_code = ao_range_code_64xx,
640 .ai_fifo = &ai_fifo_64xx,
641 .has_8255 = 1,
642 },
643 {
644 .name = "pci-das64/m1/16",
645 .device_id = 0x35,
646 .ai_se_chans = 64,
647 .ai_bits = 16,
648 .ai_speed = 1000,
649 .ao_nchan = 2,
650 .ao_bits = 16,
651 .ao_scan_speed = 10000,
652 .layout = LAYOUT_64XX,
653 .ai_range_table = &ai_ranges_64xx,
654 .ao_range_table = &ao_ranges_64xx,
655 .ao_range_code = ao_range_code_64xx,
656 .ai_fifo = &ai_fifo_64xx,
657 .has_8255 = 1,
658 },
659 {
660 .name = "pci-das64/m2/16",
661 .device_id = 0x36,
662 .ai_se_chans = 64,
663 .ai_bits = 16,
664 .ai_speed = 500,
665 .ao_nchan = 2,
666 .ao_bits = 16,
667 .ao_scan_speed = 10000,
668 .layout = LAYOUT_64XX,
669 .ai_range_table = &ai_ranges_64xx,
670 .ao_range_table = &ao_ranges_64xx,
671 .ao_range_code = ao_range_code_64xx,
672 .ai_fifo = &ai_fifo_64xx,
673 .has_8255 = 1,
674 },
675 {
676 .name = "pci-das64/m3/16",
677 .device_id = 0x37,
678 .ai_se_chans = 64,
679 .ai_bits = 16,
680 .ai_speed = 333,
681 .ao_nchan = 2,
682 .ao_bits = 16,
683 .ao_scan_speed = 10000,
684 .layout = LAYOUT_64XX,
685 .ai_range_table = &ai_ranges_64xx,
686 .ao_range_table = &ao_ranges_64xx,
687 .ao_range_code = ao_range_code_64xx,
688 .ai_fifo = &ai_fifo_64xx,
689 .has_8255 = 1,
690 },
691 {
692 .name = "pci-das6013",
693 .device_id = 0x78,
694 .ai_se_chans = 16,
695 .ai_bits = 16,
696 .ai_speed = 5000,
697 .ao_nchan = 0,
698 .ao_bits = 16,
699 .layout = LAYOUT_60XX,
700 .ai_range_table = &ai_ranges_60xx,
701 .ao_range_table = &ao_ranges_60xx,
702 .ao_range_code = ao_range_code_60xx,
703 .ai_fifo = &ai_fifo_60xx,
704 .has_8255 = 0,
705 },
706 {
707 .name = "pci-das6014",
708 .device_id = 0x79,
709 .ai_se_chans = 16,
710 .ai_bits = 16,
711 .ai_speed = 5000,
712 .ao_nchan = 2,
713 .ao_bits = 16,
714 .ao_scan_speed = 100000,
715 .layout = LAYOUT_60XX,
716 .ai_range_table = &ai_ranges_60xx,
717 .ao_range_table = &ao_ranges_60xx,
718 .ao_range_code = ao_range_code_60xx,
719 .ai_fifo = &ai_fifo_60xx,
720 .has_8255 = 0,
721 },
722 {
723 .name = "pci-das6023",
724 .device_id = 0x5d,
725 .ai_se_chans = 16,
726 .ai_bits = 12,
727 .ai_speed = 5000,
728 .ao_nchan = 0,
729 .ao_scan_speed = 100000,
730 .layout = LAYOUT_60XX,
731 .ai_range_table = &ai_ranges_60xx,
732 .ao_range_table = &ao_ranges_60xx,
733 .ao_range_code = ao_range_code_60xx,
734 .ai_fifo = &ai_fifo_60xx,
735 .has_8255 = 1,
736 },
737 {
738 .name = "pci-das6025",
739 .device_id = 0x5e,
740 .ai_se_chans = 16,
741 .ai_bits = 12,
742 .ai_speed = 5000,
743 .ao_nchan = 2,
744 .ao_bits = 12,
745 .ao_scan_speed = 100000,
746 .layout = LAYOUT_60XX,
747 .ai_range_table = &ai_ranges_60xx,
748 .ao_range_table = &ao_ranges_60xx,
749 .ao_range_code = ao_range_code_60xx,
750 .ai_fifo = &ai_fifo_60xx,
751 .has_8255 = 1,
752 },
753 {
754 .name = "pci-das6030",
755 .device_id = 0x5f,
756 .ai_se_chans = 16,
757 .ai_bits = 16,
758 .ai_speed = 10000,
759 .ao_nchan = 2,
760 .ao_bits = 16,
761 .ao_scan_speed = 10000,
762 .layout = LAYOUT_60XX,
763 .ai_range_table = &ai_ranges_6030,
764 .ao_range_table = &ao_ranges_6030,
765 .ao_range_code = ao_range_code_6030,
766 .ai_fifo = &ai_fifo_60xx,
767 .has_8255 = 0,
768 },
769 {
770 .name = "pci-das6031",
771 .device_id = 0x60,
772 .ai_se_chans = 64,
773 .ai_bits = 16,
774 .ai_speed = 10000,
775 .ao_nchan = 2,
776 .ao_bits = 16,
777 .ao_scan_speed = 10000,
778 .layout = LAYOUT_60XX,
779 .ai_range_table = &ai_ranges_6030,
780 .ao_range_table = &ao_ranges_6030,
781 .ao_range_code = ao_range_code_6030,
782 .ai_fifo = &ai_fifo_60xx,
783 .has_8255 = 0,
784 },
785 {
786 .name = "pci-das6032",
787 .device_id = 0x61,
788 .ai_se_chans = 16,
789 .ai_bits = 16,
790 .ai_speed = 10000,
791 .ao_nchan = 0,
792 .layout = LAYOUT_60XX,
793 .ai_range_table = &ai_ranges_6030,
794 .ai_fifo = &ai_fifo_60xx,
795 .has_8255 = 0,
796 },
797 {
798 .name = "pci-das6033",
799 .device_id = 0x62,
800 .ai_se_chans = 64,
801 .ai_bits = 16,
802 .ai_speed = 10000,
803 .ao_nchan = 0,
804 .layout = LAYOUT_60XX,
805 .ai_range_table = &ai_ranges_6030,
806 .ai_fifo = &ai_fifo_60xx,
807 .has_8255 = 0,
808 },
809 {
810 .name = "pci-das6034",
811 .device_id = 0x63,
812 .ai_se_chans = 16,
813 .ai_bits = 16,
814 .ai_speed = 5000,
815 .ao_nchan = 0,
816 .ao_scan_speed = 0,
817 .layout = LAYOUT_60XX,
818 .ai_range_table = &ai_ranges_60xx,
819 .ai_fifo = &ai_fifo_60xx,
820 .has_8255 = 0,
821 },
822 {
823 .name = "pci-das6035",
824 .device_id = 0x64,
825 .ai_se_chans = 16,
826 .ai_bits = 16,
827 .ai_speed = 5000,
828 .ao_nchan = 2,
829 .ao_bits = 12,
830 .ao_scan_speed = 100000,
831 .layout = LAYOUT_60XX,
832 .ai_range_table = &ai_ranges_60xx,
833 .ao_range_table = &ao_ranges_60xx,
834 .ao_range_code = ao_range_code_60xx,
835 .ai_fifo = &ai_fifo_60xx,
836 .has_8255 = 0,
837 },
838 {
839 .name = "pci-das6036",
840 .device_id = 0x6f,
841 .ai_se_chans = 16,
842 .ai_bits = 16,
843 .ai_speed = 5000,
844 .ao_nchan = 2,
845 .ao_bits = 16,
846 .ao_scan_speed = 100000,
847 .layout = LAYOUT_60XX,
848 .ai_range_table = &ai_ranges_60xx,
849 .ao_range_table = &ao_ranges_60xx,
850 .ao_range_code = ao_range_code_60xx,
851 .ai_fifo = &ai_fifo_60xx,
852 .has_8255 = 0,
853 },
854 {
855 .name = "pci-das6040",
856 .device_id = 0x65,
857 .ai_se_chans = 16,
858 .ai_bits = 12,
859 .ai_speed = 2000,
860 .ao_nchan = 2,
861 .ao_bits = 12,
862 .ao_scan_speed = 1000,
863 .layout = LAYOUT_60XX,
864 .ai_range_table = &ai_ranges_6052,
865 .ao_range_table = &ao_ranges_6030,
866 .ao_range_code = ao_range_code_6030,
867 .ai_fifo = &ai_fifo_60xx,
868 .has_8255 = 0,
869 },
870 {
871 .name = "pci-das6052",
872 .device_id = 0x66,
873 .ai_se_chans = 16,
874 .ai_bits = 16,
875 .ai_speed = 3333,
876 .ao_nchan = 2,
877 .ao_bits = 16,
878 .ao_scan_speed = 3333,
879 .layout = LAYOUT_60XX,
880 .ai_range_table = &ai_ranges_6052,
881 .ao_range_table = &ao_ranges_6030,
882 .ao_range_code = ao_range_code_6030,
883 .ai_fifo = &ai_fifo_60xx,
884 .has_8255 = 0,
885 },
886 {
887 .name = "pci-das6070",
888 .device_id = 0x67,
889 .ai_se_chans = 16,
890 .ai_bits = 12,
891 .ai_speed = 800,
892 .ao_nchan = 2,
893 .ao_bits = 12,
894 .ao_scan_speed = 1000,
895 .layout = LAYOUT_60XX,
896 .ai_range_table = &ai_ranges_6052,
897 .ao_range_table = &ao_ranges_6030,
898 .ao_range_code = ao_range_code_6030,
899 .ai_fifo = &ai_fifo_60xx,
900 .has_8255 = 0,
901 },
902 {
903 .name = "pci-das6071",
904 .device_id = 0x68,
905 .ai_se_chans = 64,
906 .ai_bits = 12,
907 .ai_speed = 800,
908 .ao_nchan = 2,
909 .ao_bits = 12,
910 .ao_scan_speed = 1000,
911 .layout = LAYOUT_60XX,
912 .ai_range_table = &ai_ranges_6052,
913 .ao_range_table = &ao_ranges_6030,
914 .ao_range_code = ao_range_code_6030,
915 .ai_fifo = &ai_fifo_60xx,
916 .has_8255 = 0,
917 },
918 {
919 .name = "pci-das4020/12",
920 .device_id = 0x52,
921 .ai_se_chans = 4,
922 .ai_bits = 12,
923 .ai_speed = 50,
924 .ao_bits = 12,
925 .ao_nchan = 2,
926 .ao_scan_speed = 0, /* no hardware pacing on ao */
927 .layout = LAYOUT_4020,
928 .ai_range_table = &ai_ranges_4020,
929 .ao_range_table = &ao_ranges_4020,
930 .ao_range_code = ao_range_code_4020,
931 .ai_fifo = &ai_fifo_4020,
932 .has_8255 = 1,
933 },
934 #if 0
935 {
936 .name = "pci-das6402/16/jr",
937 .device_id = 0 /* XXX, */
938 .ai_se_chans = 64,
939 .ai_bits = 16,
940 .ai_speed = 5000,
941 .ao_nchan = 0,
942 .ao_scan_speed = 10000,
943 .layout = LAYOUT_64XX,
944 .ai_range_table = &ai_ranges_64xx,
945 .ai_fifo = ai_fifo_64xx,
946 .has_8255 = 1,
947 },
948 {
949 .name = "pci-das64/m1/16/jr",
950 .device_id = 0 /* XXX, */
951 .ai_se_chans = 64,
952 .ai_bits = 16,
953 .ai_speed = 1000,
954 .ao_nchan = 0,
955 .ao_scan_speed = 10000,
956 .layout = LAYOUT_64XX,
957 .ai_range_table = &ai_ranges_64xx,
958 .ai_fifo = ai_fifo_64xx,
959 .has_8255 = 1,
960 },
961 {
962 .name = "pci-das64/m2/16/jr",
963 .device_id = 0 /* XXX, */
964 .ai_se_chans = 64,
965 .ai_bits = 16,
966 .ai_speed = 500,
967 .ao_nchan = 0,
968 .ao_scan_speed = 10000,
969 .layout = LAYOUT_64XX,
970 .ai_range_table = &ai_ranges_64xx,
971 .ai_fifo = ai_fifo_64xx,
972 .has_8255 = 1,
973 },
974 {
975 .name = "pci-das64/m3/16/jr",
976 .device_id = 0 /* XXX, */
977 .ai_se_chans = 64,
978 .ai_bits = 16,
979 .ai_speed = 333,
980 .ao_nchan = 0,
981 .ao_scan_speed = 10000,
982 .layout = LAYOUT_64XX,
983 .ai_range_table = &ai_ranges_64xx,
984 .ai_fifo = ai_fifo_64xx,
985 .has_8255 = 1,
986 },
987 {
988 .name = "pci-das64/m1/14",
989 .device_id = 0, /* XXX */
990 .ai_se_chans = 64,
991 .ai_bits = 14,
992 .ai_speed = 1000,
993 .ao_nchan = 2,
994 .ao_scan_speed = 10000,
995 .layout = LAYOUT_64XX,
996 .ai_range_table = &ai_ranges_64xx,
997 .ai_fifo = ai_fifo_64xx,
998 .has_8255 = 1,
999 },
1000 {
1001 .name = "pci-das64/m2/14",
1002 .device_id = 0, /* XXX */
1003 .ai_se_chans = 64,
1004 .ai_bits = 14,
1005 .ai_speed = 500,
1006 .ao_nchan = 2,
1007 .ao_scan_speed = 10000,
1008 .layout = LAYOUT_64XX,
1009 .ai_range_table = &ai_ranges_64xx,
1010 .ai_fifo = ai_fifo_64xx,
1011 .has_8255 = 1,
1012 },
1013 {
1014 .name = "pci-das64/m3/14",
1015 .device_id = 0, /* XXX */
1016 .ai_se_chans = 64,
1017 .ai_bits = 14,
1018 .ai_speed = 333,
1019 .ao_nchan = 2,
1020 .ao_scan_speed = 10000,
1021 .layout = LAYOUT_64XX,
1022 .ai_range_table = &ai_ranges_64xx,
1023 .ai_fifo = ai_fifo_64xx,
1024 .has_8255 = 1,
1025 },
1026 #endif
1027 };
1028
1029 static DEFINE_PCI_DEVICE_TABLE(pcidas64_pci_table) = {
1030 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x001d) },
1031 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x001e) },
1032 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0035) },
1033 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0036) },
1034 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0037) },
1035 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0052) },
1036 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x005d) },
1037 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x005e) },
1038 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x005f) },
1039 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0061) },
1040 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0062) },
1041 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0063) },
1042 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0064) },
1043 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0066) },
1044 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0067) },
1045 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0068) },
1046 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x006f) },
1047 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0078) },
1048 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0079) },
1049 { 0 }
1050 };
1051
1052 MODULE_DEVICE_TABLE(pci, pcidas64_pci_table);
1053
1054 static inline struct pcidas64_board *board(const struct comedi_device *dev)
1055 {
1056 return (struct pcidas64_board *)dev->board_ptr;
1057 }
1058
1059 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1060 int use_differential)
1061 {
1062 if ((board(dev)->layout == LAYOUT_64XX && !use_differential) ||
1063 (board(dev)->layout == LAYOUT_60XX && use_differential))
1064 return ADC_SE_DIFF_BIT;
1065 else
1066 return 0;
1067 };
1068
1069 struct ext_clock_info {
1070 unsigned int divisor; /* master clock divisor to use for scans with external master clock */
1071 unsigned int chanspec; /* chanspec for master clock input when used as scan begin src */
1072 };
1073
1074 /* this structure is for data unique to this hardware driver. */
1075 struct pcidas64_private {
1076
1077 struct pci_dev *hw_dev; /* pointer to board's pci_dev struct */
1078 /* base addresses (physical) */
1079 resource_size_t plx9080_phys_iobase;
1080 resource_size_t main_phys_iobase;
1081 resource_size_t dio_counter_phys_iobase;
1082 /* base addresses (ioremapped) */
1083 void __iomem *plx9080_iobase;
1084 void __iomem *main_iobase;
1085 void __iomem *dio_counter_iobase;
1086 /* local address (used by dma controller) */
1087 uint32_t local0_iobase;
1088 uint32_t local1_iobase;
1089 volatile unsigned int ai_count; /* number of analog input samples remaining */
1090 uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT]; /* dma buffers for analog input */
1091 dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT]; /* physical addresses of ai dma buffers */
1092 struct plx_dma_desc *ai_dma_desc; /* array of ai dma descriptors read by plx9080, allocated to get proper alignment */
1093 dma_addr_t ai_dma_desc_bus_addr; /* physical address of ai dma descriptor array */
1094 volatile unsigned int ai_dma_index; /* index of the ai dma descriptor/buffer that is currently being used */
1095 uint16_t *ao_buffer[AO_DMA_RING_COUNT]; /* dma buffers for analog output */
1096 dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT]; /* physical addresses of ao dma buffers */
1097 struct plx_dma_desc *ao_dma_desc;
1098 dma_addr_t ao_dma_desc_bus_addr;
1099 volatile unsigned int ao_dma_index; /* keeps track of buffer where the next ao sample should go */
1100 volatile unsigned long ao_count; /* number of analog output samples remaining */
1101 volatile unsigned int ao_value[2]; /* remember what the analog outputs are set to, to allow readback */
1102 unsigned int hw_revision; /* stc chip hardware revision number */
1103 volatile unsigned int intr_enable_bits; /* last bits sent to INTR_ENABLE_REG register */
1104 volatile uint16_t adc_control1_bits; /* last bits sent to ADC_CONTROL1_REG register */
1105 volatile uint16_t fifo_size_bits; /* last bits sent to FIFO_SIZE_REG register */
1106 volatile uint16_t hw_config_bits; /* last bits sent to HW_CONFIG_REG register */
1107 volatile uint16_t dac_control1_bits;
1108 volatile uint32_t plx_control_bits; /* last bits written to plx9080 control register */
1109 volatile uint32_t plx_intcsr_bits; /* last bits written to plx interrupt control and status register */
1110 volatile int calibration_source; /* index of calibration source readable through ai ch0 */
1111 volatile uint8_t i2c_cal_range_bits; /* bits written to i2c calibration/range register */
1112 volatile unsigned int ext_trig_falling; /* configure digital triggers to trigger on falling edge */
1113 /* states of various devices stored to enable read-back */
1114 unsigned int ad8402_state[2];
1115 unsigned int caldac_state[8];
1116 volatile short ai_cmd_running;
1117 unsigned int ai_fifo_segment_length;
1118 struct ext_clock_info ext_clock;
1119 short ao_bounce_buffer[DAC_FIFO_SIZE];
1120 };
1121
1122 /* inline function that makes it easier to
1123 * access the private structure.
1124 */
1125 static inline struct pcidas64_private *priv(struct comedi_device *dev)
1126 {
1127 return dev->private;
1128 }
1129
1130 /*
1131 * The comedi_driver structure tells the Comedi core module
1132 * which functions to call to configure/deconfigure (attach/detach)
1133 * the board, and also about the kernel module that contains
1134 * the device code.
1135 */
1136 static int attach(struct comedi_device *dev, struct comedi_devconfig *it);
1137 static int detach(struct comedi_device *dev);
1138 static struct comedi_driver driver_cb_pcidas = {
1139 .driver_name = "cb_pcidas64",
1140 .module = THIS_MODULE,
1141 .attach = attach,
1142 .detach = detach,
1143 };
1144
1145 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1146 struct comedi_insn *insn, unsigned int *data);
1147 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1148 struct comedi_insn *insn, unsigned int *data);
1149 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
1150 struct comedi_insn *insn, unsigned int *data);
1151 static int ao_readback_insn(struct comedi_device *dev,
1152 struct comedi_subdevice *s,
1153 struct comedi_insn *insn, unsigned int *data);
1154 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
1155 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
1156 struct comedi_cmd *cmd);
1157 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
1158 static int ao_inttrig(struct comedi_device *dev,
1159 struct comedi_subdevice *subdev, unsigned int trig_num);
1160 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
1161 struct comedi_cmd *cmd);
1162 static irqreturn_t handle_interrupt(int irq, void *d);
1163 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
1164 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
1165 static int dio_callback(int dir, int port, int data, unsigned long arg);
1166 static int dio_callback_4020(int dir, int port, int data, unsigned long arg);
1167 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
1168 struct comedi_insn *insn, unsigned int *data);
1169 static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
1170 struct comedi_insn *insn, unsigned int *data);
1171 static int dio_60xx_config_insn(struct comedi_device *dev,
1172 struct comedi_subdevice *s,
1173 struct comedi_insn *insn, unsigned int *data);
1174 static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
1175 struct comedi_insn *insn, unsigned int *data);
1176 static int calib_read_insn(struct comedi_device *dev,
1177 struct comedi_subdevice *s, struct comedi_insn *insn,
1178 unsigned int *data);
1179 static int calib_write_insn(struct comedi_device *dev,
1180 struct comedi_subdevice *s,
1181 struct comedi_insn *insn, unsigned int *data);
1182 static int ad8402_read_insn(struct comedi_device *dev,
1183 struct comedi_subdevice *s,
1184 struct comedi_insn *insn, unsigned int *data);
1185 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
1186 unsigned int value);
1187 static int ad8402_write_insn(struct comedi_device *dev,
1188 struct comedi_subdevice *s,
1189 struct comedi_insn *insn, unsigned int *data);
1190 static int eeprom_read_insn(struct comedi_device *dev,
1191 struct comedi_subdevice *s,
1192 struct comedi_insn *insn, unsigned int *data);
1193 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd);
1194 static unsigned int get_divisor(unsigned int ns, unsigned int flags);
1195 static void i2c_write(struct comedi_device *dev, unsigned int address,
1196 const uint8_t * data, unsigned int length);
1197 static void caldac_write(struct comedi_device *dev, unsigned int channel,
1198 unsigned int value);
1199 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
1200 uint8_t value);
1201 /* static int dac_1590_write(struct comedi_device *dev, unsigned int dac_a, unsigned int dac_b); */
1202 static int caldac_i2c_write(struct comedi_device *dev,
1203 unsigned int caldac_channel, unsigned int value);
1204 static void abort_dma(struct comedi_device *dev, unsigned int channel);
1205 static void disable_plx_interrupts(struct comedi_device *dev);
1206 static int set_ai_fifo_size(struct comedi_device *dev,
1207 unsigned int num_samples);
1208 static unsigned int ai_fifo_size(struct comedi_device *dev);
1209 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1210 unsigned int num_entries);
1211 static void disable_ai_pacing(struct comedi_device *dev);
1212 static void disable_ai_interrupts(struct comedi_device *dev);
1213 static void enable_ai_interrupts(struct comedi_device *dev,
1214 const struct comedi_cmd *cmd);
1215 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags);
1216 static void load_ao_dma(struct comedi_device *dev,
1217 const struct comedi_cmd *cmd);
1218
1219 static int __devinit driver_cb_pcidas_pci_probe(struct pci_dev *dev,
1220 const struct pci_device_id *ent)
1221 {
1222 return comedi_pci_auto_config(dev, driver_cb_pcidas.driver_name);
1223 }
1224
1225 static void __devexit driver_cb_pcidas_pci_remove(struct pci_dev *dev)
1226 {
1227 comedi_pci_auto_unconfig(dev);
1228 }
1229
1230 static struct pci_driver driver_cb_pcidas_pci_driver = {
1231 .id_table = pcidas64_pci_table,
1232 .probe = &driver_cb_pcidas_pci_probe,
1233 .remove = __devexit_p(&driver_cb_pcidas_pci_remove)
1234 };
1235
1236 static int __init driver_cb_pcidas_init_module(void)
1237 {
1238 int retval;
1239
1240 retval = comedi_driver_register(&driver_cb_pcidas);
1241 if (retval < 0)
1242 return retval;
1243
1244 driver_cb_pcidas_pci_driver.name = (char *)driver_cb_pcidas.driver_name;
1245 return pci_register_driver(&driver_cb_pcidas_pci_driver);
1246 }
1247
1248 static void __exit driver_cb_pcidas_cleanup_module(void)
1249 {
1250 pci_unregister_driver(&driver_cb_pcidas_pci_driver);
1251 comedi_driver_unregister(&driver_cb_pcidas);
1252 }
1253
1254 module_init(driver_cb_pcidas_init_module);
1255 module_exit(driver_cb_pcidas_cleanup_module);
1256
1257 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1258 unsigned int range_index)
1259 {
1260 const struct comedi_krange *range =
1261 &board(dev)->ai_range_table->range[range_index];
1262 unsigned int bits = 0;
1263
1264 switch (range->max) {
1265 case 10000000:
1266 bits = 0x000;
1267 break;
1268 case 5000000:
1269 bits = 0x100;
1270 break;
1271 case 2000000:
1272 case 2500000:
1273 bits = 0x200;
1274 break;
1275 case 1000000:
1276 case 1250000:
1277 bits = 0x300;
1278 break;
1279 case 500000:
1280 bits = 0x400;
1281 break;
1282 case 200000:
1283 case 250000:
1284 bits = 0x500;
1285 break;
1286 case 100000:
1287 bits = 0x600;
1288 break;
1289 case 50000:
1290 bits = 0x700;
1291 break;
1292 default:
1293 comedi_error(dev, "bug! in ai_range_bits_6xxx");
1294 break;
1295 }
1296 if (range->min == 0)
1297 bits += 0x900;
1298 return bits;
1299 }
1300
1301 static unsigned int hw_revision(const struct comedi_device *dev,
1302 uint16_t hw_status_bits)
1303 {
1304 if (board(dev)->layout == LAYOUT_4020)
1305 return (hw_status_bits >> 13) & 0x7;
1306
1307 return (hw_status_bits >> 12) & 0xf;
1308 }
1309
1310 static void set_dac_range_bits(struct comedi_device *dev,
1311 volatile uint16_t * bits, unsigned int channel,
1312 unsigned int range)
1313 {
1314 unsigned int code = board(dev)->ao_range_code[range];
1315
1316 if (channel > 1)
1317 comedi_error(dev, "bug! bad channel?");
1318 if (code & ~0x3)
1319 comedi_error(dev, "bug! bad range code?");
1320
1321 *bits &= ~(0x3 << (2 * channel));
1322 *bits |= code << (2 * channel);
1323 };
1324
1325 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1326 {
1327 return board->ao_nchan && board->layout != LAYOUT_4020;
1328 }
1329
1330 /* initialize plx9080 chip */
1331 static void init_plx9080(struct comedi_device *dev)
1332 {
1333 uint32_t bits;
1334 void __iomem *plx_iobase = priv(dev)->plx9080_iobase;
1335
1336 priv(dev)->plx_control_bits =
1337 readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG);
1338
1339 /* plx9080 dump */
1340 DEBUG_PRINT(" plx interrupt status 0x%x\n",
1341 readl(plx_iobase + PLX_INTRCS_REG));
1342 DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
1343 DEBUG_PRINT(" plx control reg 0x%x\n", priv(dev)->plx_control_bits);
1344 DEBUG_PRINT(" plx mode/arbitration reg 0x%x\n",
1345 readl(plx_iobase + PLX_MARB_REG));
1346 DEBUG_PRINT(" plx region0 reg 0x%x\n",
1347 readl(plx_iobase + PLX_REGION0_REG));
1348 DEBUG_PRINT(" plx region1 reg 0x%x\n",
1349 readl(plx_iobase + PLX_REGION1_REG));
1350
1351 DEBUG_PRINT(" plx revision 0x%x\n",
1352 readl(plx_iobase + PLX_REVISION_REG));
1353 DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
1354 readl(plx_iobase + PLX_DMA0_MODE_REG));
1355 DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
1356 readl(plx_iobase + PLX_DMA1_MODE_REG));
1357 DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
1358 readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
1359 DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
1360 readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
1361 DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
1362 readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
1363 DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
1364 readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
1365 DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
1366 readb(plx_iobase + PLX_DMA0_CS_REG));
1367 DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
1368 readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
1369 DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
1370
1371 #ifdef __BIG_ENDIAN
1372 bits = BIGEND_DMA0 | BIGEND_DMA1;
1373 #else
1374 bits = 0;
1375 #endif
1376 writel(bits, priv(dev)->plx9080_iobase + PLX_BIGEND_REG);
1377
1378 disable_plx_interrupts(dev);
1379
1380 abort_dma(dev, 0);
1381 abort_dma(dev, 1);
1382
1383 /* configure dma0 mode */
1384 bits = 0;
1385 /* enable ready input, not sure if this is necessary */
1386 bits |= PLX_DMA_EN_READYIN_BIT;
1387 /* enable bterm, not sure if this is necessary */
1388 bits |= PLX_EN_BTERM_BIT;
1389 /* enable dma chaining */
1390 bits |= PLX_EN_CHAIN_BIT;
1391 /* enable interrupt on dma done (probably don't need this, since chain never finishes) */
1392 bits |= PLX_EN_DMA_DONE_INTR_BIT;
1393 /* don't increment local address during transfers (we are transferring from a fixed fifo register) */
1394 bits |= PLX_LOCAL_ADDR_CONST_BIT;
1395 /* route dma interrupt to pci bus */
1396 bits |= PLX_DMA_INTR_PCI_BIT;
1397 /* enable demand mode */
1398 bits |= PLX_DEMAND_MODE_BIT;
1399 /* enable local burst mode */
1400 bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1401 /* 4020 uses 32 bit dma */
1402 if (board(dev)->layout == LAYOUT_4020) {
1403 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1404 } else { /* localspace0 bus is 16 bits wide */
1405 bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1406 }
1407 writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1408 if (ao_cmd_is_supported(board(dev)))
1409 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1410
1411 /* enable interrupts on plx 9080 */
1412 priv(dev)->plx_intcsr_bits |=
1413 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1414 ICS_DMA0_E | ICS_DMA1_E;
1415 writel(priv(dev)->plx_intcsr_bits,
1416 priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
1417 }
1418
1419 /* Allocate and initialize the subdevice structures.
1420 */
1421 static int setup_subdevices(struct comedi_device *dev)
1422 {
1423 struct comedi_subdevice *s;
1424 void __iomem *dio_8255_iobase;
1425 int i;
1426
1427 if (alloc_subdevices(dev, 10) < 0)
1428 return -ENOMEM;
1429
1430 s = dev->subdevices + 0;
1431 /* analog input subdevice */
1432 dev->read_subdev = s;
1433 s->type = COMEDI_SUBD_AI;
1434 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
1435 if (board(dev)->layout == LAYOUT_60XX)
1436 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
1437 else if (board(dev)->layout == LAYOUT_64XX)
1438 s->subdev_flags |= SDF_DIFF;
1439 /* XXX Number of inputs in differential mode is ignored */
1440 s->n_chan = board(dev)->ai_se_chans;
1441 s->len_chanlist = 0x2000;
1442 s->maxdata = (1 << board(dev)->ai_bits) - 1;
1443 s->range_table = board(dev)->ai_range_table;
1444 s->insn_read = ai_rinsn;
1445 s->insn_config = ai_config_insn;
1446 s->do_cmd = ai_cmd;
1447 s->do_cmdtest = ai_cmdtest;
1448 s->cancel = ai_cancel;
1449 if (board(dev)->layout == LAYOUT_4020) {
1450 uint8_t data;
1451 /* set adc to read from inputs (not internal calibration sources) */
1452 priv(dev)->i2c_cal_range_bits = adc_src_4020_bits(4);
1453 /* set channels to +-5 volt input ranges */
1454 for (i = 0; i < s->n_chan; i++)
1455 priv(dev)->i2c_cal_range_bits |= attenuate_bit(i);
1456 data = priv(dev)->i2c_cal_range_bits;
1457 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
1458 }
1459
1460 /* analog output subdevice */
1461 s = dev->subdevices + 1;
1462 if (board(dev)->ao_nchan) {
1463 s->type = COMEDI_SUBD_AO;
1464 s->subdev_flags =
1465 SDF_READABLE | SDF_WRITABLE | SDF_GROUND | SDF_CMD_WRITE;
1466 s->n_chan = board(dev)->ao_nchan;
1467 s->maxdata = (1 << board(dev)->ao_bits) - 1;
1468 s->range_table = board(dev)->ao_range_table;
1469 s->insn_read = ao_readback_insn;
1470 s->insn_write = ao_winsn;
1471 if (ao_cmd_is_supported(board(dev))) {
1472 dev->write_subdev = s;
1473 s->do_cmdtest = ao_cmdtest;
1474 s->do_cmd = ao_cmd;
1475 s->len_chanlist = board(dev)->ao_nchan;
1476 s->cancel = ao_cancel;
1477 }
1478 } else {
1479 s->type = COMEDI_SUBD_UNUSED;
1480 }
1481
1482 /* digital input */
1483 s = dev->subdevices + 2;
1484 if (board(dev)->layout == LAYOUT_64XX) {
1485 s->type = COMEDI_SUBD_DI;
1486 s->subdev_flags = SDF_READABLE;
1487 s->n_chan = 4;
1488 s->maxdata = 1;
1489 s->range_table = &range_digital;
1490 s->insn_bits = di_rbits;
1491 } else
1492 s->type = COMEDI_SUBD_UNUSED;
1493
1494 /* digital output */
1495 if (board(dev)->layout == LAYOUT_64XX) {
1496 s = dev->subdevices + 3;
1497 s->type = COMEDI_SUBD_DO;
1498 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1499 s->n_chan = 4;
1500 s->maxdata = 1;
1501 s->range_table = &range_digital;
1502 s->insn_bits = do_wbits;
1503 } else
1504 s->type = COMEDI_SUBD_UNUSED;
1505
1506 /* 8255 */
1507 s = dev->subdevices + 4;
1508 if (board(dev)->has_8255) {
1509 if (board(dev)->layout == LAYOUT_4020) {
1510 dio_8255_iobase =
1511 priv(dev)->main_iobase + I8255_4020_REG;
1512 subdev_8255_init(dev, s, dio_callback_4020,
1513 (unsigned long)dio_8255_iobase);
1514 } else {
1515 dio_8255_iobase =
1516 priv(dev)->dio_counter_iobase + DIO_8255_OFFSET;
1517 subdev_8255_init(dev, s, dio_callback,
1518 (unsigned long)dio_8255_iobase);
1519 }
1520 } else
1521 s->type = COMEDI_SUBD_UNUSED;
1522
1523 /* 8 channel dio for 60xx */
1524 s = dev->subdevices + 5;
1525 if (board(dev)->layout == LAYOUT_60XX) {
1526 s->type = COMEDI_SUBD_DIO;
1527 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1528 s->n_chan = 8;
1529 s->maxdata = 1;
1530 s->range_table = &range_digital;
1531 s->insn_config = dio_60xx_config_insn;
1532 s->insn_bits = dio_60xx_wbits;
1533 } else
1534 s->type = COMEDI_SUBD_UNUSED;
1535
1536 /* caldac */
1537 s = dev->subdevices + 6;
1538 s->type = COMEDI_SUBD_CALIB;
1539 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
1540 s->n_chan = 8;
1541 if (board(dev)->layout == LAYOUT_4020)
1542 s->maxdata = 0xfff;
1543 else
1544 s->maxdata = 0xff;
1545 s->insn_read = calib_read_insn;
1546 s->insn_write = calib_write_insn;
1547 for (i = 0; i < s->n_chan; i++)
1548 caldac_write(dev, i, s->maxdata / 2);
1549
1550 /* 2 channel ad8402 potentiometer */
1551 s = dev->subdevices + 7;
1552 if (board(dev)->layout == LAYOUT_64XX) {
1553 s->type = COMEDI_SUBD_CALIB;
1554 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
1555 s->n_chan = 2;
1556 s->insn_read = ad8402_read_insn;
1557 s->insn_write = ad8402_write_insn;
1558 s->maxdata = 0xff;
1559 for (i = 0; i < s->n_chan; i++)
1560 ad8402_write(dev, i, s->maxdata / 2);
1561 } else
1562 s->type = COMEDI_SUBD_UNUSED;
1563
1564 /* serial EEPROM, if present */
1565 s = dev->subdevices + 8;
1566 if (readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
1567 s->type = COMEDI_SUBD_MEMORY;
1568 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
1569 s->n_chan = 128;
1570 s->maxdata = 0xffff;
1571 s->insn_read = eeprom_read_insn;
1572 } else
1573 s->type = COMEDI_SUBD_UNUSED;
1574
1575 /* user counter subd XXX */
1576 s = dev->subdevices + 9;
1577 s->type = COMEDI_SUBD_UNUSED;
1578
1579 return 0;
1580 }
1581
1582 static void disable_plx_interrupts(struct comedi_device *dev)
1583 {
1584 priv(dev)->plx_intcsr_bits = 0;
1585 writel(priv(dev)->plx_intcsr_bits,
1586 priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
1587 }
1588
1589 static void init_stc_registers(struct comedi_device *dev)
1590 {
1591 uint16_t bits;
1592 unsigned long flags;
1593
1594 spin_lock_irqsave(&dev->spinlock, flags);
1595
1596 /* bit should be set for 6025, although docs say boards with <= 16 chans should be cleared XXX */
1597 if (1)
1598 priv(dev)->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1599 writew(priv(dev)->adc_control1_bits,
1600 priv(dev)->main_iobase + ADC_CONTROL1_REG);
1601
1602 /* 6402/16 manual says this register must be initialized to 0xff? */
1603 writew(0xff, priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1604
1605 bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1606 if (board(dev)->layout == LAYOUT_4020)
1607 bits |= INTERNAL_CLOCK_4020_BITS;
1608 priv(dev)->hw_config_bits |= bits;
1609 writew(priv(dev)->hw_config_bits,
1610 priv(dev)->main_iobase + HW_CONFIG_REG);
1611
1612 writew(0, priv(dev)->main_iobase + DAQ_SYNC_REG);
1613 writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
1614
1615 spin_unlock_irqrestore(&dev->spinlock, flags);
1616
1617 /* set fifos to maximum size */
1618 priv(dev)->fifo_size_bits |= DAC_FIFO_BITS;
1619 set_ai_fifo_segment_length(dev,
1620 board(dev)->ai_fifo->max_segment_length);
1621
1622 priv(dev)->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1623 priv(dev)->intr_enable_bits = /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1624 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1625 writew(priv(dev)->intr_enable_bits,
1626 priv(dev)->main_iobase + INTR_ENABLE_REG);
1627
1628 disable_ai_pacing(dev);
1629 };
1630
1631 static int alloc_and_init_dma_members(struct comedi_device *dev)
1632 {
1633 int i;
1634
1635 /* alocate pci dma buffers */
1636 for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1637 priv(dev)->ai_buffer[i] =
1638 pci_alloc_consistent(priv(dev)->hw_dev, DMA_BUFFER_SIZE,
1639 &priv(dev)->ai_buffer_bus_addr[i]);
1640 if (priv(dev)->ai_buffer[i] == NULL)
1641 return -ENOMEM;
1642
1643 }
1644 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1645 if (ao_cmd_is_supported(board(dev))) {
1646 priv(dev)->ao_buffer[i] =
1647 pci_alloc_consistent(priv(dev)->hw_dev,
1648 DMA_BUFFER_SIZE,
1649 &priv(dev)->
1650 ao_buffer_bus_addr[i]);
1651 if (priv(dev)->ao_buffer[i] == NULL)
1652 return -ENOMEM;
1653
1654 }
1655 }
1656 /* allocate dma descriptors */
1657 priv(dev)->ai_dma_desc =
1658 pci_alloc_consistent(priv(dev)->hw_dev,
1659 sizeof(struct plx_dma_desc) *
1660 ai_dma_ring_count(board(dev)),
1661 &priv(dev)->ai_dma_desc_bus_addr);
1662 if (priv(dev)->ai_dma_desc == NULL)
1663 return -ENOMEM;
1664
1665 DEBUG_PRINT("ai dma descriptors start at bus addr 0x%x\n",
1666 priv(dev)->ai_dma_desc_bus_addr);
1667 if (ao_cmd_is_supported(board(dev))) {
1668 priv(dev)->ao_dma_desc =
1669 pci_alloc_consistent(priv(dev)->hw_dev,
1670 sizeof(struct plx_dma_desc) *
1671 AO_DMA_RING_COUNT,
1672 &priv(dev)->ao_dma_desc_bus_addr);
1673 if (priv(dev)->ao_dma_desc == NULL)
1674 return -ENOMEM;
1675
1676 DEBUG_PRINT("ao dma descriptors start at bus addr 0x%x\n",
1677 priv(dev)->ao_dma_desc_bus_addr);
1678 }
1679 /* initialize dma descriptors */
1680 for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1681 priv(dev)->ai_dma_desc[i].pci_start_addr =
1682 cpu_to_le32(priv(dev)->ai_buffer_bus_addr[i]);
1683 if (board(dev)->layout == LAYOUT_4020)
1684 priv(dev)->ai_dma_desc[i].local_start_addr =
1685 cpu_to_le32(priv(dev)->local1_iobase +
1686 ADC_FIFO_REG);
1687 else
1688 priv(dev)->ai_dma_desc[i].local_start_addr =
1689 cpu_to_le32(priv(dev)->local0_iobase +
1690 ADC_FIFO_REG);
1691 priv(dev)->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1692 priv(dev)->ai_dma_desc[i].next =
1693 cpu_to_le32((priv(dev)->ai_dma_desc_bus_addr + ((i +
1694 1) %
1695 ai_dma_ring_count
1696 (board
1697 (dev))) *
1698 sizeof(priv(dev)->ai_dma_desc[0])) |
1699 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
1700 PLX_XFER_LOCAL_TO_PCI);
1701 }
1702 if (ao_cmd_is_supported(board(dev))) {
1703 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1704 priv(dev)->ao_dma_desc[i].pci_start_addr =
1705 cpu_to_le32(priv(dev)->ao_buffer_bus_addr[i]);
1706 priv(dev)->ao_dma_desc[i].local_start_addr =
1707 cpu_to_le32(priv(dev)->local0_iobase +
1708 DAC_FIFO_REG);
1709 priv(dev)->ao_dma_desc[i].transfer_size =
1710 cpu_to_le32(0);
1711 priv(dev)->ao_dma_desc[i].next =
1712 cpu_to_le32((priv(dev)->ao_dma_desc_bus_addr +
1713 ((i + 1) % (AO_DMA_RING_COUNT)) *
1714 sizeof(priv(dev)->ao_dma_desc[0])) |
1715 PLX_DESC_IN_PCI_BIT |
1716 PLX_INTR_TERM_COUNT);
1717 }
1718 }
1719 return 0;
1720 }
1721
1722 static inline void warn_external_queue(struct comedi_device *dev)
1723 {
1724 comedi_error(dev,
1725 "AO command and AI external channel queue cannot be used simultaneously.");
1726 comedi_error(dev,
1727 "Use internal AI channel queue (channels must be consecutive and use same range/aref)");
1728 }
1729
1730 /*
1731 * Attach is called by the Comedi core to configure the driver
1732 * for a particular board.
1733 */
1734 static int attach(struct comedi_device *dev, struct comedi_devconfig *it)
1735 {
1736 struct pci_dev *pcidev = NULL;
1737 int index;
1738 uint32_t local_range, local_decode;
1739 int retval;
1740
1741 /*
1742 * Allocate the private structure area.
1743 */
1744 if (alloc_private(dev, sizeof(struct pcidas64_private)) < 0)
1745 return -ENOMEM;
1746
1747 /*
1748 * Probe the device to determine what device in the series it is.
1749 */
1750
1751 for_each_pci_dev(pcidev) {
1752 /* is it not a computer boards card? */
1753 if (pcidev->vendor != PCI_VENDOR_ID_COMPUTERBOARDS)
1754 continue;
1755 /* loop through cards supported by this driver */
1756 for (index = 0; index < ARRAY_SIZE(pcidas64_boards); index++) {
1757 if (pcidas64_boards[index].device_id != pcidev->device)
1758 continue;
1759 /* was a particular bus/slot requested? */
1760 if (it->options[0] || it->options[1]) {
1761 /* are we on the wrong bus/slot? */
1762 if (pcidev->bus->number != it->options[0] ||
1763 PCI_SLOT(pcidev->devfn) != it->options[1]) {
1764 continue;
1765 }
1766 }
1767 priv(dev)->hw_dev = pcidev;
1768 dev->board_ptr = pcidas64_boards + index;
1769 break;
1770 }
1771 if (dev->board_ptr)
1772 break;
1773 }
1774
1775 if (dev->board_ptr == NULL) {
1776 printk
1777 ("No supported ComputerBoards/MeasurementComputing card found\n");
1778 return -EIO;
1779 }
1780
1781 dev_dbg(dev->hw_dev, "Found %s on bus %i, slot %i\n", board(dev)->name,
1782 pcidev->bus->number, PCI_SLOT(pcidev->devfn));
1783
1784 if (comedi_pci_enable(pcidev, driver_cb_pcidas.driver_name)) {
1785 dev_warn(dev->hw_dev, "failed to enable PCI device and request regions\n");
1786 return -EIO;
1787 }
1788 pci_set_master(pcidev);
1789
1790 /* Initialize dev->board_name */
1791 dev->board_name = board(dev)->name;
1792
1793 priv(dev)->plx9080_phys_iobase =
1794 pci_resource_start(pcidev, PLX9080_BADDRINDEX);
1795 priv(dev)->main_phys_iobase =
1796 pci_resource_start(pcidev, MAIN_BADDRINDEX);
1797 priv(dev)->dio_counter_phys_iobase =
1798 pci_resource_start(pcidev, DIO_COUNTER_BADDRINDEX);
1799
1800 /* remap, won't work with 2.0 kernels but who cares */
1801 priv(dev)->plx9080_iobase = ioremap(priv(dev)->plx9080_phys_iobase,
1802 pci_resource_len(pcidev,
1803 PLX9080_BADDRINDEX));
1804 priv(dev)->main_iobase =
1805 ioremap(priv(dev)->main_phys_iobase,
1806 pci_resource_len(pcidev, MAIN_BADDRINDEX));
1807 priv(dev)->dio_counter_iobase =
1808 ioremap(priv(dev)->dio_counter_phys_iobase,
1809 pci_resource_len(pcidev, DIO_COUNTER_BADDRINDEX));
1810
1811 if (!priv(dev)->plx9080_iobase || !priv(dev)->main_iobase
1812 || !priv(dev)->dio_counter_iobase) {
1813 dev_warn(dev->hw_dev, "failed to remap io memory\n");
1814 return -ENOMEM;
1815 }
1816
1817 DEBUG_PRINT(" plx9080 remapped to 0x%p\n", priv(dev)->plx9080_iobase);
1818 DEBUG_PRINT(" main remapped to 0x%p\n", priv(dev)->main_iobase);
1819 DEBUG_PRINT(" diocounter remapped to 0x%p\n",
1820 priv(dev)->dio_counter_iobase);
1821
1822 /* figure out what local addresses are */
1823 local_range =
1824 readl(priv(dev)->plx9080_iobase + PLX_LAS0RNG_REG) & LRNG_MEM_MASK;
1825 local_decode =
1826 readl(priv(dev)->plx9080_iobase +
1827 PLX_LAS0MAP_REG) & local_range & LMAP_MEM_MASK;
1828 priv(dev)->local0_iobase =
1829 ((uint32_t) priv(dev)->main_phys_iobase & ~local_range) |
1830 local_decode;
1831 local_range =
1832 readl(priv(dev)->plx9080_iobase + PLX_LAS1RNG_REG) & LRNG_MEM_MASK;
1833 local_decode =
1834 readl(priv(dev)->plx9080_iobase +
1835 PLX_LAS1MAP_REG) & local_range & LMAP_MEM_MASK;
1836 priv(dev)->local1_iobase =
1837 ((uint32_t) priv(dev)->dio_counter_phys_iobase & ~local_range) |
1838 local_decode;
1839
1840 DEBUG_PRINT(" local 0 io addr 0x%x\n", priv(dev)->local0_iobase);
1841 DEBUG_PRINT(" local 1 io addr 0x%x\n", priv(dev)->local1_iobase);
1842
1843 retval = alloc_and_init_dma_members(dev);
1844 if (retval < 0)
1845 return retval;
1846
1847 priv(dev)->hw_revision =
1848 hw_revision(dev, readw(priv(dev)->main_iobase + HW_STATUS_REG));
1849 dev_dbg(dev->hw_dev, "stc hardware revision %i\n",
1850 priv(dev)->hw_revision);
1851 init_plx9080(dev);
1852 init_stc_registers(dev);
1853 /* get irq */
1854 if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
1855 "cb_pcidas64", dev)) {
1856 dev_dbg(dev->hw_dev, "unable to allocate irq %u\n",
1857 pcidev->irq);
1858 return -EINVAL;
1859 }
1860 dev->irq = pcidev->irq;
1861 dev_dbg(dev->hw_dev, "irq %u\n", dev->irq);
1862
1863 retval = setup_subdevices(dev);
1864 if (retval < 0)
1865 return retval;
1866
1867
1868 return 0;
1869 }
1870
1871 /*
1872 * _detach is called to deconfigure a device. It should deallocate
1873 * resources.
1874 * This function is also called when _attach() fails, so it should be
1875 * careful not to release resources that were not necessarily
1876 * allocated by _attach(). dev->private and dev->subdevices are
1877 * deallocated automatically by the core.
1878 */
1879 static int detach(struct comedi_device *dev)
1880 {
1881 unsigned int i;
1882
1883 if (dev->irq)
1884 free_irq(dev->irq, dev);
1885 if (priv(dev)) {
1886 if (priv(dev)->hw_dev) {
1887 if (priv(dev)->plx9080_iobase) {
1888 disable_plx_interrupts(dev);
1889 iounmap(priv(dev)->plx9080_iobase);
1890 }
1891 if (priv(dev)->main_iobase)
1892 iounmap(priv(dev)->main_iobase);
1893 if (priv(dev)->dio_counter_iobase)
1894 iounmap(priv(dev)->dio_counter_iobase);
1895 /* free pci dma buffers */
1896 for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1897 if (priv(dev)->ai_buffer[i])
1898 pci_free_consistent(priv(dev)->hw_dev,
1899 DMA_BUFFER_SIZE,
1900 priv(dev)->
1901 ai_buffer[i],
1902 priv
1903 (dev)->ai_buffer_bus_addr
1904 [i]);
1905 }
1906 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1907 if (priv(dev)->ao_buffer[i])
1908 pci_free_consistent(priv(dev)->hw_dev,
1909 DMA_BUFFER_SIZE,
1910 priv(dev)->
1911 ao_buffer[i],
1912 priv
1913 (dev)->ao_buffer_bus_addr
1914 [i]);
1915 }
1916 /* free dma descriptors */
1917 if (priv(dev)->ai_dma_desc)
1918 pci_free_consistent(priv(dev)->hw_dev,
1919 sizeof(struct plx_dma_desc)
1920 *
1921 ai_dma_ring_count(board
1922 (dev)),
1923 priv(dev)->ai_dma_desc,
1924 priv(dev)->
1925 ai_dma_desc_bus_addr);
1926 if (priv(dev)->ao_dma_desc)
1927 pci_free_consistent(priv(dev)->hw_dev,
1928 sizeof(struct plx_dma_desc)
1929 * AO_DMA_RING_COUNT,
1930 priv(dev)->ao_dma_desc,
1931 priv(dev)->
1932 ao_dma_desc_bus_addr);
1933 if (priv(dev)->main_phys_iobase)
1934 comedi_pci_disable(priv(dev)->hw_dev);
1935
1936 pci_dev_put(priv(dev)->hw_dev);
1937 }
1938 }
1939 if (dev->subdevices)
1940 subdev_8255_cleanup(dev, dev->subdevices + 4);
1941
1942 return 0;
1943 }
1944
1945 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1946 struct comedi_insn *insn, unsigned int *data)
1947 {
1948 unsigned int bits = 0, n, i;
1949 unsigned int channel, range, aref;
1950 unsigned long flags;
1951 static const int timeout = 100;
1952
1953 DEBUG_PRINT("chanspec 0x%x\n", insn->chanspec);
1954 channel = CR_CHAN(insn->chanspec);
1955 range = CR_RANGE(insn->chanspec);
1956 aref = CR_AREF(insn->chanspec);
1957
1958 /* disable card's analog input interrupt sources and pacing */
1959 /* 4020 generates dac done interrupts even though they are disabled */
1960 disable_ai_pacing(dev);
1961
1962 spin_lock_irqsave(&dev->spinlock, flags);
1963 if (insn->chanspec & CR_ALT_FILTER)
1964 priv(dev)->adc_control1_bits |= ADC_DITHER_BIT;
1965 else
1966 priv(dev)->adc_control1_bits &= ~ADC_DITHER_BIT;
1967 writew(priv(dev)->adc_control1_bits,
1968 priv(dev)->main_iobase + ADC_CONTROL1_REG);
1969 spin_unlock_irqrestore(&dev->spinlock, flags);
1970
1971 if (board(dev)->layout != LAYOUT_4020) {
1972 /* use internal queue */
1973 priv(dev)->hw_config_bits &= ~EXT_QUEUE_BIT;
1974 writew(priv(dev)->hw_config_bits,
1975 priv(dev)->main_iobase + HW_CONFIG_REG);
1976
1977 /* ALT_SOURCE is internal calibration reference */
1978 if (insn->chanspec & CR_ALT_SOURCE) {
1979 unsigned int cal_en_bit;
1980
1981 DEBUG_PRINT("reading calibration source\n");
1982 if (board(dev)->layout == LAYOUT_60XX)
1983 cal_en_bit = CAL_EN_60XX_BIT;
1984 else
1985 cal_en_bit = CAL_EN_64XX_BIT;
1986 /* select internal reference source to connect to channel 0 */
1987 writew(cal_en_bit |
1988 adc_src_bits(priv(dev)->calibration_source),
1989 priv(dev)->main_iobase + CALIBRATION_REG);
1990 } else {
1991 /* make sure internal calibration source is turned off */
1992 writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
1993 }
1994 /* load internal queue */
1995 bits = 0;
1996 /* set gain */
1997 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1998 /* set single-ended / differential */
1999 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
2000 if (aref == AREF_COMMON)
2001 bits |= ADC_COMMON_BIT;
2002 bits |= adc_chan_bits(channel);
2003 /* set stop channel */
2004 writew(adc_chan_bits(channel),
2005 priv(dev)->main_iobase + ADC_QUEUE_HIGH_REG);
2006 /* set start channel, and rest of settings */
2007 writew(bits, priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
2008 } else {
2009 uint8_t old_cal_range_bits = priv(dev)->i2c_cal_range_bits;
2010
2011 priv(dev)->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2012 if (insn->chanspec & CR_ALT_SOURCE) {
2013 DEBUG_PRINT("reading calibration source\n");
2014 priv(dev)->i2c_cal_range_bits |=
2015 adc_src_4020_bits(priv(dev)->calibration_source);
2016 } else { /* select BNC inputs */
2017 priv(dev)->i2c_cal_range_bits |= adc_src_4020_bits(4);
2018 }
2019 /* select range */
2020 if (range == 0)
2021 priv(dev)->i2c_cal_range_bits |= attenuate_bit(channel);
2022 else
2023 priv(dev)->i2c_cal_range_bits &=
2024 ~attenuate_bit(channel);
2025 /* update calibration/range i2c register only if necessary, as it is very slow */
2026 if (old_cal_range_bits != priv(dev)->i2c_cal_range_bits) {
2027 uint8_t i2c_data = priv(dev)->i2c_cal_range_bits;
2028 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2029 sizeof(i2c_data));
2030 }
2031
2032 /* 4020 manual asks that sample interval register to be set before writing to convert register.
2033 * Using somewhat arbitrary setting of 4 master clock ticks = 0.1 usec */
2034 writew(0,
2035 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2036 writew(2,
2037 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2038 }
2039
2040 for (n = 0; n < insn->n; n++) {
2041
2042 /* clear adc buffer (inside loop for 4020 sake) */
2043 writew(0, priv(dev)->main_iobase + ADC_BUFFER_CLEAR_REG);
2044
2045 /* trigger conversion, bits sent only matter for 4020 */
2046 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
2047 priv(dev)->main_iobase + ADC_CONVERT_REG);
2048
2049 /* wait for data */
2050 for (i = 0; i < timeout; i++) {
2051 bits = readw(priv(dev)->main_iobase + HW_STATUS_REG);
2052 DEBUG_PRINT(" pipe bits 0x%x\n", pipe_full_bits(bits));
2053 if (board(dev)->layout == LAYOUT_4020) {
2054 if (readw(priv(dev)->main_iobase +
2055 ADC_WRITE_PNTR_REG))
2056 break;
2057 } else {
2058 if (pipe_full_bits(bits))
2059 break;
2060 }
2061 udelay(1);
2062 }
2063 DEBUG_PRINT(" looped %i times waiting for data\n", i);
2064 if (i == timeout) {
2065 comedi_error(dev, " analog input read insn timed out");
2066 printk(" status 0x%x\n", bits);
2067 return -ETIME;
2068 }
2069 if (board(dev)->layout == LAYOUT_4020)
2070 data[n] =
2071 readl(priv(dev)->dio_counter_iobase +
2072 ADC_FIFO_REG) & 0xffff;
2073 else
2074 data[n] =
2075 readw(priv(dev)->main_iobase + PIPE1_READ_REG);
2076 }
2077
2078 return n;
2079 }
2080
2081 static int ai_config_calibration_source(struct comedi_device *dev,
2082 unsigned int *data)
2083 {
2084 unsigned int source = data[1];
2085 int num_calibration_sources;
2086
2087 if (board(dev)->layout == LAYOUT_60XX)
2088 num_calibration_sources = 16;
2089 else
2090 num_calibration_sources = 8;
2091 if (source >= num_calibration_sources) {
2092 dev_dbg(dev->hw_dev, "invalid calibration source: %i\n",
2093 source);
2094 return -EINVAL;
2095 }
2096
2097 DEBUG_PRINT("setting calibration source to %i\n", source);
2098 priv(dev)->calibration_source = source;
2099
2100 return 2;
2101 }
2102
2103 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
2104 {
2105 int fifo_size;
2106 const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
2107 unsigned int block_size, requested_block_size;
2108 int retval;
2109
2110 requested_block_size = data[1];
2111
2112 if (requested_block_size) {
2113 fifo_size =
2114 requested_block_size * fifo->num_segments / bytes_in_sample;
2115
2116 retval = set_ai_fifo_size(dev, fifo_size);
2117 if (retval < 0)
2118 return retval;
2119
2120 }
2121
2122 block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
2123
2124 data[1] = block_size;
2125
2126 return 2;
2127 }
2128
2129 static int ai_config_master_clock_4020(struct comedi_device *dev,
2130 unsigned int *data)
2131 {
2132 unsigned int divisor = data[4];
2133 int retval = 0;
2134
2135 if (divisor < 2) {
2136 divisor = 2;
2137 retval = -EAGAIN;
2138 }
2139
2140 switch (data[1]) {
2141 case COMEDI_EV_SCAN_BEGIN:
2142 priv(dev)->ext_clock.divisor = divisor;
2143 priv(dev)->ext_clock.chanspec = data[2];
2144 break;
2145 default:
2146 return -EINVAL;
2147 break;
2148 }
2149
2150 data[4] = divisor;
2151
2152 return retval ? retval : 5;
2153 }
2154
2155 /* XXX could add support for 60xx series */
2156 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
2157 {
2158
2159 switch (board(dev)->layout) {
2160 case LAYOUT_4020:
2161 return ai_config_master_clock_4020(dev, data);
2162 break;
2163 default:
2164 return -EINVAL;
2165 break;
2166 }
2167
2168 return -EINVAL;
2169 }
2170
2171 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
2172 struct comedi_insn *insn, unsigned int *data)
2173 {
2174 int id = data[0];
2175
2176 switch (id) {
2177 case INSN_CONFIG_ALT_SOURCE:
2178 return ai_config_calibration_source(dev, data);
2179 break;
2180 case INSN_CONFIG_BLOCK_SIZE:
2181 return ai_config_block_size(dev, data);
2182 break;
2183 case INSN_CONFIG_TIMER_1:
2184 return ai_config_master_clock(dev, data);
2185 break;
2186 default:
2187 return -EINVAL;
2188 break;
2189 }
2190 return -EINVAL;
2191 }
2192
2193 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2194 struct comedi_cmd *cmd)
2195 {
2196 int err = 0;
2197 int tmp;
2198 unsigned int tmp_arg, tmp_arg2;
2199 int i;
2200 int aref;
2201 unsigned int triggers;
2202
2203 /* step 1: make sure trigger sources are trivially valid */
2204
2205 tmp = cmd->start_src;
2206 cmd->start_src &= TRIG_NOW | TRIG_EXT;
2207 if (!cmd->start_src || tmp != cmd->start_src)
2208 err++;
2209
2210 tmp = cmd->scan_begin_src;
2211 triggers = TRIG_TIMER;
2212 if (board(dev)->layout == LAYOUT_4020)
2213 triggers |= TRIG_OTHER;
2214 else
2215 triggers |= TRIG_FOLLOW;
2216 cmd->scan_begin_src &= triggers;
2217 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
2218 err++;
2219
2220 tmp = cmd->convert_src;
2221 triggers = TRIG_TIMER;
2222 if (board(dev)->layout == LAYOUT_4020)
2223 triggers |= TRIG_NOW;
2224 else
2225 triggers |= TRIG_EXT;
2226 cmd->convert_src &= triggers;
2227 if (!cmd->convert_src || tmp != cmd->convert_src)
2228 err++;
2229
2230 tmp = cmd->scan_end_src;
2231 cmd->scan_end_src &= TRIG_COUNT;
2232 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
2233 err++;
2234
2235 tmp = cmd->stop_src;
2236 cmd->stop_src &= TRIG_COUNT | TRIG_EXT | TRIG_NONE;
2237 if (!cmd->stop_src || tmp != cmd->stop_src)
2238 err++;
2239
2240 if (err)
2241 return 1;
2242
2243 /* step 2: make sure trigger sources are unique and mutually compatible */
2244
2245 /* uniqueness check */
2246 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT)
2247 err++;
2248 if (cmd->scan_begin_src != TRIG_TIMER &&
2249 cmd->scan_begin_src != TRIG_OTHER &&
2250 cmd->scan_begin_src != TRIG_FOLLOW)
2251 err++;
2252 if (cmd->convert_src != TRIG_TIMER &&
2253 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW)
2254 err++;
2255 if (cmd->stop_src != TRIG_COUNT &&
2256 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
2257 err++;
2258
2259 /* compatibility check */
2260 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2261 err++;
2262 if (cmd->stop_src != TRIG_COUNT &&
2263 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
2264 err++;
2265
2266 if (err)
2267 return 2;
2268
2269 /* step 3: make sure arguments are trivially compatible */
2270
2271 if (cmd->convert_src == TRIG_TIMER) {
2272 if (board(dev)->layout == LAYOUT_4020) {
2273 if (cmd->convert_arg) {
2274 cmd->convert_arg = 0;
2275 err++;
2276 }
2277 } else {
2278 if (cmd->convert_arg < board(dev)->ai_speed) {
2279 cmd->convert_arg = board(dev)->ai_speed;
2280 err++;
2281 }
2282 if (cmd->scan_begin_src == TRIG_TIMER) {
2283 /* if scans are timed faster than conversion rate allows */
2284 if (cmd->convert_arg * cmd->chanlist_len >
2285 cmd->scan_begin_arg) {
2286 cmd->scan_begin_arg =
2287 cmd->convert_arg *
2288 cmd->chanlist_len;
2289 err++;
2290 }
2291 }
2292 }
2293 }
2294
2295 if (!cmd->chanlist_len) {
2296 cmd->chanlist_len = 1;
2297 err++;
2298 }
2299 if (cmd->scan_end_arg != cmd->chanlist_len) {
2300 cmd->scan_end_arg = cmd->chanlist_len;
2301 err++;
2302 }
2303
2304 switch (cmd->stop_src) {
2305 case TRIG_EXT:
2306 break;
2307 case TRIG_COUNT:
2308 if (!cmd->stop_arg) {
2309 cmd->stop_arg = 1;
2310 err++;
2311 }
2312 break;
2313 case TRIG_NONE:
2314 if (cmd->stop_arg != 0) {
2315 cmd->stop_arg = 0;
2316 err++;
2317 }
2318 break;
2319 default:
2320 break;
2321 }
2322
2323 if (err)
2324 return 3;
2325
2326 /* step 4: fix up any arguments */
2327
2328 if (cmd->convert_src == TRIG_TIMER) {
2329 tmp_arg = cmd->convert_arg;
2330 tmp_arg2 = cmd->scan_begin_arg;
2331 check_adc_timing(dev, cmd);
2332 if (tmp_arg != cmd->convert_arg)
2333 err++;
2334 if (tmp_arg2 != cmd->scan_begin_arg)
2335 err++;
2336 }
2337
2338 if (err)
2339 return 4;
2340
2341 /* make sure user is doesn't change analog reference mid chanlist */
2342 if (cmd->chanlist) {
2343 aref = CR_AREF(cmd->chanlist[0]);
2344 for (i = 1; i < cmd->chanlist_len; i++) {
2345 if (aref != CR_AREF(cmd->chanlist[i])) {
2346 comedi_error(dev,
2347 "all elements in chanlist must use the same analog reference");
2348 err++;
2349 break;
2350 }
2351 }
2352 /* check 4020 chanlist */
2353 if (board(dev)->layout == LAYOUT_4020) {
2354 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
2355 for (i = 1; i < cmd->chanlist_len; i++) {
2356 if (CR_CHAN(cmd->chanlist[i]) !=
2357 first_channel + i) {
2358 comedi_error(dev,
2359 "chanlist must use consecutive channels");
2360 err++;
2361 break;
2362 }
2363 }
2364 if (cmd->chanlist_len == 3) {
2365 comedi_error(dev,
2366 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels");
2367 err++;
2368 }
2369 }
2370 }
2371
2372 if (err)
2373 return 5;
2374
2375 return 0;
2376 }
2377
2378 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2379 {
2380 /* disable for now until I work out a race */
2381 return 0;
2382
2383 if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2384 return 1;
2385 else
2386 return 0;
2387 }
2388
2389 static void setup_sample_counters(struct comedi_device *dev,
2390 struct comedi_cmd *cmd)
2391 {
2392 if (cmd->stop_src == TRIG_COUNT) {
2393 /* set software count */
2394 priv(dev)->ai_count = cmd->stop_arg * cmd->chanlist_len;
2395 }
2396 /* load hardware conversion counter */
2397 if (use_hw_sample_counter(cmd)) {
2398 writew(cmd->stop_arg & 0xffff,
2399 priv(dev)->main_iobase + ADC_COUNT_LOWER_REG);
2400 writew((cmd->stop_arg >> 16) & 0xff,
2401 priv(dev)->main_iobase + ADC_COUNT_UPPER_REG);
2402 } else {
2403 writew(1, priv(dev)->main_iobase + ADC_COUNT_LOWER_REG);
2404 }
2405 }
2406
2407 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2408 {
2409 unsigned int num_samples;
2410
2411 num_samples =
2412 priv(dev)->ai_fifo_segment_length *
2413 board(dev)->ai_fifo->sample_packing_ratio;
2414 if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2415 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2416
2417 return num_samples;
2418 }
2419
2420 static void disable_ai_pacing(struct comedi_device *dev)
2421 {
2422 unsigned long flags;
2423
2424 disable_ai_interrupts(dev);
2425
2426 spin_lock_irqsave(&dev->spinlock, flags);
2427 priv(dev)->adc_control1_bits &= ~ADC_SW_GATE_BIT;
2428 writew(priv(dev)->adc_control1_bits,
2429 priv(dev)->main_iobase + ADC_CONTROL1_REG);
2430 spin_unlock_irqrestore(&dev->spinlock, flags);
2431
2432 /* disable pacing, triggering, etc */
2433 writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
2434 priv(dev)->main_iobase + ADC_CONTROL0_REG);
2435 }
2436
2437 static void disable_ai_interrupts(struct comedi_device *dev)
2438 {
2439 unsigned long flags;
2440
2441 spin_lock_irqsave(&dev->spinlock, flags);
2442 priv(dev)->intr_enable_bits &=
2443 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
2444 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
2445 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
2446 writew(priv(dev)->intr_enable_bits,
2447 priv(dev)->main_iobase + INTR_ENABLE_REG);
2448 spin_unlock_irqrestore(&dev->spinlock, flags);
2449
2450 DEBUG_PRINT("intr enable bits 0x%x\n", priv(dev)->intr_enable_bits);
2451 }
2452
2453 static void enable_ai_interrupts(struct comedi_device *dev,
2454 const struct comedi_cmd *cmd)
2455 {
2456 uint32_t bits;
2457 unsigned long flags;
2458
2459 bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
2460 EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
2461 /* Use pio transfer and interrupt on end of conversion if TRIG_WAKE_EOS flag is set. */
2462 if (cmd->flags & TRIG_WAKE_EOS) {
2463 /* 4020 doesn't support pio transfers except for fifo dregs */
2464 if (board(dev)->layout != LAYOUT_4020)
2465 bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
2466 }
2467 spin_lock_irqsave(&dev->spinlock, flags);
2468 priv(dev)->intr_enable_bits |= bits;
2469 writew(priv(dev)->intr_enable_bits,
2470 priv(dev)->main_iobase + INTR_ENABLE_REG);
2471 DEBUG_PRINT("intr enable bits 0x%x\n", priv(dev)->intr_enable_bits);
2472 spin_unlock_irqrestore(&dev->spinlock, flags);
2473 }
2474
2475 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2476 const struct comedi_cmd *cmd)
2477 {
2478 /* supposed to load counter with desired divisor minus 3 */
2479 return cmd->convert_arg / TIMER_BASE - 3;
2480 }
2481
2482 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2483 struct comedi_cmd *cmd)
2484 {
2485 uint32_t count;
2486 /* figure out how long we need to delay at end of scan */
2487 switch (cmd->scan_begin_src) {
2488 case TRIG_TIMER:
2489 count = (cmd->scan_begin_arg -
2490 (cmd->convert_arg * (cmd->chanlist_len - 1)))
2491 / TIMER_BASE;
2492 break;
2493 case TRIG_FOLLOW:
2494 count = cmd->convert_arg / TIMER_BASE;
2495 break;
2496 default:
2497 return 0;
2498 break;
2499 }
2500 return count - 3;
2501 }
2502
2503 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2504 struct comedi_cmd *cmd)
2505 {
2506 unsigned int divisor;
2507
2508 switch (cmd->scan_begin_src) {
2509 case TRIG_TIMER:
2510 divisor = cmd->scan_begin_arg / TIMER_BASE;
2511 break;
2512 case TRIG_OTHER:
2513 divisor = priv(dev)->ext_clock.divisor;
2514 break;
2515 default: /* should never happen */
2516 comedi_error(dev, "bug! failed to set ai pacing!");
2517 divisor = 1000;
2518 break;
2519 }
2520
2521 /* supposed to load counter with desired divisor minus 2 for 4020 */
2522 return divisor - 2;
2523 }
2524
2525 static void select_master_clock_4020(struct comedi_device *dev,
2526 const struct comedi_cmd *cmd)
2527 {
2528 /* select internal/external master clock */
2529 priv(dev)->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2530 if (cmd->scan_begin_src == TRIG_OTHER) {
2531 int chanspec = priv(dev)->ext_clock.chanspec;
2532
2533 if (CR_CHAN(chanspec))
2534 priv(dev)->hw_config_bits |= BNC_CLOCK_4020_BITS;
2535 else
2536 priv(dev)->hw_config_bits |= EXT_CLOCK_4020_BITS;
2537 } else {
2538 priv(dev)->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2539 }
2540 writew(priv(dev)->hw_config_bits,
2541 priv(dev)->main_iobase + HW_CONFIG_REG);
2542 }
2543
2544 static void select_master_clock(struct comedi_device *dev,
2545 const struct comedi_cmd *cmd)
2546 {
2547 switch (board(dev)->layout) {
2548 case LAYOUT_4020:
2549 select_master_clock_4020(dev, cmd);
2550 break;
2551 default:
2552 break;
2553 }
2554 }
2555
2556 static inline void dma_start_sync(struct comedi_device *dev,
2557 unsigned int channel)
2558 {
2559 unsigned long flags;
2560
2561 /* spinlock for plx dma control/status reg */
2562 spin_lock_irqsave(&dev->spinlock, flags);
2563 if (channel)
2564 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2565 PLX_CLEAR_DMA_INTR_BIT,
2566 priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
2567 else
2568 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2569 PLX_CLEAR_DMA_INTR_BIT,
2570 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
2571 spin_unlock_irqrestore(&dev->spinlock, flags);
2572 }
2573
2574 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2575 {
2576 uint32_t convert_counter = 0, scan_counter = 0;
2577
2578 check_adc_timing(dev, cmd);
2579
2580 select_master_clock(dev, cmd);
2581
2582 if (board(dev)->layout == LAYOUT_4020) {
2583 convert_counter = ai_convert_counter_4020(dev, cmd);
2584 } else {
2585 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2586 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2587 }
2588
2589 /* load lower 16 bits of convert interval */
2590 writew(convert_counter & 0xffff,
2591 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2592 DEBUG_PRINT("convert counter 0x%x\n", convert_counter);
2593 /* load upper 8 bits of convert interval */
2594 writew((convert_counter >> 16) & 0xff,
2595 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2596 /* load lower 16 bits of scan delay */
2597 writew(scan_counter & 0xffff,
2598 priv(dev)->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2599 /* load upper 8 bits of scan delay */
2600 writew((scan_counter >> 16) & 0xff,
2601 priv(dev)->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2602 DEBUG_PRINT("scan counter 0x%x\n", scan_counter);
2603 }
2604
2605 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2606 {
2607 int i;
2608 for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2609 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2610 CR_CHAN(cmd->chanlist[i]) + 1)
2611 return 0;
2612 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2613 CR_RANGE(cmd->chanlist[i]))
2614 return 0;
2615 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2616 return 0;
2617 }
2618 return 1;
2619 }
2620
2621 static int setup_channel_queue(struct comedi_device *dev,
2622 const struct comedi_cmd *cmd)
2623 {
2624 unsigned short bits;
2625 int i;
2626
2627 if (board(dev)->layout != LAYOUT_4020) {
2628 if (use_internal_queue_6xxx(cmd)) {
2629 priv(dev)->hw_config_bits &= ~EXT_QUEUE_BIT;
2630 writew(priv(dev)->hw_config_bits,
2631 priv(dev)->main_iobase + HW_CONFIG_REG);
2632 bits = 0;
2633 /* set channel */
2634 bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2635 /* set gain */
2636 bits |= ai_range_bits_6xxx(dev,
2637 CR_RANGE(cmd->chanlist[0]));
2638 /* set single-ended / differential */
2639 bits |= se_diff_bit_6xxx(dev,
2640 CR_AREF(cmd->chanlist[0]) ==
2641 AREF_DIFF);
2642 if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2643 bits |= ADC_COMMON_BIT;
2644 /* set stop channel */
2645 writew(adc_chan_bits
2646 (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2647 priv(dev)->main_iobase + ADC_QUEUE_HIGH_REG);
2648 /* set start channel, and rest of settings */
2649 writew(bits,
2650 priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
2651 } else {
2652 /* use external queue */
2653 if (dev->write_subdev && dev->write_subdev->busy) {
2654 warn_external_queue(dev);
2655 return -EBUSY;
2656 }
2657 priv(dev)->hw_config_bits |= EXT_QUEUE_BIT;
2658 writew(priv(dev)->hw_config_bits,
2659 priv(dev)->main_iobase + HW_CONFIG_REG);
2660 /* clear DAC buffer to prevent weird interactions */
2661 writew(0,
2662 priv(dev)->main_iobase + DAC_BUFFER_CLEAR_REG);
2663 /* clear queue pointer */
2664 writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
2665 /* load external queue */
2666 for (i = 0; i < cmd->chanlist_len; i++) {
2667 bits = 0;
2668 /* set channel */
2669 bits |=
2670 adc_chan_bits(CR_CHAN(cmd->chanlist[i]));
2671 /* set gain */
2672 bits |= ai_range_bits_6xxx(dev,
2673 CR_RANGE(cmd->
2674 chanlist
2675 [i]));
2676 /* set single-ended / differential */
2677 bits |= se_diff_bit_6xxx(dev,
2678 CR_AREF(cmd->
2679 chanlist[i]) ==
2680 AREF_DIFF);
2681 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2682 bits |= ADC_COMMON_BIT;
2683 /* mark end of queue */
2684 if (i == cmd->chanlist_len - 1)
2685 bits |= QUEUE_EOSCAN_BIT |
2686 QUEUE_EOSEQ_BIT;
2687 writew(bits,
2688 priv(dev)->main_iobase +
2689 ADC_QUEUE_FIFO_REG);
2690 DEBUG_PRINT
2691 ("wrote 0x%x to external channel queue\n",
2692 bits);
2693 }
2694 /* doing a queue clear is not specified in board docs,
2695 * but required for reliable operation */
2696 writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
2697 /* prime queue holding register */
2698 writew(0, priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
2699 }
2700 } else {
2701 unsigned short old_cal_range_bits =
2702 priv(dev)->i2c_cal_range_bits;
2703
2704 priv(dev)->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2705 /* select BNC inputs */
2706 priv(dev)->i2c_cal_range_bits |= adc_src_4020_bits(4);
2707 /* select ranges */
2708 for (i = 0; i < cmd->chanlist_len; i++) {
2709 unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2710 unsigned int range = CR_RANGE(cmd->chanlist[i]);
2711
2712 if (range == 0)
2713 priv(dev)->i2c_cal_range_bits |=
2714 attenuate_bit(channel);
2715 else
2716 priv(dev)->i2c_cal_range_bits &=
2717 ~attenuate_bit(channel);
2718 }
2719 /* update calibration/range i2c register only if necessary, as it is very slow */
2720 if (old_cal_range_bits != priv(dev)->i2c_cal_range_bits) {
2721 uint8_t i2c_data = priv(dev)->i2c_cal_range_bits;
2722 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2723 sizeof(i2c_data));
2724 }
2725 }
2726 return 0;
2727 }
2728
2729 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2730 unsigned int dma_channel,
2731 unsigned int descriptor_bits)
2732 {
2733 /* The transfer size, pci address, and local address registers
2734 * are supposedly unused during chained dma,
2735 * but I have found that left over values from last operation
2736 * occasionally cause problems with transfer of first dma
2737 * block. Initializing them to zero seems to fix the problem. */
2738 if (dma_channel) {
2739 writel(0,
2740 priv(dev)->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2741 writel(0, priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2742 writel(0,
2743 priv(dev)->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2744 writel(descriptor_bits,
2745 priv(dev)->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2746 } else {
2747 writel(0,
2748 priv(dev)->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2749 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2750 writel(0,
2751 priv(dev)->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2752 writel(descriptor_bits,
2753 priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2754 }
2755 }
2756
2757 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2758 {
2759 struct comedi_async *async = s->async;
2760 struct comedi_cmd *cmd = &async->cmd;
2761 uint32_t bits;
2762 unsigned int i;
2763 unsigned long flags;
2764 int retval;
2765
2766 disable_ai_pacing(dev);
2767 abort_dma(dev, 1);
2768
2769 retval = setup_channel_queue(dev, cmd);
2770 if (retval < 0)
2771 return retval;
2772
2773 /* make sure internal calibration source is turned off */
2774 writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
2775
2776 set_ai_pacing(dev, cmd);
2777
2778 setup_sample_counters(dev, cmd);
2779
2780 enable_ai_interrupts(dev, cmd);
2781
2782 spin_lock_irqsave(&dev->spinlock, flags);
2783 /* set mode, allow conversions through software gate */
2784 priv(dev)->adc_control1_bits |= ADC_SW_GATE_BIT;
2785 priv(dev)->adc_control1_bits &= ~ADC_DITHER_BIT;
2786 if (board(dev)->layout != LAYOUT_4020) {
2787 priv(dev)->adc_control1_bits &= ~ADC_MODE_MASK;
2788 if (cmd->convert_src == TRIG_EXT)
2789 priv(dev)->adc_control1_bits |= adc_mode_bits(13); /* good old mode 13 */
2790 else
2791 priv(dev)->adc_control1_bits |= adc_mode_bits(8); /* mode 8. What else could you need? */
2792 } else {
2793 priv(dev)->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2794 if (cmd->chanlist_len == 4)
2795 priv(dev)->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2796 else if (cmd->chanlist_len == 2)
2797 priv(dev)->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2798 priv(dev)->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2799 priv(dev)->adc_control1_bits |=
2800 adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2801 priv(dev)->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2802 priv(dev)->adc_control1_bits |=
2803 adc_hi_chan_4020_bits(CR_CHAN
2804 (cmd->
2805 chanlist[cmd->chanlist_len - 1]));
2806 }
2807 writew(priv(dev)->adc_control1_bits,
2808 priv(dev)->main_iobase + ADC_CONTROL1_REG);
2809 DEBUG_PRINT("control1 bits 0x%x\n", priv(dev)->adc_control1_bits);
2810 spin_unlock_irqrestore(&dev->spinlock, flags);
2811
2812 /* clear adc buffer */
2813 writew(0, priv(dev)->main_iobase + ADC_BUFFER_CLEAR_REG);
2814
2815 if ((cmd->flags & TRIG_WAKE_EOS) == 0 ||
2816 board(dev)->layout == LAYOUT_4020) {
2817 priv(dev)->ai_dma_index = 0;
2818
2819 /* set dma transfer size */
2820 for (i = 0; i < ai_dma_ring_count(board(dev)); i++)
2821 priv(dev)->ai_dma_desc[i].transfer_size =
2822 cpu_to_le32(dma_transfer_size(dev) *
2823 sizeof(uint16_t));
2824
2825 /* give location of first dma descriptor */
2826 load_first_dma_descriptor(dev, 1,
2827 priv(dev)->ai_dma_desc_bus_addr |
2828 PLX_DESC_IN_PCI_BIT |
2829 PLX_INTR_TERM_COUNT |
2830 PLX_XFER_LOCAL_TO_PCI);
2831
2832 dma_start_sync(dev, 1);
2833 }
2834
2835 if (board(dev)->layout == LAYOUT_4020) {
2836 /* set source for external triggers */
2837 bits = 0;
2838 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2839 bits |= EXT_START_TRIG_BNC_BIT;
2840 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2841 bits |= EXT_STOP_TRIG_BNC_BIT;
2842 writew(bits, priv(dev)->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2843 }
2844
2845 spin_lock_irqsave(&dev->spinlock, flags);
2846
2847 /* enable pacing, triggering, etc */
2848 bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2849 if (cmd->flags & TRIG_WAKE_EOS)
2850 bits |= ADC_DMA_DISABLE_BIT;
2851 /* set start trigger */
2852 if (cmd->start_src == TRIG_EXT) {
2853 bits |= ADC_START_TRIG_EXT_BITS;
2854 if (cmd->start_arg & CR_INVERT)
2855 bits |= ADC_START_TRIG_FALLING_BIT;
2856 } else if (cmd->start_src == TRIG_NOW)
2857 bits |= ADC_START_TRIG_SOFT_BITS;
2858 if (use_hw_sample_counter(cmd))
2859 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2860 writew(bits, priv(dev)->main_iobase + ADC_CONTROL0_REG);
2861 DEBUG_PRINT("control0 bits 0x%x\n", bits);
2862
2863 priv(dev)->ai_cmd_running = 1;
2864
2865 spin_unlock_irqrestore(&dev->spinlock, flags);
2866
2867 /* start acquisition */
2868 if (cmd->start_src == TRIG_NOW) {
2869 writew(0, priv(dev)->main_iobase + ADC_START_REG);
2870 DEBUG_PRINT("soft trig\n");
2871 }
2872
2873 return 0;
2874 }
2875
2876 /* read num_samples from 16 bit wide ai fifo */
2877 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2878 {
2879 struct comedi_subdevice *s = dev->read_subdev;
2880 struct comedi_async *async = s->async;
2881 struct comedi_cmd *cmd = &async->cmd;
2882 unsigned int i;
2883 uint16_t prepost_bits;
2884 int read_segment, read_index, write_segment, write_index;
2885 int num_samples;
2886
2887 do {
2888 /* get least significant 15 bits */
2889 read_index =
2890 readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2891 write_index =
2892 readw(priv(dev)->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2893 /* Get most significant bits (grey code). Different boards use different code
2894 * so use a scheme that doesn't depend on encoding. This read must
2895 * occur after reading least significant 15 bits to avoid race
2896 * with fifo switching to next segment. */
2897 prepost_bits = readw(priv(dev)->main_iobase + PREPOST_REG);
2898
2899 /* if read and write pointers are not on the same fifo segment, read to the
2900 * end of the read segment */
2901 read_segment = adc_upper_read_ptr_code(prepost_bits);
2902 write_segment = adc_upper_write_ptr_code(prepost_bits);
2903
2904 DEBUG_PRINT(" rd seg %i, wrt seg %i, rd idx %i, wrt idx %i\n",
2905 read_segment, write_segment, read_index,
2906 write_index);
2907
2908 if (read_segment != write_segment)
2909 num_samples =
2910 priv(dev)->ai_fifo_segment_length - read_index;
2911 else
2912 num_samples = write_index - read_index;
2913
2914 if (cmd->stop_src == TRIG_COUNT) {
2915 if (priv(dev)->ai_count == 0)
2916 break;
2917 if (num_samples > priv(dev)->ai_count)
2918 num_samples = priv(dev)->ai_count;
2919
2920 priv(dev)->ai_count -= num_samples;
2921 }
2922
2923 if (num_samples < 0) {
2924 dev_err(dev->hw_dev, "cb_pcidas64: bug! num_samples < 0\n");
2925 break;
2926 }
2927
2928 DEBUG_PRINT(" read %i samples from fifo\n", num_samples);
2929
2930 for (i = 0; i < num_samples; i++) {
2931 cfc_write_to_buffer(s,
2932 readw(priv(dev)->main_iobase +
2933 ADC_FIFO_REG));
2934 }
2935
2936 } while (read_segment != write_segment);
2937 }
2938
2939 /* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of pointers.
2940 * The pci-4020 hardware only supports
2941 * dma transfers (it only supports the use of pio for draining the last remaining
2942 * points from the fifo when a data acquisition operation has completed).
2943 */
2944 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2945 {
2946 struct comedi_subdevice *s = dev->read_subdev;
2947 struct comedi_async *async = s->async;
2948 struct comedi_cmd *cmd = &async->cmd;
2949 unsigned int i;
2950 unsigned int max_transfer = 100000;
2951 uint32_t fifo_data;
2952 int write_code =
2953 readw(priv(dev)->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2954 int read_code =
2955 readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2956
2957 if (cmd->stop_src == TRIG_COUNT) {
2958 if (max_transfer > priv(dev)->ai_count)
2959 max_transfer = priv(dev)->ai_count;
2960
2961 }
2962 for (i = 0; read_code != write_code && i < max_transfer;) {
2963 fifo_data = readl(priv(dev)->dio_counter_iobase + ADC_FIFO_REG);
2964 cfc_write_to_buffer(s, fifo_data & 0xffff);
2965 i++;
2966 if (i < max_transfer) {
2967 cfc_write_to_buffer(s, (fifo_data >> 16) & 0xffff);
2968 i++;
2969 }
2970 read_code =
2971 readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2972 }
2973 priv(dev)->ai_count -= i;
2974 }
2975
2976 /* empty fifo */
2977 static void pio_drain_ai_fifo(struct comedi_device *dev)
2978 {
2979 if (board(dev)->layout == LAYOUT_4020)
2980 pio_drain_ai_fifo_32(dev);
2981 else
2982 pio_drain_ai_fifo_16(dev);
2983 }
2984
2985 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2986 {
2987 struct comedi_async *async = dev->read_subdev->async;
2988 uint32_t next_transfer_addr;
2989 int j;
2990 int num_samples = 0;
2991 void __iomem *pci_addr_reg;
2992
2993 if (channel)
2994 pci_addr_reg =
2995 priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2996 else
2997 pci_addr_reg =
2998 priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2999
3000 /* loop until we have read all the full buffers */
3001 for (j = 0, next_transfer_addr = readl(pci_addr_reg);
3002 (next_transfer_addr <
3003 priv(dev)->ai_buffer_bus_addr[priv(dev)->ai_dma_index]
3004 || next_transfer_addr >=
3005 priv(dev)->ai_buffer_bus_addr[priv(dev)->ai_dma_index] +
3006 DMA_BUFFER_SIZE) && j < ai_dma_ring_count(board(dev)); j++) {
3007 /* transfer data from dma buffer to comedi buffer */
3008 num_samples = dma_transfer_size(dev);
3009 if (async->cmd.stop_src == TRIG_COUNT) {
3010 if (num_samples > priv(dev)->ai_count)
3011 num_samples = priv(dev)->ai_count;
3012 priv(dev)->ai_count -= num_samples;
3013 }
3014 cfc_write_array_to_buffer(dev->read_subdev,
3015 priv(dev)->ai_buffer[priv(dev)->
3016 ai_dma_index],
3017 num_samples * sizeof(uint16_t));
3018 priv(dev)->ai_dma_index =
3019 (priv(dev)->ai_dma_index +
3020 1) % ai_dma_ring_count(board(dev));
3021
3022 DEBUG_PRINT("next buffer addr 0x%lx\n",
3023 (unsigned long)priv(dev)->
3024 ai_buffer_bus_addr[priv(dev)->ai_dma_index]);
3025 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
3026 }
3027 /* XXX check for dma ring buffer overrun (use end-of-chain bit to mark last
3028 * unused buffer) */
3029 }
3030
3031 static void handle_ai_interrupt(struct comedi_device *dev,
3032 unsigned short status,
3033 unsigned int plx_status)
3034 {
3035 struct comedi_subdevice *s = dev->read_subdev;
3036 struct comedi_async *async = s->async;
3037 struct comedi_cmd *cmd = &async->cmd;
3038 uint8_t dma1_status;
3039 unsigned long flags;
3040
3041 /* check for fifo overrun */
3042 if (status & ADC_OVERRUN_BIT) {
3043 comedi_error(dev, "fifo overrun");
3044 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
3045 }
3046 /* spin lock makes sure no one else changes plx dma control reg */
3047 spin_lock_irqsave(&dev->spinlock, flags);
3048 dma1_status = readb(priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
3049 if (plx_status & ICS_DMA1_A) { /* dma chan 1 interrupt */
3050 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
3051 priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
3052 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
3053
3054 if (dma1_status & PLX_DMA_EN_BIT)
3055 drain_dma_buffers(dev, 1);
3056
3057 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
3058 }
3059 spin_unlock_irqrestore(&dev->spinlock, flags);
3060
3061 if (status & ADC_DONE_BIT)
3062 DEBUG_PRINT("adc done interrupt\n");
3063
3064 /* drain fifo with pio */
3065 if ((status & ADC_DONE_BIT) ||
3066 ((cmd->flags & TRIG_WAKE_EOS) &&
3067 (status & ADC_INTR_PENDING_BIT) &&
3068 (board(dev)->layout != LAYOUT_4020))) {
3069 DEBUG_PRINT("pio fifo drain\n");
3070 spin_lock_irqsave(&dev->spinlock, flags);
3071 if (priv(dev)->ai_cmd_running) {
3072 spin_unlock_irqrestore(&dev->spinlock, flags);
3073 pio_drain_ai_fifo(dev);
3074 } else
3075 spin_unlock_irqrestore(&dev->spinlock, flags);
3076 }
3077 /* if we are have all the data, then quit */
3078 if ((cmd->stop_src == TRIG_COUNT && (int)priv(dev)->ai_count <= 0) ||
3079 (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) {
3080 async->events |= COMEDI_CB_EOA;
3081 }
3082
3083 cfc_handle_events(dev, s);
3084 }
3085
3086 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
3087 {
3088 unsigned int buffer_index;
3089
3090 if (priv(dev)->ao_dma_index == 0)
3091 buffer_index = AO_DMA_RING_COUNT - 1;
3092 else
3093 buffer_index = priv(dev)->ao_dma_index - 1;
3094 return buffer_index;
3095 }
3096
3097 static int last_ao_dma_load_completed(struct comedi_device *dev)
3098 {
3099 unsigned int buffer_index;
3100 unsigned int transfer_address;
3101 unsigned short dma_status;
3102
3103 buffer_index = prev_ao_dma_index(dev);
3104 dma_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3105 if ((dma_status & PLX_DMA_DONE_BIT) == 0)
3106 return 0;
3107
3108 transfer_address =
3109 readl(priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
3110 if (transfer_address != priv(dev)->ao_buffer_bus_addr[buffer_index])
3111 return 0;
3112
3113 return 1;
3114 }
3115
3116 static int ao_stopped_by_error(struct comedi_device *dev,
3117 const struct comedi_cmd *cmd)
3118 {
3119 if (cmd->stop_src == TRIG_NONE)
3120 return 1;
3121 if (cmd->stop_src == TRIG_COUNT) {
3122 if (priv(dev)->ao_count)
3123 return 1;
3124 if (last_ao_dma_load_completed(dev) == 0)
3125 return 1;
3126 }
3127 return 0;
3128 }
3129
3130 static inline int ao_dma_needs_restart(struct comedi_device *dev,
3131 unsigned short dma_status)
3132 {
3133 if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
3134 (dma_status & PLX_DMA_EN_BIT) == 0)
3135 return 0;
3136 if (last_ao_dma_load_completed(dev))
3137 return 0;
3138
3139 return 1;
3140 }
3141
3142 static void restart_ao_dma(struct comedi_device *dev)
3143 {
3144 unsigned int dma_desc_bits;
3145
3146 dma_desc_bits =
3147 readl(priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
3148 dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
3149 DEBUG_PRINT("restarting ao dma, descriptor reg 0x%x\n", dma_desc_bits);
3150 load_first_dma_descriptor(dev, 0, dma_desc_bits);
3151
3152 dma_start_sync(dev, 0);
3153 }
3154
3155 static void handle_ao_interrupt(struct comedi_device *dev,
3156 unsigned short status, unsigned int plx_status)
3157 {
3158 struct comedi_subdevice *s = dev->write_subdev;
3159 struct comedi_async *async;
3160 struct comedi_cmd *cmd;
3161 uint8_t dma0_status;
3162 unsigned long flags;
3163
3164 /* board might not support ao, in which case write_subdev is NULL */
3165 if (s == NULL)
3166 return;
3167 async = s->async;
3168 cmd = &async->cmd;
3169
3170 /* spin lock makes sure no one else changes plx dma control reg */
3171 spin_lock_irqsave(&dev->spinlock, flags);
3172 dma0_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3173 if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
3174 if ((dma0_status & PLX_DMA_EN_BIT)
3175 && !(dma0_status & PLX_DMA_DONE_BIT))
3176 writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
3177 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3178 else
3179 writeb(PLX_CLEAR_DMA_INTR_BIT,
3180 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3181 spin_unlock_irqrestore(&dev->spinlock, flags);
3182 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
3183 if (dma0_status & PLX_DMA_EN_BIT) {
3184 load_ao_dma(dev, cmd);
3185 /* try to recover from dma end-of-chain event */
3186 if (ao_dma_needs_restart(dev, dma0_status))
3187 restart_ao_dma(dev);
3188 }
3189 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
3190 } else
3191 spin_unlock_irqrestore(&dev->spinlock, flags);
3192
3193 if ((status & DAC_DONE_BIT)) {
3194 async->events |= COMEDI_CB_EOA;
3195 if (ao_stopped_by_error(dev, cmd))
3196 async->events |= COMEDI_CB_ERROR;
3197 DEBUG_PRINT("plx dma0 desc reg 0x%x\n",
3198 readl(priv(dev)->plx9080_iobase +
3199 PLX_DMA0_DESCRIPTOR_REG));
3200 DEBUG_PRINT("plx dma0 address reg 0x%x\n",
3201 readl(priv(dev)->plx9080_iobase +
3202 PLX_DMA0_PCI_ADDRESS_REG));
3203 }
3204 cfc_handle_events(dev, s);
3205 }
3206
3207 static irqreturn_t handle_interrupt(int irq, void *d)
3208 {
3209 struct comedi_device *dev = d;
3210 unsigned short status;
3211 uint32_t plx_status;
3212 uint32_t plx_bits;
3213
3214 plx_status = readl(priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
3215 status = readw(priv(dev)->main_iobase + HW_STATUS_REG);
3216
3217 DEBUG_PRINT("cb_pcidas64: hw status 0x%x ", status);
3218 DEBUG_PRINT("plx status 0x%x\n", plx_status);
3219
3220 /* an interrupt before all the postconfig stuff gets done could
3221 * cause a NULL dereference if we continue through the
3222 * interrupt handler */
3223 if (dev->attached == 0) {
3224 DEBUG_PRINT("cb_pcidas64: premature interrupt, ignoring",
3225 status);
3226 return IRQ_HANDLED;
3227 }
3228 handle_ai_interrupt(dev, status, plx_status);
3229 handle_ao_interrupt(dev, status, plx_status);
3230
3231 /* clear possible plx9080 interrupt sources */
3232 if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
3233 plx_bits = readl(priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
3234 writel(plx_bits, priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
3235 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
3236 }
3237
3238 DEBUG_PRINT("exiting handler\n");
3239
3240 return IRQ_HANDLED;
3241 }
3242
3243 static void abort_dma(struct comedi_device *dev, unsigned int channel)
3244 {
3245 unsigned long flags;
3246
3247 /* spinlock for plx dma control/status reg */
3248 spin_lock_irqsave(&dev->spinlock, flags);
3249
3250 plx9080_abort_dma(priv(dev)->plx9080_iobase, channel);
3251
3252 spin_unlock_irqrestore(&dev->spinlock, flags);
3253 }
3254
3255 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3256 {
3257 unsigned long flags;
3258
3259 spin_lock_irqsave(&dev->spinlock, flags);
3260 if (priv(dev)->ai_cmd_running == 0) {
3261 spin_unlock_irqrestore(&dev->spinlock, flags);
3262 return 0;
3263 }
3264 priv(dev)->ai_cmd_running = 0;
3265 spin_unlock_irqrestore(&dev->spinlock, flags);
3266
3267 disable_ai_pacing(dev);
3268
3269 abort_dma(dev, 1);
3270
3271 DEBUG_PRINT("ai canceled\n");
3272 return 0;
3273 }
3274
3275 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3276 struct comedi_insn *insn, unsigned int *data)
3277 {
3278 int chan = CR_CHAN(insn->chanspec);
3279 int range = CR_RANGE(insn->chanspec);
3280
3281 /* do some initializing */
3282 writew(0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3283
3284 /* set range */
3285 set_dac_range_bits(dev, &priv(dev)->dac_control1_bits, chan, range);
3286 writew(priv(dev)->dac_control1_bits,
3287 priv(dev)->main_iobase + DAC_CONTROL1_REG);
3288
3289 /* write to channel */
3290 if (board(dev)->layout == LAYOUT_4020) {
3291 writew(data[0] & 0xff,
3292 priv(dev)->main_iobase + dac_lsb_4020_reg(chan));
3293 writew((data[0] >> 8) & 0xf,
3294 priv(dev)->main_iobase + dac_msb_4020_reg(chan));
3295 } else {
3296 writew(data[0], priv(dev)->main_iobase + dac_convert_reg(chan));
3297 }
3298
3299 /* remember output value */
3300 priv(dev)->ao_value[chan] = data[0];
3301
3302 return 1;
3303 }
3304
3305 static int ao_readback_insn(struct comedi_device *dev,
3306 struct comedi_subdevice *s,
3307 struct comedi_insn *insn, unsigned int *data)
3308 {
3309 data[0] = priv(dev)->ao_value[CR_CHAN(insn->chanspec)];
3310
3311 return 1;
3312 }
3313
3314 static void set_dac_control0_reg(struct comedi_device *dev,
3315 const struct comedi_cmd *cmd)
3316 {
3317 unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3318 WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3319
3320 if (cmd->start_src == TRIG_EXT) {
3321 bits |= WAVEFORM_TRIG_EXT_BITS;
3322 if (cmd->start_arg & CR_INVERT)
3323 bits |= WAVEFORM_TRIG_FALLING_BIT;
3324 } else {
3325 bits |= WAVEFORM_TRIG_SOFT_BITS;
3326 }
3327 if (cmd->scan_begin_src == TRIG_EXT) {
3328 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3329 if (cmd->scan_begin_arg & CR_INVERT)
3330 bits |= DAC_EXT_UPDATE_FALLING_BIT;
3331 }
3332 writew(bits, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3333 }
3334
3335 static void set_dac_control1_reg(struct comedi_device *dev,
3336 const struct comedi_cmd *cmd)
3337 {
3338 int i;
3339
3340 for (i = 0; i < cmd->chanlist_len; i++) {
3341 int channel, range;
3342
3343 channel = CR_CHAN(cmd->chanlist[i]);
3344 range = CR_RANGE(cmd->chanlist[i]);
3345 set_dac_range_bits(dev, &priv(dev)->dac_control1_bits, channel,
3346 range);
3347 }
3348 priv(dev)->dac_control1_bits |= DAC_SW_GATE_BIT;
3349 writew(priv(dev)->dac_control1_bits,
3350 priv(dev)->main_iobase + DAC_CONTROL1_REG);
3351 }
3352
3353 static void set_dac_select_reg(struct comedi_device *dev,
3354 const struct comedi_cmd *cmd)
3355 {
3356 uint16_t bits;
3357 unsigned int first_channel, last_channel;
3358
3359 first_channel = CR_CHAN(cmd->chanlist[0]);
3360 last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3361 if (last_channel < first_channel)
3362 comedi_error(dev, "bug! last ao channel < first ao channel");
3363
3364 bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3365
3366 writew(bits, priv(dev)->main_iobase + DAC_SELECT_REG);
3367 }
3368
3369 static void set_dac_interval_regs(struct comedi_device *dev,
3370 const struct comedi_cmd *cmd)
3371 {
3372 unsigned int divisor;
3373
3374 if (cmd->scan_begin_src != TRIG_TIMER)
3375 return;
3376
3377 divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3378 if (divisor > max_counter_value) {
3379 comedi_error(dev, "bug! ao divisor too big");
3380 divisor = max_counter_value;
3381 }
3382 writew(divisor & 0xffff,
3383 priv(dev)->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3384 writew((divisor >> 16) & 0xff,
3385 priv(dev)->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3386 }
3387
3388 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
3389 const struct comedi_cmd *cmd)
3390 {
3391 unsigned int num_bytes, buffer_index, prev_buffer_index;
3392 unsigned int next_bits;
3393
3394 buffer_index = priv(dev)->ao_dma_index;
3395 prev_buffer_index = prev_ao_dma_index(dev);
3396
3397 DEBUG_PRINT("attempting to load ao buffer %i (0x%x)\n", buffer_index,
3398 priv(dev)->ao_buffer_bus_addr[buffer_index]);
3399
3400 num_bytes = comedi_buf_read_n_available(dev->write_subdev->async);
3401 if (num_bytes > DMA_BUFFER_SIZE)
3402 num_bytes = DMA_BUFFER_SIZE;
3403 if (cmd->stop_src == TRIG_COUNT && num_bytes > priv(dev)->ao_count)
3404 num_bytes = priv(dev)->ao_count;
3405 num_bytes -= num_bytes % bytes_in_sample;
3406
3407 if (num_bytes == 0)
3408 return 0;
3409
3410 DEBUG_PRINT("loading %i bytes\n", num_bytes);
3411
3412 num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3413 priv(dev)->
3414 ao_buffer[buffer_index],
3415 num_bytes);
3416 priv(dev)->ao_dma_desc[buffer_index].transfer_size =
3417 cpu_to_le32(num_bytes);
3418 /* set end of chain bit so we catch underruns */
3419 next_bits = le32_to_cpu(priv(dev)->ao_dma_desc[buffer_index].next);
3420 next_bits |= PLX_END_OF_CHAIN_BIT;
3421 priv(dev)->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
3422 /* clear end of chain bit on previous buffer now that we have set it
3423 * for the last buffer */
3424 next_bits = le32_to_cpu(priv(dev)->ao_dma_desc[prev_buffer_index].next);
3425 next_bits &= ~PLX_END_OF_CHAIN_BIT;
3426 priv(dev)->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
3427
3428 priv(dev)->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
3429 priv(dev)->ao_count -= num_bytes;
3430
3431 return num_bytes;
3432 }
3433
3434 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3435 {
3436 unsigned int num_bytes;
3437 unsigned int next_transfer_addr;
3438 void __iomem *pci_addr_reg =
3439 priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
3440 unsigned int buffer_index;
3441
3442 do {
3443 buffer_index = priv(dev)->ao_dma_index;
3444 /* don't overwrite data that hasn't been transferred yet */
3445 next_transfer_addr = readl(pci_addr_reg);
3446 if (next_transfer_addr >=
3447 priv(dev)->ao_buffer_bus_addr[buffer_index]
3448 && next_transfer_addr <
3449 priv(dev)->ao_buffer_bus_addr[buffer_index] +
3450 DMA_BUFFER_SIZE)
3451 return;
3452 num_bytes = load_ao_dma_buffer(dev, cmd);
3453 } while (num_bytes >= DMA_BUFFER_SIZE);
3454 }
3455
3456 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3457 {
3458 unsigned int num_bytes;
3459 int i;
3460
3461 /* clear queue pointer too, since external queue has
3462 * weird interactions with ao fifo */
3463 writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
3464 writew(0, priv(dev)->main_iobase + DAC_BUFFER_CLEAR_REG);
3465
3466 num_bytes = (DAC_FIFO_SIZE / 2) * bytes_in_sample;
3467 if (cmd->stop_src == TRIG_COUNT &&
3468 num_bytes / bytes_in_sample > priv(dev)->ao_count)
3469 num_bytes = priv(dev)->ao_count * bytes_in_sample;
3470 num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3471 priv(dev)->ao_bounce_buffer,
3472 num_bytes);
3473 for (i = 0; i < num_bytes / bytes_in_sample; i++) {
3474 writew(priv(dev)->ao_bounce_buffer[i],
3475 priv(dev)->main_iobase + DAC_FIFO_REG);
3476 }
3477 priv(dev)->ao_count -= num_bytes / bytes_in_sample;
3478 if (cmd->stop_src == TRIG_COUNT && priv(dev)->ao_count == 0)
3479 return 0;
3480 num_bytes = load_ao_dma_buffer(dev, cmd);
3481 if (num_bytes == 0)
3482 return -1;
3483 if (num_bytes >= DMA_BUFFER_SIZE) ;
3484 load_ao_dma(dev, cmd);
3485
3486 dma_start_sync(dev, 0);
3487
3488 return 0;
3489 }
3490
3491 static inline int external_ai_queue_in_use(struct comedi_device *dev)
3492 {
3493 if (dev->read_subdev->busy)
3494 return 0;
3495 if (board(dev)->layout == LAYOUT_4020)
3496 return 0;
3497 else if (use_internal_queue_6xxx(&dev->read_subdev->async->cmd))
3498 return 0;
3499 return 1;
3500 }
3501
3502 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3503 {
3504 struct comedi_cmd *cmd = &s->async->cmd;
3505
3506 if (external_ai_queue_in_use(dev)) {
3507 warn_external_queue(dev);
3508 return -EBUSY;
3509 }
3510 /* disable analog output system during setup */
3511 writew(0x0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3512
3513 priv(dev)->ao_dma_index = 0;
3514 priv(dev)->ao_count = cmd->stop_arg * cmd->chanlist_len;
3515
3516 set_dac_select_reg(dev, cmd);
3517 set_dac_interval_regs(dev, cmd);
3518 load_first_dma_descriptor(dev, 0, priv(dev)->ao_dma_desc_bus_addr |
3519 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3520
3521 set_dac_control1_reg(dev, cmd);
3522 s->async->inttrig = ao_inttrig;
3523
3524 return 0;
3525 }
3526
3527 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3528 unsigned int trig_num)
3529 {
3530 struct comedi_cmd *cmd = &s->async->cmd;
3531 int retval;
3532
3533 if (trig_num != 0)
3534 return -EINVAL;
3535
3536 retval = prep_ao_dma(dev, cmd);
3537 if (retval < 0)
3538 return -EPIPE;
3539
3540 set_dac_control0_reg(dev, cmd);
3541
3542 if (cmd->start_src == TRIG_INT)
3543 writew(0, priv(dev)->main_iobase + DAC_START_REG);
3544
3545 s->async->inttrig = NULL;
3546
3547 return 0;
3548 }
3549
3550 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3551 struct comedi_cmd *cmd)
3552 {
3553 int err = 0;
3554 int tmp;
3555 unsigned int tmp_arg;
3556 int i;
3557
3558 /* step 1: make sure trigger sources are trivially valid */
3559
3560 tmp = cmd->start_src;
3561 cmd->start_src &= TRIG_INT | TRIG_EXT;
3562 if (!cmd->start_src || tmp != cmd->start_src)
3563 err++;
3564
3565 tmp = cmd->scan_begin_src;
3566 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
3567 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
3568 err++;
3569
3570 tmp = cmd->convert_src;
3571 cmd->convert_src &= TRIG_NOW;
3572 if (!cmd->convert_src || tmp != cmd->convert_src)
3573 err++;
3574
3575 tmp = cmd->scan_end_src;
3576 cmd->scan_end_src &= TRIG_COUNT;
3577 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
3578 err++;
3579
3580 tmp = cmd->stop_src;
3581 cmd->stop_src &= TRIG_NONE;
3582 if (!cmd->stop_src || tmp != cmd->stop_src)
3583 err++;
3584
3585 if (err)
3586 return 1;
3587
3588 /* step 2: make sure trigger sources are unique and mutually compatible */
3589
3590 /* uniqueness check */
3591 if (cmd->start_src != TRIG_INT && cmd->start_src != TRIG_EXT)
3592 err++;
3593 if (cmd->scan_begin_src != TRIG_TIMER &&
3594 cmd->scan_begin_src != TRIG_EXT)
3595 err++;
3596
3597 /* compatibility check */
3598 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3599 err++;
3600 if (cmd->stop_src != TRIG_COUNT &&
3601 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3602 err++;
3603
3604 if (err)
3605 return 2;
3606
3607 /* step 3: make sure arguments are trivially compatible */
3608
3609 if (cmd->scan_begin_src == TRIG_TIMER) {
3610 if (cmd->scan_begin_arg < board(dev)->ao_scan_speed) {
3611 cmd->scan_begin_arg = board(dev)->ao_scan_speed;
3612 err++;
3613 }
3614 if (get_ao_divisor(cmd->scan_begin_arg,
3615 cmd->flags) > max_counter_value) {
3616 cmd->scan_begin_arg =
3617 (max_counter_value + 2) * TIMER_BASE;
3618 err++;
3619 }
3620 }
3621
3622 if (!cmd->chanlist_len) {
3623 cmd->chanlist_len = 1;
3624 err++;
3625 }
3626 if (cmd->scan_end_arg != cmd->chanlist_len) {
3627 cmd->scan_end_arg = cmd->chanlist_len;
3628 err++;
3629 }
3630
3631 if (err)
3632 return 3;
3633
3634 /* step 4: fix up any arguments */
3635
3636 if (cmd->scan_begin_src == TRIG_TIMER) {
3637 tmp_arg = cmd->scan_begin_arg;
3638 cmd->scan_begin_arg =
3639 get_divisor(cmd->scan_begin_arg, cmd->flags) * TIMER_BASE;
3640 if (tmp_arg != cmd->scan_begin_arg)
3641 err++;
3642 }
3643
3644 if (err)
3645 return 4;
3646
3647 if (cmd->chanlist) {
3648 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
3649 for (i = 1; i < cmd->chanlist_len; i++) {
3650 if (CR_CHAN(cmd->chanlist[i]) != first_channel + i) {
3651 comedi_error(dev,
3652 "chanlist must use consecutive channels");
3653 err++;
3654 break;
3655 }
3656 }
3657 }
3658
3659 if (err)
3660 return 5;
3661
3662 return 0;
3663 }
3664
3665 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3666 {
3667 writew(0x0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3668 abort_dma(dev, 0);
3669 return 0;
3670 }
3671
3672 static int dio_callback(int dir, int port, int data, unsigned long arg)
3673 {
3674 void __iomem *iobase = (void __iomem *)arg;
3675 if (dir) {
3676 writeb(data, iobase + port);
3677 DEBUG_PRINT("wrote 0x%x to port %i\n", data, port);
3678 return 0;
3679 } else {
3680 return readb(iobase + port);
3681 }
3682 }
3683
3684 static int dio_callback_4020(int dir, int port, int data, unsigned long arg)
3685 {
3686 void __iomem *iobase = (void __iomem *)arg;
3687 if (dir) {
3688 writew(data, iobase + 2 * port);
3689 return 0;
3690 } else {
3691 return readw(iobase + 2 * port);
3692 }
3693 }
3694
3695 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3696 struct comedi_insn *insn, unsigned int *data)
3697 {
3698 unsigned int bits;
3699
3700 bits = readb(priv(dev)->dio_counter_iobase + DI_REG);
3701 bits &= 0xf;
3702 data[1] = bits;
3703 data[0] = 0;
3704
3705 return 2;
3706 }
3707
3708 static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3709 struct comedi_insn *insn, unsigned int *data)
3710 {
3711 data[0] &= 0xf;
3712 /* zero bits we are going to change */
3713 s->state &= ~data[0];
3714 /* set new bits */
3715 s->state |= data[0] & data[1];
3716
3717 writeb(s->state, priv(dev)->dio_counter_iobase + DO_REG);
3718
3719 data[1] = s->state;
3720
3721 return 2;
3722 }
3723
3724 static int dio_60xx_config_insn(struct comedi_device *dev,
3725 struct comedi_subdevice *s,
3726 struct comedi_insn *insn, unsigned int *data)
3727 {
3728 unsigned int mask;
3729
3730 mask = 1 << CR_CHAN(insn->chanspec);
3731
3732 switch (data[0]) {
3733 case INSN_CONFIG_DIO_INPUT:
3734 s->io_bits &= ~mask;
3735 break;
3736 case INSN_CONFIG_DIO_OUTPUT:
3737 s->io_bits |= mask;
3738 break;
3739 case INSN_CONFIG_DIO_QUERY:
3740 data[1] = (s->io_bits & mask) ? COMEDI_OUTPUT : COMEDI_INPUT;
3741 return 2;
3742 default:
3743 return -EINVAL;
3744 }
3745
3746 writeb(s->io_bits,
3747 priv(dev)->dio_counter_iobase + DIO_DIRECTION_60XX_REG);
3748
3749 return 1;
3750 }
3751
3752 static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3753 struct comedi_insn *insn, unsigned int *data)
3754 {
3755 if (data[0]) {
3756 s->state &= ~data[0];
3757 s->state |= (data[0] & data[1]);
3758 writeb(s->state,
3759 priv(dev)->dio_counter_iobase + DIO_DATA_60XX_REG);
3760 }
3761
3762 data[1] = readb(priv(dev)->dio_counter_iobase + DIO_DATA_60XX_REG);
3763
3764 return 2;
3765 }
3766
3767 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3768 unsigned int value)
3769 {
3770 priv(dev)->caldac_state[channel] = value;
3771
3772 switch (board(dev)->layout) {
3773 case LAYOUT_60XX:
3774 case LAYOUT_64XX:
3775 caldac_8800_write(dev, channel, value);
3776 break;
3777 case LAYOUT_4020:
3778 caldac_i2c_write(dev, channel, value);
3779 break;
3780 default:
3781 break;
3782 }
3783 }
3784
3785 static int calib_write_insn(struct comedi_device *dev,
3786 struct comedi_subdevice *s,
3787 struct comedi_insn *insn, unsigned int *data)
3788 {
3789 int channel = CR_CHAN(insn->chanspec);
3790
3791 /* return immediately if setting hasn't changed, since
3792 * programming these things is slow */
3793 if (priv(dev)->caldac_state[channel] == data[0])
3794 return 1;
3795
3796 caldac_write(dev, channel, data[0]);
3797
3798 return 1;
3799 }
3800
3801 static int calib_read_insn(struct comedi_device *dev,
3802 struct comedi_subdevice *s, struct comedi_insn *insn,
3803 unsigned int *data)
3804 {
3805 unsigned int channel = CR_CHAN(insn->chanspec);
3806
3807 data[0] = priv(dev)->caldac_state[channel];
3808
3809 return 1;
3810 }
3811
3812 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3813 unsigned int value)
3814 {
3815 static const int bitstream_length = 10;
3816 unsigned int bit, register_bits;
3817 unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3818 static const int ad8402_udelay = 1;
3819
3820 priv(dev)->ad8402_state[channel] = value;
3821
3822 register_bits = SELECT_8402_64XX_BIT;
3823 udelay(ad8402_udelay);
3824 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
3825
3826 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3827 if (bitstream & bit)
3828 register_bits |= SERIAL_DATA_IN_BIT;
3829 else
3830 register_bits &= ~SERIAL_DATA_IN_BIT;
3831 udelay(ad8402_udelay);
3832 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
3833 udelay(ad8402_udelay);
3834 writew(register_bits | SERIAL_CLOCK_BIT,
3835 priv(dev)->main_iobase + CALIBRATION_REG);
3836 }
3837
3838 udelay(ad8402_udelay);
3839 writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
3840 }
3841
3842 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3843 static int ad8402_write_insn(struct comedi_device *dev,
3844 struct comedi_subdevice *s,
3845 struct comedi_insn *insn, unsigned int *data)
3846 {
3847 int channel = CR_CHAN(insn->chanspec);
3848
3849 /* return immediately if setting hasn't changed, since
3850 * programming these things is slow */
3851 if (priv(dev)->ad8402_state[channel] == data[0])
3852 return 1;
3853
3854 priv(dev)->ad8402_state[channel] = data[0];
3855
3856 ad8402_write(dev, channel, data[0]);
3857
3858 return 1;
3859 }
3860
3861 static int ad8402_read_insn(struct comedi_device *dev,
3862 struct comedi_subdevice *s,
3863 struct comedi_insn *insn, unsigned int *data)
3864 {
3865 unsigned int channel = CR_CHAN(insn->chanspec);
3866
3867 data[0] = priv(dev)->ad8402_state[channel];
3868
3869 return 1;
3870 }
3871
3872 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3873 {
3874 static const int bitstream_length = 11;
3875 static const int read_command = 0x6;
3876 unsigned int bitstream = (read_command << 8) | address;
3877 unsigned int bit;
3878 void __iomem * const plx_control_addr =
3879 priv(dev)->plx9080_iobase + PLX_CONTROL_REG;
3880 uint16_t value;
3881 static const int value_length = 16;
3882 static const int eeprom_udelay = 1;
3883
3884 udelay(eeprom_udelay);
3885 priv(dev)->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3886 /* make sure we don't send anything to the i2c bus on 4020 */
3887 priv(dev)->plx_control_bits |= CTL_USERO;
3888 writel(priv(dev)->plx_control_bits, plx_control_addr);
3889 /* activate serial eeprom */
3890 udelay(eeprom_udelay);
3891 priv(dev)->plx_control_bits |= CTL_EE_CS;
3892 writel(priv(dev)->plx_control_bits, plx_control_addr);
3893
3894 /* write read command and desired memory address */
3895 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3896 /* set bit to be written */
3897 udelay(eeprom_udelay);
3898 if (bitstream & bit)
3899 priv(dev)->plx_control_bits |= CTL_EE_W;
3900 else
3901 priv(dev)->plx_control_bits &= ~CTL_EE_W;
3902 writel(priv(dev)->plx_control_bits, plx_control_addr);
3903 /* clock in bit */
3904 udelay(eeprom_udelay);
3905 priv(dev)->plx_control_bits |= CTL_EE_CLK;
3906 writel(priv(dev)->plx_control_bits, plx_control_addr);
3907 udelay(eeprom_udelay);
3908 priv(dev)->plx_control_bits &= ~CTL_EE_CLK;
3909 writel(priv(dev)->plx_control_bits, plx_control_addr);
3910 }
3911 /* read back value from eeprom memory location */
3912 value = 0;
3913 for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3914 /* clock out bit */
3915 udelay(eeprom_udelay);
3916 priv(dev)->plx_control_bits |= CTL_EE_CLK;
3917 writel(priv(dev)->plx_control_bits, plx_control_addr);
3918 udelay(eeprom_udelay);
3919 priv(dev)->plx_control_bits &= ~CTL_EE_CLK;
3920 writel(priv(dev)->plx_control_bits, plx_control_addr);
3921 udelay(eeprom_udelay);
3922 if (readl(plx_control_addr) & CTL_EE_R)
3923 value |= bit;
3924 }
3925
3926 /* deactivate eeprom serial input */
3927 udelay(eeprom_udelay);
3928 priv(dev)->plx_control_bits &= ~CTL_EE_CS;
3929 writel(priv(dev)->plx_control_bits, plx_control_addr);
3930
3931 return value;
3932 }
3933
3934 static int eeprom_read_insn(struct comedi_device *dev,
3935 struct comedi_subdevice *s,
3936 struct comedi_insn *insn, unsigned int *data)
3937 {
3938 data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3939
3940 return 1;
3941 }
3942
3943 /* utility function that rounds desired timing to an achievable time, and
3944 * sets cmd members appropriately.
3945 * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
3946 */
3947 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
3948 {
3949 unsigned int convert_divisor = 0, scan_divisor;
3950 static const int min_convert_divisor = 3;
3951 static const int max_convert_divisor =
3952 max_counter_value + min_convert_divisor;
3953 static const int min_scan_divisor_4020 = 2;
3954 unsigned long long max_scan_divisor, min_scan_divisor;
3955
3956 if (cmd->convert_src == TRIG_TIMER) {
3957 if (board(dev)->layout == LAYOUT_4020) {
3958 cmd->convert_arg = 0;
3959 } else {
3960 convert_divisor =
3961 get_divisor(cmd->convert_arg, cmd->flags);
3962 if (convert_divisor > max_convert_divisor)
3963 convert_divisor = max_convert_divisor;
3964 if (convert_divisor < min_convert_divisor)
3965 convert_divisor = min_convert_divisor;
3966 cmd->convert_arg = convert_divisor * TIMER_BASE;
3967 }
3968 } else if (cmd->convert_src == TRIG_NOW)
3969 cmd->convert_arg = 0;
3970
3971 if (cmd->scan_begin_src == TRIG_TIMER) {
3972 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
3973 if (cmd->convert_src == TRIG_TIMER) {
3974 /* XXX check for integer overflows */
3975 min_scan_divisor = convert_divisor * cmd->chanlist_len;
3976 max_scan_divisor =
3977 (convert_divisor * cmd->chanlist_len - 1) +
3978 max_counter_value;
3979 } else {
3980 min_scan_divisor = min_scan_divisor_4020;
3981 max_scan_divisor = max_counter_value + min_scan_divisor;
3982 }
3983 if (scan_divisor > max_scan_divisor)
3984 scan_divisor = max_scan_divisor;
3985 if (scan_divisor < min_scan_divisor)
3986 scan_divisor = min_scan_divisor;
3987 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
3988 }
3989
3990 return;
3991 }
3992
3993 /* Gets nearest achievable timing given master clock speed, does not
3994 * take into account possible minimum/maximum divisor values. Used
3995 * by other timing checking functions. */
3996 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
3997 {
3998 unsigned int divisor;
3999
4000 switch (flags & TRIG_ROUND_MASK) {
4001 case TRIG_ROUND_UP:
4002 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
4003 break;
4004 case TRIG_ROUND_DOWN:
4005 divisor = ns / TIMER_BASE;
4006 break;
4007 case TRIG_ROUND_NEAREST:
4008 default:
4009 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
4010 break;
4011 }
4012 return divisor;
4013 }
4014
4015 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
4016 {
4017 return get_divisor(ns, flags) - 2;
4018 }
4019
4020 /* adjusts the size of hardware fifo (which determines block size for dma xfers) */
4021 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
4022 {
4023 unsigned int num_fifo_entries;
4024 int retval;
4025 const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
4026
4027 num_fifo_entries = num_samples / fifo->sample_packing_ratio;
4028
4029 retval = set_ai_fifo_segment_length(dev,
4030 num_fifo_entries /
4031 fifo->num_segments);
4032 if (retval < 0)
4033 return retval;
4034
4035 num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
4036
4037 DEBUG_PRINT("set hardware fifo size to %i\n", num_samples);
4038
4039 return num_samples;
4040 }
4041
4042 /* query length of fifo */
4043 static unsigned int ai_fifo_size(struct comedi_device *dev)
4044 {
4045 return priv(dev)->ai_fifo_segment_length *
4046 board(dev)->ai_fifo->num_segments *
4047 board(dev)->ai_fifo->sample_packing_ratio;
4048 }
4049
4050 static int set_ai_fifo_segment_length(struct comedi_device *dev,
4051 unsigned int num_entries)
4052 {
4053 static const int increment_size = 0x100;
4054 const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
4055 unsigned int num_increments;
4056 uint16_t bits;
4057
4058 if (num_entries < increment_size)
4059 num_entries = increment_size;
4060 if (num_entries > fifo->max_segment_length)
4061 num_entries = fifo->max_segment_length;
4062
4063 /* 1 == 256 entries, 2 == 512 entries, etc */
4064 num_increments = (num_entries + increment_size / 2) / increment_size;
4065
4066 bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
4067 priv(dev)->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
4068 priv(dev)->fifo_size_bits |= bits;
4069 writew(priv(dev)->fifo_size_bits,
4070 priv(dev)->main_iobase + FIFO_SIZE_REG);
4071
4072 priv(dev)->ai_fifo_segment_length = num_increments * increment_size;
4073
4074 DEBUG_PRINT("set hardware fifo segment length to %i\n",
4075 priv(dev)->ai_fifo_segment_length);
4076
4077 return priv(dev)->ai_fifo_segment_length;
4078 }
4079
4080 /* pci-6025 8800 caldac:
4081 * address 0 == dac channel 0 offset
4082 * address 1 == dac channel 0 gain
4083 * address 2 == dac channel 1 offset
4084 * address 3 == dac channel 1 gain
4085 * address 4 == fine adc offset
4086 * address 5 == coarse adc offset
4087 * address 6 == coarse adc gain
4088 * address 7 == fine adc gain
4089 */
4090 /* pci-6402/16 uses all 8 channels for dac:
4091 * address 0 == dac channel 0 fine gain
4092 * address 1 == dac channel 0 coarse gain
4093 * address 2 == dac channel 0 coarse offset
4094 * address 3 == dac channel 1 coarse offset
4095 * address 4 == dac channel 1 fine gain
4096 * address 5 == dac channel 1 coarse gain
4097 * address 6 == dac channel 0 fine offset
4098 * address 7 == dac channel 1 fine offset
4099 */
4100
4101 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
4102 uint8_t value)
4103 {
4104 static const int num_caldac_channels = 8;
4105 static const int bitstream_length = 11;
4106 unsigned int bitstream = ((address & 0x7) << 8) | value;
4107 unsigned int bit, register_bits;
4108 static const int caldac_8800_udelay = 1;
4109
4110 if (address >= num_caldac_channels) {
4111 comedi_error(dev, "illegal caldac channel");
4112 return -1;
4113 }
4114 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
4115 register_bits = 0;
4116 if (bitstream & bit)
4117 register_bits |= SERIAL_DATA_IN_BIT;
4118 udelay(caldac_8800_udelay);
4119 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
4120 register_bits |= SERIAL_CLOCK_BIT;
4121 udelay(caldac_8800_udelay);
4122 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
4123 }
4124 udelay(caldac_8800_udelay);
4125 writew(SELECT_8800_BIT, priv(dev)->main_iobase + CALIBRATION_REG);
4126 udelay(caldac_8800_udelay);
4127 writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
4128 udelay(caldac_8800_udelay);
4129 return 0;
4130 }
4131
4132 /* 4020 caldacs */
4133 static int caldac_i2c_write(struct comedi_device *dev,
4134 unsigned int caldac_channel, unsigned int value)
4135 {
4136 uint8_t serial_bytes[3];
4137 uint8_t i2c_addr;
4138 enum pointer_bits {
4139 /* manual has gain and offset bits switched */
4140 OFFSET_0_2 = 0x1,
4141 GAIN_0_2 = 0x2,
4142 OFFSET_1_3 = 0x4,
4143 GAIN_1_3 = 0x8,
4144 };
4145 enum data_bits {
4146 NOT_CLEAR_REGISTERS = 0x20,
4147 };
4148
4149 switch (caldac_channel) {
4150 case 0: /* chan 0 offset */
4151 i2c_addr = CALDAC0_I2C_ADDR;
4152 serial_bytes[0] = OFFSET_0_2;
4153 break;
4154 case 1: /* chan 1 offset */
4155 i2c_addr = CALDAC0_I2C_ADDR;
4156 serial_bytes[0] = OFFSET_1_3;
4157 break;
4158 case 2: /* chan 2 offset */
4159 i2c_addr = CALDAC1_I2C_ADDR;
4160 serial_bytes[0] = OFFSET_0_2;
4161 break;
4162 case 3: /* chan 3 offset */
4163 i2c_addr = CALDAC1_I2C_ADDR;
4164 serial_bytes[0] = OFFSET_1_3;
4165 break;
4166 case 4: /* chan 0 gain */
4167 i2c_addr = CALDAC0_I2C_ADDR;
4168 serial_bytes[0] = GAIN_0_2;
4169 break;
4170 case 5: /* chan 1 gain */
4171 i2c_addr = CALDAC0_I2C_ADDR;
4172 serial_bytes[0] = GAIN_1_3;
4173 break;
4174 case 6: /* chan 2 gain */
4175 i2c_addr = CALDAC1_I2C_ADDR;
4176 serial_bytes[0] = GAIN_0_2;
4177 break;
4178 case 7: /* chan 3 gain */
4179 i2c_addr = CALDAC1_I2C_ADDR;
4180 serial_bytes[0] = GAIN_1_3;
4181 break;
4182 default:
4183 comedi_error(dev, "invalid caldac channel\n");
4184 return -1;
4185 break;
4186 }
4187 serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
4188 serial_bytes[2] = value & 0xff;
4189 i2c_write(dev, i2c_addr, serial_bytes, 3);
4190 return 0;
4191 }
4192
4193 /* Their i2c requires a huge delay on setting clock or data high for some reason */
4194 static const int i2c_high_udelay = 1000;
4195 static const int i2c_low_udelay = 10;
4196
4197 /* set i2c data line high or low */
4198 static void i2c_set_sda(struct comedi_device *dev, int state)
4199 {
4200 static const int data_bit = CTL_EE_W;
4201 void __iomem *plx_control_addr = priv(dev)->plx9080_iobase +
4202 PLX_CONTROL_REG;
4203
4204 if (state) {
4205 /* set data line high */
4206 priv(dev)->plx_control_bits &= ~data_bit;
4207 writel(priv(dev)->plx_control_bits, plx_control_addr);
4208 udelay(i2c_high_udelay);
4209 } else { /* set data line low */
4210
4211 priv(dev)->plx_control_bits |= data_bit;
4212 writel(priv(dev)->plx_control_bits, plx_control_addr);
4213 udelay(i2c_low_udelay);
4214 }
4215 }
4216
4217 /* set i2c clock line high or low */
4218 static void i2c_set_scl(struct comedi_device *dev, int state)
4219 {
4220 static const int clock_bit = CTL_USERO;
4221 void __iomem *plx_control_addr = priv(dev)->plx9080_iobase +
4222 PLX_CONTROL_REG;
4223
4224 if (state) {
4225 /* set clock line high */
4226 priv(dev)->plx_control_bits &= ~clock_bit;
4227 writel(priv(dev)->plx_control_bits, plx_control_addr);
4228 udelay(i2c_high_udelay);
4229 } else { /* set clock line low */
4230
4231 priv(dev)->plx_control_bits |= clock_bit;
4232 writel(priv(dev)->plx_control_bits, plx_control_addr);
4233 udelay(i2c_low_udelay);
4234 }
4235 }
4236
4237 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
4238 {
4239 uint8_t bit;
4240 unsigned int num_bits = 8;
4241
4242 DEBUG_PRINT("writing to i2c byte 0x%x\n", byte);
4243
4244 for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
4245 i2c_set_scl(dev, 0);
4246 if ((byte & bit))
4247 i2c_set_sda(dev, 1);
4248 else
4249 i2c_set_sda(dev, 0);
4250 i2c_set_scl(dev, 1);
4251 }
4252 }
4253
4254 /* we can't really read the lines, so fake it */
4255 static int i2c_read_ack(struct comedi_device *dev)
4256 {
4257 i2c_set_scl(dev, 0);
4258 i2c_set_sda(dev, 1);
4259 i2c_set_scl(dev, 1);
4260
4261 return 0; /* return fake acknowledge bit */
4262 }
4263
4264 /* send start bit */
4265 static void i2c_start(struct comedi_device *dev)
4266 {
4267 i2c_set_scl(dev, 1);
4268 i2c_set_sda(dev, 1);
4269 i2c_set_sda(dev, 0);
4270 }
4271
4272 /* send stop bit */
4273 static void i2c_stop(struct comedi_device *dev)
4274 {
4275 i2c_set_scl(dev, 0);
4276 i2c_set_sda(dev, 0);
4277 i2c_set_scl(dev, 1);
4278 i2c_set_sda(dev, 1);
4279 }
4280
4281 static void i2c_write(struct comedi_device *dev, unsigned int address,
4282 const uint8_t * data, unsigned int length)
4283 {
4284 unsigned int i;
4285 uint8_t bitstream;
4286 static const int read_bit = 0x1;
4287
4288 /* XXX need mutex to prevent simultaneous attempts to access eeprom and i2c bus */
4289
4290 /* make sure we dont send anything to eeprom */
4291 priv(dev)->plx_control_bits &= ~CTL_EE_CS;
4292
4293 i2c_stop(dev);
4294 i2c_start(dev);
4295
4296 /* send address and write bit */
4297 bitstream = (address << 1) & ~read_bit;
4298 i2c_write_byte(dev, bitstream);
4299
4300 /* get acknowledge */
4301 if (i2c_read_ack(dev) != 0) {
4302 comedi_error(dev, "i2c write failed: no acknowledge");
4303 i2c_stop(dev);
4304 return;
4305 }
4306 /* write data bytes */
4307 for (i = 0; i < length; i++) {
4308 i2c_write_byte(dev, data[i]);
4309 if (i2c_read_ack(dev) != 0) {
4310 comedi_error(dev, "i2c write failed: no acknowledge");
4311 i2c_stop(dev);
4312 return;
4313 }
4314 }
4315 i2c_stop(dev);
4316 }
4317
4318 MODULE_AUTHOR("Comedi http://www.comedi.org");
4319 MODULE_DESCRIPTION("Comedi low-level driver");
4320 MODULE_LICENSE("GPL");
Linus' kernel tree