2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
16 * Support functions for the OMAP internal DMA channels.
18 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
19 * Converted DMA library into DMA platform driver.
20 * - G, Manjunath Kondaiah <manjugk@ti.com>
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
39 #include <mach/hardware.h>
46 #ifndef CONFIG_ARCH_OMAP1
47 enum { DMA_CH_ALLOC_DONE
, DMA_CH_PARAMS_SET_DONE
, DMA_CH_STARTED
,
48 DMA_CH_QUEUED
, DMA_CH_NOTSTARTED
, DMA_CH_PAUSED
, DMA_CH_LINK_ENABLED
51 enum { DMA_CHAIN_STARTED
, DMA_CHAIN_NOTSTARTED
};
54 #define OMAP_DMA_ACTIVE 0x01
55 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
57 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
59 static struct omap_system_dma_plat_info
*p
;
60 static struct omap_dma_dev_attr
*d
;
62 static int enable_1510_mode
;
65 static struct omap_dma_global_context_registers
{
67 u32 dma_ocp_sysconfig
;
69 } omap_dma_global_context
;
71 struct dma_link_info
{
73 int no_of_lchs_linked
;
84 static struct dma_link_info
*dma_linked_lch
;
86 #ifndef CONFIG_ARCH_OMAP1
88 /* Chain handling macros */
89 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
91 dma_linked_lch[chain_id].q_head = \
92 dma_linked_lch[chain_id].q_tail = \
93 dma_linked_lch[chain_id].q_count = 0; \
95 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
96 (dma_linked_lch[chain_id].no_of_lchs_linked == \
97 dma_linked_lch[chain_id].q_count)
98 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
100 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
101 dma_linked_lch[chain_id].q_count) \
103 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
104 (0 == dma_linked_lch[chain_id].q_count)
105 #define __OMAP_DMA_CHAIN_INCQ(end) \
106 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
107 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
109 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
110 dma_linked_lch[chain_id].q_count--; \
113 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
115 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
116 dma_linked_lch[chain_id].q_count++; \
120 static int dma_lch_count
;
121 static int dma_chan_count
;
122 static int omap_dma_reserve_channels
;
124 static spinlock_t dma_chan_lock
;
125 static struct omap_dma_lch
*dma_chan
;
127 static inline void disable_lnk(int lch
);
128 static void omap_disable_channel_irq(int lch
);
129 static inline void omap_enable_channel_irq(int lch
);
131 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
134 #ifdef CONFIG_ARCH_OMAP15XX
135 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
136 static int omap_dma_in_1510_mode(void)
138 return enable_1510_mode
;
141 #define omap_dma_in_1510_mode() 0
144 #ifdef CONFIG_ARCH_OMAP1
145 static inline int get_gdma_dev(int req
)
147 u32 reg
= OMAP_FUNC_MUX_ARM_BASE
+ ((req
- 1) / 5) * 4;
148 int shift
= ((req
- 1) % 5) * 6;
150 return ((omap_readl(reg
) >> shift
) & 0x3f) + 1;
153 static inline void set_gdma_dev(int req
, int dev
)
155 u32 reg
= OMAP_FUNC_MUX_ARM_BASE
+ ((req
- 1) / 5) * 4;
156 int shift
= ((req
- 1) % 5) * 6;
160 l
&= ~(0x3f << shift
);
161 l
|= (dev
- 1) << shift
;
165 #define set_gdma_dev(req, dev) do {} while (0)
168 void omap_set_dma_priority(int lch
, int dst_port
, int priority
)
173 if (cpu_class_is_omap1()) {
175 case OMAP_DMA_PORT_OCP_T1
: /* FFFECC00 */
176 reg
= OMAP_TC_OCPT1_PRIOR
;
178 case OMAP_DMA_PORT_OCP_T2
: /* FFFECCD0 */
179 reg
= OMAP_TC_OCPT2_PRIOR
;
181 case OMAP_DMA_PORT_EMIFF
: /* FFFECC08 */
182 reg
= OMAP_TC_EMIFF_PRIOR
;
184 case OMAP_DMA_PORT_EMIFS
: /* FFFECC04 */
185 reg
= OMAP_TC_EMIFS_PRIOR
;
193 l
|= (priority
& 0xf) << 8;
197 if (cpu_class_is_omap2()) {
200 ccr
= p
->dma_read(CCR
, lch
);
205 p
->dma_write(ccr
, CCR
, lch
);
208 EXPORT_SYMBOL(omap_set_dma_priority
);
210 void omap_set_dma_transfer_params(int lch
, int data_type
, int elem_count
,
211 int frame_count
, int sync_mode
,
212 int dma_trigger
, int src_or_dst_synch
)
216 l
= p
->dma_read(CSDP
, lch
);
219 p
->dma_write(l
, CSDP
, lch
);
221 if (cpu_class_is_omap1()) {
224 ccr
= p
->dma_read(CCR
, lch
);
226 if (sync_mode
== OMAP_DMA_SYNC_FRAME
)
228 p
->dma_write(ccr
, CCR
, lch
);
230 ccr
= p
->dma_read(CCR2
, lch
);
232 if (sync_mode
== OMAP_DMA_SYNC_BLOCK
)
234 p
->dma_write(ccr
, CCR2
, lch
);
237 if (cpu_class_is_omap2() && dma_trigger
) {
240 val
= p
->dma_read(CCR
, lch
);
242 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
243 val
&= ~((1 << 23) | (3 << 19) | 0x1f);
244 val
|= (dma_trigger
& ~0x1f) << 14;
245 val
|= dma_trigger
& 0x1f;
247 if (sync_mode
& OMAP_DMA_SYNC_FRAME
)
252 if (sync_mode
& OMAP_DMA_SYNC_BLOCK
)
257 if (src_or_dst_synch
== OMAP_DMA_DST_SYNC_PREFETCH
) {
258 val
&= ~(1 << 24); /* dest synch */
259 val
|= (1 << 23); /* Prefetch */
260 } else if (src_or_dst_synch
) {
261 val
|= 1 << 24; /* source synch */
263 val
&= ~(1 << 24); /* dest synch */
265 p
->dma_write(val
, CCR
, lch
);
268 p
->dma_write(elem_count
, CEN
, lch
);
269 p
->dma_write(frame_count
, CFN
, lch
);
271 EXPORT_SYMBOL(omap_set_dma_transfer_params
);
273 void omap_set_dma_color_mode(int lch
, enum omap_dma_color_mode mode
, u32 color
)
275 BUG_ON(omap_dma_in_1510_mode());
277 if (cpu_class_is_omap1()) {
280 w
= p
->dma_read(CCR2
, lch
);
284 case OMAP_DMA_CONSTANT_FILL
:
287 case OMAP_DMA_TRANSPARENT_COPY
:
290 case OMAP_DMA_COLOR_DIS
:
295 p
->dma_write(w
, CCR2
, lch
);
297 w
= p
->dma_read(LCH_CTRL
, lch
);
299 /* Default is channel type 2D */
301 p
->dma_write(color
, COLOR
, lch
);
302 w
|= 1; /* Channel type G */
304 p
->dma_write(w
, LCH_CTRL
, lch
);
307 if (cpu_class_is_omap2()) {
310 val
= p
->dma_read(CCR
, lch
);
311 val
&= ~((1 << 17) | (1 << 16));
314 case OMAP_DMA_CONSTANT_FILL
:
317 case OMAP_DMA_TRANSPARENT_COPY
:
320 case OMAP_DMA_COLOR_DIS
:
325 p
->dma_write(val
, CCR
, lch
);
328 p
->dma_write(color
, COLOR
, lch
);
331 EXPORT_SYMBOL(omap_set_dma_color_mode
);
333 void omap_set_dma_write_mode(int lch
, enum omap_dma_write_mode mode
)
335 if (cpu_class_is_omap2()) {
338 csdp
= p
->dma_read(CSDP
, lch
);
339 csdp
&= ~(0x3 << 16);
340 csdp
|= (mode
<< 16);
341 p
->dma_write(csdp
, CSDP
, lch
);
344 EXPORT_SYMBOL(omap_set_dma_write_mode
);
346 void omap_set_dma_channel_mode(int lch
, enum omap_dma_channel_mode mode
)
348 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
351 l
= p
->dma_read(LCH_CTRL
, lch
);
354 p
->dma_write(l
, LCH_CTRL
, lch
);
357 EXPORT_SYMBOL(omap_set_dma_channel_mode
);
359 /* Note that src_port is only for omap1 */
360 void omap_set_dma_src_params(int lch
, int src_port
, int src_amode
,
361 unsigned long src_start
,
362 int src_ei
, int src_fi
)
366 if (cpu_class_is_omap1()) {
369 w
= p
->dma_read(CSDP
, lch
);
372 p
->dma_write(w
, CSDP
, lch
);
375 l
= p
->dma_read(CCR
, lch
);
377 l
|= src_amode
<< 12;
378 p
->dma_write(l
, CCR
, lch
);
380 p
->dma_write(src_start
, CSSA
, lch
);
382 p
->dma_write(src_ei
, CSEI
, lch
);
383 p
->dma_write(src_fi
, CSFI
, lch
);
385 EXPORT_SYMBOL(omap_set_dma_src_params
);
387 void omap_set_dma_params(int lch
, struct omap_dma_channel_params
*params
)
389 omap_set_dma_transfer_params(lch
, params
->data_type
,
390 params
->elem_count
, params
->frame_count
,
391 params
->sync_mode
, params
->trigger
,
392 params
->src_or_dst_synch
);
393 omap_set_dma_src_params(lch
, params
->src_port
,
394 params
->src_amode
, params
->src_start
,
395 params
->src_ei
, params
->src_fi
);
397 omap_set_dma_dest_params(lch
, params
->dst_port
,
398 params
->dst_amode
, params
->dst_start
,
399 params
->dst_ei
, params
->dst_fi
);
400 if (params
->read_prio
|| params
->write_prio
)
401 omap_dma_set_prio_lch(lch
, params
->read_prio
,
404 EXPORT_SYMBOL(omap_set_dma_params
);
406 void omap_set_dma_src_index(int lch
, int eidx
, int fidx
)
408 if (cpu_class_is_omap2())
411 p
->dma_write(eidx
, CSEI
, lch
);
412 p
->dma_write(fidx
, CSFI
, lch
);
414 EXPORT_SYMBOL(omap_set_dma_src_index
);
416 void omap_set_dma_src_data_pack(int lch
, int enable
)
420 l
= p
->dma_read(CSDP
, lch
);
424 p
->dma_write(l
, CSDP
, lch
);
426 EXPORT_SYMBOL(omap_set_dma_src_data_pack
);
428 void omap_set_dma_src_burst_mode(int lch
, enum omap_dma_burst_mode burst_mode
)
430 unsigned int burst
= 0;
433 l
= p
->dma_read(CSDP
, lch
);
436 switch (burst_mode
) {
437 case OMAP_DMA_DATA_BURST_DIS
:
439 case OMAP_DMA_DATA_BURST_4
:
440 if (cpu_class_is_omap2())
445 case OMAP_DMA_DATA_BURST_8
:
446 if (cpu_class_is_omap2()) {
451 * not supported by current hardware on OMAP1
455 case OMAP_DMA_DATA_BURST_16
:
456 if (cpu_class_is_omap2()) {
461 * OMAP1 don't support burst 16
469 p
->dma_write(l
, CSDP
, lch
);
471 EXPORT_SYMBOL(omap_set_dma_src_burst_mode
);
473 /* Note that dest_port is only for OMAP1 */
474 void omap_set_dma_dest_params(int lch
, int dest_port
, int dest_amode
,
475 unsigned long dest_start
,
476 int dst_ei
, int dst_fi
)
480 if (cpu_class_is_omap1()) {
481 l
= p
->dma_read(CSDP
, lch
);
484 p
->dma_write(l
, CSDP
, lch
);
487 l
= p
->dma_read(CCR
, lch
);
489 l
|= dest_amode
<< 14;
490 p
->dma_write(l
, CCR
, lch
);
492 p
->dma_write(dest_start
, CDSA
, lch
);
494 p
->dma_write(dst_ei
, CDEI
, lch
);
495 p
->dma_write(dst_fi
, CDFI
, lch
);
497 EXPORT_SYMBOL(omap_set_dma_dest_params
);
499 void omap_set_dma_dest_index(int lch
, int eidx
, int fidx
)
501 if (cpu_class_is_omap2())
504 p
->dma_write(eidx
, CDEI
, lch
);
505 p
->dma_write(fidx
, CDFI
, lch
);
507 EXPORT_SYMBOL(omap_set_dma_dest_index
);
509 void omap_set_dma_dest_data_pack(int lch
, int enable
)
513 l
= p
->dma_read(CSDP
, lch
);
517 p
->dma_write(l
, CSDP
, lch
);
519 EXPORT_SYMBOL(omap_set_dma_dest_data_pack
);
521 void omap_set_dma_dest_burst_mode(int lch
, enum omap_dma_burst_mode burst_mode
)
523 unsigned int burst
= 0;
526 l
= p
->dma_read(CSDP
, lch
);
529 switch (burst_mode
) {
530 case OMAP_DMA_DATA_BURST_DIS
:
532 case OMAP_DMA_DATA_BURST_4
:
533 if (cpu_class_is_omap2())
538 case OMAP_DMA_DATA_BURST_8
:
539 if (cpu_class_is_omap2())
544 case OMAP_DMA_DATA_BURST_16
:
545 if (cpu_class_is_omap2()) {
550 * OMAP1 don't support burst 16
554 printk(KERN_ERR
"Invalid DMA burst mode\n");
559 p
->dma_write(l
, CSDP
, lch
);
561 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode
);
563 static inline void omap_enable_channel_irq(int lch
)
568 if (cpu_class_is_omap1())
569 status
= p
->dma_read(CSR
, lch
);
570 else if (cpu_class_is_omap2())
571 p
->dma_write(OMAP2_DMA_CSR_CLEAR_MASK
, CSR
, lch
);
573 /* Enable some nice interrupts. */
574 p
->dma_write(dma_chan
[lch
].enabled_irqs
, CICR
, lch
);
577 static void omap_disable_channel_irq(int lch
)
579 if (cpu_class_is_omap2())
580 p
->dma_write(0, CICR
, lch
);
583 void omap_enable_dma_irq(int lch
, u16 bits
)
585 dma_chan
[lch
].enabled_irqs
|= bits
;
587 EXPORT_SYMBOL(omap_enable_dma_irq
);
589 void omap_disable_dma_irq(int lch
, u16 bits
)
591 dma_chan
[lch
].enabled_irqs
&= ~bits
;
593 EXPORT_SYMBOL(omap_disable_dma_irq
);
595 static inline void enable_lnk(int lch
)
599 l
= p
->dma_read(CLNK_CTRL
, lch
);
601 if (cpu_class_is_omap1())
604 /* Set the ENABLE_LNK bits */
605 if (dma_chan
[lch
].next_lch
!= -1)
606 l
= dma_chan
[lch
].next_lch
| (1 << 15);
608 #ifndef CONFIG_ARCH_OMAP1
609 if (cpu_class_is_omap2())
610 if (dma_chan
[lch
].next_linked_ch
!= -1)
611 l
= dma_chan
[lch
].next_linked_ch
| (1 << 15);
614 p
->dma_write(l
, CLNK_CTRL
, lch
);
617 static inline void disable_lnk(int lch
)
621 l
= p
->dma_read(CLNK_CTRL
, lch
);
623 /* Disable interrupts */
624 if (cpu_class_is_omap1()) {
625 p
->dma_write(0, CICR
, lch
);
626 /* Set the STOP_LNK bit */
630 if (cpu_class_is_omap2()) {
631 omap_disable_channel_irq(lch
);
632 /* Clear the ENABLE_LNK bit */
636 p
->dma_write(l
, CLNK_CTRL
, lch
);
637 dma_chan
[lch
].flags
&= ~OMAP_DMA_ACTIVE
;
640 static inline void omap2_enable_irq_lch(int lch
)
645 if (!cpu_class_is_omap2())
648 spin_lock_irqsave(&dma_chan_lock
, flags
);
649 val
= p
->dma_read(IRQENABLE_L0
, lch
);
651 p
->dma_write(val
, IRQENABLE_L0
, lch
);
652 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
655 static inline void omap2_disable_irq_lch(int lch
)
660 if (!cpu_class_is_omap2())
663 spin_lock_irqsave(&dma_chan_lock
, flags
);
664 val
= p
->dma_read(IRQENABLE_L0
, lch
);
666 p
->dma_write(val
, IRQENABLE_L0
, lch
);
667 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
670 int omap_request_dma(int dev_id
, const char *dev_name
,
671 void (*callback
)(int lch
, u16 ch_status
, void *data
),
672 void *data
, int *dma_ch_out
)
674 int ch
, free_ch
= -1;
676 struct omap_dma_lch
*chan
;
678 spin_lock_irqsave(&dma_chan_lock
, flags
);
679 for (ch
= 0; ch
< dma_chan_count
; ch
++) {
680 if (free_ch
== -1 && dma_chan
[ch
].dev_id
== -1) {
687 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
690 chan
= dma_chan
+ free_ch
;
691 chan
->dev_id
= dev_id
;
693 if (p
->clear_lch_regs
)
694 p
->clear_lch_regs(free_ch
);
696 if (cpu_class_is_omap2())
697 omap_clear_dma(free_ch
);
699 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
701 chan
->dev_name
= dev_name
;
702 chan
->callback
= callback
;
706 #ifndef CONFIG_ARCH_OMAP1
707 if (cpu_class_is_omap2()) {
709 chan
->next_linked_ch
= -1;
713 chan
->enabled_irqs
= OMAP_DMA_DROP_IRQ
| OMAP_DMA_BLOCK_IRQ
;
715 if (cpu_class_is_omap1())
716 chan
->enabled_irqs
|= OMAP1_DMA_TOUT_IRQ
;
717 else if (cpu_class_is_omap2())
718 chan
->enabled_irqs
|= OMAP2_DMA_MISALIGNED_ERR_IRQ
|
719 OMAP2_DMA_TRANS_ERR_IRQ
;
721 if (cpu_is_omap16xx()) {
722 /* If the sync device is set, configure it dynamically. */
724 set_gdma_dev(free_ch
+ 1, dev_id
);
725 dev_id
= free_ch
+ 1;
728 * Disable the 1510 compatibility mode and set the sync device
731 p
->dma_write(dev_id
| (1 << 10), CCR
, free_ch
);
732 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
733 p
->dma_write(dev_id
, CCR
, free_ch
);
736 if (cpu_class_is_omap2()) {
737 omap2_enable_irq_lch(free_ch
);
738 omap_enable_channel_irq(free_ch
);
739 /* Clear the CSR register and IRQ status register */
740 p
->dma_write(OMAP2_DMA_CSR_CLEAR_MASK
, CSR
, free_ch
);
741 p
->dma_write(1 << free_ch
, IRQSTATUS_L0
, 0);
744 *dma_ch_out
= free_ch
;
748 EXPORT_SYMBOL(omap_request_dma
);
750 void omap_free_dma(int lch
)
754 if (dma_chan
[lch
].dev_id
== -1) {
755 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
760 if (cpu_class_is_omap1()) {
761 /* Disable all DMA interrupts for the channel. */
762 p
->dma_write(0, CICR
, lch
);
763 /* Make sure the DMA transfer is stopped. */
764 p
->dma_write(0, CCR
, lch
);
767 if (cpu_class_is_omap2()) {
768 omap2_disable_irq_lch(lch
);
770 /* Clear the CSR register and IRQ status register */
771 p
->dma_write(OMAP2_DMA_CSR_CLEAR_MASK
, CSR
, lch
);
772 p
->dma_write(1 << lch
, IRQSTATUS_L0
, lch
);
774 /* Disable all DMA interrupts for the channel. */
775 p
->dma_write(0, CICR
, lch
);
777 /* Make sure the DMA transfer is stopped. */
778 p
->dma_write(0, CCR
, lch
);
782 spin_lock_irqsave(&dma_chan_lock
, flags
);
783 dma_chan
[lch
].dev_id
= -1;
784 dma_chan
[lch
].next_lch
= -1;
785 dma_chan
[lch
].callback
= NULL
;
786 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
788 EXPORT_SYMBOL(omap_free_dma
);
791 * @brief omap_dma_set_global_params : Set global priority settings for dma
794 * @param max_fifo_depth
795 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
796 * DMA_THREAD_RESERVE_ONET
797 * DMA_THREAD_RESERVE_TWOT
798 * DMA_THREAD_RESERVE_THREET
801 omap_dma_set_global_params(int arb_rate
, int max_fifo_depth
, int tparams
)
805 if (!cpu_class_is_omap2()) {
806 printk(KERN_ERR
"FIXME: no %s on 15xx/16xx\n", __func__
);
810 if (max_fifo_depth
== 0)
815 reg
= 0xff & max_fifo_depth
;
816 reg
|= (0x3 & tparams
) << 12;
817 reg
|= (arb_rate
& 0xff) << 16;
819 p
->dma_write(reg
, GCR
, 0);
821 EXPORT_SYMBOL(omap_dma_set_global_params
);
824 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
827 * @param read_prio - Read priority
828 * @param write_prio - Write priority
829 * Both of the above can be set with one of the following values :
830 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
833 omap_dma_set_prio_lch(int lch
, unsigned char read_prio
,
834 unsigned char write_prio
)
838 if (unlikely((lch
< 0 || lch
>= dma_lch_count
))) {
839 printk(KERN_ERR
"Invalid channel id\n");
842 l
= p
->dma_read(CCR
, lch
);
843 l
&= ~((1 << 6) | (1 << 26));
844 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
845 l
|= ((read_prio
& 0x1) << 6) | ((write_prio
& 0x1) << 26);
847 l
|= ((read_prio
& 0x1) << 6);
849 p
->dma_write(l
, CCR
, lch
);
853 EXPORT_SYMBOL(omap_dma_set_prio_lch
);
856 * Clears any DMA state so the DMA engine is ready to restart with new buffers
857 * through omap_start_dma(). Any buffers in flight are discarded.
859 void omap_clear_dma(int lch
)
863 local_irq_save(flags
);
865 local_irq_restore(flags
);
867 EXPORT_SYMBOL(omap_clear_dma
);
869 void omap_start_dma(int lch
)
874 * The CPC/CDAC register needs to be initialized to zero
875 * before starting dma transfer.
877 if (cpu_is_omap15xx())
878 p
->dma_write(0, CPC
, lch
);
880 p
->dma_write(0, CDAC
, lch
);
882 if (!omap_dma_in_1510_mode() && dma_chan
[lch
].next_lch
!= -1) {
883 int next_lch
, cur_lch
;
884 char dma_chan_link_map
[dma_lch_count
];
886 dma_chan_link_map
[lch
] = 1;
887 /* Set the link register of the first channel */
890 memset(dma_chan_link_map
, 0, sizeof(dma_chan_link_map
));
891 cur_lch
= dma_chan
[lch
].next_lch
;
893 next_lch
= dma_chan
[cur_lch
].next_lch
;
895 /* The loop case: we've been here already */
896 if (dma_chan_link_map
[cur_lch
])
898 /* Mark the current channel */
899 dma_chan_link_map
[cur_lch
] = 1;
902 omap_enable_channel_irq(cur_lch
);
905 } while (next_lch
!= -1);
906 } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS
))
907 p
->dma_write(lch
, CLNK_CTRL
, lch
);
909 omap_enable_channel_irq(lch
);
911 l
= p
->dma_read(CCR
, lch
);
913 if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING
))
914 l
|= OMAP_DMA_CCR_BUFFERING_DISABLE
;
915 l
|= OMAP_DMA_CCR_EN
;
917 p
->dma_write(l
, CCR
, lch
);
919 dma_chan
[lch
].flags
|= OMAP_DMA_ACTIVE
;
921 EXPORT_SYMBOL(omap_start_dma
);
923 void omap_stop_dma(int lch
)
927 /* Disable all interrupts on the channel */
928 if (cpu_class_is_omap1())
929 p
->dma_write(0, CICR
, lch
);
931 l
= p
->dma_read(CCR
, lch
);
932 if (IS_DMA_ERRATA(DMA_ERRATA_i541
) &&
933 (l
& OMAP_DMA_CCR_SEL_SRC_DST_SYNC
)) {
937 /* Configure No-Standby */
938 l
= p
->dma_read(OCP_SYSCONFIG
, lch
);
940 l
&= ~DMA_SYSCONFIG_MIDLEMODE_MASK
;
941 l
|= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE
);
942 p
->dma_write(l
, OCP_SYSCONFIG
, 0);
944 l
= p
->dma_read(CCR
, lch
);
945 l
&= ~OMAP_DMA_CCR_EN
;
946 p
->dma_write(l
, CCR
, lch
);
948 /* Wait for sDMA FIFO drain */
949 l
= p
->dma_read(CCR
, lch
);
950 while (i
< 100 && (l
& (OMAP_DMA_CCR_RD_ACTIVE
|
951 OMAP_DMA_CCR_WR_ACTIVE
))) {
954 l
= p
->dma_read(CCR
, lch
);
957 printk(KERN_ERR
"DMA drain did not complete on "
959 /* Restore OCP_SYSCONFIG */
960 p
->dma_write(sys_cf
, OCP_SYSCONFIG
, lch
);
962 l
&= ~OMAP_DMA_CCR_EN
;
963 p
->dma_write(l
, CCR
, lch
);
966 if (!omap_dma_in_1510_mode() && dma_chan
[lch
].next_lch
!= -1) {
967 int next_lch
, cur_lch
= lch
;
968 char dma_chan_link_map
[dma_lch_count
];
970 memset(dma_chan_link_map
, 0, sizeof(dma_chan_link_map
));
972 /* The loop case: we've been here already */
973 if (dma_chan_link_map
[cur_lch
])
975 /* Mark the current channel */
976 dma_chan_link_map
[cur_lch
] = 1;
978 disable_lnk(cur_lch
);
980 next_lch
= dma_chan
[cur_lch
].next_lch
;
982 } while (next_lch
!= -1);
985 dma_chan
[lch
].flags
&= ~OMAP_DMA_ACTIVE
;
987 EXPORT_SYMBOL(omap_stop_dma
);
990 * Allows changing the DMA callback function or data. This may be needed if
991 * the driver shares a single DMA channel for multiple dma triggers.
993 int omap_set_dma_callback(int lch
,
994 void (*callback
)(int lch
, u16 ch_status
, void *data
),
1002 spin_lock_irqsave(&dma_chan_lock
, flags
);
1003 if (dma_chan
[lch
].dev_id
== -1) {
1004 printk(KERN_ERR
"DMA callback for not set for free channel\n");
1005 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
1008 dma_chan
[lch
].callback
= callback
;
1009 dma_chan
[lch
].data
= data
;
1010 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
1014 EXPORT_SYMBOL(omap_set_dma_callback
);
1017 * Returns current physical source address for the given DMA channel.
1018 * If the channel is running the caller must disable interrupts prior calling
1019 * this function and process the returned value before re-enabling interrupt to
1020 * prevent races with the interrupt handler. Note that in continuous mode there
1021 * is a chance for CSSA_L register overflow between the two reads resulting
1022 * in incorrect return value.
1024 dma_addr_t
omap_get_dma_src_pos(int lch
)
1026 dma_addr_t offset
= 0;
1028 if (cpu_is_omap15xx())
1029 offset
= p
->dma_read(CPC
, lch
);
1031 offset
= p
->dma_read(CSAC
, lch
);
1033 if (IS_DMA_ERRATA(DMA_ERRATA_3_3
) && offset
== 0)
1034 offset
= p
->dma_read(CSAC
, lch
);
1036 if (!cpu_is_omap15xx()) {
1038 * CDAC == 0 indicates that the DMA transfer on the channel has
1039 * not been started (no data has been transferred so far).
1040 * Return the programmed source start address in this case.
1042 if (likely(p
->dma_read(CDAC
, lch
)))
1043 offset
= p
->dma_read(CSAC
, lch
);
1045 offset
= p
->dma_read(CSSA
, lch
);
1048 if (cpu_class_is_omap1())
1049 offset
|= (p
->dma_read(CSSA
, lch
) & 0xFFFF0000);
1053 EXPORT_SYMBOL(omap_get_dma_src_pos
);
1056 * Returns current physical destination address for the given DMA channel.
1057 * If the channel is running the caller must disable interrupts prior calling
1058 * this function and process the returned value before re-enabling interrupt to
1059 * prevent races with the interrupt handler. Note that in continuous mode there
1060 * is a chance for CDSA_L register overflow between the two reads resulting
1061 * in incorrect return value.
1063 dma_addr_t
omap_get_dma_dst_pos(int lch
)
1065 dma_addr_t offset
= 0;
1067 if (cpu_is_omap15xx())
1068 offset
= p
->dma_read(CPC
, lch
);
1070 offset
= p
->dma_read(CDAC
, lch
);
1073 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1074 * read before the DMA controller finished disabling the channel.
1076 if (!cpu_is_omap15xx() && offset
== 0) {
1077 offset
= p
->dma_read(CDAC
, lch
);
1079 * CDAC == 0 indicates that the DMA transfer on the channel has
1080 * not been started (no data has been transferred so far).
1081 * Return the programmed destination start address in this case.
1083 if (unlikely(!offset
))
1084 offset
= p
->dma_read(CDSA
, lch
);
1087 if (cpu_class_is_omap1())
1088 offset
|= (p
->dma_read(CDSA
, lch
) & 0xFFFF0000);
1092 EXPORT_SYMBOL(omap_get_dma_dst_pos
);
1094 int omap_get_dma_active_status(int lch
)
1096 return (p
->dma_read(CCR
, lch
) & OMAP_DMA_CCR_EN
) != 0;
1098 EXPORT_SYMBOL(omap_get_dma_active_status
);
1100 int omap_dma_running(void)
1104 if (cpu_class_is_omap1())
1105 if (omap_lcd_dma_running())
1108 for (lch
= 0; lch
< dma_chan_count
; lch
++)
1109 if (p
->dma_read(CCR
, lch
) & OMAP_DMA_CCR_EN
)
1116 * lch_queue DMA will start right after lch_head one is finished.
1117 * For this DMA link to start, you still need to start (see omap_start_dma)
1118 * the first one. That will fire up the entire queue.
1120 void omap_dma_link_lch(int lch_head
, int lch_queue
)
1122 if (omap_dma_in_1510_mode()) {
1123 if (lch_head
== lch_queue
) {
1124 p
->dma_write(p
->dma_read(CCR
, lch_head
) | (3 << 8),
1128 printk(KERN_ERR
"DMA linking is not supported in 1510 mode\n");
1133 if ((dma_chan
[lch_head
].dev_id
== -1) ||
1134 (dma_chan
[lch_queue
].dev_id
== -1)) {
1135 printk(KERN_ERR
"omap_dma: trying to link "
1136 "non requested channels\n");
1140 dma_chan
[lch_head
].next_lch
= lch_queue
;
1142 EXPORT_SYMBOL(omap_dma_link_lch
);
1145 * Once the DMA queue is stopped, we can destroy it.
1147 void omap_dma_unlink_lch(int lch_head
, int lch_queue
)
1149 if (omap_dma_in_1510_mode()) {
1150 if (lch_head
== lch_queue
) {
1151 p
->dma_write(p
->dma_read(CCR
, lch_head
) & ~(3 << 8),
1155 printk(KERN_ERR
"DMA linking is not supported in 1510 mode\n");
1160 if (dma_chan
[lch_head
].next_lch
!= lch_queue
||
1161 dma_chan
[lch_head
].next_lch
== -1) {
1162 printk(KERN_ERR
"omap_dma: trying to unlink "
1163 "non linked channels\n");
1167 if ((dma_chan
[lch_head
].flags
& OMAP_DMA_ACTIVE
) ||
1168 (dma_chan
[lch_queue
].flags
& OMAP_DMA_ACTIVE
)) {
1169 printk(KERN_ERR
"omap_dma: You need to stop the DMA channels "
1170 "before unlinking\n");
1174 dma_chan
[lch_head
].next_lch
= -1;
1176 EXPORT_SYMBOL(omap_dma_unlink_lch
);
1178 #ifndef CONFIG_ARCH_OMAP1
1179 /* Create chain of DMA channesls */
1180 static void create_dma_lch_chain(int lch_head
, int lch_queue
)
1184 /* Check if this is the first link in chain */
1185 if (dma_chan
[lch_head
].next_linked_ch
== -1) {
1186 dma_chan
[lch_head
].next_linked_ch
= lch_queue
;
1187 dma_chan
[lch_head
].prev_linked_ch
= lch_queue
;
1188 dma_chan
[lch_queue
].next_linked_ch
= lch_head
;
1189 dma_chan
[lch_queue
].prev_linked_ch
= lch_head
;
1192 /* a link exists, link the new channel in circular chain */
1194 dma_chan
[lch_queue
].next_linked_ch
=
1195 dma_chan
[lch_head
].next_linked_ch
;
1196 dma_chan
[lch_queue
].prev_linked_ch
= lch_head
;
1197 dma_chan
[lch_head
].next_linked_ch
= lch_queue
;
1198 dma_chan
[dma_chan
[lch_queue
].next_linked_ch
].prev_linked_ch
=
1202 l
= p
->dma_read(CLNK_CTRL
, lch_head
);
1205 p
->dma_write(l
, CLNK_CTRL
, lch_head
);
1207 l
= p
->dma_read(CLNK_CTRL
, lch_queue
);
1209 l
|= (dma_chan
[lch_queue
].next_linked_ch
);
1210 p
->dma_write(l
, CLNK_CTRL
, lch_queue
);
1214 * @brief omap_request_dma_chain : Request a chain of DMA channels
1216 * @param dev_id - Device id using the dma channel
1217 * @param dev_name - Device name
1218 * @param callback - Call back function
1220 * @no_of_chans - Number of channels requested
1221 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1222 * OMAP_DMA_DYNAMIC_CHAIN
1223 * @params - Channel parameters
1225 * @return - Success : 0
1226 * Failure: -EINVAL/-ENOMEM
1228 int omap_request_dma_chain(int dev_id
, const char *dev_name
,
1229 void (*callback
) (int lch
, u16 ch_status
,
1231 int *chain_id
, int no_of_chans
, int chain_mode
,
1232 struct omap_dma_channel_params params
)
1237 /* Is the chain mode valid ? */
1238 if (chain_mode
!= OMAP_DMA_STATIC_CHAIN
1239 && chain_mode
!= OMAP_DMA_DYNAMIC_CHAIN
) {
1240 printk(KERN_ERR
"Invalid chain mode requested\n");
1244 if (unlikely((no_of_chans
< 1
1245 || no_of_chans
> dma_lch_count
))) {
1246 printk(KERN_ERR
"Invalid Number of channels requested\n");
1251 * Allocate a queue to maintain the status of the channels
1254 channels
= kmalloc(sizeof(*channels
) * no_of_chans
, GFP_KERNEL
);
1255 if (channels
== NULL
) {
1256 printk(KERN_ERR
"omap_dma: No memory for channel queue\n");
1260 /* request and reserve DMA channels for the chain */
1261 for (i
= 0; i
< no_of_chans
; i
++) {
1262 err
= omap_request_dma(dev_id
, dev_name
,
1263 callback
, NULL
, &channels
[i
]);
1266 for (j
= 0; j
< i
; j
++)
1267 omap_free_dma(channels
[j
]);
1269 printk(KERN_ERR
"omap_dma: Request failed %d\n", err
);
1272 dma_chan
[channels
[i
]].prev_linked_ch
= -1;
1273 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1276 * Allowing client drivers to set common parameters now,
1277 * so that later only relevant (src_start, dest_start
1278 * and element count) can be set
1280 omap_set_dma_params(channels
[i
], ¶ms
);
1283 *chain_id
= channels
[0];
1284 dma_linked_lch
[*chain_id
].linked_dmach_q
= channels
;
1285 dma_linked_lch
[*chain_id
].chain_mode
= chain_mode
;
1286 dma_linked_lch
[*chain_id
].chain_state
= DMA_CHAIN_NOTSTARTED
;
1287 dma_linked_lch
[*chain_id
].no_of_lchs_linked
= no_of_chans
;
1289 for (i
= 0; i
< no_of_chans
; i
++)
1290 dma_chan
[channels
[i
]].chain_id
= *chain_id
;
1292 /* Reset the Queue pointers */
1293 OMAP_DMA_CHAIN_QINIT(*chain_id
);
1295 /* Set up the chain */
1296 if (no_of_chans
== 1)
1297 create_dma_lch_chain(channels
[0], channels
[0]);
1299 for (i
= 0; i
< (no_of_chans
- 1); i
++)
1300 create_dma_lch_chain(channels
[i
], channels
[i
+ 1]);
1305 EXPORT_SYMBOL(omap_request_dma_chain
);
1308 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1309 * params after setting it. Dont do this while dma is running!!
1311 * @param chain_id - Chained logical channel id.
1314 * @return - Success : 0
1317 int omap_modify_dma_chain_params(int chain_id
,
1318 struct omap_dma_channel_params params
)
1323 /* Check for input params */
1324 if (unlikely((chain_id
< 0
1325 || chain_id
>= dma_lch_count
))) {
1326 printk(KERN_ERR
"Invalid chain id\n");
1330 /* Check if the chain exists */
1331 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1332 printk(KERN_ERR
"Chain doesn't exists\n");
1335 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1337 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1339 * Allowing client drivers to set common parameters now,
1340 * so that later only relevant (src_start, dest_start
1341 * and element count) can be set
1343 omap_set_dma_params(channels
[i
], ¶ms
);
1348 EXPORT_SYMBOL(omap_modify_dma_chain_params
);
1351 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1355 * @return - Success : 0
1358 int omap_free_dma_chain(int chain_id
)
1363 /* Check for input params */
1364 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1365 printk(KERN_ERR
"Invalid chain id\n");
1369 /* Check if the chain exists */
1370 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1371 printk(KERN_ERR
"Chain doesn't exists\n");
1375 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1376 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1377 dma_chan
[channels
[i
]].next_linked_ch
= -1;
1378 dma_chan
[channels
[i
]].prev_linked_ch
= -1;
1379 dma_chan
[channels
[i
]].chain_id
= -1;
1380 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1381 omap_free_dma(channels
[i
]);
1386 dma_linked_lch
[chain_id
].linked_dmach_q
= NULL
;
1387 dma_linked_lch
[chain_id
].chain_mode
= -1;
1388 dma_linked_lch
[chain_id
].chain_state
= -1;
1392 EXPORT_SYMBOL(omap_free_dma_chain
);
1395 * @brief omap_dma_chain_status - Check if the chain is in
1396 * active / inactive state.
1399 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1402 int omap_dma_chain_status(int chain_id
)
1404 /* Check for input params */
1405 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1406 printk(KERN_ERR
"Invalid chain id\n");
1410 /* Check if the chain exists */
1411 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1412 printk(KERN_ERR
"Chain doesn't exists\n");
1415 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id
,
1416 dma_linked_lch
[chain_id
].q_count
);
1418 if (OMAP_DMA_CHAIN_QEMPTY(chain_id
))
1419 return OMAP_DMA_CHAIN_INACTIVE
;
1421 return OMAP_DMA_CHAIN_ACTIVE
;
1423 EXPORT_SYMBOL(omap_dma_chain_status
);
1426 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1427 * set the params and start the transfer.
1430 * @param src_start - buffer start address
1431 * @param dest_start - Dest address
1433 * @param frame_count
1434 * @param callbk_data - channel callback parameter data.
1436 * @return - Success : 0
1437 * Failure: -EINVAL/-EBUSY
1439 int omap_dma_chain_a_transfer(int chain_id
, int src_start
, int dest_start
,
1440 int elem_count
, int frame_count
, void *callbk_data
)
1447 * if buffer size is less than 1 then there is
1448 * no use of starting the chain
1450 if (elem_count
< 1) {
1451 printk(KERN_ERR
"Invalid buffer size\n");
1455 /* Check for input params */
1456 if (unlikely((chain_id
< 0
1457 || chain_id
>= dma_lch_count
))) {
1458 printk(KERN_ERR
"Invalid chain id\n");
1462 /* Check if the chain exists */
1463 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1464 printk(KERN_ERR
"Chain doesn't exist\n");
1468 /* Check if all the channels in chain are in use */
1469 if (OMAP_DMA_CHAIN_QFULL(chain_id
))
1472 /* Frame count may be negative in case of indexed transfers */
1473 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1475 /* Get a free channel */
1476 lch
= channels
[dma_linked_lch
[chain_id
].q_tail
];
1478 /* Store the callback data */
1479 dma_chan
[lch
].data
= callbk_data
;
1481 /* Increment the q_tail */
1482 OMAP_DMA_CHAIN_INCQTAIL(chain_id
);
1484 /* Set the params to the free channel */
1486 p
->dma_write(src_start
, CSSA
, lch
);
1487 if (dest_start
!= 0)
1488 p
->dma_write(dest_start
, CDSA
, lch
);
1490 /* Write the buffer size */
1491 p
->dma_write(elem_count
, CEN
, lch
);
1492 p
->dma_write(frame_count
, CFN
, lch
);
1495 * If the chain is dynamically linked,
1496 * then we may have to start the chain if its not active
1498 if (dma_linked_lch
[chain_id
].chain_mode
== OMAP_DMA_DYNAMIC_CHAIN
) {
1501 * In Dynamic chain, if the chain is not started,
1504 if (dma_linked_lch
[chain_id
].chain_state
==
1505 DMA_CHAIN_NOTSTARTED
) {
1506 /* Enable the link in previous channel */
1507 if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
==
1509 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1510 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1514 * Chain is already started, make sure its active,
1515 * if not then start the chain
1520 if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
==
1522 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1523 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1525 if (0 == ((1 << 7) & p
->dma_read(
1526 CCR
, dma_chan
[lch
].prev_linked_ch
))) {
1527 disable_lnk(dma_chan
[lch
].
1529 pr_debug("\n prev ch is stopped\n");
1534 else if (dma_chan
[dma_chan
[lch
].prev_linked_ch
].state
1536 enable_lnk(dma_chan
[lch
].prev_linked_ch
);
1537 dma_chan
[lch
].state
= DMA_CH_QUEUED
;
1540 omap_enable_channel_irq(lch
);
1542 l
= p
->dma_read(CCR
, lch
);
1544 if ((0 == (l
& (1 << 24))))
1548 if (start_dma
== 1) {
1549 if (0 == (l
& (1 << 7))) {
1551 dma_chan
[lch
].state
= DMA_CH_STARTED
;
1552 pr_debug("starting %d\n", lch
);
1553 p
->dma_write(l
, CCR
, lch
);
1557 if (0 == (l
& (1 << 7)))
1558 p
->dma_write(l
, CCR
, lch
);
1560 dma_chan
[lch
].flags
|= OMAP_DMA_ACTIVE
;
1566 EXPORT_SYMBOL(omap_dma_chain_a_transfer
);
1569 * @brief omap_start_dma_chain_transfers - Start the chain
1573 * @return - Success : 0
1574 * Failure : -EINVAL/-EBUSY
1576 int omap_start_dma_chain_transfers(int chain_id
)
1581 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1582 printk(KERN_ERR
"Invalid chain id\n");
1586 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1588 if (dma_linked_lch
[channels
[0]].chain_state
== DMA_CHAIN_STARTED
) {
1589 printk(KERN_ERR
"Chain is already started\n");
1593 if (dma_linked_lch
[chain_id
].chain_mode
== OMAP_DMA_STATIC_CHAIN
) {
1594 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
;
1596 enable_lnk(channels
[i
]);
1597 omap_enable_channel_irq(channels
[i
]);
1600 omap_enable_channel_irq(channels
[0]);
1603 l
= p
->dma_read(CCR
, channels
[0]);
1605 dma_linked_lch
[chain_id
].chain_state
= DMA_CHAIN_STARTED
;
1606 dma_chan
[channels
[0]].state
= DMA_CH_STARTED
;
1608 if ((0 == (l
& (1 << 24))))
1612 p
->dma_write(l
, CCR
, channels
[0]);
1614 dma_chan
[channels
[0]].flags
|= OMAP_DMA_ACTIVE
;
1618 EXPORT_SYMBOL(omap_start_dma_chain_transfers
);
1621 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1625 * @return - Success : 0
1628 int omap_stop_dma_chain_transfers(int chain_id
)
1634 /* Check for input params */
1635 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1636 printk(KERN_ERR
"Invalid chain id\n");
1640 /* Check if the chain exists */
1641 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1642 printk(KERN_ERR
"Chain doesn't exists\n");
1645 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1647 if (IS_DMA_ERRATA(DMA_ERRATA_i88
)) {
1648 sys_cf
= p
->dma_read(OCP_SYSCONFIG
, 0);
1650 /* Middle mode reg set no Standby */
1651 l
&= ~((1 << 12)|(1 << 13));
1652 p
->dma_write(l
, OCP_SYSCONFIG
, 0);
1655 for (i
= 0; i
< dma_linked_lch
[chain_id
].no_of_lchs_linked
; i
++) {
1657 /* Stop the Channel transmission */
1658 l
= p
->dma_read(CCR
, channels
[i
]);
1660 p
->dma_write(l
, CCR
, channels
[i
]);
1662 /* Disable the link in all the channels */
1663 disable_lnk(channels
[i
]);
1664 dma_chan
[channels
[i
]].state
= DMA_CH_NOTSTARTED
;
1667 dma_linked_lch
[chain_id
].chain_state
= DMA_CHAIN_NOTSTARTED
;
1669 /* Reset the Queue pointers */
1670 OMAP_DMA_CHAIN_QINIT(chain_id
);
1672 if (IS_DMA_ERRATA(DMA_ERRATA_i88
))
1673 p
->dma_write(sys_cf
, OCP_SYSCONFIG
, 0);
1677 EXPORT_SYMBOL(omap_stop_dma_chain_transfers
);
1679 /* Get the index of the ongoing DMA in chain */
1681 * @brief omap_get_dma_chain_index - Get the element and frame index
1682 * of the ongoing DMA in chain
1685 * @param ei - Element index
1686 * @param fi - Frame index
1688 * @return - Success : 0
1691 int omap_get_dma_chain_index(int chain_id
, int *ei
, int *fi
)
1696 /* Check for input params */
1697 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1698 printk(KERN_ERR
"Invalid chain id\n");
1702 /* Check if the chain exists */
1703 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1704 printk(KERN_ERR
"Chain doesn't exists\n");
1710 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1712 /* Get the current channel */
1713 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1715 *ei
= p
->dma_read(CCEN
, lch
);
1716 *fi
= p
->dma_read(CCFN
, lch
);
1720 EXPORT_SYMBOL(omap_get_dma_chain_index
);
1723 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1724 * ongoing DMA in chain
1728 * @return - Success : Destination position
1731 int omap_get_dma_chain_dst_pos(int chain_id
)
1736 /* Check for input params */
1737 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1738 printk(KERN_ERR
"Invalid chain id\n");
1742 /* Check if the chain exists */
1743 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1744 printk(KERN_ERR
"Chain doesn't exists\n");
1748 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1750 /* Get the current channel */
1751 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1753 return p
->dma_read(CDAC
, lch
);
1755 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos
);
1758 * @brief omap_get_dma_chain_src_pos - Get the source position
1759 * of the ongoing DMA in chain
1762 * @return - Success : Destination position
1765 int omap_get_dma_chain_src_pos(int chain_id
)
1770 /* Check for input params */
1771 if (unlikely((chain_id
< 0 || chain_id
>= dma_lch_count
))) {
1772 printk(KERN_ERR
"Invalid chain id\n");
1776 /* Check if the chain exists */
1777 if (dma_linked_lch
[chain_id
].linked_dmach_q
== NULL
) {
1778 printk(KERN_ERR
"Chain doesn't exists\n");
1782 channels
= dma_linked_lch
[chain_id
].linked_dmach_q
;
1784 /* Get the current channel */
1785 lch
= channels
[dma_linked_lch
[chain_id
].q_head
];
1787 return p
->dma_read(CSAC
, lch
);
1789 EXPORT_SYMBOL(omap_get_dma_chain_src_pos
);
1790 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1792 /*----------------------------------------------------------------------------*/
1794 #ifdef CONFIG_ARCH_OMAP1
1796 static int omap1_dma_handle_ch(int ch
)
1800 if (enable_1510_mode
&& ch
>= 6) {
1801 csr
= dma_chan
[ch
].saved_csr
;
1802 dma_chan
[ch
].saved_csr
= 0;
1804 csr
= p
->dma_read(CSR
, ch
);
1805 if (enable_1510_mode
&& ch
<= 2 && (csr
>> 7) != 0) {
1806 dma_chan
[ch
+ 6].saved_csr
= csr
>> 7;
1809 if ((csr
& 0x3f) == 0)
1811 if (unlikely(dma_chan
[ch
].dev_id
== -1)) {
1812 printk(KERN_WARNING
"Spurious interrupt from DMA channel "
1813 "%d (CSR %04x)\n", ch
, csr
);
1816 if (unlikely(csr
& OMAP1_DMA_TOUT_IRQ
))
1817 printk(KERN_WARNING
"DMA timeout with device %d\n",
1818 dma_chan
[ch
].dev_id
);
1819 if (unlikely(csr
& OMAP_DMA_DROP_IRQ
))
1820 printk(KERN_WARNING
"DMA synchronization event drop occurred "
1821 "with device %d\n", dma_chan
[ch
].dev_id
);
1822 if (likely(csr
& OMAP_DMA_BLOCK_IRQ
))
1823 dma_chan
[ch
].flags
&= ~OMAP_DMA_ACTIVE
;
1824 if (likely(dma_chan
[ch
].callback
!= NULL
))
1825 dma_chan
[ch
].callback(ch
, csr
, dma_chan
[ch
].data
);
1830 static irqreturn_t
omap1_dma_irq_handler(int irq
, void *dev_id
)
1832 int ch
= ((int) dev_id
) - 1;
1836 int handled_now
= 0;
1838 handled_now
+= omap1_dma_handle_ch(ch
);
1839 if (enable_1510_mode
&& dma_chan
[ch
+ 6].saved_csr
)
1840 handled_now
+= omap1_dma_handle_ch(ch
+ 6);
1843 handled
+= handled_now
;
1846 return handled
? IRQ_HANDLED
: IRQ_NONE
;
1850 #define omap1_dma_irq_handler NULL
1853 #ifdef CONFIG_ARCH_OMAP2PLUS
1855 static int omap2_dma_handle_ch(int ch
)
1857 u32 status
= p
->dma_read(CSR
, ch
);
1860 if (printk_ratelimit())
1861 printk(KERN_WARNING
"Spurious DMA IRQ for lch %d\n",
1863 p
->dma_write(1 << ch
, IRQSTATUS_L0
, ch
);
1866 if (unlikely(dma_chan
[ch
].dev_id
== -1)) {
1867 if (printk_ratelimit())
1868 printk(KERN_WARNING
"IRQ %04x for non-allocated DMA"
1869 "channel %d\n", status
, ch
);
1872 if (unlikely(status
& OMAP_DMA_DROP_IRQ
))
1874 "DMA synchronization event drop occurred with device "
1875 "%d\n", dma_chan
[ch
].dev_id
);
1876 if (unlikely(status
& OMAP2_DMA_TRANS_ERR_IRQ
)) {
1877 printk(KERN_INFO
"DMA transaction error with device %d\n",
1878 dma_chan
[ch
].dev_id
);
1879 if (IS_DMA_ERRATA(DMA_ERRATA_i378
)) {
1882 ccr
= p
->dma_read(CCR
, ch
);
1883 ccr
&= ~OMAP_DMA_CCR_EN
;
1884 p
->dma_write(ccr
, CCR
, ch
);
1885 dma_chan
[ch
].flags
&= ~OMAP_DMA_ACTIVE
;
1888 if (unlikely(status
& OMAP2_DMA_SECURE_ERR_IRQ
))
1889 printk(KERN_INFO
"DMA secure error with device %d\n",
1890 dma_chan
[ch
].dev_id
);
1891 if (unlikely(status
& OMAP2_DMA_MISALIGNED_ERR_IRQ
))
1892 printk(KERN_INFO
"DMA misaligned error with device %d\n",
1893 dma_chan
[ch
].dev_id
);
1895 p
->dma_write(status
, CSR
, ch
);
1896 p
->dma_write(1 << ch
, IRQSTATUS_L0
, ch
);
1897 /* read back the register to flush the write */
1898 p
->dma_read(IRQSTATUS_L0
, ch
);
1900 /* If the ch is not chained then chain_id will be -1 */
1901 if (dma_chan
[ch
].chain_id
!= -1) {
1902 int chain_id
= dma_chan
[ch
].chain_id
;
1903 dma_chan
[ch
].state
= DMA_CH_NOTSTARTED
;
1904 if (p
->dma_read(CLNK_CTRL
, ch
) & (1 << 15))
1905 dma_chan
[dma_chan
[ch
].next_linked_ch
].state
=
1907 if (dma_linked_lch
[chain_id
].chain_mode
==
1908 OMAP_DMA_DYNAMIC_CHAIN
)
1911 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id
))
1912 OMAP_DMA_CHAIN_INCQHEAD(chain_id
);
1914 status
= p
->dma_read(CSR
, ch
);
1915 p
->dma_write(status
, CSR
, ch
);
1918 if (likely(dma_chan
[ch
].callback
!= NULL
))
1919 dma_chan
[ch
].callback(ch
, status
, dma_chan
[ch
].data
);
1924 /* STATUS register count is from 1-32 while our is 0-31 */
1925 static irqreturn_t
omap2_dma_irq_handler(int irq
, void *dev_id
)
1927 u32 val
, enable_reg
;
1930 val
= p
->dma_read(IRQSTATUS_L0
, 0);
1932 if (printk_ratelimit())
1933 printk(KERN_WARNING
"Spurious DMA IRQ\n");
1936 enable_reg
= p
->dma_read(IRQENABLE_L0
, 0);
1937 val
&= enable_reg
; /* Dispatch only relevant interrupts */
1938 for (i
= 0; i
< dma_lch_count
&& val
!= 0; i
++) {
1940 omap2_dma_handle_ch(i
);
1947 static struct irqaction omap24xx_dma_irq
= {
1949 .handler
= omap2_dma_irq_handler
,
1950 .flags
= IRQF_DISABLED
1954 static struct irqaction omap24xx_dma_irq
;
1957 /*----------------------------------------------------------------------------*/
1959 void omap_dma_global_context_save(void)
1961 omap_dma_global_context
.dma_irqenable_l0
=
1962 p
->dma_read(IRQENABLE_L0
, 0);
1963 omap_dma_global_context
.dma_ocp_sysconfig
=
1964 p
->dma_read(OCP_SYSCONFIG
, 0);
1965 omap_dma_global_context
.dma_gcr
= p
->dma_read(GCR
, 0);
1968 void omap_dma_global_context_restore(void)
1972 p
->dma_write(omap_dma_global_context
.dma_gcr
, GCR
, 0);
1973 p
->dma_write(omap_dma_global_context
.dma_ocp_sysconfig
,
1975 p
->dma_write(omap_dma_global_context
.dma_irqenable_l0
,
1978 if (IS_DMA_ERRATA(DMA_ROMCODE_BUG
))
1979 p
->dma_write(0x3 , IRQSTATUS_L0
, 0);
1981 for (ch
= 0; ch
< dma_chan_count
; ch
++)
1982 if (dma_chan
[ch
].dev_id
!= -1)
1986 static int __devinit
omap_system_dma_probe(struct platform_device
*pdev
)
1993 p
= pdev
->dev
.platform_data
;
1995 dev_err(&pdev
->dev
, "%s: System DMA initialized without"
1996 "platform data\n", __func__
);
2003 if ((d
->dev_caps
& RESERVE_CHANNEL
) && omap_dma_reserve_channels
2004 && (omap_dma_reserve_channels
<= dma_lch_count
))
2005 d
->lch_count
= omap_dma_reserve_channels
;
2007 dma_lch_count
= d
->lch_count
;
2008 dma_chan_count
= dma_lch_count
;
2010 enable_1510_mode
= d
->dev_caps
& ENABLE_1510_MODE
;
2012 if (cpu_class_is_omap2()) {
2013 dma_linked_lch
= kzalloc(sizeof(struct dma_link_info
) *
2014 dma_lch_count
, GFP_KERNEL
);
2015 if (!dma_linked_lch
) {
2017 goto exit_dma_lch_fail
;
2021 spin_lock_init(&dma_chan_lock
);
2022 for (ch
= 0; ch
< dma_chan_count
; ch
++) {
2024 if (cpu_class_is_omap2())
2025 omap2_disable_irq_lch(ch
);
2027 dma_chan
[ch
].dev_id
= -1;
2028 dma_chan
[ch
].next_lch
= -1;
2030 if (ch
>= 6 && enable_1510_mode
)
2033 if (cpu_class_is_omap1()) {
2035 * request_irq() doesn't like dev_id (ie. ch) being
2036 * zero, so we have to kludge around this.
2038 sprintf(&irq_name
[0], "%d", ch
);
2039 dma_irq
= platform_get_irq_byname(pdev
, irq_name
);
2043 goto exit_dma_irq_fail
;
2046 /* INT_DMA_LCD is handled in lcd_dma.c */
2047 if (dma_irq
== INT_DMA_LCD
)
2050 ret
= request_irq(dma_irq
,
2051 omap1_dma_irq_handler
, 0, "DMA",
2054 goto exit_dma_irq_fail
;
2058 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2059 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE
,
2060 DMA_DEFAULT_FIFO_DEPTH
, 0);
2062 if (cpu_class_is_omap2()) {
2063 strcpy(irq_name
, "0");
2064 dma_irq
= platform_get_irq_byname(pdev
, irq_name
);
2066 dev_err(&pdev
->dev
, "failed: request IRQ %d", dma_irq
);
2067 goto exit_dma_lch_fail
;
2069 ret
= setup_irq(dma_irq
, &omap24xx_dma_irq
);
2071 dev_err(&pdev
->dev
, "set_up failed for IRQ %d"
2072 "for DMA (error %d)\n", dma_irq
, ret
);
2073 goto exit_dma_lch_fail
;
2077 /* reserve dma channels 0 and 1 in high security devices */
2078 if (cpu_is_omap34xx() &&
2079 (omap_type() != OMAP2_DEVICE_TYPE_GP
)) {
2080 printk(KERN_INFO
"Reserving DMA channels 0 and 1 for "
2082 dma_chan
[0].dev_id
= 0;
2083 dma_chan
[1].dev_id
= 1;
2089 dev_err(&pdev
->dev
, "unable to request IRQ %d"
2090 "for DMA (error %d)\n", dma_irq
, ret
);
2091 for (irq_rel
= 0; irq_rel
< ch
; irq_rel
++) {
2092 dma_irq
= platform_get_irq(pdev
, irq_rel
);
2093 free_irq(dma_irq
, (void *)(irq_rel
+ 1));
2103 static int __devexit
omap_system_dma_remove(struct platform_device
*pdev
)
2107 if (cpu_class_is_omap2()) {
2109 strcpy(irq_name
, "0");
2110 dma_irq
= platform_get_irq_byname(pdev
, irq_name
);
2111 remove_irq(dma_irq
, &omap24xx_dma_irq
);
2114 for ( ; irq_rel
< dma_chan_count
; irq_rel
++) {
2115 dma_irq
= platform_get_irq(pdev
, irq_rel
);
2116 free_irq(dma_irq
, (void *)(irq_rel
+ 1));
2125 static struct platform_driver omap_system_dma_driver
= {
2126 .probe
= omap_system_dma_probe
,
2127 .remove
= omap_system_dma_remove
,
2129 .name
= "omap_dma_system"
2133 static int __init
omap_system_dma_init(void)
2135 return platform_driver_register(&omap_system_dma_driver
);
2137 arch_initcall(omap_system_dma_init
);
2139 static void __exit
omap_system_dma_exit(void)
2141 platform_driver_unregister(&omap_system_dma_driver
);
2144 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2145 MODULE_LICENSE("GPL");
2146 MODULE_ALIAS("platform:" DRIVER_NAME
);
2147 MODULE_AUTHOR("Texas Instruments Inc");
2150 * Reserve the omap SDMA channels using cmdline bootarg
2151 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2153 static int __init
omap_dma_cmdline_reserve_ch(char *str
)
2155 if (get_option(&str
, &omap_dma_reserve_channels
) != 1)
2156 omap_dma_reserve_channels
= 0;
2160 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch
);