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Disintegrate asm/system.h for ARM
[linux-2.6.git] / arch / arm / plat-omap / dma.c
blobdbb10497d2ac85288f3f496618f29944688eb3dd
1 /*
2 * linux/arch/arm/plat-omap/dma.c
3 *
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 *
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 *
16 * Support functions for the OMAP internal DMA channels.
17 *
18 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
19 * Converted DMA library into DMA platform driver.
20 * - G, Manjunath Kondaiah <manjugk@ti.com>
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
25 *
26 */
27
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
35 #include <linux/io.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
38
39 #include <mach/hardware.h>
40 #include <plat/dma.h>
41
42 #include <plat/tc.h>
43
44 #undef DEBUG
45
46 #ifndef CONFIG_ARCH_OMAP1
47 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
48 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
49 };
50
51 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
52 #endif
53
54 #define OMAP_DMA_ACTIVE 0x01
55 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
56
57 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
58
59 static struct omap_system_dma_plat_info *p;
60 static struct omap_dma_dev_attr *d;
61
62 static int enable_1510_mode;
63 static u32 errata;
64
65 static struct omap_dma_global_context_registers {
66 u32 dma_irqenable_l0;
67 u32 dma_ocp_sysconfig;
68 u32 dma_gcr;
69 } omap_dma_global_context;
70
71 struct dma_link_info {
72 int *linked_dmach_q;
73 int no_of_lchs_linked;
74
75 int q_count;
76 int q_tail;
77 int q_head;
78
79 int chain_state;
80 int chain_mode;
81
82 };
83
84 static struct dma_link_info *dma_linked_lch;
85
86 #ifndef CONFIG_ARCH_OMAP1
87
88 /* Chain handling macros */
89 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
90 do { \
91 dma_linked_lch[chain_id].q_head = \
92 dma_linked_lch[chain_id].q_tail = \
93 dma_linked_lch[chain_id].q_count = 0; \
94 } while (0)
95 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
96 (dma_linked_lch[chain_id].no_of_lchs_linked == \
97 dma_linked_lch[chain_id].q_count)
98 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
99 do { \
100 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
101 dma_linked_lch[chain_id].q_count) \
102 } while (0)
103 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
104 (0 == dma_linked_lch[chain_id].q_count)
105 #define __OMAP_DMA_CHAIN_INCQ(end) \
106 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
107 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
108 do { \
109 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
110 dma_linked_lch[chain_id].q_count--; \
111 } while (0)
112
113 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
114 do { \
115 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
116 dma_linked_lch[chain_id].q_count++; \
117 } while (0)
118 #endif
119
120 static int dma_lch_count;
121 static int dma_chan_count;
122 static int omap_dma_reserve_channels;
123
124 static spinlock_t dma_chan_lock;
125 static struct omap_dma_lch *dma_chan;
126
127 static inline void disable_lnk(int lch);
128 static void omap_disable_channel_irq(int lch);
129 static inline void omap_enable_channel_irq(int lch);
130
131 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
132 __func__);
133
134 #ifdef CONFIG_ARCH_OMAP15XX
135 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
136 static int omap_dma_in_1510_mode(void)
137 {
138 return enable_1510_mode;
139 }
140 #else
141 #define omap_dma_in_1510_mode() 0
142 #endif
143
144 #ifdef CONFIG_ARCH_OMAP1
145 static inline int get_gdma_dev(int req)
146 {
147 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
148 int shift = ((req - 1) % 5) * 6;
149
150 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
151 }
152
153 static inline void set_gdma_dev(int req, int dev)
154 {
155 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
156 int shift = ((req - 1) % 5) * 6;
157 u32 l;
158
159 l = omap_readl(reg);
160 l &= ~(0x3f << shift);
161 l |= (dev - 1) << shift;
162 omap_writel(l, reg);
163 }
164 #else
165 #define set_gdma_dev(req, dev) do {} while (0)
166 #endif
167
168 void omap_set_dma_priority(int lch, int dst_port, int priority)
169 {
170 unsigned long reg;
171 u32 l;
172
173 if (cpu_class_is_omap1()) {
174 switch (dst_port) {
175 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
176 reg = OMAP_TC_OCPT1_PRIOR;
177 break;
178 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
179 reg = OMAP_TC_OCPT2_PRIOR;
180 break;
181 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
182 reg = OMAP_TC_EMIFF_PRIOR;
183 break;
184 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
185 reg = OMAP_TC_EMIFS_PRIOR;
186 break;
187 default:
188 BUG();
189 return;
190 }
191 l = omap_readl(reg);
192 l &= ~(0xf << 8);
193 l |= (priority & 0xf) << 8;
194 omap_writel(l, reg);
195 }
196
197 if (cpu_class_is_omap2()) {
198 u32 ccr;
199
200 ccr = p->dma_read(CCR, lch);
201 if (priority)
202 ccr |= (1 << 6);
203 else
204 ccr &= ~(1 << 6);
205 p->dma_write(ccr, CCR, lch);
206 }
207 }
208 EXPORT_SYMBOL(omap_set_dma_priority);
209
210 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
211 int frame_count, int sync_mode,
212 int dma_trigger, int src_or_dst_synch)
213 {
214 u32 l;
215
216 l = p->dma_read(CSDP, lch);
217 l &= ~0x03;
218 l |= data_type;
219 p->dma_write(l, CSDP, lch);
220
221 if (cpu_class_is_omap1()) {
222 u16 ccr;
223
224 ccr = p->dma_read(CCR, lch);
225 ccr &= ~(1 << 5);
226 if (sync_mode == OMAP_DMA_SYNC_FRAME)
227 ccr |= 1 << 5;
228 p->dma_write(ccr, CCR, lch);
229
230 ccr = p->dma_read(CCR2, lch);
231 ccr &= ~(1 << 2);
232 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
233 ccr |= 1 << 2;
234 p->dma_write(ccr, CCR2, lch);
235 }
236
237 if (cpu_class_is_omap2() && dma_trigger) {
238 u32 val;
239
240 val = p->dma_read(CCR, lch);
241
242 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
243 val &= ~((1 << 23) | (3 << 19) | 0x1f);
244 val |= (dma_trigger & ~0x1f) << 14;
245 val |= dma_trigger & 0x1f;
246
247 if (sync_mode & OMAP_DMA_SYNC_FRAME)
248 val |= 1 << 5;
249 else
250 val &= ~(1 << 5);
251
252 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
253 val |= 1 << 18;
254 else
255 val &= ~(1 << 18);
256
257 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
258 val &= ~(1 << 24); /* dest synch */
259 val |= (1 << 23); /* Prefetch */
260 } else if (src_or_dst_synch) {
261 val |= 1 << 24; /* source synch */
262 } else {
263 val &= ~(1 << 24); /* dest synch */
264 }
265 p->dma_write(val, CCR, lch);
266 }
267
268 p->dma_write(elem_count, CEN, lch);
269 p->dma_write(frame_count, CFN, lch);
270 }
271 EXPORT_SYMBOL(omap_set_dma_transfer_params);
272
273 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
274 {
275 BUG_ON(omap_dma_in_1510_mode());
276
277 if (cpu_class_is_omap1()) {
278 u16 w;
279
280 w = p->dma_read(CCR2, lch);
281 w &= ~0x03;
282
283 switch (mode) {
284 case OMAP_DMA_CONSTANT_FILL:
285 w |= 0x01;
286 break;
287 case OMAP_DMA_TRANSPARENT_COPY:
288 w |= 0x02;
289 break;
290 case OMAP_DMA_COLOR_DIS:
291 break;
292 default:
293 BUG();
294 }
295 p->dma_write(w, CCR2, lch);
296
297 w = p->dma_read(LCH_CTRL, lch);
298 w &= ~0x0f;
299 /* Default is channel type 2D */
300 if (mode) {
301 p->dma_write(color, COLOR, lch);
302 w |= 1; /* Channel type G */
303 }
304 p->dma_write(w, LCH_CTRL, lch);
305 }
306
307 if (cpu_class_is_omap2()) {
308 u32 val;
309
310 val = p->dma_read(CCR, lch);
311 val &= ~((1 << 17) | (1 << 16));
312
313 switch (mode) {
314 case OMAP_DMA_CONSTANT_FILL:
315 val |= 1 << 16;
316 break;
317 case OMAP_DMA_TRANSPARENT_COPY:
318 val |= 1 << 17;
319 break;
320 case OMAP_DMA_COLOR_DIS:
321 break;
322 default:
323 BUG();
324 }
325 p->dma_write(val, CCR, lch);
326
327 color &= 0xffffff;
328 p->dma_write(color, COLOR, lch);
329 }
330 }
331 EXPORT_SYMBOL(omap_set_dma_color_mode);
332
333 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
334 {
335 if (cpu_class_is_omap2()) {
336 u32 csdp;
337
338 csdp = p->dma_read(CSDP, lch);
339 csdp &= ~(0x3 << 16);
340 csdp |= (mode << 16);
341 p->dma_write(csdp, CSDP, lch);
342 }
343 }
344 EXPORT_SYMBOL(omap_set_dma_write_mode);
345
346 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
347 {
348 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
349 u32 l;
350
351 l = p->dma_read(LCH_CTRL, lch);
352 l &= ~0x7;
353 l |= mode;
354 p->dma_write(l, LCH_CTRL, lch);
355 }
356 }
357 EXPORT_SYMBOL(omap_set_dma_channel_mode);
358
359 /* Note that src_port is only for omap1 */
360 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
361 unsigned long src_start,
362 int src_ei, int src_fi)
363 {
364 u32 l;
365
366 if (cpu_class_is_omap1()) {
367 u16 w;
368
369 w = p->dma_read(CSDP, lch);
370 w &= ~(0x1f << 2);
371 w |= src_port << 2;
372 p->dma_write(w, CSDP, lch);
373 }
374
375 l = p->dma_read(CCR, lch);
376 l &= ~(0x03 << 12);
377 l |= src_amode << 12;
378 p->dma_write(l, CCR, lch);
379
380 p->dma_write(src_start, CSSA, lch);
381
382 p->dma_write(src_ei, CSEI, lch);
383 p->dma_write(src_fi, CSFI, lch);
384 }
385 EXPORT_SYMBOL(omap_set_dma_src_params);
386
387 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
388 {
389 omap_set_dma_transfer_params(lch, params->data_type,
390 params->elem_count, params->frame_count,
391 params->sync_mode, params->trigger,
392 params->src_or_dst_synch);
393 omap_set_dma_src_params(lch, params->src_port,
394 params->src_amode, params->src_start,
395 params->src_ei, params->src_fi);
396
397 omap_set_dma_dest_params(lch, params->dst_port,
398 params->dst_amode, params->dst_start,
399 params->dst_ei, params->dst_fi);
400 if (params->read_prio || params->write_prio)
401 omap_dma_set_prio_lch(lch, params->read_prio,
402 params->write_prio);
403 }
404 EXPORT_SYMBOL(omap_set_dma_params);
405
406 void omap_set_dma_src_index(int lch, int eidx, int fidx)
407 {
408 if (cpu_class_is_omap2())
409 return;
410
411 p->dma_write(eidx, CSEI, lch);
412 p->dma_write(fidx, CSFI, lch);
413 }
414 EXPORT_SYMBOL(omap_set_dma_src_index);
415
416 void omap_set_dma_src_data_pack(int lch, int enable)
417 {
418 u32 l;
419
420 l = p->dma_read(CSDP, lch);
421 l &= ~(1 << 6);
422 if (enable)
423 l |= (1 << 6);
424 p->dma_write(l, CSDP, lch);
425 }
426 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
427
428 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
429 {
430 unsigned int burst = 0;
431 u32 l;
432
433 l = p->dma_read(CSDP, lch);
434 l &= ~(0x03 << 7);
435
436 switch (burst_mode) {
437 case OMAP_DMA_DATA_BURST_DIS:
438 break;
439 case OMAP_DMA_DATA_BURST_4:
440 if (cpu_class_is_omap2())
441 burst = 0x1;
442 else
443 burst = 0x2;
444 break;
445 case OMAP_DMA_DATA_BURST_8:
446 if (cpu_class_is_omap2()) {
447 burst = 0x2;
448 break;
449 }
450 /*
451 * not supported by current hardware on OMAP1
452 * w |= (0x03 << 7);
453 * fall through
454 */
455 case OMAP_DMA_DATA_BURST_16:
456 if (cpu_class_is_omap2()) {
457 burst = 0x3;
458 break;
459 }
460 /*
461 * OMAP1 don't support burst 16
462 * fall through
463 */
464 default:
465 BUG();
466 }
467
468 l |= (burst << 7);
469 p->dma_write(l, CSDP, lch);
470 }
471 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
472
473 /* Note that dest_port is only for OMAP1 */
474 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
475 unsigned long dest_start,
476 int dst_ei, int dst_fi)
477 {
478 u32 l;
479
480 if (cpu_class_is_omap1()) {
481 l = p->dma_read(CSDP, lch);
482 l &= ~(0x1f << 9);
483 l |= dest_port << 9;
484 p->dma_write(l, CSDP, lch);
485 }
486
487 l = p->dma_read(CCR, lch);
488 l &= ~(0x03 << 14);
489 l |= dest_amode << 14;
490 p->dma_write(l, CCR, lch);
491
492 p->dma_write(dest_start, CDSA, lch);
493
494 p->dma_write(dst_ei, CDEI, lch);
495 p->dma_write(dst_fi, CDFI, lch);
496 }
497 EXPORT_SYMBOL(omap_set_dma_dest_params);
498
499 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
500 {
501 if (cpu_class_is_omap2())
502 return;
503
504 p->dma_write(eidx, CDEI, lch);
505 p->dma_write(fidx, CDFI, lch);
506 }
507 EXPORT_SYMBOL(omap_set_dma_dest_index);
508
509 void omap_set_dma_dest_data_pack(int lch, int enable)
510 {
511 u32 l;
512
513 l = p->dma_read(CSDP, lch);
514 l &= ~(1 << 13);
515 if (enable)
516 l |= 1 << 13;
517 p->dma_write(l, CSDP, lch);
518 }
519 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
520
521 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
522 {
523 unsigned int burst = 0;
524 u32 l;
525
526 l = p->dma_read(CSDP, lch);
527 l &= ~(0x03 << 14);
528
529 switch (burst_mode) {
530 case OMAP_DMA_DATA_BURST_DIS:
531 break;
532 case OMAP_DMA_DATA_BURST_4:
533 if (cpu_class_is_omap2())
534 burst = 0x1;
535 else
536 burst = 0x2;
537 break;
538 case OMAP_DMA_DATA_BURST_8:
539 if (cpu_class_is_omap2())
540 burst = 0x2;
541 else
542 burst = 0x3;
543 break;
544 case OMAP_DMA_DATA_BURST_16:
545 if (cpu_class_is_omap2()) {
546 burst = 0x3;
547 break;
548 }
549 /*
550 * OMAP1 don't support burst 16
551 * fall through
552 */
553 default:
554 printk(KERN_ERR "Invalid DMA burst mode\n");
555 BUG();
556 return;
557 }
558 l |= (burst << 14);
559 p->dma_write(l, CSDP, lch);
560 }
561 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
562
563 static inline void omap_enable_channel_irq(int lch)
564 {
565 u32 status;
566
567 /* Clear CSR */
568 if (cpu_class_is_omap1())
569 status = p->dma_read(CSR, lch);
570 else if (cpu_class_is_omap2())
571 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
572
573 /* Enable some nice interrupts. */
574 p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
575 }
576
577 static void omap_disable_channel_irq(int lch)
578 {
579 if (cpu_class_is_omap2())
580 p->dma_write(0, CICR, lch);
581 }
582
583 void omap_enable_dma_irq(int lch, u16 bits)
584 {
585 dma_chan[lch].enabled_irqs |= bits;
586 }
587 EXPORT_SYMBOL(omap_enable_dma_irq);
588
589 void omap_disable_dma_irq(int lch, u16 bits)
590 {
591 dma_chan[lch].enabled_irqs &= ~bits;
592 }
593 EXPORT_SYMBOL(omap_disable_dma_irq);
594
595 static inline void enable_lnk(int lch)
596 {
597 u32 l;
598
599 l = p->dma_read(CLNK_CTRL, lch);
600
601 if (cpu_class_is_omap1())
602 l &= ~(1 << 14);
603
604 /* Set the ENABLE_LNK bits */
605 if (dma_chan[lch].next_lch != -1)
606 l = dma_chan[lch].next_lch | (1 << 15);
607
608 #ifndef CONFIG_ARCH_OMAP1
609 if (cpu_class_is_omap2())
610 if (dma_chan[lch].next_linked_ch != -1)
611 l = dma_chan[lch].next_linked_ch | (1 << 15);
612 #endif
613
614 p->dma_write(l, CLNK_CTRL, lch);
615 }
616
617 static inline void disable_lnk(int lch)
618 {
619 u32 l;
620
621 l = p->dma_read(CLNK_CTRL, lch);
622
623 /* Disable interrupts */
624 if (cpu_class_is_omap1()) {
625 p->dma_write(0, CICR, lch);
626 /* Set the STOP_LNK bit */
627 l |= 1 << 14;
628 }
629
630 if (cpu_class_is_omap2()) {
631 omap_disable_channel_irq(lch);
632 /* Clear the ENABLE_LNK bit */
633 l &= ~(1 << 15);
634 }
635
636 p->dma_write(l, CLNK_CTRL, lch);
637 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
638 }
639
640 static inline void omap2_enable_irq_lch(int lch)
641 {
642 u32 val;
643 unsigned long flags;
644
645 if (!cpu_class_is_omap2())
646 return;
647
648 spin_lock_irqsave(&dma_chan_lock, flags);
649 val = p->dma_read(IRQENABLE_L0, lch);
650 val |= 1 << lch;
651 p->dma_write(val, IRQENABLE_L0, lch);
652 spin_unlock_irqrestore(&dma_chan_lock, flags);
653 }
654
655 static inline void omap2_disable_irq_lch(int lch)
656 {
657 u32 val;
658 unsigned long flags;
659
660 if (!cpu_class_is_omap2())
661 return;
662
663 spin_lock_irqsave(&dma_chan_lock, flags);
664 val = p->dma_read(IRQENABLE_L0, lch);
665 val &= ~(1 << lch);
666 p->dma_write(val, IRQENABLE_L0, lch);
667 spin_unlock_irqrestore(&dma_chan_lock, flags);
668 }
669
670 int omap_request_dma(int dev_id, const char *dev_name,
671 void (*callback)(int lch, u16 ch_status, void *data),
672 void *data, int *dma_ch_out)
673 {
674 int ch, free_ch = -1;
675 unsigned long flags;
676 struct omap_dma_lch *chan;
677
678 spin_lock_irqsave(&dma_chan_lock, flags);
679 for (ch = 0; ch < dma_chan_count; ch++) {
680 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
681 free_ch = ch;
682 if (dev_id == 0)
683 break;
684 }
685 }
686 if (free_ch == -1) {
687 spin_unlock_irqrestore(&dma_chan_lock, flags);
688 return -EBUSY;
689 }
690 chan = dma_chan + free_ch;
691 chan->dev_id = dev_id;
692
693 if (p->clear_lch_regs)
694 p->clear_lch_regs(free_ch);
695
696 if (cpu_class_is_omap2())
697 omap_clear_dma(free_ch);
698
699 spin_unlock_irqrestore(&dma_chan_lock, flags);
700
701 chan->dev_name = dev_name;
702 chan->callback = callback;
703 chan->data = data;
704 chan->flags = 0;
705
706 #ifndef CONFIG_ARCH_OMAP1
707 if (cpu_class_is_omap2()) {
708 chan->chain_id = -1;
709 chan->next_linked_ch = -1;
710 }
711 #endif
712
713 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
714
715 if (cpu_class_is_omap1())
716 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
717 else if (cpu_class_is_omap2())
718 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
719 OMAP2_DMA_TRANS_ERR_IRQ;
720
721 if (cpu_is_omap16xx()) {
722 /* If the sync device is set, configure it dynamically. */
723 if (dev_id != 0) {
724 set_gdma_dev(free_ch + 1, dev_id);
725 dev_id = free_ch + 1;
726 }
727 /*
728 * Disable the 1510 compatibility mode and set the sync device
729 * id.
730 */
731 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
732 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
733 p->dma_write(dev_id, CCR, free_ch);
734 }
735
736 if (cpu_class_is_omap2()) {
737 omap2_enable_irq_lch(free_ch);
738 omap_enable_channel_irq(free_ch);
739 /* Clear the CSR register and IRQ status register */
740 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);
741 p->dma_write(1 << free_ch, IRQSTATUS_L0, 0);
742 }
743
744 *dma_ch_out = free_ch;
745
746 return 0;
747 }
748 EXPORT_SYMBOL(omap_request_dma);
749
750 void omap_free_dma(int lch)
751 {
752 unsigned long flags;
753
754 if (dma_chan[lch].dev_id == -1) {
755 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
756 lch);
757 return;
758 }
759
760 if (cpu_class_is_omap1()) {
761 /* Disable all DMA interrupts for the channel. */
762 p->dma_write(0, CICR, lch);
763 /* Make sure the DMA transfer is stopped. */
764 p->dma_write(0, CCR, lch);
765 }
766
767 if (cpu_class_is_omap2()) {
768 omap2_disable_irq_lch(lch);
769
770 /* Clear the CSR register and IRQ status register */
771 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
772 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
773
774 /* Disable all DMA interrupts for the channel. */
775 p->dma_write(0, CICR, lch);
776
777 /* Make sure the DMA transfer is stopped. */
778 p->dma_write(0, CCR, lch);
779 omap_clear_dma(lch);
780 }
781
782 spin_lock_irqsave(&dma_chan_lock, flags);
783 dma_chan[lch].dev_id = -1;
784 dma_chan[lch].next_lch = -1;
785 dma_chan[lch].callback = NULL;
786 spin_unlock_irqrestore(&dma_chan_lock, flags);
787 }
788 EXPORT_SYMBOL(omap_free_dma);
789
790 /**
791 * @brief omap_dma_set_global_params : Set global priority settings for dma
792 *
793 * @param arb_rate
794 * @param max_fifo_depth
795 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
796 * DMA_THREAD_RESERVE_ONET
797 * DMA_THREAD_RESERVE_TWOT
798 * DMA_THREAD_RESERVE_THREET
799 */
800 void
801 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
802 {
803 u32 reg;
804
805 if (!cpu_class_is_omap2()) {
806 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
807 return;
808 }
809
810 if (max_fifo_depth == 0)
811 max_fifo_depth = 1;
812 if (arb_rate == 0)
813 arb_rate = 1;
814
815 reg = 0xff & max_fifo_depth;
816 reg |= (0x3 & tparams) << 12;
817 reg |= (arb_rate & 0xff) << 16;
818
819 p->dma_write(reg, GCR, 0);
820 }
821 EXPORT_SYMBOL(omap_dma_set_global_params);
822
823 /**
824 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
825 *
826 * @param lch
827 * @param read_prio - Read priority
828 * @param write_prio - Write priority
829 * Both of the above can be set with one of the following values :
830 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
831 */
832 int
833 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
834 unsigned char write_prio)
835 {
836 u32 l;
837
838 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
839 printk(KERN_ERR "Invalid channel id\n");
840 return -EINVAL;
841 }
842 l = p->dma_read(CCR, lch);
843 l &= ~((1 << 6) | (1 << 26));
844 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
845 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
846 else
847 l |= ((read_prio & 0x1) << 6);
848
849 p->dma_write(l, CCR, lch);
850
851 return 0;
852 }
853 EXPORT_SYMBOL(omap_dma_set_prio_lch);
854
855 /*
856 * Clears any DMA state so the DMA engine is ready to restart with new buffers
857 * through omap_start_dma(). Any buffers in flight are discarded.
858 */
859 void omap_clear_dma(int lch)
860 {
861 unsigned long flags;
862
863 local_irq_save(flags);
864 p->clear_dma(lch);
865 local_irq_restore(flags);
866 }
867 EXPORT_SYMBOL(omap_clear_dma);
868
869 void omap_start_dma(int lch)
870 {
871 u32 l;
872
873 /*
874 * The CPC/CDAC register needs to be initialized to zero
875 * before starting dma transfer.
876 */
877 if (cpu_is_omap15xx())
878 p->dma_write(0, CPC, lch);
879 else
880 p->dma_write(0, CDAC, lch);
881
882 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
883 int next_lch, cur_lch;
884 char dma_chan_link_map[dma_lch_count];
885
886 dma_chan_link_map[lch] = 1;
887 /* Set the link register of the first channel */
888 enable_lnk(lch);
889
890 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
891 cur_lch = dma_chan[lch].next_lch;
892 do {
893 next_lch = dma_chan[cur_lch].next_lch;
894
895 /* The loop case: we've been here already */
896 if (dma_chan_link_map[cur_lch])
897 break;
898 /* Mark the current channel */
899 dma_chan_link_map[cur_lch] = 1;
900
901 enable_lnk(cur_lch);
902 omap_enable_channel_irq(cur_lch);
903
904 cur_lch = next_lch;
905 } while (next_lch != -1);
906 } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
907 p->dma_write(lch, CLNK_CTRL, lch);
908
909 omap_enable_channel_irq(lch);
910
911 l = p->dma_read(CCR, lch);
912
913 if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
914 l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
915 l |= OMAP_DMA_CCR_EN;
916
917 p->dma_write(l, CCR, lch);
918
919 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
920 }
921 EXPORT_SYMBOL(omap_start_dma);
922
923 void omap_stop_dma(int lch)
924 {
925 u32 l;
926
927 /* Disable all interrupts on the channel */
928 if (cpu_class_is_omap1())
929 p->dma_write(0, CICR, lch);
930
931 l = p->dma_read(CCR, lch);
932 if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
933 (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
934 int i = 0;
935 u32 sys_cf;
936
937 /* Configure No-Standby */
938 l = p->dma_read(OCP_SYSCONFIG, lch);
939 sys_cf = l;
940 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
941 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
942 p->dma_write(l , OCP_SYSCONFIG, 0);
943
944 l = p->dma_read(CCR, lch);
945 l &= ~OMAP_DMA_CCR_EN;
946 p->dma_write(l, CCR, lch);
947
948 /* Wait for sDMA FIFO drain */
949 l = p->dma_read(CCR, lch);
950 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
951 OMAP_DMA_CCR_WR_ACTIVE))) {
952 udelay(5);
953 i++;
954 l = p->dma_read(CCR, lch);
955 }
956 if (i >= 100)
957 printk(KERN_ERR "DMA drain did not complete on "
958 "lch %d\n", lch);
959 /* Restore OCP_SYSCONFIG */
960 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
961 } else {
962 l &= ~OMAP_DMA_CCR_EN;
963 p->dma_write(l, CCR, lch);
964 }
965
966 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
967 int next_lch, cur_lch = lch;
968 char dma_chan_link_map[dma_lch_count];
969
970 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
971 do {
972 /* The loop case: we've been here already */
973 if (dma_chan_link_map[cur_lch])
974 break;
975 /* Mark the current channel */
976 dma_chan_link_map[cur_lch] = 1;
977
978 disable_lnk(cur_lch);
979
980 next_lch = dma_chan[cur_lch].next_lch;
981 cur_lch = next_lch;
982 } while (next_lch != -1);
983 }
984
985 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
986 }
987 EXPORT_SYMBOL(omap_stop_dma);
988
989 /*
990 * Allows changing the DMA callback function or data. This may be needed if
991 * the driver shares a single DMA channel for multiple dma triggers.
992 */
993 int omap_set_dma_callback(int lch,
994 void (*callback)(int lch, u16 ch_status, void *data),
995 void *data)
996 {
997 unsigned long flags;
998
999 if (lch < 0)
1000 return -ENODEV;
1001
1002 spin_lock_irqsave(&dma_chan_lock, flags);
1003 if (dma_chan[lch].dev_id == -1) {
1004 printk(KERN_ERR "DMA callback for not set for free channel\n");
1005 spin_unlock_irqrestore(&dma_chan_lock, flags);
1006 return -EINVAL;
1007 }
1008 dma_chan[lch].callback = callback;
1009 dma_chan[lch].data = data;
1010 spin_unlock_irqrestore(&dma_chan_lock, flags);
1011
1012 return 0;
1013 }
1014 EXPORT_SYMBOL(omap_set_dma_callback);
1015
1016 /*
1017 * Returns current physical source address for the given DMA channel.
1018 * If the channel is running the caller must disable interrupts prior calling
1019 * this function and process the returned value before re-enabling interrupt to
1020 * prevent races with the interrupt handler. Note that in continuous mode there
1021 * is a chance for CSSA_L register overflow between the two reads resulting
1022 * in incorrect return value.
1023 */
1024 dma_addr_t omap_get_dma_src_pos(int lch)
1025 {
1026 dma_addr_t offset = 0;
1027
1028 if (cpu_is_omap15xx())
1029 offset = p->dma_read(CPC, lch);
1030 else
1031 offset = p->dma_read(CSAC, lch);
1032
1033 if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
1034 offset = p->dma_read(CSAC, lch);
1035
1036 if (!cpu_is_omap15xx()) {
1037 /*
1038 * CDAC == 0 indicates that the DMA transfer on the channel has
1039 * not been started (no data has been transferred so far).
1040 * Return the programmed source start address in this case.
1041 */
1042 if (likely(p->dma_read(CDAC, lch)))
1043 offset = p->dma_read(CSAC, lch);
1044 else
1045 offset = p->dma_read(CSSA, lch);
1046 }
1047
1048 if (cpu_class_is_omap1())
1049 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
1050
1051 return offset;
1052 }
1053 EXPORT_SYMBOL(omap_get_dma_src_pos);
1054
1055 /*
1056 * Returns current physical destination address for the given DMA channel.
1057 * If the channel is running the caller must disable interrupts prior calling
1058 * this function and process the returned value before re-enabling interrupt to
1059 * prevent races with the interrupt handler. Note that in continuous mode there
1060 * is a chance for CDSA_L register overflow between the two reads resulting
1061 * in incorrect return value.
1062 */
1063 dma_addr_t omap_get_dma_dst_pos(int lch)
1064 {
1065 dma_addr_t offset = 0;
1066
1067 if (cpu_is_omap15xx())
1068 offset = p->dma_read(CPC, lch);
1069 else
1070 offset = p->dma_read(CDAC, lch);
1071
1072 /*
1073 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1074 * read before the DMA controller finished disabling the channel.
1075 */
1076 if (!cpu_is_omap15xx() && offset == 0) {
1077 offset = p->dma_read(CDAC, lch);
1078 /*
1079 * CDAC == 0 indicates that the DMA transfer on the channel has
1080 * not been started (no data has been transferred so far).
1081 * Return the programmed destination start address in this case.
1082 */
1083 if (unlikely(!offset))
1084 offset = p->dma_read(CDSA, lch);
1085 }
1086
1087 if (cpu_class_is_omap1())
1088 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1089
1090 return offset;
1091 }
1092 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1093
1094 int omap_get_dma_active_status(int lch)
1095 {
1096 return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1097 }
1098 EXPORT_SYMBOL(omap_get_dma_active_status);
1099
1100 int omap_dma_running(void)
1101 {
1102 int lch;
1103
1104 if (cpu_class_is_omap1())
1105 if (omap_lcd_dma_running())
1106 return 1;
1107
1108 for (lch = 0; lch < dma_chan_count; lch++)
1109 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1110 return 1;
1111
1112 return 0;
1113 }
1114
1115 /*
1116 * lch_queue DMA will start right after lch_head one is finished.
1117 * For this DMA link to start, you still need to start (see omap_start_dma)
1118 * the first one. That will fire up the entire queue.
1119 */
1120 void omap_dma_link_lch(int lch_head, int lch_queue)
1121 {
1122 if (omap_dma_in_1510_mode()) {
1123 if (lch_head == lch_queue) {
1124 p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1125 CCR, lch_head);
1126 return;
1127 }
1128 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1129 BUG();
1130 return;
1131 }
1132
1133 if ((dma_chan[lch_head].dev_id == -1) ||
1134 (dma_chan[lch_queue].dev_id == -1)) {
1135 printk(KERN_ERR "omap_dma: trying to link "
1136 "non requested channels\n");
1137 dump_stack();
1138 }
1139
1140 dma_chan[lch_head].next_lch = lch_queue;
1141 }
1142 EXPORT_SYMBOL(omap_dma_link_lch);
1143
1144 /*
1145 * Once the DMA queue is stopped, we can destroy it.
1146 */
1147 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1148 {
1149 if (omap_dma_in_1510_mode()) {
1150 if (lch_head == lch_queue) {
1151 p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
1152 CCR, lch_head);
1153 return;
1154 }
1155 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1156 BUG();
1157 return;
1158 }
1159
1160 if (dma_chan[lch_head].next_lch != lch_queue ||
1161 dma_chan[lch_head].next_lch == -1) {
1162 printk(KERN_ERR "omap_dma: trying to unlink "
1163 "non linked channels\n");
1164 dump_stack();
1165 }
1166
1167 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1168 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1169 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1170 "before unlinking\n");
1171 dump_stack();
1172 }
1173
1174 dma_chan[lch_head].next_lch = -1;
1175 }
1176 EXPORT_SYMBOL(omap_dma_unlink_lch);
1177
1178 #ifndef CONFIG_ARCH_OMAP1
1179 /* Create chain of DMA channesls */
1180 static void create_dma_lch_chain(int lch_head, int lch_queue)
1181 {
1182 u32 l;
1183
1184 /* Check if this is the first link in chain */
1185 if (dma_chan[lch_head].next_linked_ch == -1) {
1186 dma_chan[lch_head].next_linked_ch = lch_queue;
1187 dma_chan[lch_head].prev_linked_ch = lch_queue;
1188 dma_chan[lch_queue].next_linked_ch = lch_head;
1189 dma_chan[lch_queue].prev_linked_ch = lch_head;
1190 }
1191
1192 /* a link exists, link the new channel in circular chain */
1193 else {
1194 dma_chan[lch_queue].next_linked_ch =
1195 dma_chan[lch_head].next_linked_ch;
1196 dma_chan[lch_queue].prev_linked_ch = lch_head;
1197 dma_chan[lch_head].next_linked_ch = lch_queue;
1198 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1199 lch_queue;
1200 }
1201
1202 l = p->dma_read(CLNK_CTRL, lch_head);
1203 l &= ~(0x1f);
1204 l |= lch_queue;
1205 p->dma_write(l, CLNK_CTRL, lch_head);
1206
1207 l = p->dma_read(CLNK_CTRL, lch_queue);
1208 l &= ~(0x1f);
1209 l |= (dma_chan[lch_queue].next_linked_ch);
1210 p->dma_write(l, CLNK_CTRL, lch_queue);
1211 }
1212
1213 /**
1214 * @brief omap_request_dma_chain : Request a chain of DMA channels
1215 *
1216 * @param dev_id - Device id using the dma channel
1217 * @param dev_name - Device name
1218 * @param callback - Call back function
1219 * @chain_id -
1220 * @no_of_chans - Number of channels requested
1221 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1222 * OMAP_DMA_DYNAMIC_CHAIN
1223 * @params - Channel parameters
1224 *
1225 * @return - Success : 0
1226 * Failure: -EINVAL/-ENOMEM
1227 */
1228 int omap_request_dma_chain(int dev_id, const char *dev_name,
1229 void (*callback) (int lch, u16 ch_status,
1230 void *data),
1231 int *chain_id, int no_of_chans, int chain_mode,
1232 struct omap_dma_channel_params params)
1233 {
1234 int *channels;
1235 int i, err;
1236
1237 /* Is the chain mode valid ? */
1238 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1239 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1240 printk(KERN_ERR "Invalid chain mode requested\n");
1241 return -EINVAL;
1242 }
1243
1244 if (unlikely((no_of_chans < 1
1245 || no_of_chans > dma_lch_count))) {
1246 printk(KERN_ERR "Invalid Number of channels requested\n");
1247 return -EINVAL;
1248 }
1249
1250 /*
1251 * Allocate a queue to maintain the status of the channels
1252 * in the chain
1253 */
1254 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1255 if (channels == NULL) {
1256 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1257 return -ENOMEM;
1258 }
1259
1260 /* request and reserve DMA channels for the chain */
1261 for (i = 0; i < no_of_chans; i++) {
1262 err = omap_request_dma(dev_id, dev_name,
1263 callback, NULL, &channels[i]);
1264 if (err < 0) {
1265 int j;
1266 for (j = 0; j < i; j++)
1267 omap_free_dma(channels[j]);
1268 kfree(channels);
1269 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1270 return err;
1271 }
1272 dma_chan[channels[i]].prev_linked_ch = -1;
1273 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1274
1275 /*
1276 * Allowing client drivers to set common parameters now,
1277 * so that later only relevant (src_start, dest_start
1278 * and element count) can be set
1279 */
1280 omap_set_dma_params(channels[i], &params);
1281 }
1282
1283 *chain_id = channels[0];
1284 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1285 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1286 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1287 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1288
1289 for (i = 0; i < no_of_chans; i++)
1290 dma_chan[channels[i]].chain_id = *chain_id;
1291
1292 /* Reset the Queue pointers */
1293 OMAP_DMA_CHAIN_QINIT(*chain_id);
1294
1295 /* Set up the chain */
1296 if (no_of_chans == 1)
1297 create_dma_lch_chain(channels[0], channels[0]);
1298 else {
1299 for (i = 0; i < (no_of_chans - 1); i++)
1300 create_dma_lch_chain(channels[i], channels[i + 1]);
1301 }
1302
1303 return 0;
1304 }
1305 EXPORT_SYMBOL(omap_request_dma_chain);
1306
1307 /**
1308 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1309 * params after setting it. Dont do this while dma is running!!
1310 *
1311 * @param chain_id - Chained logical channel id.
1312 * @param params
1313 *
1314 * @return - Success : 0
1315 * Failure : -EINVAL
1316 */
1317 int omap_modify_dma_chain_params(int chain_id,
1318 struct omap_dma_channel_params params)
1319 {
1320 int *channels;
1321 u32 i;
1322
1323 /* Check for input params */
1324 if (unlikely((chain_id < 0
1325 || chain_id >= dma_lch_count))) {
1326 printk(KERN_ERR "Invalid chain id\n");
1327 return -EINVAL;
1328 }
1329
1330 /* Check if the chain exists */
1331 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1332 printk(KERN_ERR "Chain doesn't exists\n");
1333 return -EINVAL;
1334 }
1335 channels = dma_linked_lch[chain_id].linked_dmach_q;
1336
1337 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1338 /*
1339 * Allowing client drivers to set common parameters now,
1340 * so that later only relevant (src_start, dest_start
1341 * and element count) can be set
1342 */
1343 omap_set_dma_params(channels[i], &params);
1344 }
1345
1346 return 0;
1347 }
1348 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1349
1350 /**
1351 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1352 *
1353 * @param chain_id
1354 *
1355 * @return - Success : 0
1356 * Failure : -EINVAL
1357 */
1358 int omap_free_dma_chain(int chain_id)
1359 {
1360 int *channels;
1361 u32 i;
1362
1363 /* Check for input params */
1364 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1365 printk(KERN_ERR "Invalid chain id\n");
1366 return -EINVAL;
1367 }
1368
1369 /* Check if the chain exists */
1370 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1371 printk(KERN_ERR "Chain doesn't exists\n");
1372 return -EINVAL;
1373 }
1374
1375 channels = dma_linked_lch[chain_id].linked_dmach_q;
1376 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1377 dma_chan[channels[i]].next_linked_ch = -1;
1378 dma_chan[channels[i]].prev_linked_ch = -1;
1379 dma_chan[channels[i]].chain_id = -1;
1380 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1381 omap_free_dma(channels[i]);
1382 }
1383
1384 kfree(channels);
1385
1386 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1387 dma_linked_lch[chain_id].chain_mode = -1;
1388 dma_linked_lch[chain_id].chain_state = -1;
1389
1390 return (0);
1391 }
1392 EXPORT_SYMBOL(omap_free_dma_chain);
1393
1394 /**
1395 * @brief omap_dma_chain_status - Check if the chain is in
1396 * active / inactive state.
1397 * @param chain_id
1398 *
1399 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1400 * Failure : -EINVAL
1401 */
1402 int omap_dma_chain_status(int chain_id)
1403 {
1404 /* Check for input params */
1405 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1406 printk(KERN_ERR "Invalid chain id\n");
1407 return -EINVAL;
1408 }
1409
1410 /* Check if the chain exists */
1411 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1412 printk(KERN_ERR "Chain doesn't exists\n");
1413 return -EINVAL;
1414 }
1415 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1416 dma_linked_lch[chain_id].q_count);
1417
1418 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1419 return OMAP_DMA_CHAIN_INACTIVE;
1420
1421 return OMAP_DMA_CHAIN_ACTIVE;
1422 }
1423 EXPORT_SYMBOL(omap_dma_chain_status);
1424
1425 /**
1426 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1427 * set the params and start the transfer.
1428 *
1429 * @param chain_id
1430 * @param src_start - buffer start address
1431 * @param dest_start - Dest address
1432 * @param elem_count
1433 * @param frame_count
1434 * @param callbk_data - channel callback parameter data.
1435 *
1436 * @return - Success : 0
1437 * Failure: -EINVAL/-EBUSY
1438 */
1439 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1440 int elem_count, int frame_count, void *callbk_data)
1441 {
1442 int *channels;
1443 u32 l, lch;
1444 int start_dma = 0;
1445
1446 /*
1447 * if buffer size is less than 1 then there is
1448 * no use of starting the chain
1449 */
1450 if (elem_count < 1) {
1451 printk(KERN_ERR "Invalid buffer size\n");
1452 return -EINVAL;
1453 }
1454
1455 /* Check for input params */
1456 if (unlikely((chain_id < 0
1457 || chain_id >= dma_lch_count))) {
1458 printk(KERN_ERR "Invalid chain id\n");
1459 return -EINVAL;
1460 }
1461
1462 /* Check if the chain exists */
1463 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1464 printk(KERN_ERR "Chain doesn't exist\n");
1465 return -EINVAL;
1466 }
1467
1468 /* Check if all the channels in chain are in use */
1469 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1470 return -EBUSY;
1471
1472 /* Frame count may be negative in case of indexed transfers */
1473 channels = dma_linked_lch[chain_id].linked_dmach_q;
1474
1475 /* Get a free channel */
1476 lch = channels[dma_linked_lch[chain_id].q_tail];
1477
1478 /* Store the callback data */
1479 dma_chan[lch].data = callbk_data;
1480
1481 /* Increment the q_tail */
1482 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1483
1484 /* Set the params to the free channel */
1485 if (src_start != 0)
1486 p->dma_write(src_start, CSSA, lch);
1487 if (dest_start != 0)
1488 p->dma_write(dest_start, CDSA, lch);
1489
1490 /* Write the buffer size */
1491 p->dma_write(elem_count, CEN, lch);
1492 p->dma_write(frame_count, CFN, lch);
1493
1494 /*
1495 * If the chain is dynamically linked,
1496 * then we may have to start the chain if its not active
1497 */
1498 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1499
1500 /*
1501 * In Dynamic chain, if the chain is not started,
1502 * queue the channel
1503 */
1504 if (dma_linked_lch[chain_id].chain_state ==
1505 DMA_CHAIN_NOTSTARTED) {
1506 /* Enable the link in previous channel */
1507 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1508 DMA_CH_QUEUED)
1509 enable_lnk(dma_chan[lch].prev_linked_ch);
1510 dma_chan[lch].state = DMA_CH_QUEUED;
1511 }
1512
1513 /*
1514 * Chain is already started, make sure its active,
1515 * if not then start the chain
1516 */
1517 else {
1518 start_dma = 1;
1519
1520 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1521 DMA_CH_STARTED) {
1522 enable_lnk(dma_chan[lch].prev_linked_ch);
1523 dma_chan[lch].state = DMA_CH_QUEUED;
1524 start_dma = 0;
1525 if (0 == ((1 << 7) & p->dma_read(
1526 CCR, dma_chan[lch].prev_linked_ch))) {
1527 disable_lnk(dma_chan[lch].
1528 prev_linked_ch);
1529 pr_debug("\n prev ch is stopped\n");
1530 start_dma = 1;
1531 }
1532 }
1533
1534 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1535 == DMA_CH_QUEUED) {
1536 enable_lnk(dma_chan[lch].prev_linked_ch);
1537 dma_chan[lch].state = DMA_CH_QUEUED;
1538 start_dma = 0;
1539 }
1540 omap_enable_channel_irq(lch);
1541
1542 l = p->dma_read(CCR, lch);
1543
1544 if ((0 == (l & (1 << 24))))
1545 l &= ~(1 << 25);
1546 else
1547 l |= (1 << 25);
1548 if (start_dma == 1) {
1549 if (0 == (l & (1 << 7))) {
1550 l |= (1 << 7);
1551 dma_chan[lch].state = DMA_CH_STARTED;
1552 pr_debug("starting %d\n", lch);
1553 p->dma_write(l, CCR, lch);
1554 } else
1555 start_dma = 0;
1556 } else {
1557 if (0 == (l & (1 << 7)))
1558 p->dma_write(l, CCR, lch);
1559 }
1560 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1561 }
1562 }
1563
1564 return 0;
1565 }
1566 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1567
1568 /**
1569 * @brief omap_start_dma_chain_transfers - Start the chain
1570 *
1571 * @param chain_id
1572 *
1573 * @return - Success : 0
1574 * Failure : -EINVAL/-EBUSY
1575 */
1576 int omap_start_dma_chain_transfers(int chain_id)
1577 {
1578 int *channels;
1579 u32 l, i;
1580
1581 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1582 printk(KERN_ERR "Invalid chain id\n");
1583 return -EINVAL;
1584 }
1585
1586 channels = dma_linked_lch[chain_id].linked_dmach_q;
1587
1588 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1589 printk(KERN_ERR "Chain is already started\n");
1590 return -EBUSY;
1591 }
1592
1593 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1594 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1595 i++) {
1596 enable_lnk(channels[i]);
1597 omap_enable_channel_irq(channels[i]);
1598 }
1599 } else {
1600 omap_enable_channel_irq(channels[0]);
1601 }
1602
1603 l = p->dma_read(CCR, channels[0]);
1604 l |= (1 << 7);
1605 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1606 dma_chan[channels[0]].state = DMA_CH_STARTED;
1607
1608 if ((0 == (l & (1 << 24))))
1609 l &= ~(1 << 25);
1610 else
1611 l |= (1 << 25);
1612 p->dma_write(l, CCR, channels[0]);
1613
1614 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1615
1616 return 0;
1617 }
1618 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1619
1620 /**
1621 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1622 *
1623 * @param chain_id
1624 *
1625 * @return - Success : 0
1626 * Failure : EINVAL
1627 */
1628 int omap_stop_dma_chain_transfers(int chain_id)
1629 {
1630 int *channels;
1631 u32 l, i;
1632 u32 sys_cf = 0;
1633
1634 /* Check for input params */
1635 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1636 printk(KERN_ERR "Invalid chain id\n");
1637 return -EINVAL;
1638 }
1639
1640 /* Check if the chain exists */
1641 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1642 printk(KERN_ERR "Chain doesn't exists\n");
1643 return -EINVAL;
1644 }
1645 channels = dma_linked_lch[chain_id].linked_dmach_q;
1646
1647 if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
1648 sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
1649 l = sys_cf;
1650 /* Middle mode reg set no Standby */
1651 l &= ~((1 << 12)|(1 << 13));
1652 p->dma_write(l, OCP_SYSCONFIG, 0);
1653 }
1654
1655 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1656
1657 /* Stop the Channel transmission */
1658 l = p->dma_read(CCR, channels[i]);
1659 l &= ~(1 << 7);
1660 p->dma_write(l, CCR, channels[i]);
1661
1662 /* Disable the link in all the channels */
1663 disable_lnk(channels[i]);
1664 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1665
1666 }
1667 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1668
1669 /* Reset the Queue pointers */
1670 OMAP_DMA_CHAIN_QINIT(chain_id);
1671
1672 if (IS_DMA_ERRATA(DMA_ERRATA_i88))
1673 p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
1674
1675 return 0;
1676 }
1677 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1678
1679 /* Get the index of the ongoing DMA in chain */
1680 /**
1681 * @brief omap_get_dma_chain_index - Get the element and frame index
1682 * of the ongoing DMA in chain
1683 *
1684 * @param chain_id
1685 * @param ei - Element index
1686 * @param fi - Frame index
1687 *
1688 * @return - Success : 0
1689 * Failure : -EINVAL
1690 */
1691 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1692 {
1693 int lch;
1694 int *channels;
1695
1696 /* Check for input params */
1697 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1698 printk(KERN_ERR "Invalid chain id\n");
1699 return -EINVAL;
1700 }
1701
1702 /* Check if the chain exists */
1703 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1704 printk(KERN_ERR "Chain doesn't exists\n");
1705 return -EINVAL;
1706 }
1707 if ((!ei) || (!fi))
1708 return -EINVAL;
1709
1710 channels = dma_linked_lch[chain_id].linked_dmach_q;
1711
1712 /* Get the current channel */
1713 lch = channels[dma_linked_lch[chain_id].q_head];
1714
1715 *ei = p->dma_read(CCEN, lch);
1716 *fi = p->dma_read(CCFN, lch);
1717
1718 return 0;
1719 }
1720 EXPORT_SYMBOL(omap_get_dma_chain_index);
1721
1722 /**
1723 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1724 * ongoing DMA in chain
1725 *
1726 * @param chain_id
1727 *
1728 * @return - Success : Destination position
1729 * Failure : -EINVAL
1730 */
1731 int omap_get_dma_chain_dst_pos(int chain_id)
1732 {
1733 int lch;
1734 int *channels;
1735
1736 /* Check for input params */
1737 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1738 printk(KERN_ERR "Invalid chain id\n");
1739 return -EINVAL;
1740 }
1741
1742 /* Check if the chain exists */
1743 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1744 printk(KERN_ERR "Chain doesn't exists\n");
1745 return -EINVAL;
1746 }
1747
1748 channels = dma_linked_lch[chain_id].linked_dmach_q;
1749
1750 /* Get the current channel */
1751 lch = channels[dma_linked_lch[chain_id].q_head];
1752
1753 return p->dma_read(CDAC, lch);
1754 }
1755 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1756
1757 /**
1758 * @brief omap_get_dma_chain_src_pos - Get the source position
1759 * of the ongoing DMA in chain
1760 * @param chain_id
1761 *
1762 * @return - Success : Destination position
1763 * Failure : -EINVAL
1764 */
1765 int omap_get_dma_chain_src_pos(int chain_id)
1766 {
1767 int lch;
1768 int *channels;
1769
1770 /* Check for input params */
1771 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1772 printk(KERN_ERR "Invalid chain id\n");
1773 return -EINVAL;
1774 }
1775
1776 /* Check if the chain exists */
1777 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1778 printk(KERN_ERR "Chain doesn't exists\n");
1779 return -EINVAL;
1780 }
1781
1782 channels = dma_linked_lch[chain_id].linked_dmach_q;
1783
1784 /* Get the current channel */
1785 lch = channels[dma_linked_lch[chain_id].q_head];
1786
1787 return p->dma_read(CSAC, lch);
1788 }
1789 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1790 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1791
1792 /*----------------------------------------------------------------------------*/
1793
1794 #ifdef CONFIG_ARCH_OMAP1
1795
1796 static int omap1_dma_handle_ch(int ch)
1797 {
1798 u32 csr;
1799
1800 if (enable_1510_mode && ch >= 6) {
1801 csr = dma_chan[ch].saved_csr;
1802 dma_chan[ch].saved_csr = 0;
1803 } else
1804 csr = p->dma_read(CSR, ch);
1805 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1806 dma_chan[ch + 6].saved_csr = csr >> 7;
1807 csr &= 0x7f;
1808 }
1809 if ((csr & 0x3f) == 0)
1810 return 0;
1811 if (unlikely(dma_chan[ch].dev_id == -1)) {
1812 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1813 "%d (CSR %04x)\n", ch, csr);
1814 return 0;
1815 }
1816 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1817 printk(KERN_WARNING "DMA timeout with device %d\n",
1818 dma_chan[ch].dev_id);
1819 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1820 printk(KERN_WARNING "DMA synchronization event drop occurred "
1821 "with device %d\n", dma_chan[ch].dev_id);
1822 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1823 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1824 if (likely(dma_chan[ch].callback != NULL))
1825 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1826
1827 return 1;
1828 }
1829
1830 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1831 {
1832 int ch = ((int) dev_id) - 1;
1833 int handled = 0;
1834
1835 for (;;) {
1836 int handled_now = 0;
1837
1838 handled_now += omap1_dma_handle_ch(ch);
1839 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1840 handled_now += omap1_dma_handle_ch(ch + 6);
1841 if (!handled_now)
1842 break;
1843 handled += handled_now;
1844 }
1845
1846 return handled ? IRQ_HANDLED : IRQ_NONE;
1847 }
1848
1849 #else
1850 #define omap1_dma_irq_handler NULL
1851 #endif
1852
1853 #ifdef CONFIG_ARCH_OMAP2PLUS
1854
1855 static int omap2_dma_handle_ch(int ch)
1856 {
1857 u32 status = p->dma_read(CSR, ch);
1858
1859 if (!status) {
1860 if (printk_ratelimit())
1861 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1862 ch);
1863 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1864 return 0;
1865 }
1866 if (unlikely(dma_chan[ch].dev_id == -1)) {
1867 if (printk_ratelimit())
1868 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1869 "channel %d\n", status, ch);
1870 return 0;
1871 }
1872 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1873 printk(KERN_INFO
1874 "DMA synchronization event drop occurred with device "
1875 "%d\n", dma_chan[ch].dev_id);
1876 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1877 printk(KERN_INFO "DMA transaction error with device %d\n",
1878 dma_chan[ch].dev_id);
1879 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1880 u32 ccr;
1881
1882 ccr = p->dma_read(CCR, ch);
1883 ccr &= ~OMAP_DMA_CCR_EN;
1884 p->dma_write(ccr, CCR, ch);
1885 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1886 }
1887 }
1888 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1889 printk(KERN_INFO "DMA secure error with device %d\n",
1890 dma_chan[ch].dev_id);
1891 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1892 printk(KERN_INFO "DMA misaligned error with device %d\n",
1893 dma_chan[ch].dev_id);
1894
1895 p->dma_write(status, CSR, ch);
1896 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1897 /* read back the register to flush the write */
1898 p->dma_read(IRQSTATUS_L0, ch);
1899
1900 /* If the ch is not chained then chain_id will be -1 */
1901 if (dma_chan[ch].chain_id != -1) {
1902 int chain_id = dma_chan[ch].chain_id;
1903 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1904 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1905 dma_chan[dma_chan[ch].next_linked_ch].state =
1906 DMA_CH_STARTED;
1907 if (dma_linked_lch[chain_id].chain_mode ==
1908 OMAP_DMA_DYNAMIC_CHAIN)
1909 disable_lnk(ch);
1910
1911 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1912 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1913
1914 status = p->dma_read(CSR, ch);
1915 p->dma_write(status, CSR, ch);
1916 }
1917
1918 if (likely(dma_chan[ch].callback != NULL))
1919 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1920
1921 return 0;
1922 }
1923
1924 /* STATUS register count is from 1-32 while our is 0-31 */
1925 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1926 {
1927 u32 val, enable_reg;
1928 int i;
1929
1930 val = p->dma_read(IRQSTATUS_L0, 0);
1931 if (val == 0) {
1932 if (printk_ratelimit())
1933 printk(KERN_WARNING "Spurious DMA IRQ\n");
1934 return IRQ_HANDLED;
1935 }
1936 enable_reg = p->dma_read(IRQENABLE_L0, 0);
1937 val &= enable_reg; /* Dispatch only relevant interrupts */
1938 for (i = 0; i < dma_lch_count && val != 0; i++) {
1939 if (val & 1)
1940 omap2_dma_handle_ch(i);
1941 val >>= 1;
1942 }
1943
1944 return IRQ_HANDLED;
1945 }
1946
1947 static struct irqaction omap24xx_dma_irq = {
1948 .name = "DMA",
1949 .handler = omap2_dma_irq_handler,
1950 .flags = IRQF_DISABLED
1951 };
1952
1953 #else
1954 static struct irqaction omap24xx_dma_irq;
1955 #endif
1956
1957 /*----------------------------------------------------------------------------*/
1958
1959 void omap_dma_global_context_save(void)
1960 {
1961 omap_dma_global_context.dma_irqenable_l0 =
1962 p->dma_read(IRQENABLE_L0, 0);
1963 omap_dma_global_context.dma_ocp_sysconfig =
1964 p->dma_read(OCP_SYSCONFIG, 0);
1965 omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1966 }
1967
1968 void omap_dma_global_context_restore(void)
1969 {
1970 int ch;
1971
1972 p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1973 p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1974 OCP_SYSCONFIG, 0);
1975 p->dma_write(omap_dma_global_context.dma_irqenable_l0,
1976 IRQENABLE_L0, 0);
1977
1978 if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
1979 p->dma_write(0x3 , IRQSTATUS_L0, 0);
1980
1981 for (ch = 0; ch < dma_chan_count; ch++)
1982 if (dma_chan[ch].dev_id != -1)
1983 omap_clear_dma(ch);
1984 }
1985
1986 static int __devinit omap_system_dma_probe(struct platform_device *pdev)
1987 {
1988 int ch, ret = 0;
1989 int dma_irq;
1990 char irq_name[4];
1991 int irq_rel;
1992
1993 p = pdev->dev.platform_data;
1994 if (!p) {
1995 dev_err(&pdev->dev, "%s: System DMA initialized without"
1996 "platform data\n", __func__);
1997 return -EINVAL;
1998 }
1999
2000 d = p->dma_attr;
2001 errata = p->errata;
2002
2003 if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
2004 && (omap_dma_reserve_channels <= dma_lch_count))
2005 d->lch_count = omap_dma_reserve_channels;
2006
2007 dma_lch_count = d->lch_count;
2008 dma_chan_count = dma_lch_count;
2009 dma_chan = d->chan;
2010 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
2011
2012 if (cpu_class_is_omap2()) {
2013 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2014 dma_lch_count, GFP_KERNEL);
2015 if (!dma_linked_lch) {
2016 ret = -ENOMEM;
2017 goto exit_dma_lch_fail;
2018 }
2019 }
2020
2021 spin_lock_init(&dma_chan_lock);
2022 for (ch = 0; ch < dma_chan_count; ch++) {
2023 omap_clear_dma(ch);
2024 if (cpu_class_is_omap2())
2025 omap2_disable_irq_lch(ch);
2026
2027 dma_chan[ch].dev_id = -1;
2028 dma_chan[ch].next_lch = -1;
2029
2030 if (ch >= 6 && enable_1510_mode)
2031 continue;
2032
2033 if (cpu_class_is_omap1()) {
2034 /*
2035 * request_irq() doesn't like dev_id (ie. ch) being
2036 * zero, so we have to kludge around this.
2037 */
2038 sprintf(&irq_name[0], "%d", ch);
2039 dma_irq = platform_get_irq_byname(pdev, irq_name);
2040
2041 if (dma_irq < 0) {
2042 ret = dma_irq;
2043 goto exit_dma_irq_fail;
2044 }
2045
2046 /* INT_DMA_LCD is handled in lcd_dma.c */
2047 if (dma_irq == INT_DMA_LCD)
2048 continue;
2049
2050 ret = request_irq(dma_irq,
2051 omap1_dma_irq_handler, 0, "DMA",
2052 (void *) (ch + 1));
2053 if (ret != 0)
2054 goto exit_dma_irq_fail;
2055 }
2056 }
2057
2058 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2059 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2060 DMA_DEFAULT_FIFO_DEPTH, 0);
2061
2062 if (cpu_class_is_omap2()) {
2063 strcpy(irq_name, "0");
2064 dma_irq = platform_get_irq_byname(pdev, irq_name);
2065 if (dma_irq < 0) {
2066 dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
2067 goto exit_dma_lch_fail;
2068 }
2069 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
2070 if (ret) {
2071 dev_err(&pdev->dev, "set_up failed for IRQ %d"
2072 "for DMA (error %d)\n", dma_irq, ret);
2073 goto exit_dma_lch_fail;
2074 }
2075 }
2076
2077 /* reserve dma channels 0 and 1 in high security devices */
2078 if (cpu_is_omap34xx() &&
2079 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2080 printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2081 "HS ROM code\n");
2082 dma_chan[0].dev_id = 0;
2083 dma_chan[1].dev_id = 1;
2084 }
2085 p->show_dma_caps();
2086 return 0;
2087
2088 exit_dma_irq_fail:
2089 dev_err(&pdev->dev, "unable to request IRQ %d"
2090 "for DMA (error %d)\n", dma_irq, ret);
2091 for (irq_rel = 0; irq_rel < ch; irq_rel++) {
2092 dma_irq = platform_get_irq(pdev, irq_rel);
2093 free_irq(dma_irq, (void *)(irq_rel + 1));
2094 }
2095
2096 exit_dma_lch_fail:
2097 kfree(p);
2098 kfree(d);
2099 kfree(dma_chan);
2100 return ret;
2101 }
2102
2103 static int __devexit omap_system_dma_remove(struct platform_device *pdev)
2104 {
2105 int dma_irq;
2106
2107 if (cpu_class_is_omap2()) {
2108 char irq_name[4];
2109 strcpy(irq_name, "0");
2110 dma_irq = platform_get_irq_byname(pdev, irq_name);
2111 remove_irq(dma_irq, &omap24xx_dma_irq);
2112 } else {
2113 int irq_rel = 0;
2114 for ( ; irq_rel < dma_chan_count; irq_rel++) {
2115 dma_irq = platform_get_irq(pdev, irq_rel);
2116 free_irq(dma_irq, (void *)(irq_rel + 1));
2117 }
2118 }
2119 kfree(p);
2120 kfree(d);
2121 kfree(dma_chan);
2122 return 0;
2123 }
2124
2125 static struct platform_driver omap_system_dma_driver = {
2126 .probe = omap_system_dma_probe,
2127 .remove = omap_system_dma_remove,
2128 .driver = {
2129 .name = "omap_dma_system"
2130 },
2131 };
2132
2133 static int __init omap_system_dma_init(void)
2134 {
2135 return platform_driver_register(&omap_system_dma_driver);
2136 }
2137 arch_initcall(omap_system_dma_init);
2138
2139 static void __exit omap_system_dma_exit(void)
2140 {
2141 platform_driver_unregister(&omap_system_dma_driver);
2142 }
2143
2144 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2145 MODULE_LICENSE("GPL");
2146 MODULE_ALIAS("platform:" DRIVER_NAME);
2147 MODULE_AUTHOR("Texas Instruments Inc");
2148
2149 /*
2150 * Reserve the omap SDMA channels using cmdline bootarg
2151 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2152 */
2153 static int __init omap_dma_cmdline_reserve_ch(char *str)
2154 {
2155 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2156 omap_dma_reserve_channels = 0;
2157 return 1;
2158 }
2159
2160 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2161
2162
Linus' kernel tree