arch/arm/mach-shmobile/pm-sh7372.c

   1 /*
   2  * sh7372 Power management support
   3  *
   4  *  Copyright (C) 2011 Magnus Damm
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #include <linux/pm.h>
  12 #include <linux/suspend.h>
  13 #include <linux/cpuidle.h>
  14 #include <linux/module.h>
  15 #include <linux/list.h>
  16 #include <linux/err.h>
  17 #include <linux/slab.h>
  18 #include <linux/pm_clock.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/delay.h>
  21 #include <linux/irq.h>
  22 #include <linux/bitrev.h>
  23 #include <linux/console.h>
  24 #include <asm/io.h>
  25 #include <asm/tlbflush.h>
  26 #include <asm/suspend.h>
  27 #include <mach/common.h>
  28 #include <mach/sh7372.h>
  29
  30 /* DBG */
  31 #define DBGREG1 0xe6100020
  32 #define DBGREG9 0xe6100040
  33
  34 /* CPGA */
  35 #define SYSTBCR 0xe6150024
  36 #define MSTPSR0 0xe6150030
  37 #define MSTPSR1 0xe6150038
  38 #define MSTPSR2 0xe6150040
  39 #define MSTPSR3 0xe6150048
  40 #define MSTPSR4 0xe615004c
  41 #define PLLC01STPCR 0xe61500c8
  42
  43 /* SYSC */
  44 #define SPDCR 0xe6180008
  45 #define SWUCR 0xe6180014
  46 #define SBAR 0xe6180020
  47 #define WUPRMSK 0xe6180028
  48 #define WUPSMSK 0xe618002c
  49 #define WUPSMSK2 0xe6180048
  50 #define PSTR 0xe6180080
  51 #define WUPSFAC 0xe6180098
  52 #define IRQCR 0xe618022c
  53 #define IRQCR2 0xe6180238
  54 #define IRQCR3 0xe6180244
  55 #define IRQCR4 0xe6180248
  56 #define PDNSEL 0xe6180254
  57
  58 /* INTC */
  59 #define ICR1A 0xe6900000
  60 #define ICR2A 0xe6900004
  61 #define ICR3A 0xe6900008
  62 #define ICR4A 0xe690000c
  63 #define INTMSK00A 0xe6900040
  64 #define INTMSK10A 0xe6900044
  65 #define INTMSK20A 0xe6900048
  66 #define INTMSK30A 0xe690004c
  67
  68 /* MFIS */
  69 #define SMFRAM 0xe6a70000
  70
  71 /* AP-System Core */
  72 #define APARMBAREA 0xe6f10020
  73
  74 #define PSTR_RETRIES 100
  75 #define PSTR_DELAY_US 10
  76
  77 #ifdef CONFIG_PM
  78
  79 static int pd_power_down(struct generic_pm_domain *genpd)
  80 {
  81         struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
  82         unsigned int mask = 1 << sh7372_pd->bit_shift;
  83
  84         if (sh7372_pd->suspend) {
  85                 int ret = sh7372_pd->suspend();
  86
  87                 if (ret)
  88                         return ret;
  89         }
  90
  91         if (__raw_readl(PSTR) & mask) {
  92                 unsigned int retry_count;
  93
  94                 __raw_writel(mask, SPDCR);
  95
  96                 for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
  97                         if (!(__raw_readl(SPDCR) & mask))
  98                                 break;
  99                         cpu_relax();
 100                 }
 101         }
 102
 103         if (!sh7372_pd->no_debug)
 104                 pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n",
 105                          genpd->name, mask, __raw_readl(PSTR));
 106
 107         return 0;
 108 }
 109
 110 static int __pd_power_up(struct sh7372_pm_domain *sh7372_pd, bool do_resume)
 111 {
 112         unsigned int mask = 1 << sh7372_pd->bit_shift;
 113         unsigned int retry_count;
 114         int ret = 0;
 115
 116         if (__raw_readl(PSTR) & mask)
 117                 goto out;
 118
 119         __raw_writel(mask, SWUCR);
 120
 121         for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
 122                 if (!(__raw_readl(SWUCR) & mask))
 123                         break;
 124                 if (retry_count > PSTR_RETRIES)
 125                         udelay(PSTR_DELAY_US);
 126                 else
 127                         cpu_relax();
 128         }
 129         if (!retry_count)
 130                 ret = -EIO;
 131
 132         if (!sh7372_pd->no_debug)
 133                 pr_debug("%s: Power on, 0x%08x -> PSTR = 0x%08x\n",
 134                          sh7372_pd->genpd.name, mask, __raw_readl(PSTR));
 135
 136  out:
 137         if (ret == 0 && sh7372_pd->resume && do_resume)
 138                 sh7372_pd->resume();
 139
 140         return ret;
 141 }
 142
 143 static int pd_power_up(struct generic_pm_domain *genpd)
 144 {
 145          return __pd_power_up(to_sh7372_pd(genpd), true);
 146 }
 147
 148 static int sh7372_a4r_suspend(void)
 149 {
 150         sh7372_intcs_suspend();
 151         __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */
 152         return 0;
 153 }
 154
 155 static bool pd_active_wakeup(struct device *dev)
 156 {
 157         bool (*active_wakeup)(struct device *dev);
 158
 159         active_wakeup = dev_gpd_data(dev)->ops.active_wakeup;
 160         return active_wakeup ? active_wakeup(dev) : true;
 161 }
 162
 163 static int sh7372_stop_dev(struct device *dev)
 164 {
 165         int (*stop)(struct device *dev);
 166
 167         stop = dev_gpd_data(dev)->ops.stop;
 168         if (stop) {
 169                 int ret = stop(dev);
 170                 if (ret)
 171                         return ret;
 172         }
 173         return pm_clk_suspend(dev);
 174 }
 175
 176 static int sh7372_start_dev(struct device *dev)
 177 {
 178         int (*start)(struct device *dev);
 179         int ret;
 180
 181         ret = pm_clk_resume(dev);
 182         if (ret)
 183                 return ret;
 184
 185         start = dev_gpd_data(dev)->ops.start;
 186         if (start)
 187                 ret = start(dev);
 188
 189         return ret;
 190 }
 191
 192 void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
 193 {
 194         struct generic_pm_domain *genpd = &sh7372_pd->genpd;
 195         struct dev_power_governor *gov = sh7372_pd->gov;
 196
 197         pm_genpd_init(genpd, gov ? : &simple_qos_governor, false);
 198         genpd->dev_ops.stop = sh7372_stop_dev;
 199         genpd->dev_ops.start = sh7372_start_dev;
 200         genpd->dev_ops.active_wakeup = pd_active_wakeup;
 201         genpd->dev_irq_safe = true;
 202         genpd->power_off = pd_power_down;
 203         genpd->power_on = pd_power_up;
 204         __pd_power_up(sh7372_pd, false);
 205 }
 206
 207 void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
 208                                  struct platform_device *pdev)
 209 {
 210         struct device *dev = &pdev->dev;
 211
 212         pm_genpd_add_device(&sh7372_pd->genpd, dev);
 213         if (pm_clk_no_clocks(dev))
 214                 pm_clk_add(dev, NULL);
 215 }
 216
 217 void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd,
 218                              struct sh7372_pm_domain *sh7372_sd)
 219 {
 220         pm_genpd_add_subdomain(&sh7372_pd->genpd, &sh7372_sd->genpd);
 221 }
 222
 223 struct sh7372_pm_domain sh7372_a4lc = {
 224         .genpd.name = "A4LC",
 225         .bit_shift = 1,
 226 };
 227
 228 struct sh7372_pm_domain sh7372_a4mp = {
 229         .genpd.name = "A4MP",
 230         .bit_shift = 2,
 231 };
 232
 233 struct sh7372_pm_domain sh7372_d4 = {
 234         .genpd.name = "D4",
 235         .bit_shift = 3,
 236 };
 237
 238 struct sh7372_pm_domain sh7372_a4r = {
 239         .genpd.name = "A4R",
 240         .bit_shift = 5,
 241         .suspend = sh7372_a4r_suspend,
 242         .resume = sh7372_intcs_resume,
 243 };
 244
 245 struct sh7372_pm_domain sh7372_a3rv = {
 246         .genpd.name = "A3RV",
 247         .bit_shift = 6,
 248 };
 249
 250 struct sh7372_pm_domain sh7372_a3ri = {
 251         .genpd.name = "A3RI",
 252         .bit_shift = 8,
 253 };
 254
 255 static int sh7372_a4s_suspend(void)
 256 {
 257         /*
 258          * The A4S domain contains the CPU core and therefore it should
 259          * only be turned off if the CPU is in use.
 260          */
 261         return -EBUSY;
 262 }
 263
 264 struct sh7372_pm_domain sh7372_a4s = {
 265         .genpd.name = "A4S",
 266         .bit_shift = 10,
 267         .gov = &pm_domain_always_on_gov,
 268         .no_debug = true,
 269         .suspend = sh7372_a4s_suspend,
 270 };
 271
 272 static int sh7372_a3sp_suspend(void)
 273 {
 274         /*
 275          * Serial consoles make use of SCIF hardware located in A3SP,
 276          * keep such power domain on if "no_console_suspend" is set.
 277          */
 278         return console_suspend_enabled ? 0 : -EBUSY;
 279 }
 280
 281 struct sh7372_pm_domain sh7372_a3sp = {
 282         .genpd.name = "A3SP",
 283         .bit_shift = 11,
 284         .gov = &pm_domain_always_on_gov,
 285         .no_debug = true,
 286         .suspend = sh7372_a3sp_suspend,
 287 };
 288
 289 struct sh7372_pm_domain sh7372_a3sg = {
 290         .genpd.name = "A3SG",
 291         .bit_shift = 13,
 292 };
 293
 294 #else /* !CONFIG_PM */
 295
 296 static inline void sh7372_a3sp_init(void) {}
 297
 298 #endif /* !CONFIG_PM */
 299
 300 #if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
 301 static int sh7372_do_idle_core_standby(unsigned long unused)
 302 {
 303         cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
 304         return 0;
 305 }
 306
 307 static void sh7372_set_reset_vector(unsigned long address)
 308 {
 309         /* set reset vector, translate 4k */
 310         __raw_writel(address, SBAR);
 311         __raw_writel(0, APARMBAREA);
 312 }
 313
 314 static void sh7372_enter_core_standby(void)
 315 {
 316         sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
 317
 318         /* enter sleep mode with SYSTBCR to 0x10 */
 319         __raw_writel(0x10, SYSTBCR);
 320         cpu_suspend(0, sh7372_do_idle_core_standby);
 321         __raw_writel(0, SYSTBCR);
 322
 323          /* disable reset vector translation */
 324         __raw_writel(0, SBAR);
 325 }
 326 #endif
 327
 328 #ifdef CONFIG_SUSPEND
 329 static void sh7372_enter_sysc(int pllc0_on, unsigned long sleep_mode)
 330 {
 331         if (pllc0_on)
 332                 __raw_writel(0, PLLC01STPCR);
 333         else
 334                 __raw_writel(1 << 28, PLLC01STPCR);
 335
 336         __raw_readl(WUPSFAC); /* read wakeup int. factor before sleep */
 337         cpu_suspend(sleep_mode, sh7372_do_idle_sysc);
 338         __raw_readl(WUPSFAC); /* read wakeup int. factor after wakeup */
 339
 340          /* disable reset vector translation */
 341         __raw_writel(0, SBAR);
 342 }
 343
 344 static int sh7372_sysc_valid(unsigned long *mskp, unsigned long *msk2p)
 345 {
 346         unsigned long mstpsr0, mstpsr1, mstpsr2, mstpsr3, mstpsr4;
 347         unsigned long msk, msk2;
 348
 349         /* check active clocks to determine potential wakeup sources */
 350
 351         mstpsr0 = __raw_readl(MSTPSR0);
 352         if ((mstpsr0 & 0x00000003) != 0x00000003) {
 353                 pr_debug("sh7372 mstpsr0 0x%08lx\n", mstpsr0);
 354                 return 0;
 355         }
 356
 357         mstpsr1 = __raw_readl(MSTPSR1);
 358         if ((mstpsr1 & 0xff079b7f) != 0xff079b7f) {
 359                 pr_debug("sh7372 mstpsr1 0x%08lx\n", mstpsr1);
 360                 return 0;
 361         }
 362
 363         mstpsr2 = __raw_readl(MSTPSR2);
 364         if ((mstpsr2 & 0x000741ff) != 0x000741ff) {
 365                 pr_debug("sh7372 mstpsr2 0x%08lx\n", mstpsr2);
 366                 return 0;
 367         }
 368
 369         mstpsr3 = __raw_readl(MSTPSR3);
 370         if ((mstpsr3 & 0x1a60f010) != 0x1a60f010) {
 371                 pr_debug("sh7372 mstpsr3 0x%08lx\n", mstpsr3);
 372                 return 0;
 373         }
 374
 375         mstpsr4 = __raw_readl(MSTPSR4);
 376         if ((mstpsr4 & 0x00008cf0) != 0x00008cf0) {
 377                 pr_debug("sh7372 mstpsr4 0x%08lx\n", mstpsr4);
 378                 return 0;
 379         }
 380
 381         msk = 0;
 382         msk2 = 0;
 383
 384         /* make bitmaps of limited number of wakeup sources */
 385
 386         if ((mstpsr2 & (1 << 23)) == 0) /* SPU2 */
 387                 msk |= 1 << 31;
 388
 389         if ((mstpsr2 & (1 << 12)) == 0) /* MFI_MFIM */
 390                 msk |= 1 << 21;
 391
 392         if ((mstpsr4 & (1 << 3)) == 0) /* KEYSC */
 393                 msk |= 1 << 2;
 394
 395         if ((mstpsr1 & (1 << 24)) == 0) /* CMT0 */
 396                 msk |= 1 << 1;
 397
 398         if ((mstpsr3 & (1 << 29)) == 0) /* CMT1 */
 399                 msk |= 1 << 1;
 400
 401         if ((mstpsr4 & (1 << 0)) == 0) /* CMT2 */
 402                 msk |= 1 << 1;
 403
 404         if ((mstpsr2 & (1 << 13)) == 0) /* MFI_MFIS */
 405                 msk2 |= 1 << 17;
 406
 407         *mskp = msk;
 408         *msk2p = msk2;
 409
 410         return 1;
 411 }
 412
 413 static void sh7372_icr_to_irqcr(unsigned long icr, u16 *irqcr1p, u16 *irqcr2p)
 414 {
 415         u16 tmp, irqcr1, irqcr2;
 416         int k;
 417
 418         irqcr1 = 0;
 419         irqcr2 = 0;
 420
 421         /* convert INTCA ICR register layout to SYSC IRQCR+IRQCR2 */
 422         for (k = 0; k <= 7; k++) {
 423                 tmp = (icr >> ((7 - k) * 4)) & 0xf;
 424                 irqcr1 |= (tmp & 0x03) << (k * 2);
 425                 irqcr2 |= (tmp >> 2) << (k * 2);
 426         }
 427
 428         *irqcr1p = irqcr1;
 429         *irqcr2p = irqcr2;
 430 }
 431
 432 static void sh7372_setup_sysc(unsigned long msk, unsigned long msk2)
 433 {
 434         u16 irqcrx_low, irqcrx_high, irqcry_low, irqcry_high;
 435         unsigned long tmp;
 436
 437         /* read IRQ0A -> IRQ15A mask */
 438         tmp = bitrev8(__raw_readb(INTMSK00A));
 439         tmp |= bitrev8(__raw_readb(INTMSK10A)) << 8;
 440
 441         /* setup WUPSMSK from clocks and external IRQ mask */
 442         msk = (~msk & 0xc030000f) | (tmp << 4);
 443         __raw_writel(msk, WUPSMSK);
 444
 445         /* propage level/edge trigger for external IRQ 0->15 */
 446         sh7372_icr_to_irqcr(__raw_readl(ICR1A), &irqcrx_low, &irqcry_low);
 447         sh7372_icr_to_irqcr(__raw_readl(ICR2A), &irqcrx_high, &irqcry_high);
 448         __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR);
 449         __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR2);
 450
 451         /* read IRQ16A -> IRQ31A mask */
 452         tmp = bitrev8(__raw_readb(INTMSK20A));
 453         tmp |= bitrev8(__raw_readb(INTMSK30A)) << 8;
 454
 455         /* setup WUPSMSK2 from clocks and external IRQ mask */
 456         msk2 = (~msk2 & 0x00030000) | tmp;
 457         __raw_writel(msk2, WUPSMSK2);
 458
 459         /* propage level/edge trigger for external IRQ 16->31 */
 460         sh7372_icr_to_irqcr(__raw_readl(ICR3A), &irqcrx_low, &irqcry_low);
 461         sh7372_icr_to_irqcr(__raw_readl(ICR4A), &irqcrx_high, &irqcry_high);
 462         __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR3);
 463         __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR4);
 464 }
 465
 466 static void sh7372_enter_a3sm_common(int pllc0_on)
 467 {
 468         sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
 469         sh7372_enter_sysc(pllc0_on, 1 << 12);
 470 }
 471
 472 static void sh7372_enter_a4s_common(int pllc0_on)
 473 {
 474         sh7372_intca_suspend();
 475         memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
 476         sh7372_set_reset_vector(SMFRAM);
 477         sh7372_enter_sysc(pllc0_on, 1 << 10);
 478         sh7372_intca_resume();
 479 }
 480
 481 #endif
 482
 483 #ifdef CONFIG_CPU_IDLE
 484
 485 static void sh7372_cpuidle_setup(struct cpuidle_driver *drv)
 486 {
 487         struct cpuidle_state *state = &drv->states[drv->state_count];
 488
 489         snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
 490         strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
 491         state->exit_latency = 10;
 492         state->target_residency = 20 + 10;
 493         state->flags = CPUIDLE_FLAG_TIME_VALID;
 494         shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_core_standby;
 495
 496         drv->state_count++;
 497 }
 498
 499 static void sh7372_cpuidle_init(void)
 500 {
 501         shmobile_cpuidle_setup = sh7372_cpuidle_setup;
 502 }
 503 #else
 504 static void sh7372_cpuidle_init(void) {}
 505 #endif
 506
 507 #ifdef CONFIG_SUSPEND
 508
 509 static int sh7372_enter_suspend(suspend_state_t suspend_state)
 510 {
 511         unsigned long msk, msk2;
 512
 513         /* check active clocks to determine potential wakeup sources */
 514         if (sh7372_sysc_valid(&msk, &msk2)) {
 515                 /* convert INTC mask and sense to SYSC mask and sense */
 516                 sh7372_setup_sysc(msk, msk2);
 517
 518                 if (!console_suspend_enabled &&
 519                     sh7372_a4s.genpd.status == GPD_STATE_POWER_OFF) {
 520                         /* enter A4S sleep with PLLC0 off */
 521                         pr_debug("entering A4S\n");
 522                         sh7372_enter_a4s_common(0);
 523                 } else {
 524                         /* enter A3SM sleep with PLLC0 off */
 525                         pr_debug("entering A3SM\n");
 526                         sh7372_enter_a3sm_common(0);
 527                 }
 528         } else {
 529                 /* default to Core Standby that supports all wakeup sources */
 530                 pr_debug("entering Core Standby\n");
 531                 sh7372_enter_core_standby();
 532         }
 533         return 0;
 534 }
 535
 536 /**
 537  * sh7372_pm_notifier_fn - SH7372 PM notifier routine.
 538  * @notifier: Unused.
 539  * @pm_event: Event being handled.
 540  * @unused: Unused.
 541  */
 542 static int sh7372_pm_notifier_fn(struct notifier_block *notifier,
 543                                  unsigned long pm_event, void *unused)
 544 {
 545         switch (pm_event) {
 546         case PM_SUSPEND_PREPARE:
 547                 /*
 548                  * This is necessary, because the A4R domain has to be "on"
 549                  * when suspend_device_irqs() and resume_device_irqs() are
 550                  * executed during system suspend and resume, respectively, so
 551                  * that those functions don't crash while accessing the INTCS.
 552                  */
 553                 pm_genpd_poweron(&sh7372_a4r.genpd);
 554                 break;
 555         case PM_POST_SUSPEND:
 556                 pm_genpd_poweroff_unused();
 557                 break;
 558         }
 559
 560         return NOTIFY_DONE;
 561 }
 562
 563 static void sh7372_suspend_init(void)
 564 {
 565         shmobile_suspend_ops.enter = sh7372_enter_suspend;
 566         pm_notifier(sh7372_pm_notifier_fn, 0);
 567 }
 568 #else
 569 static void sh7372_suspend_init(void) {}
 570 #endif
 571
 572 void __init sh7372_pm_init(void)
 573 {
 574         /* enable DBG hardware block to kick SYSC */
 575         __raw_writel(0x0000a500, DBGREG9);
 576         __raw_writel(0x0000a501, DBGREG9);
 577         __raw_writel(0x00000000, DBGREG1);
 578
 579         /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */
 580         __raw_writel(0, PDNSEL);
 581
 582         sh7372_suspend_init();
 583         sh7372_cpuidle_init();
 584 }