1 /* linux/arch/arm/mach-s3c2412/s3c2412.c
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/init.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/device.h>
22 #include <linux/syscore_ops.h>
23 #include <linux/serial_core.h>
24 #include <linux/platform_device.h>
27 #include <asm/mach/arch.h>
28 #include <asm/mach/map.h>
29 #include <asm/mach/irq.h>
31 #include <mach/hardware.h>
32 #include <asm/proc-fns.h>
34 #include <asm/system_misc.h>
36 #include <mach/idle.h>
38 #include <plat/cpu-freq.h>
40 #include <mach/regs-clock.h>
41 #include <plat/regs-serial.h>
42 #include <mach/regs-power.h>
43 #include <mach/regs-gpio.h>
44 #include <mach/regs-gpioj.h>
45 #include <mach/regs-dsc.h>
46 #include <plat/regs-spi.h>
47 #include <mach/regs-s3c2412.h>
49 #include <plat/s3c2412.h>
51 #include <plat/devs.h>
52 #include <plat/clock.h>
55 #include <plat/nand-core.h>
57 #ifndef CONFIG_CPU_S3C2412_ONLY
58 void __iomem
*s3c24xx_va_gpio2
= S3C24XX_VA_GPIO
;
60 static inline void s3c2412_init_gpio2(void)
62 s3c24xx_va_gpio2
= S3C24XX_VA_GPIO
+ 0x10;
65 #define s3c2412_init_gpio2() do { } while(0)
68 /* Initial IO mappings */
70 static struct map_desc s3c2412_iodesc
[] __initdata
= {
75 .virtual = (unsigned long)S3C2412_VA_SSMC
,
76 .pfn
= __phys_to_pfn(S3C2412_PA_SSMC
),
81 .virtual = (unsigned long)S3C2412_VA_EBI
,
82 .pfn
= __phys_to_pfn(S3C2412_PA_EBI
),
88 /* uart registration process */
90 void __init
s3c2412_init_uarts(struct s3c2410_uartcfg
*cfg
, int no
)
92 s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources
, cfg
, no
);
94 /* rename devices that are s3c2412/s3c2413 specific */
95 s3c_device_sdi
.name
= "s3c2412-sdi";
96 s3c_device_lcd
.name
= "s3c2412-lcd";
97 s3c_nand_setname("s3c2412-nand");
99 /* alter IRQ of SDI controller */
101 s3c_device_sdi
.resource
[1].start
= IRQ_S3C2412_SDI
;
102 s3c_device_sdi
.resource
[1].end
= IRQ_S3C2412_SDI
;
104 /* spi channel related changes, s3c2412/13 specific */
105 s3c_device_spi0
.name
= "s3c2412-spi";
106 s3c_device_spi0
.resource
[0].end
= S3C24XX_PA_SPI
+ 0x24;
107 s3c_device_spi1
.name
= "s3c2412-spi";
108 s3c_device_spi1
.resource
[0].start
= S3C24XX_PA_SPI
+ S3C2412_SPI1
;
109 s3c_device_spi1
.resource
[0].end
= S3C24XX_PA_SPI
+ S3C2412_SPI1
+ 0x24;
115 * use the standard idle call by ensuring the idle mode
116 * in power config, then issuing the idle co-processor
120 static void s3c2412_idle(void)
124 /* ensure our idle mode is to go to idle */
126 tmp
= __raw_readl(S3C2412_PWRCFG
);
127 tmp
&= ~S3C2412_PWRCFG_STANDBYWFI_MASK
;
128 tmp
|= S3C2412_PWRCFG_STANDBYWFI_IDLE
;
129 __raw_writel(tmp
, S3C2412_PWRCFG
);
134 void s3c2412_restart(char mode
, const char *cmd
)
139 /* errata "Watch-dog/Software Reset Problem" specifies that
140 * this reset must be done with the SYSCLK sourced from
141 * EXTCLK instead of FOUT to avoid a glitch in the reset
144 * See the watchdog section of the S3C2412 manual for more
145 * information on this fix.
148 __raw_writel(0x00, S3C2412_CLKSRC
);
149 __raw_writel(S3C2412_SWRST_RESET
, S3C2412_SWRST
);
156 * register the standard cpu IO areas, and any passed in from the
157 * machine specific initialisation.
160 void __init
s3c2412_map_io(void)
162 /* move base of IO */
164 s3c2412_init_gpio2();
166 /* set our idle function */
168 s3c24xx_idle
= s3c2412_idle
;
170 /* register our io-tables */
172 iotable_init(s3c2412_iodesc
, ARRAY_SIZE(s3c2412_iodesc
));
175 void __init_or_cpufreq
s3c2412_setup_clocks(void)
177 struct clk
*xtal_clk
;
184 xtal_clk
= clk_get(NULL
, "xtal");
185 xtal
= clk_get_rate(xtal_clk
);
188 /* now we've got our machine bits initialised, work out what
189 * clocks we've got */
191 fclk
= s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON
), xtal
* 2);
193 clk_mpll
.rate
= fclk
;
195 tmp
= __raw_readl(S3C2410_CLKDIVN
);
197 /* work out clock scalings */
199 hclk
= fclk
/ ((tmp
& S3C2412_CLKDIVN_HDIVN_MASK
) + 1);
200 hclk
/= ((tmp
& S3C2412_CLKDIVN_ARMDIVN
) ? 2 : 1);
201 pclk
= hclk
/ ((tmp
& S3C2412_CLKDIVN_PDIVN
) ? 2 : 1);
203 /* print brieft summary of clocks, etc */
205 printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
206 print_mhz(fclk
), print_mhz(hclk
), print_mhz(pclk
));
208 s3c24xx_setup_clocks(fclk
, hclk
, pclk
);
211 void __init
s3c2412_init_clocks(int xtal
)
213 /* initialise the clocks here, to allow other things like the
214 * console to use them
217 s3c24xx_register_baseclocks(xtal
);
218 s3c2412_setup_clocks();
219 s3c2412_baseclk_add();
222 /* need to register the subsystem before we actually register the device, and
223 * we also need to ensure that it has been initialised before any of the
224 * drivers even try to use it (even if not on an s3c2412 based system)
225 * as a driver which may support both 2410 and 2440 may try and use it.
228 struct bus_type s3c2412_subsys
= {
229 .name
= "s3c2412-core",
230 .dev_name
= "s3c2412-core",
233 static int __init
s3c2412_core_init(void)
235 return subsys_system_register(&s3c2412_subsys
, NULL
);
238 core_initcall(s3c2412_core_init
);
240 static struct device s3c2412_dev
= {
241 .bus
= &s3c2412_subsys
,
244 int __init
s3c2412_init(void)
246 printk("S3C2412: Initialising architecture\n");
249 register_syscore_ops(&s3c2412_pm_syscore_ops
);
251 register_syscore_ops(&s3c24xx_irq_syscore_ops
);
253 return device_register(&s3c2412_dev
);