2 * OMAP3 Power Management Routines
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
31 #include <trace/events/power.h>
33 #include <asm/suspend.h>
34 #include <asm/system_misc.h>
36 #include <plat/sram.h>
37 #include "clockdomain.h"
38 #include "powerdomain.h"
39 #include <plat/sdrc.h>
40 #include <plat/prcm.h>
41 #include <plat/gpmc.h>
45 #include "cm2xxx_3xxx.h"
46 #include "cm-regbits-34xx.h"
47 #include "prm-regbits-34xx.h"
49 #include "prm2xxx_3xxx.h"
55 static suspend_state_t suspend_state
= PM_SUSPEND_ON
;
58 /* pm34xx errata defined in pm.h */
62 struct powerdomain
*pwrdm
;
67 struct list_head node
;
70 static LIST_HEAD(pwrst_list
);
72 static int (*_omap_save_secure_sram
)(u32
*addr
);
73 void (*omap3_do_wfi_sram
)(void);
75 static struct powerdomain
*mpu_pwrdm
, *neon_pwrdm
;
76 static struct powerdomain
*core_pwrdm
, *per_pwrdm
;
77 static struct powerdomain
*cam_pwrdm
;
79 static inline void omap3_per_save_context(void)
81 omap_gpio_save_context();
84 static inline void omap3_per_restore_context(void)
86 omap_gpio_restore_context();
89 static void omap3_enable_io_chain(void)
93 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK
, WKUP_MOD
,
95 /* Do a readback to assure write has been done */
96 omap2_prm_read_mod_reg(WKUP_MOD
, PM_WKEN
);
98 while (!(omap2_prm_read_mod_reg(WKUP_MOD
, PM_WKEN
) &
99 OMAP3430_ST_IO_CHAIN_MASK
)) {
101 if (timeout
> 1000) {
102 pr_err("Wake up daisy chain activation failed.\n");
105 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK
,
110 static void omap3_disable_io_chain(void)
112 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK
, WKUP_MOD
,
116 static void omap3_core_save_context(void)
118 omap3_ctrl_save_padconf();
121 * Force write last pad into memory, as this can fail in some
122 * cases according to errata 1.157, 1.185
124 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14
),
125 OMAP343X_CONTROL_MEM_WKUP
+ 0x2a0);
127 /* Save the Interrupt controller context */
128 omap_intc_save_context();
129 /* Save the GPMC context */
130 omap3_gpmc_save_context();
131 /* Save the system control module context, padconf already save above*/
132 omap3_control_save_context();
133 omap_dma_global_context_save();
136 static void omap3_core_restore_context(void)
138 /* Restore the control module context, padconf restored by h/w */
139 omap3_control_restore_context();
140 /* Restore the GPMC context */
141 omap3_gpmc_restore_context();
142 /* Restore the interrupt controller context */
143 omap_intc_restore_context();
144 omap_dma_global_context_restore();
148 * FIXME: This function should be called before entering off-mode after
149 * OMAP3 secure services have been accessed. Currently it is only called
150 * once during boot sequence, but this works as we are not using secure
153 static void omap3_save_secure_ram_context(void)
156 int mpu_next_state
= pwrdm_read_next_pwrst(mpu_pwrdm
);
158 if (omap_type() != OMAP2_DEVICE_TYPE_GP
) {
160 * MPU next state must be set to POWER_ON temporarily,
161 * otherwise the WFI executed inside the ROM code
162 * will hang the system.
164 pwrdm_set_next_pwrst(mpu_pwrdm
, PWRDM_POWER_ON
);
165 ret
= _omap_save_secure_sram((u32
*)
166 __pa(omap3_secure_ram_storage
));
167 pwrdm_set_next_pwrst(mpu_pwrdm
, mpu_next_state
);
168 /* Following is for error tracking, it should not happen */
170 printk(KERN_ERR
"save_secure_sram() returns %08x\n",
179 * PRCM Interrupt Handler Helper Function
181 * The purpose of this function is to clear any wake-up events latched
182 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
183 * may occur whilst attempting to clear a PM_WKST_x register and thus
184 * set another bit in this register. A while loop is used to ensure
185 * that any peripheral wake-up events occurring while attempting to
186 * clear the PM_WKST_x are detected and cleared.
188 static int prcm_clear_mod_irqs(s16 module
, u8 regs
, u32 ignore_bits
)
190 u32 wkst
, fclk
, iclk
, clken
;
191 u16 wkst_off
= (regs
== 3) ? OMAP3430ES2_PM_WKST3
: PM_WKST1
;
192 u16 fclk_off
= (regs
== 3) ? OMAP3430ES2_CM_FCLKEN3
: CM_FCLKEN1
;
193 u16 iclk_off
= (regs
== 3) ? CM_ICLKEN3
: CM_ICLKEN1
;
194 u16 grpsel_off
= (regs
== 3) ?
195 OMAP3430ES2_PM_MPUGRPSEL3
: OMAP3430_PM_MPUGRPSEL
;
198 wkst
= omap2_prm_read_mod_reg(module
, wkst_off
);
199 wkst
&= omap2_prm_read_mod_reg(module
, grpsel_off
);
200 wkst
&= ~ignore_bits
;
202 iclk
= omap2_cm_read_mod_reg(module
, iclk_off
);
203 fclk
= omap2_cm_read_mod_reg(module
, fclk_off
);
206 omap2_cm_set_mod_reg_bits(clken
, module
, iclk_off
);
208 * For USBHOST, we don't know whether HOST1 or
209 * HOST2 woke us up, so enable both f-clocks
211 if (module
== OMAP3430ES2_USBHOST_MOD
)
212 clken
|= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT
;
213 omap2_cm_set_mod_reg_bits(clken
, module
, fclk_off
);
214 omap2_prm_write_mod_reg(wkst
, module
, wkst_off
);
215 wkst
= omap2_prm_read_mod_reg(module
, wkst_off
);
216 wkst
&= ~ignore_bits
;
219 omap2_cm_write_mod_reg(iclk
, module
, iclk_off
);
220 omap2_cm_write_mod_reg(fclk
, module
, fclk_off
);
226 static irqreturn_t
_prcm_int_handle_io(int irq
, void *unused
)
230 c
= prcm_clear_mod_irqs(WKUP_MOD
, 1,
231 ~(OMAP3430_ST_IO_MASK
| OMAP3430_ST_IO_CHAIN_MASK
));
233 return c
? IRQ_HANDLED
: IRQ_NONE
;
236 static irqreturn_t
_prcm_int_handle_wakeup(int irq
, void *unused
)
241 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
242 * these are handled in a separate handler to avoid acking
243 * IO events before parsing in mux code
245 c
= prcm_clear_mod_irqs(WKUP_MOD
, 1,
246 OMAP3430_ST_IO_MASK
| OMAP3430_ST_IO_CHAIN_MASK
);
247 c
+= prcm_clear_mod_irqs(CORE_MOD
, 1, 0);
248 c
+= prcm_clear_mod_irqs(OMAP3430_PER_MOD
, 1, 0);
249 if (omap_rev() > OMAP3430_REV_ES1_0
) {
250 c
+= prcm_clear_mod_irqs(CORE_MOD
, 3, 0);
251 c
+= prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD
, 1, 0);
254 return c
? IRQ_HANDLED
: IRQ_NONE
;
257 static void omap34xx_save_context(u32
*save
)
261 /* Read Auxiliary Control Register */
262 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val
));
266 /* Read L2 AUX ctrl register */
267 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val
));
272 static int omap34xx_do_sram_idle(unsigned long save_state
)
274 omap34xx_cpu_suspend(save_state
);
278 void omap_sram_idle(void)
280 /* Variable to tell what needs to be saved and restored
281 * in omap_sram_idle*/
282 /* save_state = 0 => Nothing to save and restored */
283 /* save_state = 1 => Only L1 and logic lost */
284 /* save_state = 2 => Only L2 lost */
285 /* save_state = 3 => L1, L2 and logic lost */
287 int mpu_next_state
= PWRDM_POWER_ON
;
288 int per_next_state
= PWRDM_POWER_ON
;
289 int core_next_state
= PWRDM_POWER_ON
;
291 int core_prev_state
, per_prev_state
;
294 pwrdm_clear_all_prev_pwrst(mpu_pwrdm
);
295 pwrdm_clear_all_prev_pwrst(neon_pwrdm
);
296 pwrdm_clear_all_prev_pwrst(core_pwrdm
);
297 pwrdm_clear_all_prev_pwrst(per_pwrdm
);
299 mpu_next_state
= pwrdm_read_next_pwrst(mpu_pwrdm
);
300 switch (mpu_next_state
) {
302 case PWRDM_POWER_RET
:
303 /* No need to save context */
306 case PWRDM_POWER_OFF
:
311 printk(KERN_ERR
"Invalid mpu state in sram_idle\n");
316 if (pwrdm_read_pwrst(neon_pwrdm
) == PWRDM_POWER_ON
)
317 pwrdm_set_next_pwrst(neon_pwrdm
, mpu_next_state
);
319 /* Enable IO-PAD and IO-CHAIN wakeups */
320 per_next_state
= pwrdm_read_next_pwrst(per_pwrdm
);
321 core_next_state
= pwrdm_read_next_pwrst(core_pwrdm
);
322 if (omap3_has_io_wakeup() &&
323 (per_next_state
< PWRDM_POWER_ON
||
324 core_next_state
< PWRDM_POWER_ON
)) {
325 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK
, WKUP_MOD
, PM_WKEN
);
326 if (omap3_has_io_chain_ctrl())
327 omap3_enable_io_chain();
330 pwrdm_pre_transition();
333 if (per_next_state
< PWRDM_POWER_ON
) {
334 per_going_off
= (per_next_state
== PWRDM_POWER_OFF
) ? 1 : 0;
335 omap2_gpio_prepare_for_idle(per_going_off
);
336 if (per_next_state
== PWRDM_POWER_OFF
)
337 omap3_per_save_context();
341 if (core_next_state
< PWRDM_POWER_ON
) {
342 if (core_next_state
== PWRDM_POWER_OFF
) {
343 omap3_core_save_context();
344 omap3_cm_save_context();
348 omap3_intc_prepare_idle();
351 * On EMU/HS devices ROM code restores a SRDC value
352 * from scratchpad which has automatic self refresh on timeout
353 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
354 * Hence store/restore the SDRC_POWER register here.
356 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0
&&
357 (omap_type() == OMAP2_DEVICE_TYPE_EMU
||
358 omap_type() == OMAP2_DEVICE_TYPE_SEC
) &&
359 core_next_state
== PWRDM_POWER_OFF
)
360 sdrc_pwr
= sdrc_read_reg(SDRC_POWER
);
363 * omap3_arm_context is the location where some ARM context
364 * get saved. The rest is placed on the stack, and restored
365 * from there before resuming.
368 omap34xx_save_context(omap3_arm_context
);
369 if (save_state
== 1 || save_state
== 3)
370 cpu_suspend(save_state
, omap34xx_do_sram_idle
);
372 omap34xx_do_sram_idle(save_state
);
374 /* Restore normal SDRC POWER settings */
375 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0
&&
376 (omap_type() == OMAP2_DEVICE_TYPE_EMU
||
377 omap_type() == OMAP2_DEVICE_TYPE_SEC
) &&
378 core_next_state
== PWRDM_POWER_OFF
)
379 sdrc_write_reg(sdrc_pwr
, SDRC_POWER
);
382 if (core_next_state
< PWRDM_POWER_ON
) {
383 core_prev_state
= pwrdm_read_prev_pwrst(core_pwrdm
);
384 if (core_prev_state
== PWRDM_POWER_OFF
) {
385 omap3_core_restore_context();
386 omap3_cm_restore_context();
387 omap3_sram_restore_context();
388 omap2_sms_restore_context();
390 if (core_next_state
== PWRDM_POWER_OFF
)
391 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK
,
393 OMAP3_PRM_VOLTCTRL_OFFSET
);
395 omap3_intc_resume_idle();
397 pwrdm_post_transition();
400 if (per_next_state
< PWRDM_POWER_ON
) {
401 per_prev_state
= pwrdm_read_prev_pwrst(per_pwrdm
);
402 omap2_gpio_resume_after_idle();
403 if (per_prev_state
== PWRDM_POWER_OFF
)
404 omap3_per_restore_context();
407 /* Disable IO-PAD and IO-CHAIN wakeup */
408 if (omap3_has_io_wakeup() &&
409 (per_next_state
< PWRDM_POWER_ON
||
410 core_next_state
< PWRDM_POWER_ON
)) {
411 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK
, WKUP_MOD
,
413 if (omap3_has_io_chain_ctrl())
414 omap3_disable_io_chain();
417 clkdm_allow_idle(mpu_pwrdm
->pwrdm_clkdms
[0]);
420 static void omap3_pm_idle(void)
425 if (omap_irq_pending() || need_resched())
428 trace_power_start(POWER_CSTATE
, 1, smp_processor_id());
429 trace_cpu_idle(1, smp_processor_id());
433 trace_power_end(smp_processor_id());
434 trace_cpu_idle(PWR_EVENT_EXIT
, smp_processor_id());
441 #ifdef CONFIG_SUSPEND
442 static int omap3_pm_suspend(void)
444 struct power_state
*pwrst
;
447 /* Read current next_pwrsts */
448 list_for_each_entry(pwrst
, &pwrst_list
, node
)
449 pwrst
->saved_state
= pwrdm_read_next_pwrst(pwrst
->pwrdm
);
450 /* Set ones wanted by suspend */
451 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
452 if (omap_set_pwrdm_state(pwrst
->pwrdm
, pwrst
->next_state
))
454 if (pwrdm_clear_all_prev_pwrst(pwrst
->pwrdm
))
458 omap3_intc_suspend();
463 /* Restore next_pwrsts */
464 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
465 state
= pwrdm_read_prev_pwrst(pwrst
->pwrdm
);
466 if (state
> pwrst
->next_state
) {
467 printk(KERN_INFO
"Powerdomain (%s) didn't enter "
469 pwrst
->pwrdm
->name
, pwrst
->next_state
);
472 omap_set_pwrdm_state(pwrst
->pwrdm
, pwrst
->saved_state
);
475 printk(KERN_ERR
"Could not enter target state in pm_suspend\n");
477 printk(KERN_INFO
"Successfully put all powerdomains "
478 "to target state\n");
483 static int omap3_pm_enter(suspend_state_t unused
)
487 switch (suspend_state
) {
488 case PM_SUSPEND_STANDBY
:
490 ret
= omap3_pm_suspend();
499 /* Hooks to enable / disable UART interrupts during suspend */
500 static int omap3_pm_begin(suspend_state_t state
)
503 suspend_state
= state
;
504 omap_prcm_irq_prepare();
508 static void omap3_pm_end(void)
510 suspend_state
= PM_SUSPEND_ON
;
515 static void omap3_pm_finish(void)
517 omap_prcm_irq_complete();
520 static const struct platform_suspend_ops omap_pm_ops
= {
521 .begin
= omap3_pm_begin
,
523 .enter
= omap3_pm_enter
,
524 .finish
= omap3_pm_finish
,
525 .valid
= suspend_valid_only_mem
,
527 #endif /* CONFIG_SUSPEND */
531 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
534 * In cases where IVA2 is activated by bootcode, it may prevent
535 * full-chip retention or off-mode because it is not idle. This
536 * function forces the IVA2 into idle state so it can go
537 * into retention/off and thus allow full-chip retention/off.
540 static void __init
omap3_iva_idle(void)
542 /* ensure IVA2 clock is disabled */
543 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD
, CM_FCLKEN
);
545 /* if no clock activity, nothing else to do */
546 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKSTST
) &
547 OMAP3430_CLKACTIVITY_IVA2_MASK
))
551 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK
|
552 OMAP3430_RST2_IVA2_MASK
|
553 OMAP3430_RST3_IVA2_MASK
,
554 OMAP3430_IVA2_MOD
, OMAP2_RM_RSTCTRL
);
556 /* Enable IVA2 clock */
557 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK
,
558 OMAP3430_IVA2_MOD
, CM_FCLKEN
);
560 /* Set IVA2 boot mode to 'idle' */
561 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE
,
562 OMAP343X_CONTROL_IVA2_BOOTMOD
);
565 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD
, OMAP2_RM_RSTCTRL
);
567 /* Disable IVA2 clock */
568 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD
, CM_FCLKEN
);
571 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK
|
572 OMAP3430_RST2_IVA2_MASK
|
573 OMAP3430_RST3_IVA2_MASK
,
574 OMAP3430_IVA2_MOD
, OMAP2_RM_RSTCTRL
);
577 static void __init
omap3_d2d_idle(void)
581 /* In a stand alone OMAP3430 where there is not a stacked
582 * modem for the D2D Idle Ack and D2D MStandby must be pulled
583 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
584 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
585 mask
= (1 << 4) | (1 << 3); /* pull-up, enabled */
586 padconf
= omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY
);
588 omap_ctrl_writew(padconf
, OMAP3_PADCONF_SAD2D_MSTANDBY
);
590 padconf
= omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK
);
592 omap_ctrl_writew(padconf
, OMAP3_PADCONF_SAD2D_IDLEACK
);
595 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK
|
596 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK
,
597 CORE_MOD
, OMAP2_RM_RSTCTRL
);
598 omap2_prm_write_mod_reg(0, CORE_MOD
, OMAP2_RM_RSTCTRL
);
601 static void __init
prcm_setup_regs(void)
603 u32 omap3630_en_uart4_mask
= cpu_is_omap3630() ?
604 OMAP3630_EN_UART4_MASK
: 0;
605 u32 omap3630_grpsel_uart4_mask
= cpu_is_omap3630() ?
606 OMAP3630_GRPSEL_UART4_MASK
: 0;
608 /* XXX This should be handled by hwmod code or SCM init code */
609 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK
, OMAP2_CONTROL_SYSCONFIG
);
612 * Enable control of expternal oscillator through
613 * sys_clkreq. In the long run clock framework should
616 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK
,
617 1 << OMAP_AUTOEXTCLKMODE_SHIFT
,
619 OMAP3_PRM_CLKSRC_CTRL_OFFSET
);
621 /* setup wakup source */
622 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK
| OMAP3430_EN_GPIO1_MASK
|
623 OMAP3430_EN_GPT1_MASK
| OMAP3430_EN_GPT12_MASK
,
625 /* No need to write EN_IO, that is always enabled */
626 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK
|
627 OMAP3430_GRPSEL_GPT1_MASK
|
628 OMAP3430_GRPSEL_GPT12_MASK
,
629 WKUP_MOD
, OMAP3430_PM_MPUGRPSEL
);
631 /* Enable PM_WKEN to support DSS LPR */
632 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK
,
633 OMAP3430_DSS_MOD
, PM_WKEN
);
635 /* Enable wakeups in PER */
636 omap2_prm_write_mod_reg(omap3630_en_uart4_mask
|
637 OMAP3430_EN_GPIO2_MASK
| OMAP3430_EN_GPIO3_MASK
|
638 OMAP3430_EN_GPIO4_MASK
| OMAP3430_EN_GPIO5_MASK
|
639 OMAP3430_EN_GPIO6_MASK
| OMAP3430_EN_UART3_MASK
|
640 OMAP3430_EN_MCBSP2_MASK
| OMAP3430_EN_MCBSP3_MASK
|
641 OMAP3430_EN_MCBSP4_MASK
,
642 OMAP3430_PER_MOD
, PM_WKEN
);
643 /* and allow them to wake up MPU */
644 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask
|
645 OMAP3430_GRPSEL_GPIO2_MASK
|
646 OMAP3430_GRPSEL_GPIO3_MASK
|
647 OMAP3430_GRPSEL_GPIO4_MASK
|
648 OMAP3430_GRPSEL_GPIO5_MASK
|
649 OMAP3430_GRPSEL_GPIO6_MASK
|
650 OMAP3430_GRPSEL_UART3_MASK
|
651 OMAP3430_GRPSEL_MCBSP2_MASK
|
652 OMAP3430_GRPSEL_MCBSP3_MASK
|
653 OMAP3430_GRPSEL_MCBSP4_MASK
,
654 OMAP3430_PER_MOD
, OMAP3430_PM_MPUGRPSEL
);
656 /* Don't attach IVA interrupts */
657 omap2_prm_write_mod_reg(0, WKUP_MOD
, OMAP3430_PM_IVAGRPSEL
);
658 omap2_prm_write_mod_reg(0, CORE_MOD
, OMAP3430_PM_IVAGRPSEL1
);
659 omap2_prm_write_mod_reg(0, CORE_MOD
, OMAP3430ES2_PM_IVAGRPSEL3
);
660 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD
, OMAP3430_PM_IVAGRPSEL
);
662 /* Clear any pending 'reset' flags */
663 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD
, OMAP2_RM_RSTST
);
664 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD
, OMAP2_RM_RSTST
);
665 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD
, OMAP2_RM_RSTST
);
666 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD
, OMAP2_RM_RSTST
);
667 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD
, OMAP2_RM_RSTST
);
668 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD
, OMAP2_RM_RSTST
);
669 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD
, OMAP2_RM_RSTST
);
671 /* Clear any pending PRCM interrupts */
672 omap2_prm_write_mod_reg(0, OCP_MOD
, OMAP3_PRM_IRQSTATUS_MPU_OFFSET
);
678 void omap3_pm_off_mode_enable(int enable
)
680 struct power_state
*pwrst
;
684 state
= PWRDM_POWER_OFF
;
686 state
= PWRDM_POWER_RET
;
688 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
689 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583
) &&
690 pwrst
->pwrdm
== core_pwrdm
&&
691 state
== PWRDM_POWER_OFF
) {
692 pwrst
->next_state
= PWRDM_POWER_RET
;
693 pr_warn("%s: Core OFF disabled due to errata i583\n",
696 pwrst
->next_state
= state
;
698 omap_set_pwrdm_state(pwrst
->pwrdm
, pwrst
->next_state
);
702 int omap3_pm_get_suspend_state(struct powerdomain
*pwrdm
)
704 struct power_state
*pwrst
;
706 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
707 if (pwrst
->pwrdm
== pwrdm
)
708 return pwrst
->next_state
;
713 int omap3_pm_set_suspend_state(struct powerdomain
*pwrdm
, int state
)
715 struct power_state
*pwrst
;
717 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
718 if (pwrst
->pwrdm
== pwrdm
) {
719 pwrst
->next_state
= state
;
726 static int __init
pwrdms_setup(struct powerdomain
*pwrdm
, void *unused
)
728 struct power_state
*pwrst
;
733 pwrst
= kmalloc(sizeof(struct power_state
), GFP_ATOMIC
);
736 pwrst
->pwrdm
= pwrdm
;
737 pwrst
->next_state
= PWRDM_POWER_RET
;
738 list_add(&pwrst
->node
, &pwrst_list
);
740 if (pwrdm_has_hdwr_sar(pwrdm
))
741 pwrdm_enable_hdwr_sar(pwrdm
);
743 return omap_set_pwrdm_state(pwrst
->pwrdm
, pwrst
->next_state
);
747 * Enable hw supervised mode for all clockdomains if it's
748 * supported. Initiate sleep transition for other clockdomains, if
751 static int __init
clkdms_setup(struct clockdomain
*clkdm
, void *unused
)
753 if (clkdm
->flags
& CLKDM_CAN_ENABLE_AUTO
)
754 clkdm_allow_idle(clkdm
);
755 else if (clkdm
->flags
& CLKDM_CAN_FORCE_SLEEP
&&
756 atomic_read(&clkdm
->usecount
) == 0)
762 * Push functions to SRAM
764 * The minimum set of functions is pushed to SRAM for execution:
765 * - omap3_do_wfi for erratum i581 WA,
766 * - save_secure_ram_context for security extensions.
768 void omap_push_sram_idle(void)
770 omap3_do_wfi_sram
= omap_sram_push(omap3_do_wfi
, omap3_do_wfi_sz
);
772 if (omap_type() != OMAP2_DEVICE_TYPE_GP
)
773 _omap_save_secure_sram
= omap_sram_push(save_secure_ram_context
,
774 save_secure_ram_context_sz
);
777 static void __init
pm_errata_configure(void)
779 if (cpu_is_omap3630()) {
780 pm34xx_errata
|= PM_RTA_ERRATUM_i608
;
781 /* Enable the l2 cache toggling in sleep logic */
782 enable_omap3630_toggle_l2_on_restore();
783 if (omap_rev() < OMAP3630_REV_ES1_2
)
784 pm34xx_errata
|= PM_SDRC_WAKEUP_ERRATUM_i583
;
788 static int __init
omap3_pm_init(void)
790 struct power_state
*pwrst
, *tmp
;
791 struct clockdomain
*neon_clkdm
, *per_clkdm
, *mpu_clkdm
, *core_clkdm
;
794 if (!cpu_is_omap34xx())
797 if (!omap3_has_io_chain_ctrl())
798 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
800 pm_errata_configure();
802 /* XXX prcm_setup_regs needs to be before enabling hw
803 * supervised mode for powerdomains */
806 ret
= request_irq(omap_prcm_event_to_irq("wkup"),
807 _prcm_int_handle_wakeup
, IRQF_NO_SUSPEND
, "pm_wkup", NULL
);
810 pr_err("pm: Failed to request pm_wkup irq\n");
814 /* IO interrupt is shared with mux code */
815 ret
= request_irq(omap_prcm_event_to_irq("io"),
816 _prcm_int_handle_io
, IRQF_SHARED
| IRQF_NO_SUSPEND
, "pm_io",
820 pr_err("pm: Failed to request pm_io irq\n");
824 ret
= pwrdm_for_each(pwrdms_setup
, NULL
);
826 printk(KERN_ERR
"Failed to setup powerdomains\n");
830 (void) clkdm_for_each(clkdms_setup
, NULL
);
832 mpu_pwrdm
= pwrdm_lookup("mpu_pwrdm");
833 if (mpu_pwrdm
== NULL
) {
834 printk(KERN_ERR
"Failed to get mpu_pwrdm\n");
838 neon_pwrdm
= pwrdm_lookup("neon_pwrdm");
839 per_pwrdm
= pwrdm_lookup("per_pwrdm");
840 core_pwrdm
= pwrdm_lookup("core_pwrdm");
841 cam_pwrdm
= pwrdm_lookup("cam_pwrdm");
843 neon_clkdm
= clkdm_lookup("neon_clkdm");
844 mpu_clkdm
= clkdm_lookup("mpu_clkdm");
845 per_clkdm
= clkdm_lookup("per_clkdm");
846 core_clkdm
= clkdm_lookup("core_clkdm");
848 #ifdef CONFIG_SUSPEND
849 suspend_set_ops(&omap_pm_ops
);
850 #endif /* CONFIG_SUSPEND */
852 pm_idle
= omap3_pm_idle
;
856 * RTA is disabled during initialization as per erratum i608
857 * it is safer to disable RTA by the bootloader, but we would like
858 * to be doubly sure here and prevent any mishaps.
860 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608
))
861 omap3630_ctrl_disable_rta();
863 clkdm_add_wkdep(neon_clkdm
, mpu_clkdm
);
864 if (omap_type() != OMAP2_DEVICE_TYPE_GP
) {
865 omap3_secure_ram_storage
=
866 kmalloc(0x803F, GFP_KERNEL
);
867 if (!omap3_secure_ram_storage
)
868 printk(KERN_ERR
"Memory allocation failed when"
869 "allocating for secure sram context\n");
874 omap_dma_global_context_save();
875 omap3_save_secure_ram_context();
876 omap_dma_global_context_restore();
882 omap3_save_scratchpad_contents();
886 free_irq(INT_34XX_PRCM_MPU_IRQ
, NULL
);
887 list_for_each_entry_safe(pwrst
, tmp
, &pwrst_list
, node
) {
888 list_del(&pwrst
->node
);
894 late_initcall(omap3_pm_init
);