2 * linux/arch/arm/kernel/dec21285.c: PCI functions for DC21285
4 * Copyright (C) 1998-2001 Russell King
5 * Copyright (C) 1998-2000 Phil Blundell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/interrupt.h>
15 #include <linux/slab.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/irq.h>
20 #include <linux/spinlock.h>
21 #include <video/vga.h>
24 #include <asm/mach/pci.h>
25 #include <asm/hardware/dec21285.h>
29 #define PCICMD_ABORT ((PCI_STATUS_REC_MASTER_ABORT| \
30 PCI_STATUS_REC_TARGET_ABORT)<<16)
32 #define PCICMD_ERROR_BITS ((PCI_STATUS_DETECTED_PARITY | \
33 PCI_STATUS_REC_MASTER_ABORT | \
34 PCI_STATUS_REC_TARGET_ABORT | \
35 PCI_STATUS_PARITY) << 16)
37 extern int setup_arm_irq(int, struct irqaction
*);
38 extern void pcibios_report_status(u_int status_mask
, int warn
);
41 dc21285_base_address(struct pci_bus
*bus
, unsigned int devfn
)
43 unsigned long addr
= 0;
45 if (bus
->number
== 0) {
46 if (PCI_SLOT(devfn
) == 0)
48 * For devfn 0, point at the 21285
54 if (devfn
< PCI_DEVFN(MAX_SLOTS
, 0))
55 addr
= PCICFG0_BASE
| 0xc00000 | (devfn
<< 8);
58 addr
= PCICFG1_BASE
| (bus
->number
<< 16) | (devfn
<< 8);
64 dc21285_read_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
67 unsigned long addr
= dc21285_base_address(bus
, devfn
);
73 asm("ldrb %0, [%1, %2]"
74 : "=r" (v
) : "r" (addr
), "r" (where
) : "cc");
77 asm("ldrh %0, [%1, %2]"
78 : "=r" (v
) : "r" (addr
), "r" (where
) : "cc");
81 asm("ldr %0, [%1, %2]"
82 : "=r" (v
) : "r" (addr
), "r" (where
) : "cc");
89 if (v
& PCICMD_ABORT
) {
90 *CSR_PCICMD
= v
& (0xffff|PCICMD_ABORT
);
94 return PCIBIOS_SUCCESSFUL
;
98 dc21285_write_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
101 unsigned long addr
= dc21285_base_address(bus
, devfn
);
107 asm("strb %0, [%1, %2]"
108 : : "r" (value
), "r" (addr
), "r" (where
)
112 asm("strh %0, [%1, %2]"
113 : : "r" (value
), "r" (addr
), "r" (where
)
117 asm("str %0, [%1, %2]"
118 : : "r" (value
), "r" (addr
), "r" (where
)
124 if (v
& PCICMD_ABORT
) {
125 *CSR_PCICMD
= v
& (0xffff|PCICMD_ABORT
);
129 return PCIBIOS_SUCCESSFUL
;
132 static struct pci_ops dc21285_ops
= {
133 .read
= dc21285_read_config
,
134 .write
= dc21285_write_config
,
137 static struct timer_list serr_timer
;
138 static struct timer_list perr_timer
;
140 static void dc21285_enable_error(unsigned long __data
)
144 del_timer(&serr_timer
);
148 del_timer(&perr_timer
);
156 * Warn on PCI errors.
158 static irqreturn_t
dc21285_abort_irq(int irq
, void *dev_id
)
167 if (status
& PCI_STATUS_REC_MASTER_ABORT
) {
168 printk(KERN_DEBUG
"PCI: master abort, pc=0x%08lx\n",
169 instruction_pointer(get_irq_regs()));
170 cmd
|= PCI_STATUS_REC_MASTER_ABORT
<< 16;
173 if (status
& PCI_STATUS_REC_TARGET_ABORT
) {
174 printk(KERN_DEBUG
"PCI: target abort: ");
175 pcibios_report_status(PCI_STATUS_REC_MASTER_ABORT
|
176 PCI_STATUS_SIG_TARGET_ABORT
|
177 PCI_STATUS_REC_TARGET_ABORT
, 1);
180 cmd
|= PCI_STATUS_REC_TARGET_ABORT
<< 16;
188 static irqreturn_t
dc21285_serr_irq(int irq
, void *dev_id
)
190 struct timer_list
*timer
= dev_id
;
193 printk(KERN_DEBUG
"PCI: system error received: ");
194 pcibios_report_status(PCI_STATUS_SIG_SYSTEM_ERROR
, 1);
197 cntl
= *CSR_SA110_CNTL
& 0xffffdf07;
198 *CSR_SA110_CNTL
= cntl
| SA110_CNTL_RXSERR
;
201 * back off this interrupt
204 timer
->expires
= jiffies
+ HZ
;
210 static irqreturn_t
dc21285_discard_irq(int irq
, void *dev_id
)
212 printk(KERN_DEBUG
"PCI: discard timer expired\n");
213 *CSR_SA110_CNTL
&= 0xffffde07;
218 static irqreturn_t
dc21285_dparity_irq(int irq
, void *dev_id
)
222 printk(KERN_DEBUG
"PCI: data parity error detected: ");
223 pcibios_report_status(PCI_STATUS_PARITY
| PCI_STATUS_DETECTED_PARITY
, 1);
226 cmd
= *CSR_PCICMD
& 0xffff;
227 *CSR_PCICMD
= cmd
| 1 << 24;
232 static irqreturn_t
dc21285_parity_irq(int irq
, void *dev_id
)
234 struct timer_list
*timer
= dev_id
;
237 printk(KERN_DEBUG
"PCI: parity error detected: ");
238 pcibios_report_status(PCI_STATUS_PARITY
| PCI_STATUS_DETECTED_PARITY
, 1);
241 cmd
= *CSR_PCICMD
& 0xffff;
242 *CSR_PCICMD
= cmd
| 1 << 31;
245 * back off this interrupt
248 timer
->expires
= jiffies
+ HZ
;
254 int __init
dc21285_setup(int nr
, struct pci_sys_data
*sys
)
256 struct resource
*res
;
258 if (nr
|| !footbridge_cfn_mode())
261 res
= kzalloc(sizeof(struct resource
) * 2, GFP_KERNEL
);
263 printk("out of memory for root bus resources");
267 res
[0].flags
= IORESOURCE_MEM
;
268 res
[0].name
= "Footbridge non-prefetch";
269 res
[1].flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
270 res
[1].name
= "Footbridge prefetch";
272 allocate_resource(&iomem_resource
, &res
[1], 0x20000000,
273 0xa0000000, 0xffffffff, 0x20000000, NULL
, NULL
);
274 allocate_resource(&iomem_resource
, &res
[0], 0x40000000,
275 0x80000000, 0xffffffff, 0x40000000, NULL
, NULL
);
277 pci_add_resource(&sys
->resources
, &ioport_resource
);
278 pci_add_resource(&sys
->resources
, &res
[0]);
279 pci_add_resource(&sys
->resources
, &res
[1]);
280 sys
->mem_offset
= DC21285_PCI_MEM
;
285 struct pci_bus
* __init
dc21285_scan_bus(int nr
, struct pci_sys_data
*sys
)
287 return pci_scan_root_bus(NULL
, 0, &dc21285_ops
, sys
, &sys
->resources
);
290 #define dc21285_request_irq(_a, _b, _c, _d, _e) \
291 WARN_ON(request_irq(_a, _b, _c, _d, _e) < 0)
293 void __init
dc21285_preinit(void)
295 unsigned int mem_size
, mem_mask
;
298 pcibios_min_mem
= 0x81000000;
299 vga_base
= PCIMEM_BASE
;
301 mem_size
= (unsigned int)high_memory
- PAGE_OFFSET
;
302 for (mem_mask
= 0x00100000; mem_mask
< 0x10000000; mem_mask
<<= 1)
303 if (mem_mask
>= mem_size
)
307 * These registers need to be set up whether we're the
308 * central function or not.
310 *CSR_SDRAMBASEMASK
= (mem_mask
- 1) & 0x0ffc0000;
311 *CSR_SDRAMBASEOFFSET
= 0;
312 *CSR_ROMBASEMASK
= 0x80000000;
313 *CSR_CSRBASEMASK
= 0;
314 *CSR_CSRBASEOFFSET
= 0;
315 *CSR_PCIADDR_EXTN
= 0;
317 cfn_mode
= __footbridge_cfn_mode();
319 printk(KERN_INFO
"PCI: DC21285 footbridge, revision %02lX, in "
320 "%s mode\n", *CSR_CLASSREV
& 0xff, cfn_mode
?
321 "central function" : "addin");
323 if (footbridge_cfn_mode()) {
325 * Clear any existing errors - we aren't
326 * interested in historical data...
328 *CSR_SA110_CNTL
= (*CSR_SA110_CNTL
& 0xffffde07) |
330 *CSR_PCICMD
= (*CSR_PCICMD
& 0xffff) | PCICMD_ERROR_BITS
;
333 init_timer(&serr_timer
);
334 init_timer(&perr_timer
);
336 serr_timer
.data
= IRQ_PCI_SERR
;
337 serr_timer
.function
= dc21285_enable_error
;
338 perr_timer
.data
= IRQ_PCI_PERR
;
339 perr_timer
.function
= dc21285_enable_error
;
342 * We don't care if these fail.
344 dc21285_request_irq(IRQ_PCI_SERR
, dc21285_serr_irq
, IRQF_DISABLED
,
345 "PCI system error", &serr_timer
);
346 dc21285_request_irq(IRQ_PCI_PERR
, dc21285_parity_irq
, IRQF_DISABLED
,
347 "PCI parity error", &perr_timer
);
348 dc21285_request_irq(IRQ_PCI_ABORT
, dc21285_abort_irq
, IRQF_DISABLED
,
350 dc21285_request_irq(IRQ_DISCARD_TIMER
, dc21285_discard_irq
, IRQF_DISABLED
,
351 "Discard timer", NULL
);
352 dc21285_request_irq(IRQ_PCI_DPERR
, dc21285_dparity_irq
, IRQF_DISABLED
,
353 "PCI data parity", NULL
);
356 static struct resource csrio
;
358 csrio
.flags
= IORESOURCE_IO
;
359 csrio
.name
= "Footbridge";
361 allocate_resource(&ioport_resource
, &csrio
, 128,
362 0xff00, 0xffff, 128, NULL
, NULL
);
365 * Map our SDRAM at a known address in PCI space, just in case
366 * the firmware had other ideas. Using a nonzero base is
367 * necessary, since some VGA cards forcefully use PCI addresses
368 * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards).
370 *CSR_PCICSRBASE
= 0xf4000000;
371 *CSR_PCICSRIOBASE
= csrio
.start
;
372 *CSR_PCISDRAMBASE
= __virt_to_bus(PAGE_OFFSET
);
374 *CSR_PCICMD
= PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
375 PCI_COMMAND_INVALIDATE
| PCICMD_ERROR_BITS
;
376 } else if (footbridge_cfn_mode() != 0) {
378 * If we are not compiled to accept "add-in" mode, then
379 * we are using a constant virt_to_bus translation which
380 * can not hope to cater for the way the host BIOS has
381 * set up the machine.
383 panic("PCI: this kernel is compiled for central "
384 "function mode only");
388 void __init
dc21285_postinit(void)
390 register_isa_ports(DC21285_PCI_MEM
, DC21285_PCI_IO
, 0);