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regulator: fix header file missing kernel-doc
[linux-2.6.git] / drivers / media / video / pxa_camera.c
blobc639845460fff8df6a327bf1f7e21ebbb954ac34
1 /*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
19 #include <linux/fs.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mm.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29
30 #include <media/v4l2-common.h>
31 #include <media/v4l2-dev.h>
32 #include <media/videobuf-dma-sg.h>
33 #include <media/soc_camera.h>
34
35 #include <linux/videodev2.h>
36
37 #include <mach/dma.h>
38 #include <mach/camera.h>
39
40 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
41 #define PXA_CAM_DRV_NAME "pxa27x-camera"
42
43 /* Camera Interface */
44 #define CICR0 0x0000
45 #define CICR1 0x0004
46 #define CICR2 0x0008
47 #define CICR3 0x000C
48 #define CICR4 0x0010
49 #define CISR 0x0014
50 #define CIFR 0x0018
51 #define CITOR 0x001C
52 #define CIBR0 0x0028
53 #define CIBR1 0x0030
54 #define CIBR2 0x0038
55
56 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
57 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
58 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
59 #define CICR0_ENB (1 << 28) /* Camera interface enable */
60 #define CICR0_DIS (1 << 27) /* Camera interface disable */
61 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
62 #define CICR0_TOM (1 << 9) /* Time-out mask */
63 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
64 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
65 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
66 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
67 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
68 #define CICR0_CDM (1 << 3) /* Disable-done mask */
69 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
70 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
71 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
72
73 #define CICR1_TBIT (1 << 31) /* Transparency bit */
74 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
75 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
76 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
77 #define CICR1_RGB_F (1 << 11) /* RGB format */
78 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
79 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
80 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
81 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
82 #define CICR1_DW (0x7 << 0) /* Data width mask */
83
84 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
85 wait count mask */
86 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
87 wait count mask */
88 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
89 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
90 wait count mask */
91 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
92 wait count mask */
93
94 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
95 wait count mask */
96 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
97 wait count mask */
98 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
99 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
100 wait count mask */
101 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
102
103 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
104 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
105 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
106 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
107 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
108 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
109 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
110 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
111
112 #define CISR_FTO (1 << 15) /* FIFO time-out */
113 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
114 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
115 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
116 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
117 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
118 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
119 #define CISR_EOL (1 << 8) /* End of line */
120 #define CISR_PAR_ERR (1 << 7) /* Parity error */
121 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
122 #define CISR_CDD (1 << 5) /* Camera interface disable done */
123 #define CISR_SOF (1 << 4) /* Start of frame */
124 #define CISR_EOF (1 << 3) /* End of frame */
125 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
126 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
127 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
128
129 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
130 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
131 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
132 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
133 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
134 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
135 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
136 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
137
138 #define CICR0_SIM_MP (0 << 24)
139 #define CICR0_SIM_SP (1 << 24)
140 #define CICR0_SIM_MS (2 << 24)
141 #define CICR0_SIM_EP (3 << 24)
142 #define CICR0_SIM_ES (4 << 24)
143
144 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
145 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
146 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
147 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
148 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
149
150 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
151 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
152 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
153 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
154 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
155
156 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
157 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
158 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
159 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
160
161 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
162 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
163 CICR0_EOFM | CICR0_FOM)
164
165 /*
166 * YUV422P picture size should be a multiple of 16, so the heuristic aligns
167 * height, width on 4 byte boundaries to reach the 16 multiple for the size.
168 */
169 #define YUV422P_X_Y_ALIGN 4
170 #define YUV422P_SIZE_ALIGN YUV422P_X_Y_ALIGN * YUV422P_X_Y_ALIGN
171
172 /*
173 * Structures
174 */
175 enum pxa_camera_active_dma {
176 DMA_Y = 0x1,
177 DMA_U = 0x2,
178 DMA_V = 0x4,
179 };
180
181 /* descriptor needed for the PXA DMA engine */
182 struct pxa_cam_dma {
183 dma_addr_t sg_dma;
184 struct pxa_dma_desc *sg_cpu;
185 size_t sg_size;
186 int sglen;
187 };
188
189 /* buffer for one video frame */
190 struct pxa_buffer {
191 /* common v4l buffer stuff -- must be first */
192 struct videobuf_buffer vb;
193
194 const struct soc_camera_data_format *fmt;
195
196 /* our descriptor lists for Y, U and V channels */
197 struct pxa_cam_dma dmas[3];
198
199 int inwork;
200
201 enum pxa_camera_active_dma active_dma;
202 };
203
204 struct pxa_camera_dev {
205 struct device *dev;
206 /* PXA27x is only supposed to handle one camera on its Quick Capture
207 * interface. If anyone ever builds hardware to enable more than
208 * one camera, they will have to modify this driver too */
209 struct soc_camera_device *icd;
210 struct clk *clk;
211
212 unsigned int irq;
213 void __iomem *base;
214
215 int channels;
216 unsigned int dma_chans[3];
217
218 struct pxacamera_platform_data *pdata;
219 struct resource *res;
220 unsigned long platform_flags;
221 unsigned long ciclk;
222 unsigned long mclk;
223 u32 mclk_divisor;
224
225 struct list_head capture;
226
227 spinlock_t lock;
228
229 struct pxa_buffer *active;
230 struct pxa_dma_desc *sg_tail[3];
231
232 u32 save_cicr[5];
233 };
234
235 static const char *pxa_cam_driver_description = "PXA_Camera";
236
237 static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
238
239 /*
240 * Videobuf operations
241 */
242 static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
243 unsigned int *size)
244 {
245 struct soc_camera_device *icd = vq->priv_data;
246
247 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
248
249 *size = roundup(icd->width * icd->height *
250 ((icd->current_fmt->depth + 7) >> 3), 8);
251
252 if (0 == *count)
253 *count = 32;
254 while (*size * *count > vid_limit * 1024 * 1024)
255 (*count)--;
256
257 return 0;
258 }
259
260 static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
261 {
262 struct soc_camera_device *icd = vq->priv_data;
263 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
264 struct pxa_camera_dev *pcdev = ici->priv;
265 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
266 int i;
267
268 BUG_ON(in_interrupt());
269
270 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
271 &buf->vb, buf->vb.baddr, buf->vb.bsize);
272
273 /* This waits until this buffer is out of danger, i.e., until it is no
274 * longer in STATE_QUEUED or STATE_ACTIVE */
275 videobuf_waiton(&buf->vb, 0, 0);
276 videobuf_dma_unmap(vq, dma);
277 videobuf_dma_free(dma);
278
279 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
280 if (buf->dmas[i].sg_cpu)
281 dma_free_coherent(pcdev->dev, buf->dmas[i].sg_size,
282 buf->dmas[i].sg_cpu,
283 buf->dmas[i].sg_dma);
284 buf->dmas[i].sg_cpu = NULL;
285 }
286
287 buf->vb.state = VIDEOBUF_NEEDS_INIT;
288 }
289
290 static int calculate_dma_sglen(struct scatterlist *sglist, int sglen,
291 int sg_first_ofs, int size)
292 {
293 int i, offset, dma_len, xfer_len;
294 struct scatterlist *sg;
295
296 offset = sg_first_ofs;
297 for_each_sg(sglist, sg, sglen, i) {
298 dma_len = sg_dma_len(sg);
299
300 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
301 xfer_len = roundup(min(dma_len - offset, size), 8);
302
303 size = max(0, size - xfer_len);
304 offset = 0;
305 if (size == 0)
306 break;
307 }
308
309 BUG_ON(size != 0);
310 return i + 1;
311 }
312
313 /**
314 * pxa_init_dma_channel - init dma descriptors
315 * @pcdev: pxa camera device
316 * @buf: pxa buffer to find pxa dma channel
317 * @dma: dma video buffer
318 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
319 * @cibr: camera Receive Buffer Register
320 * @size: bytes to transfer
321 * @sg_first: first element of sg_list
322 * @sg_first_ofs: offset in first element of sg_list
323 *
324 * Prepares the pxa dma descriptors to transfer one camera channel.
325 * Beware sg_first and sg_first_ofs are both input and output parameters.
326 *
327 * Returns 0 or -ENOMEM if no coherent memory is available
328 */
329 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
330 struct pxa_buffer *buf,
331 struct videobuf_dmabuf *dma, int channel,
332 int cibr, int size,
333 struct scatterlist **sg_first, int *sg_first_ofs)
334 {
335 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
336 struct scatterlist *sg;
337 int i, offset, sglen;
338 int dma_len = 0, xfer_len = 0;
339
340 if (pxa_dma->sg_cpu)
341 dma_free_coherent(pcdev->dev, pxa_dma->sg_size,
342 pxa_dma->sg_cpu, pxa_dma->sg_dma);
343
344 sglen = calculate_dma_sglen(*sg_first, dma->sglen,
345 *sg_first_ofs, size);
346
347 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
348 pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->dev, pxa_dma->sg_size,
349 &pxa_dma->sg_dma, GFP_KERNEL);
350 if (!pxa_dma->sg_cpu)
351 return -ENOMEM;
352
353 pxa_dma->sglen = sglen;
354 offset = *sg_first_ofs;
355
356 dev_dbg(pcdev->dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
357 *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma);
358
359
360 for_each_sg(*sg_first, sg, sglen, i) {
361 dma_len = sg_dma_len(sg);
362
363 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
364 xfer_len = roundup(min(dma_len - offset, size), 8);
365
366 size = max(0, size - xfer_len);
367
368 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
369 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset;
370 pxa_dma->sg_cpu[i].dcmd =
371 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
372 #ifdef DEBUG
373 if (!i)
374 pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN;
375 #endif
376 pxa_dma->sg_cpu[i].ddadr =
377 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
378
379 dev_vdbg(pcdev->dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
380 pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc),
381 sg_dma_address(sg) + offset, xfer_len);
382 offset = 0;
383
384 if (size == 0)
385 break;
386 }
387
388 pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP;
389 pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN;
390
391 /*
392 * Handle 1 special case :
393 * - in 3 planes (YUV422P format), we might finish with xfer_len equal
394 * to dma_len (end on PAGE boundary). In this case, the sg element
395 * for next plane should be the next after the last used to store the
396 * last scatter gather RAM page
397 */
398 if (xfer_len >= dma_len) {
399 *sg_first_ofs = xfer_len - dma_len;
400 *sg_first = sg_next(sg);
401 } else {
402 *sg_first_ofs = xfer_len;
403 *sg_first = sg;
404 }
405
406 return 0;
407 }
408
409 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
410 struct pxa_buffer *buf)
411 {
412 buf->active_dma = DMA_Y;
413 if (pcdev->channels == 3)
414 buf->active_dma |= DMA_U | DMA_V;
415 }
416
417 /*
418 * Please check the DMA prepared buffer structure in :
419 * Documentation/video4linux/pxa_camera.txt
420 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
421 * modification while DMA chain is running will work anyway.
422 */
423 static int pxa_videobuf_prepare(struct videobuf_queue *vq,
424 struct videobuf_buffer *vb, enum v4l2_field field)
425 {
426 struct soc_camera_device *icd = vq->priv_data;
427 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
428 struct pxa_camera_dev *pcdev = ici->priv;
429 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
430 int ret;
431 int size_y, size_u = 0, size_v = 0;
432
433 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
434 vb, vb->baddr, vb->bsize);
435
436 /* Added list head initialization on alloc */
437 WARN_ON(!list_empty(&vb->queue));
438
439 #ifdef DEBUG
440 /* This can be useful if you want to see if we actually fill
441 * the buffer with something */
442 memset((void *)vb->baddr, 0xaa, vb->bsize);
443 #endif
444
445 BUG_ON(NULL == icd->current_fmt);
446
447 /* I think, in buf_prepare you only have to protect global data,
448 * the actual buffer is yours */
449 buf->inwork = 1;
450
451 if (buf->fmt != icd->current_fmt ||
452 vb->width != icd->width ||
453 vb->height != icd->height ||
454 vb->field != field) {
455 buf->fmt = icd->current_fmt;
456 vb->width = icd->width;
457 vb->height = icd->height;
458 vb->field = field;
459 vb->state = VIDEOBUF_NEEDS_INIT;
460 }
461
462 vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3);
463 if (0 != vb->baddr && vb->bsize < vb->size) {
464 ret = -EINVAL;
465 goto out;
466 }
467
468 if (vb->state == VIDEOBUF_NEEDS_INIT) {
469 int size = vb->size;
470 int next_ofs = 0;
471 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
472 struct scatterlist *sg;
473
474 ret = videobuf_iolock(vq, vb, NULL);
475 if (ret)
476 goto fail;
477
478 if (pcdev->channels == 3) {
479 size_y = size / 2;
480 size_u = size_v = size / 4;
481 } else {
482 size_y = size;
483 }
484
485 sg = dma->sglist;
486
487 /* init DMA for Y channel */
488 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y,
489 &sg, &next_ofs);
490 if (ret) {
491 dev_err(pcdev->dev,
492 "DMA initialization for Y/RGB failed\n");
493 goto fail;
494 }
495
496 /* init DMA for U channel */
497 if (size_u)
498 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1,
499 size_u, &sg, &next_ofs);
500 if (ret) {
501 dev_err(pcdev->dev,
502 "DMA initialization for U failed\n");
503 goto fail_u;
504 }
505
506 /* init DMA for V channel */
507 if (size_v)
508 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2,
509 size_v, &sg, &next_ofs);
510 if (ret) {
511 dev_err(pcdev->dev,
512 "DMA initialization for V failed\n");
513 goto fail_v;
514 }
515
516 vb->state = VIDEOBUF_PREPARED;
517 }
518
519 buf->inwork = 0;
520 pxa_videobuf_set_actdma(pcdev, buf);
521
522 return 0;
523
524 fail_v:
525 dma_free_coherent(pcdev->dev, buf->dmas[1].sg_size,
526 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
527 fail_u:
528 dma_free_coherent(pcdev->dev, buf->dmas[0].sg_size,
529 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
530 fail:
531 free_buffer(vq, buf);
532 out:
533 buf->inwork = 0;
534 return ret;
535 }
536
537 /**
538 * pxa_dma_start_channels - start DMA channel for active buffer
539 * @pcdev: pxa camera device
540 *
541 * Initialize DMA channels to the beginning of the active video buffer, and
542 * start these channels.
543 */
544 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
545 {
546 int i;
547 struct pxa_buffer *active;
548
549 active = pcdev->active;
550
551 for (i = 0; i < pcdev->channels; i++) {
552 dev_dbg(pcdev->dev, "%s (channel=%d) ddadr=%08x\n", __func__,
553 i, active->dmas[i].sg_dma);
554 DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma;
555 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
556 }
557 }
558
559 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
560 {
561 int i;
562
563 for (i = 0; i < pcdev->channels; i++) {
564 dev_dbg(pcdev->dev, "%s (channel=%d)\n", __func__, i);
565 DCSR(pcdev->dma_chans[i]) = 0;
566 }
567 }
568
569 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
570 struct pxa_buffer *buf)
571 {
572 int i;
573 struct pxa_dma_desc *buf_last_desc;
574
575 for (i = 0; i < pcdev->channels; i++) {
576 buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen;
577 buf_last_desc->ddadr = DDADR_STOP;
578
579 if (pcdev->sg_tail[i])
580 /* Link the new buffer to the old tail */
581 pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma;
582
583 /* Update the channel tail */
584 pcdev->sg_tail[i] = buf_last_desc;
585 }
586 }
587
588 /**
589 * pxa_camera_start_capture - start video capturing
590 * @pcdev: camera device
591 *
592 * Launch capturing. DMA channels should not be active yet. They should get
593 * activated at the end of frame interrupt, to capture only whole frames, and
594 * never begin the capture of a partial frame.
595 */
596 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
597 {
598 unsigned long cicr0, cifr;
599
600 dev_dbg(pcdev->dev, "%s\n", __func__);
601 /* Reset the FIFOs */
602 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
603 __raw_writel(cifr, pcdev->base + CIFR);
604 /* Enable End-Of-Frame Interrupt */
605 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
606 cicr0 &= ~CICR0_EOFM;
607 __raw_writel(cicr0, pcdev->base + CICR0);
608 }
609
610 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
611 {
612 unsigned long cicr0;
613
614 pxa_dma_stop_channels(pcdev);
615
616 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
617 __raw_writel(cicr0, pcdev->base + CICR0);
618
619 pcdev->active = NULL;
620 dev_dbg(pcdev->dev, "%s\n", __func__);
621 }
622
623 static void pxa_videobuf_queue(struct videobuf_queue *vq,
624 struct videobuf_buffer *vb)
625 {
626 struct soc_camera_device *icd = vq->priv_data;
627 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
628 struct pxa_camera_dev *pcdev = ici->priv;
629 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
630 unsigned long flags;
631
632 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d active=%p\n", __func__,
633 vb, vb->baddr, vb->bsize, pcdev->active);
634
635 spin_lock_irqsave(&pcdev->lock, flags);
636
637 list_add_tail(&vb->queue, &pcdev->capture);
638
639 vb->state = VIDEOBUF_ACTIVE;
640 pxa_dma_add_tail_buf(pcdev, buf);
641
642 if (!pcdev->active)
643 pxa_camera_start_capture(pcdev);
644
645 spin_unlock_irqrestore(&pcdev->lock, flags);
646 }
647
648 static void pxa_videobuf_release(struct videobuf_queue *vq,
649 struct videobuf_buffer *vb)
650 {
651 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
652 #ifdef DEBUG
653 struct soc_camera_device *icd = vq->priv_data;
654
655 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
656 vb, vb->baddr, vb->bsize);
657
658 switch (vb->state) {
659 case VIDEOBUF_ACTIVE:
660 dev_dbg(&icd->dev, "%s (active)\n", __func__);
661 break;
662 case VIDEOBUF_QUEUED:
663 dev_dbg(&icd->dev, "%s (queued)\n", __func__);
664 break;
665 case VIDEOBUF_PREPARED:
666 dev_dbg(&icd->dev, "%s (prepared)\n", __func__);
667 break;
668 default:
669 dev_dbg(&icd->dev, "%s (unknown)\n", __func__);
670 break;
671 }
672 #endif
673
674 free_buffer(vq, buf);
675 }
676
677 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
678 struct videobuf_buffer *vb,
679 struct pxa_buffer *buf)
680 {
681 int i;
682
683 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
684 list_del_init(&vb->queue);
685 vb->state = VIDEOBUF_DONE;
686 do_gettimeofday(&vb->ts);
687 vb->field_count++;
688 wake_up(&vb->done);
689 dev_dbg(pcdev->dev, "%s dequeud buffer (vb=0x%p)\n", __func__, vb);
690
691 if (list_empty(&pcdev->capture)) {
692 pxa_camera_stop_capture(pcdev);
693 for (i = 0; i < pcdev->channels; i++)
694 pcdev->sg_tail[i] = NULL;
695 return;
696 }
697
698 pcdev->active = list_entry(pcdev->capture.next,
699 struct pxa_buffer, vb.queue);
700 }
701
702 /**
703 * pxa_camera_check_link_miss - check missed DMA linking
704 * @pcdev: camera device
705 *
706 * The DMA chaining is done with DMA running. This means a tiny temporal window
707 * remains, where a buffer is queued on the chain, while the chain is already
708 * stopped. This means the tailed buffer would never be transfered by DMA.
709 * This function restarts the capture for this corner case, where :
710 * - DADR() == DADDR_STOP
711 * - a videobuffer is queued on the pcdev->capture list
712 *
713 * Please check the "DMA hot chaining timeslice issue" in
714 * Documentation/video4linux/pxa_camera.txt
715 *
716 * Context: should only be called within the dma irq handler
717 */
718 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev)
719 {
720 int i, is_dma_stopped = 1;
721
722 for (i = 0; i < pcdev->channels; i++)
723 if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP)
724 is_dma_stopped = 0;
725 dev_dbg(pcdev->dev, "%s : top queued buffer=%p, dma_stopped=%d\n",
726 __func__, pcdev->active, is_dma_stopped);
727 if (pcdev->active && is_dma_stopped)
728 pxa_camera_start_capture(pcdev);
729 }
730
731 static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
732 enum pxa_camera_active_dma act_dma)
733 {
734 struct pxa_buffer *buf;
735 unsigned long flags;
736 u32 status, camera_status, overrun;
737 struct videobuf_buffer *vb;
738
739 spin_lock_irqsave(&pcdev->lock, flags);
740
741 status = DCSR(channel);
742 DCSR(channel) = status;
743
744 camera_status = __raw_readl(pcdev->base + CISR);
745 overrun = CISR_IFO_0;
746 if (pcdev->channels == 3)
747 overrun |= CISR_IFO_1 | CISR_IFO_2;
748
749 if (status & DCSR_BUSERR) {
750 dev_err(pcdev->dev, "DMA Bus Error IRQ!\n");
751 goto out;
752 }
753
754 if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) {
755 dev_err(pcdev->dev, "Unknown DMA IRQ source, "
756 "status: 0x%08x\n", status);
757 goto out;
758 }
759
760 /*
761 * pcdev->active should not be NULL in DMA irq handler.
762 *
763 * But there is one corner case : if capture was stopped due to an
764 * overrun of channel 1, and at that same channel 2 was completed.
765 *
766 * When handling the overrun in DMA irq for channel 1, we'll stop the
767 * capture and restart it (and thus set pcdev->active to NULL). But the
768 * DMA irq handler will already be pending for channel 2. So on entering
769 * the DMA irq handler for channel 2 there will be no active buffer, yet
770 * that is normal.
771 */
772 if (!pcdev->active)
773 goto out;
774
775 vb = &pcdev->active->vb;
776 buf = container_of(vb, struct pxa_buffer, vb);
777 WARN_ON(buf->inwork || list_empty(&vb->queue));
778
779 dev_dbg(pcdev->dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n",
780 __func__, channel, status & DCSR_STARTINTR ? "SOF " : "",
781 status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel));
782
783 if (status & DCSR_ENDINTR) {
784 /*
785 * It's normal if the last frame creates an overrun, as there
786 * are no more DMA descriptors to fetch from QCI fifos
787 */
788 if (camera_status & overrun &&
789 !list_is_last(pcdev->capture.next, &pcdev->capture)) {
790 dev_dbg(pcdev->dev, "FIFO overrun! CISR: %x\n",
791 camera_status);
792 pxa_camera_stop_capture(pcdev);
793 pxa_camera_start_capture(pcdev);
794 goto out;
795 }
796 buf->active_dma &= ~act_dma;
797 if (!buf->active_dma) {
798 pxa_camera_wakeup(pcdev, vb, buf);
799 pxa_camera_check_link_miss(pcdev);
800 }
801 }
802
803 out:
804 spin_unlock_irqrestore(&pcdev->lock, flags);
805 }
806
807 static void pxa_camera_dma_irq_y(int channel, void *data)
808 {
809 struct pxa_camera_dev *pcdev = data;
810 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
811 }
812
813 static void pxa_camera_dma_irq_u(int channel, void *data)
814 {
815 struct pxa_camera_dev *pcdev = data;
816 pxa_camera_dma_irq(channel, pcdev, DMA_U);
817 }
818
819 static void pxa_camera_dma_irq_v(int channel, void *data)
820 {
821 struct pxa_camera_dev *pcdev = data;
822 pxa_camera_dma_irq(channel, pcdev, DMA_V);
823 }
824
825 static struct videobuf_queue_ops pxa_videobuf_ops = {
826 .buf_setup = pxa_videobuf_setup,
827 .buf_prepare = pxa_videobuf_prepare,
828 .buf_queue = pxa_videobuf_queue,
829 .buf_release = pxa_videobuf_release,
830 };
831
832 static void pxa_camera_init_videobuf(struct videobuf_queue *q,
833 struct soc_camera_device *icd)
834 {
835 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
836 struct pxa_camera_dev *pcdev = ici->priv;
837
838 /* We must pass NULL as dev pointer, then all pci_* dma operations
839 * transform to normal dma_* ones. */
840 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
841 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
842 sizeof(struct pxa_buffer), icd);
843 }
844
845 static u32 mclk_get_divisor(struct pxa_camera_dev *pcdev)
846 {
847 unsigned long mclk = pcdev->mclk;
848 u32 div;
849 unsigned long lcdclk;
850
851 lcdclk = clk_get_rate(pcdev->clk);
852 pcdev->ciclk = lcdclk;
853
854 /* mclk <= ciclk / 4 (27.4.2) */
855 if (mclk > lcdclk / 4) {
856 mclk = lcdclk / 4;
857 dev_warn(pcdev->dev, "Limiting master clock to %lu\n", mclk);
858 }
859
860 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
861 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
862
863 /* If we're not supplying MCLK, leave it at 0 */
864 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
865 pcdev->mclk = lcdclk / (2 * (div + 1));
866
867 dev_dbg(pcdev->dev, "LCD clock %luHz, target freq %luHz, "
868 "divisor %u\n", lcdclk, mclk, div);
869
870 return div;
871 }
872
873 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
874 unsigned long pclk)
875 {
876 /* We want a timeout > 1 pixel time, not ">=" */
877 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
878
879 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
880 }
881
882 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
883 {
884 struct pxacamera_platform_data *pdata = pcdev->pdata;
885 u32 cicr4 = 0;
886
887 dev_dbg(pcdev->dev, "Registered platform device at %p data %p\n",
888 pcdev, pdata);
889
890 if (pdata && pdata->init) {
891 dev_dbg(pcdev->dev, "%s: Init gpios\n", __func__);
892 pdata->init(pcdev->dev);
893 }
894
895 /* disable all interrupts */
896 __raw_writel(0x3ff, pcdev->base + CICR0);
897
898 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
899 cicr4 |= CICR4_PCLK_EN;
900 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
901 cicr4 |= CICR4_MCLK_EN;
902 if (pcdev->platform_flags & PXA_CAMERA_PCP)
903 cicr4 |= CICR4_PCP;
904 if (pcdev->platform_flags & PXA_CAMERA_HSP)
905 cicr4 |= CICR4_HSP;
906 if (pcdev->platform_flags & PXA_CAMERA_VSP)
907 cicr4 |= CICR4_VSP;
908
909 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
910
911 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
912 /* Initialise the timeout under the assumption pclk = mclk */
913 recalculate_fifo_timeout(pcdev, pcdev->mclk);
914 else
915 /* "Safe default" - 13MHz */
916 recalculate_fifo_timeout(pcdev, 13000000);
917
918 clk_enable(pcdev->clk);
919 }
920
921 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
922 {
923 clk_disable(pcdev->clk);
924 }
925
926 static irqreturn_t pxa_camera_irq(int irq, void *data)
927 {
928 struct pxa_camera_dev *pcdev = data;
929 unsigned long status, cicr0;
930 struct pxa_buffer *buf;
931 struct videobuf_buffer *vb;
932
933 status = __raw_readl(pcdev->base + CISR);
934 dev_dbg(pcdev->dev, "Camera interrupt status 0x%lx\n", status);
935
936 if (!status)
937 return IRQ_NONE;
938
939 __raw_writel(status, pcdev->base + CISR);
940
941 if (status & CISR_EOF) {
942 pcdev->active = list_first_entry(&pcdev->capture,
943 struct pxa_buffer, vb.queue);
944 vb = &pcdev->active->vb;
945 buf = container_of(vb, struct pxa_buffer, vb);
946 pxa_videobuf_set_actdma(pcdev, buf);
947
948 pxa_dma_start_channels(pcdev);
949
950 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
951 __raw_writel(cicr0, pcdev->base + CICR0);
952 }
953
954 return IRQ_HANDLED;
955 }
956
957 /*
958 * The following two functions absolutely depend on the fact, that
959 * there can be only one camera on PXA quick capture interface
960 * Called with .video_lock held
961 */
962 static int pxa_camera_add_device(struct soc_camera_device *icd)
963 {
964 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
965 struct pxa_camera_dev *pcdev = ici->priv;
966 int ret;
967
968 if (pcdev->icd) {
969 ret = -EBUSY;
970 goto ebusy;
971 }
972
973 dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n",
974 icd->devnum);
975
976 pxa_camera_activate(pcdev);
977 ret = icd->ops->init(icd);
978
979 if (!ret)
980 pcdev->icd = icd;
981
982 ebusy:
983 return ret;
984 }
985
986 /* Called with .video_lock held */
987 static void pxa_camera_remove_device(struct soc_camera_device *icd)
988 {
989 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
990 struct pxa_camera_dev *pcdev = ici->priv;
991
992 BUG_ON(icd != pcdev->icd);
993
994 dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n",
995 icd->devnum);
996
997 /* disable capture, disable interrupts */
998 __raw_writel(0x3ff, pcdev->base + CICR0);
999
1000 /* Stop DMA engine */
1001 DCSR(pcdev->dma_chans[0]) = 0;
1002 DCSR(pcdev->dma_chans[1]) = 0;
1003 DCSR(pcdev->dma_chans[2]) = 0;
1004
1005 icd->ops->release(icd);
1006
1007 pxa_camera_deactivate(pcdev);
1008
1009 pcdev->icd = NULL;
1010 }
1011
1012 static int test_platform_param(struct pxa_camera_dev *pcdev,
1013 unsigned char buswidth, unsigned long *flags)
1014 {
1015 /*
1016 * Platform specified synchronization and pixel clock polarities are
1017 * only a recommendation and are only used during probing. The PXA270
1018 * quick capture interface supports both.
1019 */
1020 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1021 SOCAM_MASTER : SOCAM_SLAVE) |
1022 SOCAM_HSYNC_ACTIVE_HIGH |
1023 SOCAM_HSYNC_ACTIVE_LOW |
1024 SOCAM_VSYNC_ACTIVE_HIGH |
1025 SOCAM_VSYNC_ACTIVE_LOW |
1026 SOCAM_DATA_ACTIVE_HIGH |
1027 SOCAM_PCLK_SAMPLE_RISING |
1028 SOCAM_PCLK_SAMPLE_FALLING;
1029
1030 /* If requested data width is supported by the platform, use it */
1031 switch (buswidth) {
1032 case 10:
1033 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
1034 return -EINVAL;
1035 *flags |= SOCAM_DATAWIDTH_10;
1036 break;
1037 case 9:
1038 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
1039 return -EINVAL;
1040 *flags |= SOCAM_DATAWIDTH_9;
1041 break;
1042 case 8:
1043 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
1044 return -EINVAL;
1045 *flags |= SOCAM_DATAWIDTH_8;
1046 break;
1047 default:
1048 return -EINVAL;
1049 }
1050
1051 return 0;
1052 }
1053
1054 static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
1055 {
1056 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1057 struct pxa_camera_dev *pcdev = ici->priv;
1058 unsigned long dw, bpp, bus_flags, camera_flags, common_flags;
1059 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0;
1060 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
1061
1062 if (ret < 0)
1063 return ret;
1064
1065 camera_flags = icd->ops->query_bus_param(icd);
1066
1067 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
1068 if (!common_flags)
1069 return -EINVAL;
1070
1071 pcdev->channels = 1;
1072
1073 /* Make choises, based on platform preferences */
1074 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
1075 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
1076 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1077 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
1078 else
1079 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
1080 }
1081
1082 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
1083 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
1084 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1085 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
1086 else
1087 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
1088 }
1089
1090 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
1091 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
1092 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1093 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
1094 else
1095 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
1096 }
1097
1098 ret = icd->ops->set_bus_param(icd, common_flags);
1099 if (ret < 0)
1100 return ret;
1101
1102 /* Datawidth is now guaranteed to be equal to one of the three values.
1103 * We fix bit-per-pixel equal to data-width... */
1104 switch (common_flags & SOCAM_DATAWIDTH_MASK) {
1105 case SOCAM_DATAWIDTH_10:
1106 dw = 4;
1107 bpp = 0x40;
1108 break;
1109 case SOCAM_DATAWIDTH_9:
1110 dw = 3;
1111 bpp = 0x20;
1112 break;
1113 default:
1114 /* Actually it can only be 8 now,
1115 * default is just to silence compiler warnings */
1116 case SOCAM_DATAWIDTH_8:
1117 dw = 2;
1118 bpp = 0;
1119 }
1120
1121 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1122 cicr4 |= CICR4_PCLK_EN;
1123 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1124 cicr4 |= CICR4_MCLK_EN;
1125 if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
1126 cicr4 |= CICR4_PCP;
1127 if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
1128 cicr4 |= CICR4_HSP;
1129 if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
1130 cicr4 |= CICR4_VSP;
1131
1132 cicr0 = __raw_readl(pcdev->base + CICR0);
1133 if (cicr0 & CICR0_ENB)
1134 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1135
1136 cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw;
1137
1138 switch (pixfmt) {
1139 case V4L2_PIX_FMT_YUV422P:
1140 pcdev->channels = 3;
1141 cicr1 |= CICR1_YCBCR_F;
1142 /*
1143 * Normally, pxa bus wants as input UYVY format. We allow all
1144 * reorderings of the YUV422 format, as no processing is done,
1145 * and the YUV stream is just passed through without any
1146 * transformation. Note that UYVY is the only format that
1147 * should be used if pxa framebuffer Overlay2 is used.
1148 */
1149 case V4L2_PIX_FMT_UYVY:
1150 case V4L2_PIX_FMT_VYUY:
1151 case V4L2_PIX_FMT_YUYV:
1152 case V4L2_PIX_FMT_YVYU:
1153 cicr1 |= CICR1_COLOR_SP_VAL(2);
1154 break;
1155 case V4L2_PIX_FMT_RGB555:
1156 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1157 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1158 break;
1159 case V4L2_PIX_FMT_RGB565:
1160 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1161 break;
1162 }
1163
1164 cicr2 = 0;
1165 cicr3 = CICR3_LPF_VAL(icd->height - 1) |
1166 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
1167 cicr4 |= pcdev->mclk_divisor;
1168
1169 __raw_writel(cicr1, pcdev->base + CICR1);
1170 __raw_writel(cicr2, pcdev->base + CICR2);
1171 __raw_writel(cicr3, pcdev->base + CICR3);
1172 __raw_writel(cicr4, pcdev->base + CICR4);
1173
1174 /* CIF interrupts are not used, only DMA */
1175 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1176 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1177 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1178 __raw_writel(cicr0, pcdev->base + CICR0);
1179
1180 return 0;
1181 }
1182
1183 static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1184 unsigned char buswidth)
1185 {
1186 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1187 struct pxa_camera_dev *pcdev = ici->priv;
1188 unsigned long bus_flags, camera_flags;
1189 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1190
1191 if (ret < 0)
1192 return ret;
1193
1194 camera_flags = icd->ops->query_bus_param(icd);
1195
1196 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
1197 }
1198
1199 static const struct soc_camera_data_format pxa_camera_formats[] = {
1200 {
1201 .name = "Planar YUV422 16 bit",
1202 .depth = 16,
1203 .fourcc = V4L2_PIX_FMT_YUV422P,
1204 .colorspace = V4L2_COLORSPACE_JPEG,
1205 },
1206 };
1207
1208 static bool buswidth_supported(struct soc_camera_device *icd, int depth)
1209 {
1210 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1211 struct pxa_camera_dev *pcdev = ici->priv;
1212
1213 switch (depth) {
1214 case 8:
1215 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8);
1216 case 9:
1217 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9);
1218 case 10:
1219 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10);
1220 }
1221 return false;
1222 }
1223
1224 static int required_buswidth(const struct soc_camera_data_format *fmt)
1225 {
1226 switch (fmt->fourcc) {
1227 case V4L2_PIX_FMT_UYVY:
1228 case V4L2_PIX_FMT_VYUY:
1229 case V4L2_PIX_FMT_YUYV:
1230 case V4L2_PIX_FMT_YVYU:
1231 case V4L2_PIX_FMT_RGB565:
1232 case V4L2_PIX_FMT_RGB555:
1233 return 8;
1234 default:
1235 return fmt->depth;
1236 }
1237 }
1238
1239 static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx,
1240 struct soc_camera_format_xlate *xlate)
1241 {
1242 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1243 int formats = 0, buswidth, ret;
1244
1245 buswidth = required_buswidth(icd->formats + idx);
1246
1247 if (!buswidth_supported(icd, buswidth))
1248 return 0;
1249
1250 ret = pxa_camera_try_bus_param(icd, buswidth);
1251 if (ret < 0)
1252 return 0;
1253
1254 switch (icd->formats[idx].fourcc) {
1255 case V4L2_PIX_FMT_UYVY:
1256 formats++;
1257 if (xlate) {
1258 xlate->host_fmt = &pxa_camera_formats[0];
1259 xlate->cam_fmt = icd->formats + idx;
1260 xlate->buswidth = buswidth;
1261 xlate++;
1262 dev_dbg(&ici->dev, "Providing format %s using %s\n",
1263 pxa_camera_formats[0].name,
1264 icd->formats[idx].name);
1265 }
1266 case V4L2_PIX_FMT_VYUY:
1267 case V4L2_PIX_FMT_YUYV:
1268 case V4L2_PIX_FMT_YVYU:
1269 case V4L2_PIX_FMT_RGB565:
1270 case V4L2_PIX_FMT_RGB555:
1271 formats++;
1272 if (xlate) {
1273 xlate->host_fmt = icd->formats + idx;
1274 xlate->cam_fmt = icd->formats + idx;
1275 xlate->buswidth = buswidth;
1276 xlate++;
1277 dev_dbg(&ici->dev, "Providing format %s packed\n",
1278 icd->formats[idx].name);
1279 }
1280 break;
1281 default:
1282 /* Generic pass-through */
1283 formats++;
1284 if (xlate) {
1285 xlate->host_fmt = icd->formats + idx;
1286 xlate->cam_fmt = icd->formats + idx;
1287 xlate->buswidth = icd->formats[idx].depth;
1288 xlate++;
1289 dev_dbg(&ici->dev,
1290 "Providing format %s in pass-through mode\n",
1291 icd->formats[idx].name);
1292 }
1293 }
1294
1295 return formats;
1296 }
1297
1298 static int pxa_camera_set_crop(struct soc_camera_device *icd,
1299 struct v4l2_rect *rect)
1300 {
1301 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1302 struct pxa_camera_dev *pcdev = ici->priv;
1303 struct soc_camera_sense sense = {
1304 .master_clock = pcdev->mclk,
1305 .pixel_clock_max = pcdev->ciclk / 4,
1306 };
1307 int ret;
1308
1309 /* If PCLK is used to latch data from the sensor, check sense */
1310 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1311 icd->sense = &sense;
1312
1313 ret = icd->ops->set_crop(icd, rect);
1314
1315 icd->sense = NULL;
1316
1317 if (ret < 0) {
1318 dev_warn(&ici->dev, "Failed to crop to %ux%u@%u:%u\n",
1319 rect->width, rect->height, rect->left, rect->top);
1320 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1321 if (sense.pixel_clock > sense.pixel_clock_max) {
1322 dev_err(&ici->dev,
1323 "pixel clock %lu set by the camera too high!",
1324 sense.pixel_clock);
1325 return -EIO;
1326 }
1327 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1328 }
1329
1330 return ret;
1331 }
1332
1333 static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1334 struct v4l2_format *f)
1335 {
1336 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1337 struct pxa_camera_dev *pcdev = ici->priv;
1338 const struct soc_camera_data_format *cam_fmt = NULL;
1339 const struct soc_camera_format_xlate *xlate = NULL;
1340 struct soc_camera_sense sense = {
1341 .master_clock = pcdev->mclk,
1342 .pixel_clock_max = pcdev->ciclk / 4,
1343 };
1344 struct v4l2_pix_format *pix = &f->fmt.pix;
1345 struct v4l2_format cam_f = *f;
1346 int ret;
1347
1348 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1349 if (!xlate) {
1350 dev_warn(&ici->dev, "Format %x not found\n", pix->pixelformat);
1351 return -EINVAL;
1352 }
1353
1354 cam_fmt = xlate->cam_fmt;
1355
1356 /* If PCLK is used to latch data from the sensor, check sense */
1357 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1358 icd->sense = &sense;
1359
1360 cam_f.fmt.pix.pixelformat = cam_fmt->fourcc;
1361 ret = icd->ops->set_fmt(icd, &cam_f);
1362
1363 icd->sense = NULL;
1364
1365 if (ret < 0) {
1366 dev_warn(&ici->dev, "Failed to configure for format %x\n",
1367 pix->pixelformat);
1368 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1369 if (sense.pixel_clock > sense.pixel_clock_max) {
1370 dev_err(&ici->dev,
1371 "pixel clock %lu set by the camera too high!",
1372 sense.pixel_clock);
1373 return -EIO;
1374 }
1375 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1376 }
1377
1378 if (!ret) {
1379 icd->buswidth = xlate->buswidth;
1380 icd->current_fmt = xlate->host_fmt;
1381 }
1382
1383 return ret;
1384 }
1385
1386 static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1387 struct v4l2_format *f)
1388 {
1389 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1390 const struct soc_camera_format_xlate *xlate;
1391 struct v4l2_pix_format *pix = &f->fmt.pix;
1392 __u32 pixfmt = pix->pixelformat;
1393 enum v4l2_field field;
1394 int ret;
1395
1396 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1397 if (!xlate) {
1398 dev_warn(&ici->dev, "Format %x not found\n", pixfmt);
1399 return -EINVAL;
1400 }
1401
1402 /* limit to pxa hardware capabilities */
1403 if (pix->height < 32)
1404 pix->height = 32;
1405 if (pix->height > 2048)
1406 pix->height = 2048;
1407 if (pix->width < 48)
1408 pix->width = 48;
1409 if (pix->width > 2048)
1410 pix->width = 2048;
1411 pix->width &= ~0x01;
1412
1413 /*
1414 * YUV422P planar format requires images size to be a 16 bytes
1415 * multiple. If not, zeros will be inserted between Y and U planes, and
1416 * U and V planes, and YUV422P standard would be violated.
1417 */
1418 if (xlate->host_fmt->fourcc == V4L2_PIX_FMT_YUV422P) {
1419 if (!IS_ALIGNED(pix->width * pix->height, YUV422P_SIZE_ALIGN))
1420 pix->height = ALIGN(pix->height, YUV422P_X_Y_ALIGN);
1421 if (!IS_ALIGNED(pix->width * pix->height, YUV422P_SIZE_ALIGN))
1422 pix->width = ALIGN(pix->width, YUV422P_X_Y_ALIGN);
1423 }
1424
1425 pix->bytesperline = pix->width *
1426 DIV_ROUND_UP(xlate->host_fmt->depth, 8);
1427 pix->sizeimage = pix->height * pix->bytesperline;
1428
1429 /* camera has to see its format, but the user the original one */
1430 pix->pixelformat = xlate->cam_fmt->fourcc;
1431 /* limit to sensor capabilities */
1432 ret = icd->ops->try_fmt(icd, f);
1433 pix->pixelformat = xlate->host_fmt->fourcc;
1434
1435 field = pix->field;
1436
1437 if (field == V4L2_FIELD_ANY) {
1438 pix->field = V4L2_FIELD_NONE;
1439 } else if (field != V4L2_FIELD_NONE) {
1440 dev_err(&icd->dev, "Field type %d unsupported.\n", field);
1441 return -EINVAL;
1442 }
1443
1444 return ret;
1445 }
1446
1447 static int pxa_camera_reqbufs(struct soc_camera_file *icf,
1448 struct v4l2_requestbuffers *p)
1449 {
1450 int i;
1451
1452 /* This is for locking debugging only. I removed spinlocks and now I
1453 * check whether .prepare is ever called on a linked buffer, or whether
1454 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1455 * it hadn't triggered */
1456 for (i = 0; i < p->count; i++) {
1457 struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
1458 struct pxa_buffer, vb);
1459 buf->inwork = 0;
1460 INIT_LIST_HEAD(&buf->vb.queue);
1461 }
1462
1463 return 0;
1464 }
1465
1466 static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
1467 {
1468 struct soc_camera_file *icf = file->private_data;
1469 struct pxa_buffer *buf;
1470
1471 buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
1472 vb.stream);
1473
1474 poll_wait(file, &buf->vb.done, pt);
1475
1476 if (buf->vb.state == VIDEOBUF_DONE ||
1477 buf->vb.state == VIDEOBUF_ERROR)
1478 return POLLIN|POLLRDNORM;
1479
1480 return 0;
1481 }
1482
1483 static int pxa_camera_querycap(struct soc_camera_host *ici,
1484 struct v4l2_capability *cap)
1485 {
1486 /* cap->name is set by the firendly caller:-> */
1487 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1488 cap->version = PXA_CAM_VERSION_CODE;
1489 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1490
1491 return 0;
1492 }
1493
1494 static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state)
1495 {
1496 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1497 struct pxa_camera_dev *pcdev = ici->priv;
1498 int i = 0, ret = 0;
1499
1500 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1501 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1502 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1503 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1504 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
1505
1506 if ((pcdev->icd) && (pcdev->icd->ops->suspend))
1507 ret = pcdev->icd->ops->suspend(pcdev->icd, state);
1508
1509 return ret;
1510 }
1511
1512 static int pxa_camera_resume(struct soc_camera_device *icd)
1513 {
1514 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1515 struct pxa_camera_dev *pcdev = ici->priv;
1516 int i = 0, ret = 0;
1517
1518 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1519 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1520 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1521
1522 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1523 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1524 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1525 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1526 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1527
1528 if ((pcdev->icd) && (pcdev->icd->ops->resume))
1529 ret = pcdev->icd->ops->resume(pcdev->icd);
1530
1531 /* Restart frame capture if active buffer exists */
1532 if (!ret && pcdev->active)
1533 pxa_camera_start_capture(pcdev);
1534
1535 return ret;
1536 }
1537
1538 static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1539 .owner = THIS_MODULE,
1540 .add = pxa_camera_add_device,
1541 .remove = pxa_camera_remove_device,
1542 .suspend = pxa_camera_suspend,
1543 .resume = pxa_camera_resume,
1544 .set_crop = pxa_camera_set_crop,
1545 .get_formats = pxa_camera_get_formats,
1546 .set_fmt = pxa_camera_set_fmt,
1547 .try_fmt = pxa_camera_try_fmt,
1548 .init_videobuf = pxa_camera_init_videobuf,
1549 .reqbufs = pxa_camera_reqbufs,
1550 .poll = pxa_camera_poll,
1551 .querycap = pxa_camera_querycap,
1552 .set_bus_param = pxa_camera_set_bus_param,
1553 };
1554
1555 /* Should be allocated dynamically too, but we have only one. */
1556 static struct soc_camera_host pxa_soc_camera_host = {
1557 .drv_name = PXA_CAM_DRV_NAME,
1558 .ops = &pxa_soc_camera_host_ops,
1559 };
1560
1561 static int pxa_camera_probe(struct platform_device *pdev)
1562 {
1563 struct pxa_camera_dev *pcdev;
1564 struct resource *res;
1565 void __iomem *base;
1566 int irq;
1567 int err = 0;
1568
1569 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1570 irq = platform_get_irq(pdev, 0);
1571 if (!res || irq < 0) {
1572 err = -ENODEV;
1573 goto exit;
1574 }
1575
1576 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1577 if (!pcdev) {
1578 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1579 err = -ENOMEM;
1580 goto exit;
1581 }
1582
1583 pcdev->clk = clk_get(&pdev->dev, NULL);
1584 if (IS_ERR(pcdev->clk)) {
1585 err = PTR_ERR(pcdev->clk);
1586 goto exit_kfree;
1587 }
1588
1589 dev_set_drvdata(&pdev->dev, pcdev);
1590 pcdev->res = res;
1591
1592 pcdev->pdata = pdev->dev.platform_data;
1593 pcdev->platform_flags = pcdev->pdata->flags;
1594 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1595 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1596 /* Platform hasn't set available data widths. This is bad.
1597 * Warn and use a default. */
1598 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1599 "data widths, using default 10 bit\n");
1600 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1601 }
1602 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1603 if (!pcdev->mclk) {
1604 dev_warn(&pdev->dev,
1605 "mclk == 0! Please, fix your platform data. "
1606 "Using default 20MHz\n");
1607 pcdev->mclk = 20000000;
1608 }
1609
1610 pcdev->dev = &pdev->dev;
1611 pcdev->mclk_divisor = mclk_get_divisor(pcdev);
1612
1613 INIT_LIST_HEAD(&pcdev->capture);
1614 spin_lock_init(&pcdev->lock);
1615
1616 /*
1617 * Request the regions.
1618 */
1619 if (!request_mem_region(res->start, res->end - res->start + 1,
1620 PXA_CAM_DRV_NAME)) {
1621 err = -EBUSY;
1622 goto exit_clk;
1623 }
1624
1625 base = ioremap(res->start, res->end - res->start + 1);
1626 if (!base) {
1627 err = -ENOMEM;
1628 goto exit_release;
1629 }
1630 pcdev->irq = irq;
1631 pcdev->base = base;
1632
1633 /* request dma */
1634 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1635 pxa_camera_dma_irq_y, pcdev);
1636 if (err < 0) {
1637 dev_err(pcdev->dev, "Can't request DMA for Y\n");
1638 goto exit_iounmap;
1639 }
1640 pcdev->dma_chans[0] = err;
1641 dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1642
1643 err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1644 pxa_camera_dma_irq_u, pcdev);
1645 if (err < 0) {
1646 dev_err(pcdev->dev, "Can't request DMA for U\n");
1647 goto exit_free_dma_y;
1648 }
1649 pcdev->dma_chans[1] = err;
1650 dev_dbg(pcdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1651
1652 err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1653 pxa_camera_dma_irq_v, pcdev);
1654 if (err < 0) {
1655 dev_err(pcdev->dev, "Can't request DMA for V\n");
1656 goto exit_free_dma_u;
1657 }
1658 pcdev->dma_chans[2] = err;
1659 dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1660
1661 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1662 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1663 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1664
1665 /* request irq */
1666 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1667 pcdev);
1668 if (err) {
1669 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1670 goto exit_free_dma;
1671 }
1672
1673 pxa_soc_camera_host.priv = pcdev;
1674 pxa_soc_camera_host.dev.parent = &pdev->dev;
1675 pxa_soc_camera_host.nr = pdev->id;
1676 err = soc_camera_host_register(&pxa_soc_camera_host);
1677 if (err)
1678 goto exit_free_irq;
1679
1680 return 0;
1681
1682 exit_free_irq:
1683 free_irq(pcdev->irq, pcdev);
1684 exit_free_dma:
1685 pxa_free_dma(pcdev->dma_chans[2]);
1686 exit_free_dma_u:
1687 pxa_free_dma(pcdev->dma_chans[1]);
1688 exit_free_dma_y:
1689 pxa_free_dma(pcdev->dma_chans[0]);
1690 exit_iounmap:
1691 iounmap(base);
1692 exit_release:
1693 release_mem_region(res->start, res->end - res->start + 1);
1694 exit_clk:
1695 clk_put(pcdev->clk);
1696 exit_kfree:
1697 kfree(pcdev);
1698 exit:
1699 return err;
1700 }
1701
1702 static int __devexit pxa_camera_remove(struct platform_device *pdev)
1703 {
1704 struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev);
1705 struct resource *res;
1706
1707 clk_put(pcdev->clk);
1708
1709 pxa_free_dma(pcdev->dma_chans[0]);
1710 pxa_free_dma(pcdev->dma_chans[1]);
1711 pxa_free_dma(pcdev->dma_chans[2]);
1712 free_irq(pcdev->irq, pcdev);
1713
1714 soc_camera_host_unregister(&pxa_soc_camera_host);
1715
1716 iounmap(pcdev->base);
1717
1718 res = pcdev->res;
1719 release_mem_region(res->start, res->end - res->start + 1);
1720
1721 kfree(pcdev);
1722
1723 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1724
1725 return 0;
1726 }
1727
1728 static struct platform_driver pxa_camera_driver = {
1729 .driver = {
1730 .name = PXA_CAM_DRV_NAME,
1731 },
1732 .probe = pxa_camera_probe,
1733 .remove = __exit_p(pxa_camera_remove),
1734 };
1735
1736
1737 static int __devinit pxa_camera_init(void)
1738 {
1739 return platform_driver_register(&pxa_camera_driver);
1740 }
1741
1742 static void __exit pxa_camera_exit(void)
1743 {
1744 platform_driver_unregister(&pxa_camera_driver);
1745 }
1746
1747 module_init(pxa_camera_init);
1748 module_exit(pxa_camera_exit);
1749
1750 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1751 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1752 MODULE_LICENSE("GPL");
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