arch/arm/boot/dts/sun7i-a20.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&gic>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 cpu@0 {
  24                         compatible = "arm,cortex-a7";
  25                         device_type = "cpu";
  26                         reg = <0>;
  27                 };
  28
  29                 cpu@1 {
  30                         compatible = "arm,cortex-a7";
  31                         device_type = "cpu";
  32                         reg = <1>;
  33                 };
  34         };
  35
  36         memory {
  37                 reg = <0x40000000 0x80000000>;
  38         };
  39
  40         clocks {
  41                 #address-cells = <1>;
  42                 #size-cells = <1>;
  43                 ranges;
  44
  45                 osc24M: osc24M@01c20050 {
  46                         #clock-cells = <0>;
  47                         compatible = "fixed-clock";
  48                         clock-frequency = <24000000>;
  49                 };
  50
  51                 osc32k: osc32k {
  52                         #clock-cells = <0>;
  53                         compatible = "fixed-clock";
  54                         clock-frequency = <32768>;
  55                 };
  56         };
  57
  58         soc@01c00000 {
  59                 compatible = "simple-bus";
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 ranges;
  63
  64                 pio: pinctrl@01c20800 {
  65                         compatible = "allwinner,sun7i-a20-pinctrl";
  66                         reg = <0x01c20800 0x400>;
  67                         interrupts = <0 28 1>;
  68                         clocks = <&osc24M>;
  69                         gpio-controller;
  70                         interrupt-controller;
  71                         #address-cells = <1>;
  72                         #size-cells = <0>;
  73                         #gpio-cells = <3>;
  74
  75                         uart0_pins_a: uart0@0 {
  76                                 allwinner,pins = "PB22", "PB23";
  77                                 allwinner,function = "uart0";
  78                                 allwinner,drive = <0>;
  79                                 allwinner,pull = <0>;
  80                         };
  81
  82                         uart6_pins_a: uart6@0 {
  83                                 allwinner,pins = "PI12", "PI13";
  84                                 allwinner,function = "uart6";
  85                                 allwinner,drive = <0>;
  86                                 allwinner,pull = <0>;
  87                         };
  88
  89                         uart7_pins_a: uart7@0 {
  90                                 allwinner,pins = "PI20", "PI21";
  91                                 allwinner,function = "uart7";
  92                                 allwinner,drive = <0>;
  93                                 allwinner,pull = <0>;
  94                         };
  95                 };
  96
  97                 timer@01c20c00 {
  98                         compatible = "allwinner,sun4i-timer";
  99                         reg = <0x01c20c00 0x90>;
 100                         interrupts = <0 22 1>,
 101                                      <0 23 1>,
 102                                      <0 24 1>,
 103                                      <0 25 1>,
 104                                      <0 67 1>,
 105                                      <0 68 1>;
 106                         clocks = <&osc24M>;
 107                 };
 108
 109                 wdt: watchdog@01c20c90 {
 110                         compatible = "allwinner,sun4i-wdt";
 111                         reg = <0x01c20c90 0x10>;
 112                 };
 113
 114                 uart0: serial@01c28000 {
 115                         compatible = "snps,dw-apb-uart";
 116                         reg = <0x01c28000 0x400>;
 117                         interrupts = <0 1 1>;
 118                         reg-shift = <2>;
 119                         reg-io-width = <4>;
 120                         clocks = <&osc24M>;
 121                         status = "disabled";
 122                 };
 123
 124                 uart1: serial@01c28400 {
 125                         compatible = "snps,dw-apb-uart";
 126                         reg = <0x01c28400 0x400>;
 127                         interrupts = <0 2 1>;
 128                         reg-shift = <2>;
 129                         reg-io-width = <4>;
 130                         clocks = <&osc24M>;
 131                         status = "disabled";
 132                 };
 133
 134                 uart2: serial@01c28800 {
 135                         compatible = "snps,dw-apb-uart";
 136                         reg = <0x01c28800 0x400>;
 137                         interrupts = <0 3 1>;
 138                         reg-shift = <2>;
 139                         reg-io-width = <4>;
 140                         clocks = <&osc24M>;
 141                         status = "disabled";
 142                 };
 143
 144                 uart3: serial@01c28c00 {
 145                         compatible = "snps,dw-apb-uart";
 146                         reg = <0x01c28c00 0x400>;
 147                         interrupts = <0 4 1>;
 148                         reg-shift = <2>;
 149                         reg-io-width = <4>;
 150                         clocks = <&osc24M>;
 151                         status = "disabled";
 152                 };
 153
 154                 uart4: serial@01c29000 {
 155                         compatible = "snps,dw-apb-uart";
 156                         reg = <0x01c29000 0x400>;
 157                         interrupts = <0 17 1>;
 158                         reg-shift = <2>;
 159                         reg-io-width = <4>;
 160                         clocks = <&osc24M>;
 161                         status = "disabled";
 162                 };
 163
 164                 uart5: serial@01c29400 {
 165                         compatible = "snps,dw-apb-uart";
 166                         reg = <0x01c29400 0x400>;
 167                         interrupts = <0 18 1>;
 168                         reg-shift = <2>;
 169                         reg-io-width = <4>;
 170                         clocks = <&osc24M>;
 171                         status = "disabled";
 172                 };
 173
 174                 uart6: serial@01c29800 {
 175                         compatible = "snps,dw-apb-uart";
 176                         reg = <0x01c29800 0x400>;
 177                         interrupts = <0 19 1>;
 178                         reg-shift = <2>;
 179                         reg-io-width = <4>;
 180                         clocks = <&osc24M>;
 181                         status = "disabled";
 182                 };
 183
 184                 uart7: serial@01c29c00 {
 185                         compatible = "snps,dw-apb-uart";
 186                         reg = <0x01c29c00 0x400>;
 187                         interrupts = <0 20 1>;
 188                         reg-shift = <2>;
 189                         reg-io-width = <4>;
 190                         clocks = <&osc24M>;
 191                         status = "disabled";
 192                 };
 193
 194                 gic: interrupt-controller@01c81000 {
 195                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 196                         reg = <0x01c81000 0x1000>,
 197                               <0x01c82000 0x1000>,
 198                               <0x01c84000 0x2000>,
 199                               <0x01c86000 0x2000>;
 200                         interrupt-controller;
 201                         #interrupt-cells = <3>;
 202                         interrupts = <1 9 0xf04>;
 203                 };
 204         };
 205 };