2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
40 #include <asm/atomic.h>
43 MLX4_FLAG_MSI_X
= 1 << 0,
44 MLX4_FLAG_OLD_PORT_CMDS
= 1 << 1,
52 MLX4_BOARD_ID_LEN
= 64
56 MLX4_DEV_CAP_FLAG_RC
= 1 << 0,
57 MLX4_DEV_CAP_FLAG_UC
= 1 << 1,
58 MLX4_DEV_CAP_FLAG_UD
= 1 << 2,
59 MLX4_DEV_CAP_FLAG_SRQ
= 1 << 6,
60 MLX4_DEV_CAP_FLAG_IPOIB_CSUM
= 1 << 7,
61 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR
= 1 << 8,
62 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR
= 1 << 9,
63 MLX4_DEV_CAP_FLAG_DPDP
= 1 << 12,
64 MLX4_DEV_CAP_FLAG_BLH
= 1 << 15,
65 MLX4_DEV_CAP_FLAG_MEM_WINDOW
= 1 << 16,
66 MLX4_DEV_CAP_FLAG_APM
= 1 << 17,
67 MLX4_DEV_CAP_FLAG_ATOMIC
= 1 << 18,
68 MLX4_DEV_CAP_FLAG_RAW_MCAST
= 1 << 19,
69 MLX4_DEV_CAP_FLAG_UD_AV_PORT
= 1 << 20,
70 MLX4_DEV_CAP_FLAG_UD_MCAST
= 1 << 21,
71 MLX4_DEV_CAP_FLAG_IBOE
= 1 << 30
75 MLX4_BMME_FLAG_LOCAL_INV
= 1 << 6,
76 MLX4_BMME_FLAG_REMOTE_INV
= 1 << 7,
77 MLX4_BMME_FLAG_TYPE_2_WIN
= 1 << 9,
78 MLX4_BMME_FLAG_RESERVED_LKEY
= 1 << 10,
79 MLX4_BMME_FLAG_FAST_REG_WR
= 1 << 11,
83 MLX4_EVENT_TYPE_COMP
= 0x00,
84 MLX4_EVENT_TYPE_PATH_MIG
= 0x01,
85 MLX4_EVENT_TYPE_COMM_EST
= 0x02,
86 MLX4_EVENT_TYPE_SQ_DRAINED
= 0x03,
87 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE
= 0x13,
88 MLX4_EVENT_TYPE_SRQ_LIMIT
= 0x14,
89 MLX4_EVENT_TYPE_CQ_ERROR
= 0x04,
90 MLX4_EVENT_TYPE_WQ_CATAS_ERROR
= 0x05,
91 MLX4_EVENT_TYPE_EEC_CATAS_ERROR
= 0x06,
92 MLX4_EVENT_TYPE_PATH_MIG_FAILED
= 0x07,
93 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR
= 0x10,
94 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR
= 0x11,
95 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR
= 0x12,
96 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR
= 0x08,
97 MLX4_EVENT_TYPE_PORT_CHANGE
= 0x09,
98 MLX4_EVENT_TYPE_EQ_OVERFLOW
= 0x0f,
99 MLX4_EVENT_TYPE_ECC_DETECT
= 0x0e,
100 MLX4_EVENT_TYPE_CMD
= 0x0a
104 MLX4_PORT_CHANGE_SUBTYPE_DOWN
= 1,
105 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE
= 4
109 MLX4_PERM_LOCAL_READ
= 1 << 10,
110 MLX4_PERM_LOCAL_WRITE
= 1 << 11,
111 MLX4_PERM_REMOTE_READ
= 1 << 12,
112 MLX4_PERM_REMOTE_WRITE
= 1 << 13,
113 MLX4_PERM_ATOMIC
= 1 << 14
117 MLX4_OPCODE_NOP
= 0x00,
118 MLX4_OPCODE_SEND_INVAL
= 0x01,
119 MLX4_OPCODE_RDMA_WRITE
= 0x08,
120 MLX4_OPCODE_RDMA_WRITE_IMM
= 0x09,
121 MLX4_OPCODE_SEND
= 0x0a,
122 MLX4_OPCODE_SEND_IMM
= 0x0b,
123 MLX4_OPCODE_LSO
= 0x0e,
124 MLX4_OPCODE_RDMA_READ
= 0x10,
125 MLX4_OPCODE_ATOMIC_CS
= 0x11,
126 MLX4_OPCODE_ATOMIC_FA
= 0x12,
127 MLX4_OPCODE_MASKED_ATOMIC_CS
= 0x14,
128 MLX4_OPCODE_MASKED_ATOMIC_FA
= 0x15,
129 MLX4_OPCODE_BIND_MW
= 0x18,
130 MLX4_OPCODE_FMR
= 0x19,
131 MLX4_OPCODE_LOCAL_INVAL
= 0x1b,
132 MLX4_OPCODE_CONFIG_CMD
= 0x1f,
134 MLX4_RECV_OPCODE_RDMA_WRITE_IMM
= 0x00,
135 MLX4_RECV_OPCODE_SEND
= 0x01,
136 MLX4_RECV_OPCODE_SEND_IMM
= 0x02,
137 MLX4_RECV_OPCODE_SEND_INVAL
= 0x03,
139 MLX4_CQE_OPCODE_ERROR
= 0x1e,
140 MLX4_CQE_OPCODE_RESIZE
= 0x16,
144 MLX4_STAT_RATE_OFFSET
= 5
148 MLX4_MTT_FLAG_PRESENT
= 1
151 enum mlx4_qp_region
{
152 MLX4_QP_REGION_FW
= 0,
153 MLX4_QP_REGION_ETH_ADDR
,
154 MLX4_QP_REGION_FC_ADDR
,
155 MLX4_QP_REGION_FC_EXCH
,
159 enum mlx4_port_type
{
160 MLX4_PORT_TYPE_IB
= 1,
161 MLX4_PORT_TYPE_ETH
= 2,
162 MLX4_PORT_TYPE_AUTO
= 3
165 enum mlx4_special_vlan_idx
{
166 MLX4_NO_VLAN_IDX
= 0,
172 MLX4_NUM_FEXCH
= 64 * 1024,
176 MLX4_MAX_FAST_REG_PAGES
= 511,
179 static inline u64
mlx4_fw_ver(u64 major
, u64 minor
, u64 subminor
)
181 return (major
<< 32) | (minor
<< 16) | subminor
;
187 int vl_cap
[MLX4_MAX_PORTS
+ 1];
188 int ib_mtu_cap
[MLX4_MAX_PORTS
+ 1];
189 __be32 ib_port_def_cap
[MLX4_MAX_PORTS
+ 1];
190 u64 def_mac
[MLX4_MAX_PORTS
+ 1];
191 int eth_mtu_cap
[MLX4_MAX_PORTS
+ 1];
192 int gid_table_len
[MLX4_MAX_PORTS
+ 1];
193 int pkey_table_len
[MLX4_MAX_PORTS
+ 1];
194 int trans_type
[MLX4_MAX_PORTS
+ 1];
195 int vendor_oui
[MLX4_MAX_PORTS
+ 1];
196 int wavelength
[MLX4_MAX_PORTS
+ 1];
197 u64 trans_code
[MLX4_MAX_PORTS
+ 1];
198 int local_ca_ack_delay
;
201 int bf_regs_per_page
;
208 int max_qp_init_rdma
;
209 int max_qp_dest_rdma
;
220 int num_comp_vectors
;
224 int fmr_reserved_mtts
;
240 u16 stat_rate_support
;
242 int loopback_support
;
243 u8 port_width_cap
[MLX4_MAX_PORTS
+ 1];
245 int reserved_qps_cnt
[MLX4_NUM_QP_REGION
];
247 int reserved_qps_base
[MLX4_NUM_QP_REGION
];
251 enum mlx4_port_type port_type
[MLX4_MAX_PORTS
+ 1];
252 u8 supported_type
[MLX4_MAX_PORTS
+ 1];
254 enum mlx4_port_type possible_type
[MLX4_MAX_PORTS
+ 1];
257 struct mlx4_buf_list
{
263 struct mlx4_buf_list direct
;
264 struct mlx4_buf_list
*page_list
;
277 MLX4_DB_PER_PAGE
= PAGE_SIZE
/ 4
280 struct mlx4_db_pgdir
{
281 struct list_head list
;
282 DECLARE_BITMAP(order0
, MLX4_DB_PER_PAGE
);
283 DECLARE_BITMAP(order1
, MLX4_DB_PER_PAGE
/ 2);
284 unsigned long *bits
[2];
289 struct mlx4_ib_user_db_page
;
294 struct mlx4_db_pgdir
*pgdir
;
295 struct mlx4_ib_user_db_page
*user_page
;
302 struct mlx4_hwq_resources
{
320 struct mlx4_mpt_entry
*mpt
;
322 dma_addr_t dma_handle
;
335 void (*comp
) (struct mlx4_cq
*);
336 void (*event
) (struct mlx4_cq
*, enum mlx4_event
);
338 struct mlx4_uar
*uar
;
350 struct completion free
;
354 void (*event
) (struct mlx4_qp
*, enum mlx4_event
);
359 struct completion free
;
363 void (*event
) (struct mlx4_srq
*, enum mlx4_event
);
371 struct completion free
;
383 __be32 sl_tclass_flowlabel
;
396 __be32 sl_tclass_flowlabel
;
405 struct mlx4_eth_av eth
;
409 struct pci_dev
*pdev
;
411 struct mlx4_caps caps
;
412 struct radix_tree_root qp_table_tree
;
414 char board_id
[MLX4_BOARD_ID_LEN
];
417 struct mlx4_init_port_param
{
431 #define mlx4_foreach_port(port, dev, type) \
432 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
433 if (((type) == MLX4_PORT_TYPE_IB ? (dev)->caps.port_mask : \
434 ~(dev)->caps.port_mask) & 1 << ((port) - 1))
436 #define mlx4_foreach_ib_transport_port(port, dev) \
437 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
438 if (((dev)->caps.port_mask & 1 << ((port) - 1)) || \
439 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
442 int mlx4_buf_alloc(struct mlx4_dev
*dev
, int size
, int max_direct
,
443 struct mlx4_buf
*buf
);
444 void mlx4_buf_free(struct mlx4_dev
*dev
, int size
, struct mlx4_buf
*buf
);
445 static inline void *mlx4_buf_offset(struct mlx4_buf
*buf
, int offset
)
447 if (BITS_PER_LONG
== 64 || buf
->nbufs
== 1)
448 return buf
->direct
.buf
+ offset
;
450 return buf
->page_list
[offset
>> PAGE_SHIFT
].buf
+
451 (offset
& (PAGE_SIZE
- 1));
454 int mlx4_pd_alloc(struct mlx4_dev
*dev
, u32
*pdn
);
455 void mlx4_pd_free(struct mlx4_dev
*dev
, u32 pdn
);
457 int mlx4_uar_alloc(struct mlx4_dev
*dev
, struct mlx4_uar
*uar
);
458 void mlx4_uar_free(struct mlx4_dev
*dev
, struct mlx4_uar
*uar
);
460 int mlx4_mtt_init(struct mlx4_dev
*dev
, int npages
, int page_shift
,
461 struct mlx4_mtt
*mtt
);
462 void mlx4_mtt_cleanup(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
);
463 u64
mlx4_mtt_addr(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
);
465 int mlx4_mr_alloc(struct mlx4_dev
*dev
, u32 pd
, u64 iova
, u64 size
, u32 access
,
466 int npages
, int page_shift
, struct mlx4_mr
*mr
);
467 void mlx4_mr_free(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
468 int mlx4_mr_enable(struct mlx4_dev
*dev
, struct mlx4_mr
*mr
);
469 int mlx4_write_mtt(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
470 int start_index
, int npages
, u64
*page_list
);
471 int mlx4_buf_write_mtt(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
472 struct mlx4_buf
*buf
);
474 int mlx4_db_alloc(struct mlx4_dev
*dev
, struct mlx4_db
*db
, int order
);
475 void mlx4_db_free(struct mlx4_dev
*dev
, struct mlx4_db
*db
);
477 int mlx4_alloc_hwq_res(struct mlx4_dev
*dev
, struct mlx4_hwq_resources
*wqres
,
478 int size
, int max_direct
);
479 void mlx4_free_hwq_res(struct mlx4_dev
*mdev
, struct mlx4_hwq_resources
*wqres
,
482 int mlx4_cq_alloc(struct mlx4_dev
*dev
, int nent
, struct mlx4_mtt
*mtt
,
483 struct mlx4_uar
*uar
, u64 db_rec
, struct mlx4_cq
*cq
,
484 unsigned vector
, int collapsed
);
485 void mlx4_cq_free(struct mlx4_dev
*dev
, struct mlx4_cq
*cq
);
487 int mlx4_qp_reserve_range(struct mlx4_dev
*dev
, int cnt
, int align
, int *base
);
488 void mlx4_qp_release_range(struct mlx4_dev
*dev
, int base_qpn
, int cnt
);
490 int mlx4_qp_alloc(struct mlx4_dev
*dev
, int qpn
, struct mlx4_qp
*qp
);
491 void mlx4_qp_free(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
);
493 int mlx4_srq_alloc(struct mlx4_dev
*dev
, u32 pdn
, struct mlx4_mtt
*mtt
,
494 u64 db_rec
, struct mlx4_srq
*srq
);
495 void mlx4_srq_free(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
);
496 int mlx4_srq_arm(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
, int limit_watermark
);
497 int mlx4_srq_query(struct mlx4_dev
*dev
, struct mlx4_srq
*srq
, int *limit_watermark
);
499 int mlx4_INIT_PORT(struct mlx4_dev
*dev
, int port
);
500 int mlx4_CLOSE_PORT(struct mlx4_dev
*dev
, int port
);
502 int mlx4_multicast_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
503 int block_mcast_loopback
);
504 int mlx4_multicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16]);
506 int mlx4_register_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
, int *index
);
507 void mlx4_unregister_mac(struct mlx4_dev
*dev
, u8 port
, int index
);
509 int mlx4_find_cached_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vid
, int *idx
);
510 int mlx4_register_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vlan
, int *index
);
511 void mlx4_unregister_vlan(struct mlx4_dev
*dev
, u8 port
, int index
);
513 int mlx4_map_phys_fmr(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
, u64
*page_list
,
514 int npages
, u64 iova
, u32
*lkey
, u32
*rkey
);
515 int mlx4_fmr_alloc(struct mlx4_dev
*dev
, u32 pd
, u32 access
, int max_pages
,
516 int max_maps
, u8 page_shift
, struct mlx4_fmr
*fmr
);
517 int mlx4_fmr_enable(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
);
518 void mlx4_fmr_unmap(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
,
519 u32
*lkey
, u32
*rkey
);
520 int mlx4_fmr_free(struct mlx4_dev
*dev
, struct mlx4_fmr
*fmr
);
521 int mlx4_SYNC_TPT(struct mlx4_dev
*dev
);
522 int mlx4_test_interrupts(struct mlx4_dev
*dev
);
524 #endif /* MLX4_DEVICE_H */