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ath9k: get EEPROM contents from platform data on AHB bus
[linux-2.6.git] / drivers / net / wireless / ath9k / eeprom.c
blob50cb3883416aafeeb6078ce083659fec9c088181
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "core.h"
18 #include "hw.h"
19 #include "reg.h"
20 #include "phy.h"
21
22 static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah,
23 u32 reg, u32 mask,
24 u32 shift, u32 val)
25 {
26 u32 regVal;
27
28 regVal = REG_READ(ah, reg) & ~mask;
29 regVal |= (val << shift) & mask;
30
31 REG_WRITE(ah, reg, regVal);
32
33 if (ah->ah_config.analog_shiftreg)
34 udelay(100);
35
36 return;
37 }
38
39 static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
40 {
41
42 if (fbin == AR5416_BCHAN_UNUSED)
43 return fbin;
44
45 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
46 }
47
48 static inline int16_t ath9k_hw_interpolate(u16 target,
49 u16 srcLeft, u16 srcRight,
50 int16_t targetLeft,
51 int16_t targetRight)
52 {
53 int16_t rv;
54
55 if (srcRight == srcLeft) {
56 rv = targetLeft;
57 } else {
58 rv = (int16_t) (((target - srcLeft) * targetRight +
59 (srcRight - target) * targetLeft) /
60 (srcRight - srcLeft));
61 }
62 return rv;
63 }
64
65 static inline bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList,
66 u16 listSize, u16 *indexL,
67 u16 *indexR)
68 {
69 u16 i;
70
71 if (target <= pList[0]) {
72 *indexL = *indexR = 0;
73 return true;
74 }
75 if (target >= pList[listSize - 1]) {
76 *indexL = *indexR = (u16) (listSize - 1);
77 return true;
78 }
79
80 for (i = 0; i < listSize - 1; i++) {
81 if (pList[i] == target) {
82 *indexL = *indexR = i;
83 return true;
84 }
85 if (target < pList[i + 1]) {
86 *indexL = i;
87 *indexR = (u16) (i + 1);
88 return false;
89 }
90 }
91 return false;
92 }
93
94 static inline bool ath9k_hw_nvram_read(struct ath_hal *ah, u32 off, u16 *data)
95 {
96 struct ath_softc *sc = ah->ah_sc;
97
98 return sc->bus_ops->eeprom_read(ah, off, data);
99 }
100
101 static bool ath9k_hw_fill_4k_eeprom(struct ath_hal *ah)
102 {
103 #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
104 struct ath_hal_5416 *ahp = AH5416(ah);
105 struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k;
106 u16 *eep_data;
107 int addr, eep_start_loc = 0;
108
109 eep_start_loc = 64;
110
111 if (!ath9k_hw_use_flash(ah)) {
112 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
113 "Reading from EEPROM, not flash\n");
114 }
115
116 eep_data = (u16 *)eep;
117
118 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
119 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
120 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
121 "Unable to read eeprom region \n");
122 return false;
123 }
124 eep_data++;
125 }
126 return true;
127 #undef SIZE_EEPROM_4K
128 }
129
130 static bool ath9k_hw_fill_def_eeprom(struct ath_hal *ah)
131 {
132 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
133 struct ath_hal_5416 *ahp = AH5416(ah);
134 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
135 u16 *eep_data;
136 int addr, ar5416_eep_start_loc = 0x100;
137
138 eep_data = (u16 *)eep;
139
140 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
141 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
142 eep_data)) {
143 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
144 "Unable to read eeprom region\n");
145 return false;
146 }
147 eep_data++;
148 }
149 return true;
150 #undef SIZE_EEPROM_DEF
151 }
152
153 static bool (*ath9k_fill_eeprom[]) (struct ath_hal *) = {
154 ath9k_hw_fill_def_eeprom,
155 ath9k_hw_fill_4k_eeprom
156 };
157
158 static inline bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
159 {
160 struct ath_hal_5416 *ahp = AH5416(ah);
161
162 return ath9k_fill_eeprom[ahp->ah_eep_map](ah);
163 }
164
165 static int ath9k_hw_check_def_eeprom(struct ath_hal *ah)
166 {
167 struct ath_hal_5416 *ahp = AH5416(ah);
168 struct ar5416_eeprom_def *eep =
169 (struct ar5416_eeprom_def *) &ahp->ah_eeprom.def;
170 u16 *eepdata, temp, magic, magic2;
171 u32 sum = 0, el;
172 bool need_swap = false;
173 int i, addr, size;
174
175 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
176 &magic)) {
177 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
178 "Reading Magic # failed\n");
179 return false;
180 }
181
182 if (!ath9k_hw_use_flash(ah)) {
183
184 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
185 "Read Magic = 0x%04X\n", magic);
186
187 if (magic != AR5416_EEPROM_MAGIC) {
188 magic2 = swab16(magic);
189
190 if (magic2 == AR5416_EEPROM_MAGIC) {
191 size = sizeof(struct ar5416_eeprom_def);
192 need_swap = true;
193 eepdata = (u16 *) (&ahp->ah_eeprom);
194
195 for (addr = 0; addr < size / sizeof(u16); addr++) {
196 temp = swab16(*eepdata);
197 *eepdata = temp;
198 eepdata++;
199
200 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
201 "0x%04X ", *eepdata);
202
203 if (((addr + 1) % 6) == 0)
204 DPRINTF(ah->ah_sc,
205 ATH_DBG_EEPROM, "\n");
206 }
207 } else {
208 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
209 "Invalid EEPROM Magic. "
210 "endianness mismatch.\n");
211 return -EINVAL;
212 }
213 }
214 }
215
216 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
217 need_swap ? "True" : "False");
218
219 if (need_swap)
220 el = swab16(ahp->ah_eeprom.def.baseEepHeader.length);
221 else
222 el = ahp->ah_eeprom.def.baseEepHeader.length;
223
224 if (el > sizeof(struct ar5416_eeprom_def))
225 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
226 else
227 el = el / sizeof(u16);
228
229 eepdata = (u16 *)(&ahp->ah_eeprom);
230
231 for (i = 0; i < el; i++)
232 sum ^= *eepdata++;
233
234 if (need_swap) {
235 u32 integer, j;
236 u16 word;
237
238 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
239 "EEPROM Endianness is not native.. Changing \n");
240
241 word = swab16(eep->baseEepHeader.length);
242 eep->baseEepHeader.length = word;
243
244 word = swab16(eep->baseEepHeader.checksum);
245 eep->baseEepHeader.checksum = word;
246
247 word = swab16(eep->baseEepHeader.version);
248 eep->baseEepHeader.version = word;
249
250 word = swab16(eep->baseEepHeader.regDmn[0]);
251 eep->baseEepHeader.regDmn[0] = word;
252
253 word = swab16(eep->baseEepHeader.regDmn[1]);
254 eep->baseEepHeader.regDmn[1] = word;
255
256 word = swab16(eep->baseEepHeader.rfSilent);
257 eep->baseEepHeader.rfSilent = word;
258
259 word = swab16(eep->baseEepHeader.blueToothOptions);
260 eep->baseEepHeader.blueToothOptions = word;
261
262 word = swab16(eep->baseEepHeader.deviceCap);
263 eep->baseEepHeader.deviceCap = word;
264
265 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
266 struct modal_eep_header *pModal =
267 &eep->modalHeader[j];
268 integer = swab32(pModal->antCtrlCommon);
269 pModal->antCtrlCommon = integer;
270
271 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
272 integer = swab32(pModal->antCtrlChain[i]);
273 pModal->antCtrlChain[i] = integer;
274 }
275
276 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
277 word = swab16(pModal->spurChans[i].spurChan);
278 pModal->spurChans[i].spurChan = word;
279 }
280 }
281 }
282
283 if (sum != 0xffff || ar5416_get_eep_ver(ahp) != AR5416_EEP_VER ||
284 ar5416_get_eep_rev(ahp) < AR5416_EEP_NO_BACK_VER) {
285 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
286 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
287 sum, ar5416_get_eep_ver(ahp));
288 return -EINVAL;
289 }
290
291 return 0;
292 }
293
294 static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah)
295 {
296 #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
297 struct ath_hal_5416 *ahp = AH5416(ah);
298 struct ar5416_eeprom_4k *eep =
299 (struct ar5416_eeprom_4k *) &ahp->ah_eeprom.map4k;
300 u16 *eepdata, temp, magic, magic2;
301 u32 sum = 0, el;
302 bool need_swap = false;
303 int i, addr;
304
305
306 if (!ath9k_hw_use_flash(ah)) {
307
308 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
309 &magic)) {
310 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
311 "Reading Magic # failed\n");
312 return false;
313 }
314
315 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
316 "Read Magic = 0x%04X\n", magic);
317
318 if (magic != AR5416_EEPROM_MAGIC) {
319 magic2 = swab16(magic);
320
321 if (magic2 == AR5416_EEPROM_MAGIC) {
322 need_swap = true;
323 eepdata = (u16 *) (&ahp->ah_eeprom);
324
325 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
326 temp = swab16(*eepdata);
327 *eepdata = temp;
328 eepdata++;
329
330 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
331 "0x%04X ", *eepdata);
332
333 if (((addr + 1) % 6) == 0)
334 DPRINTF(ah->ah_sc,
335 ATH_DBG_EEPROM, "\n");
336 }
337 } else {
338 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
339 "Invalid EEPROM Magic. "
340 "endianness mismatch.\n");
341 return -EINVAL;
342 }
343 }
344 }
345
346 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
347 need_swap ? "True" : "False");
348
349 if (need_swap)
350 el = swab16(ahp->ah_eeprom.map4k.baseEepHeader.length);
351 else
352 el = ahp->ah_eeprom.map4k.baseEepHeader.length;
353
354 if (el > sizeof(struct ar5416_eeprom_def))
355 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
356 else
357 el = el / sizeof(u16);
358
359 eepdata = (u16 *)(&ahp->ah_eeprom);
360
361 for (i = 0; i < el; i++)
362 sum ^= *eepdata++;
363
364 if (need_swap) {
365 u32 integer;
366 u16 word;
367
368 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
369 "EEPROM Endianness is not native.. Changing \n");
370
371 word = swab16(eep->baseEepHeader.length);
372 eep->baseEepHeader.length = word;
373
374 word = swab16(eep->baseEepHeader.checksum);
375 eep->baseEepHeader.checksum = word;
376
377 word = swab16(eep->baseEepHeader.version);
378 eep->baseEepHeader.version = word;
379
380 word = swab16(eep->baseEepHeader.regDmn[0]);
381 eep->baseEepHeader.regDmn[0] = word;
382
383 word = swab16(eep->baseEepHeader.regDmn[1]);
384 eep->baseEepHeader.regDmn[1] = word;
385
386 word = swab16(eep->baseEepHeader.rfSilent);
387 eep->baseEepHeader.rfSilent = word;
388
389 word = swab16(eep->baseEepHeader.blueToothOptions);
390 eep->baseEepHeader.blueToothOptions = word;
391
392 word = swab16(eep->baseEepHeader.deviceCap);
393 eep->baseEepHeader.deviceCap = word;
394
395 integer = swab32(eep->modalHeader.antCtrlCommon);
396 eep->modalHeader.antCtrlCommon = integer;
397
398 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
399 integer = swab32(eep->modalHeader.antCtrlChain[i]);
400 eep->modalHeader.antCtrlChain[i] = integer;
401 }
402
403 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
404 word = swab16(eep->modalHeader.spurChans[i].spurChan);
405 eep->modalHeader.spurChans[i].spurChan = word;
406 }
407 }
408
409 if (sum != 0xffff || ar5416_get_eep4k_ver(ahp) != AR5416_EEP_VER ||
410 ar5416_get_eep4k_rev(ahp) < AR5416_EEP_NO_BACK_VER) {
411 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
412 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
413 sum, ar5416_get_eep4k_ver(ahp));
414 return -EINVAL;
415 }
416
417 return 0;
418 #undef EEPROM_4K_SIZE
419 }
420
421 static int (*ath9k_check_eeprom[]) (struct ath_hal *) = {
422 ath9k_hw_check_def_eeprom,
423 ath9k_hw_check_4k_eeprom
424 };
425
426 static inline int ath9k_hw_check_eeprom(struct ath_hal *ah)
427 {
428 struct ath_hal_5416 *ahp = AH5416(ah);
429
430 return ath9k_check_eeprom[ahp->ah_eep_map](ah);
431 }
432
433 static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
434 u8 *pVpdList, u16 numIntercepts,
435 u8 *pRetVpdList)
436 {
437 u16 i, k;
438 u8 currPwr = pwrMin;
439 u16 idxL = 0, idxR = 0;
440
441 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
442 ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
443 numIntercepts, &(idxL),
444 &(idxR));
445 if (idxR < 1)
446 idxR = 1;
447 if (idxL == numIntercepts - 1)
448 idxL = (u16) (numIntercepts - 2);
449 if (pPwrList[idxL] == pPwrList[idxR])
450 k = pVpdList[idxL];
451 else
452 k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
453 (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
454 (pPwrList[idxR] - pPwrList[idxL]));
455 pRetVpdList[i] = (u8) k;
456 currPwr += 2;
457 }
458
459 return true;
460 }
461
462 static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hal *ah,
463 struct ath9k_channel *chan,
464 struct cal_data_per_freq_4k *pRawDataSet,
465 u8 *bChans, u16 availPiers,
466 u16 tPdGainOverlap, int16_t *pMinCalPower,
467 u16 *pPdGainBoundaries, u8 *pPDADCValues,
468 u16 numXpdGains)
469 {
470 #define TMP_VAL_VPD_TABLE \
471 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
472 int i, j, k;
473 int16_t ss;
474 u16 idxL = 0, idxR = 0, numPiers;
475 static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
476 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
477 static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
478 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
479 static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
480 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
481
482 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
483 u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
484 u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
485 int16_t vpdStep;
486 int16_t tmpVal;
487 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
488 bool match;
489 int16_t minDelta = 0;
490 struct chan_centers centers;
491 #define PD_GAIN_BOUNDARY_DEFAULT 58;
492
493 ath9k_hw_get_channel_centers(ah, chan, &centers);
494
495 for (numPiers = 0; numPiers < availPiers; numPiers++) {
496 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
497 break;
498 }
499
500 match = ath9k_hw_get_lower_upper_index(
501 (u8)FREQ2FBIN(centers.synth_center,
502 IS_CHAN_2GHZ(chan)), bChans, numPiers,
503 &idxL, &idxR);
504
505 if (match) {
506 for (i = 0; i < numXpdGains; i++) {
507 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
508 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
509 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
510 pRawDataSet[idxL].pwrPdg[i],
511 pRawDataSet[idxL].vpdPdg[i],
512 AR5416_EEP4K_PD_GAIN_ICEPTS,
513 vpdTableI[i]);
514 }
515 } else {
516 for (i = 0; i < numXpdGains; i++) {
517 pVpdL = pRawDataSet[idxL].vpdPdg[i];
518 pPwrL = pRawDataSet[idxL].pwrPdg[i];
519 pVpdR = pRawDataSet[idxR].vpdPdg[i];
520 pPwrR = pRawDataSet[idxR].pwrPdg[i];
521
522 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
523
524 maxPwrT4[i] =
525 min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1],
526 pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]);
527
528
529 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
530 pPwrL, pVpdL,
531 AR5416_EEP4K_PD_GAIN_ICEPTS,
532 vpdTableL[i]);
533 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
534 pPwrR, pVpdR,
535 AR5416_EEP4K_PD_GAIN_ICEPTS,
536 vpdTableR[i]);
537
538 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
539 vpdTableI[i][j] =
540 (u8)(ath9k_hw_interpolate((u16)
541 FREQ2FBIN(centers.
542 synth_center,
543 IS_CHAN_2GHZ
544 (chan)),
545 bChans[idxL], bChans[idxR],
546 vpdTableL[i][j], vpdTableR[i][j]));
547 }
548 }
549 }
550
551 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
552
553 k = 0;
554
555 for (i = 0; i < numXpdGains; i++) {
556 if (i == (numXpdGains - 1))
557 pPdGainBoundaries[i] =
558 (u16)(maxPwrT4[i] / 2);
559 else
560 pPdGainBoundaries[i] =
561 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
562
563 pPdGainBoundaries[i] =
564 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
565
566 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) {
567 minDelta = pPdGainBoundaries[0] - 23;
568 pPdGainBoundaries[0] = 23;
569 } else {
570 minDelta = 0;
571 }
572
573 if (i == 0) {
574 if (AR_SREV_9280_10_OR_LATER(ah))
575 ss = (int16_t)(0 - (minPwrT4[i] / 2));
576 else
577 ss = 0;
578 } else {
579 ss = (int16_t)((pPdGainBoundaries[i - 1] -
580 (minPwrT4[i] / 2)) -
581 tPdGainOverlap + 1 + minDelta);
582 }
583 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
584 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
585
586 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
587 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
588 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
589 ss++;
590 }
591
592 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
593 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
594 (minPwrT4[i] / 2));
595 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
596 tgtIndex : sizeCurrVpdTable;
597
598 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
599 pPDADCValues[k++] = vpdTableI[i][ss++];
600
601 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
602 vpdTableI[i][sizeCurrVpdTable - 2]);
603 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
604
605 if (tgtIndex > maxIndex) {
606 while ((ss <= tgtIndex) &&
607 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
608 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
609 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
610 255 : tmpVal);
611 ss++;
612 }
613 }
614 }
615
616 while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) {
617 pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
618 i++;
619 }
620
621 while (k < AR5416_NUM_PDADC_VALUES) {
622 pPDADCValues[k] = pPDADCValues[k - 1];
623 k++;
624 }
625
626 return;
627 #undef TMP_VAL_VPD_TABLE
628 }
629
630 static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hal *ah,
631 struct ath9k_channel *chan,
632 struct cal_data_per_freq *pRawDataSet,
633 u8 *bChans, u16 availPiers,
634 u16 tPdGainOverlap, int16_t *pMinCalPower,
635 u16 *pPdGainBoundaries, u8 *pPDADCValues,
636 u16 numXpdGains)
637 {
638 int i, j, k;
639 int16_t ss;
640 u16 idxL = 0, idxR = 0, numPiers;
641 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
642 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
643 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
644 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
645 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
646 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
647
648 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
649 u8 minPwrT4[AR5416_NUM_PD_GAINS];
650 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
651 int16_t vpdStep;
652 int16_t tmpVal;
653 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
654 bool match;
655 int16_t minDelta = 0;
656 struct chan_centers centers;
657
658 ath9k_hw_get_channel_centers(ah, chan, &centers);
659
660 for (numPiers = 0; numPiers < availPiers; numPiers++) {
661 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
662 break;
663 }
664
665 match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
666 IS_CHAN_2GHZ(chan)),
667 bChans, numPiers, &idxL, &idxR);
668
669 if (match) {
670 for (i = 0; i < numXpdGains; i++) {
671 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
672 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
673 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
674 pRawDataSet[idxL].pwrPdg[i],
675 pRawDataSet[idxL].vpdPdg[i],
676 AR5416_PD_GAIN_ICEPTS,
677 vpdTableI[i]);
678 }
679 } else {
680 for (i = 0; i < numXpdGains; i++) {
681 pVpdL = pRawDataSet[idxL].vpdPdg[i];
682 pPwrL = pRawDataSet[idxL].pwrPdg[i];
683 pVpdR = pRawDataSet[idxR].vpdPdg[i];
684 pPwrR = pRawDataSet[idxR].pwrPdg[i];
685
686 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
687
688 maxPwrT4[i] =
689 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
690 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
691
692
693 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
694 pPwrL, pVpdL,
695 AR5416_PD_GAIN_ICEPTS,
696 vpdTableL[i]);
697 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
698 pPwrR, pVpdR,
699 AR5416_PD_GAIN_ICEPTS,
700 vpdTableR[i]);
701
702 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
703 vpdTableI[i][j] =
704 (u8)(ath9k_hw_interpolate((u16)
705 FREQ2FBIN(centers.
706 synth_center,
707 IS_CHAN_2GHZ
708 (chan)),
709 bChans[idxL], bChans[idxR],
710 vpdTableL[i][j], vpdTableR[i][j]));
711 }
712 }
713 }
714
715 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
716
717 k = 0;
718
719 for (i = 0; i < numXpdGains; i++) {
720 if (i == (numXpdGains - 1))
721 pPdGainBoundaries[i] =
722 (u16)(maxPwrT4[i] / 2);
723 else
724 pPdGainBoundaries[i] =
725 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
726
727 pPdGainBoundaries[i] =
728 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
729
730 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) {
731 minDelta = pPdGainBoundaries[0] - 23;
732 pPdGainBoundaries[0] = 23;
733 } else {
734 minDelta = 0;
735 }
736
737 if (i == 0) {
738 if (AR_SREV_9280_10_OR_LATER(ah))
739 ss = (int16_t)(0 - (minPwrT4[i] / 2));
740 else
741 ss = 0;
742 } else {
743 ss = (int16_t)((pPdGainBoundaries[i - 1] -
744 (minPwrT4[i] / 2)) -
745 tPdGainOverlap + 1 + minDelta);
746 }
747 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
748 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
749
750 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
751 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
752 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
753 ss++;
754 }
755
756 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
757 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
758 (minPwrT4[i] / 2));
759 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
760 tgtIndex : sizeCurrVpdTable;
761
762 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
763 pPDADCValues[k++] = vpdTableI[i][ss++];
764 }
765
766 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
767 vpdTableI[i][sizeCurrVpdTable - 2]);
768 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
769
770 if (tgtIndex > maxIndex) {
771 while ((ss <= tgtIndex) &&
772 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
773 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
774 (ss - maxIndex + 1) * vpdStep));
775 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
776 255 : tmpVal);
777 ss++;
778 }
779 }
780 }
781
782 while (i < AR5416_PD_GAINS_IN_MASK) {
783 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
784 i++;
785 }
786
787 while (k < AR5416_NUM_PDADC_VALUES) {
788 pPDADCValues[k] = pPDADCValues[k - 1];
789 k++;
790 }
791
792 return;
793 }
794
795 static void ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,
796 struct ath9k_channel *chan,
797 struct cal_target_power_leg *powInfo,
798 u16 numChannels,
799 struct cal_target_power_leg *pNewPower,
800 u16 numRates, bool isExtTarget)
801 {
802 struct chan_centers centers;
803 u16 clo, chi;
804 int i;
805 int matchIndex = -1, lowIndex = -1;
806 u16 freq;
807
808 ath9k_hw_get_channel_centers(ah, chan, &centers);
809 freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
810
811 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
812 IS_CHAN_2GHZ(chan))) {
813 matchIndex = 0;
814 } else {
815 for (i = 0; (i < numChannels) &&
816 (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
817 if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
818 IS_CHAN_2GHZ(chan))) {
819 matchIndex = i;
820 break;
821 } else if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
822 IS_CHAN_2GHZ(chan))) &&
823 (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
824 IS_CHAN_2GHZ(chan)))) {
825 lowIndex = i - 1;
826 break;
827 }
828 }
829 if ((matchIndex == -1) && (lowIndex == -1))
830 matchIndex = i - 1;
831 }
832
833 if (matchIndex != -1) {
834 *pNewPower = powInfo[matchIndex];
835 } else {
836 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
837 IS_CHAN_2GHZ(chan));
838 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
839 IS_CHAN_2GHZ(chan));
840
841 for (i = 0; i < numRates; i++) {
842 pNewPower->tPow2x[i] =
843 (u8)ath9k_hw_interpolate(freq, clo, chi,
844 powInfo[lowIndex].tPow2x[i],
845 powInfo[lowIndex + 1].tPow2x[i]);
846 }
847 }
848 }
849
850 static void ath9k_hw_get_target_powers(struct ath_hal *ah,
851 struct ath9k_channel *chan,
852 struct cal_target_power_ht *powInfo,
853 u16 numChannels,
854 struct cal_target_power_ht *pNewPower,
855 u16 numRates, bool isHt40Target)
856 {
857 struct chan_centers centers;
858 u16 clo, chi;
859 int i;
860 int matchIndex = -1, lowIndex = -1;
861 u16 freq;
862
863 ath9k_hw_get_channel_centers(ah, chan, &centers);
864 freq = isHt40Target ? centers.synth_center : centers.ctl_center;
865
866 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
867 matchIndex = 0;
868 } else {
869 for (i = 0; (i < numChannels) &&
870 (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
871 if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
872 IS_CHAN_2GHZ(chan))) {
873 matchIndex = i;
874 break;
875 } else
876 if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
877 IS_CHAN_2GHZ(chan))) &&
878 (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
879 IS_CHAN_2GHZ(chan)))) {
880 lowIndex = i - 1;
881 break;
882 }
883 }
884 if ((matchIndex == -1) && (lowIndex == -1))
885 matchIndex = i - 1;
886 }
887
888 if (matchIndex != -1) {
889 *pNewPower = powInfo[matchIndex];
890 } else {
891 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
892 IS_CHAN_2GHZ(chan));
893 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
894 IS_CHAN_2GHZ(chan));
895
896 for (i = 0; i < numRates; i++) {
897 pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
898 clo, chi,
899 powInfo[lowIndex].tPow2x[i],
900 powInfo[lowIndex + 1].tPow2x[i]);
901 }
902 }
903 }
904
905 static u16 ath9k_hw_get_max_edge_power(u16 freq,
906 struct cal_ctl_edges *pRdEdgesPower,
907 bool is2GHz, int num_band_edges)
908 {
909 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
910 int i;
911
912 for (i = 0; (i < num_band_edges) &&
913 (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
914 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
915 twiceMaxEdgePower = pRdEdgesPower[i].tPower;
916 break;
917 } else if ((i > 0) &&
918 (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
919 is2GHz))) {
920 if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
921 is2GHz) < freq &&
922 pRdEdgesPower[i - 1].flag) {
923 twiceMaxEdgePower =
924 pRdEdgesPower[i - 1].tPower;
925 }
926 break;
927 }
928 }
929
930 return twiceMaxEdgePower;
931 }
932
933 static bool ath9k_hw_set_def_power_cal_table(struct ath_hal *ah,
934 struct ath9k_channel *chan,
935 int16_t *pTxPowerIndexOffset)
936 {
937 struct ath_hal_5416 *ahp = AH5416(ah);
938 struct ar5416_eeprom_def *pEepData = &ahp->ah_eeprom.def;
939 struct cal_data_per_freq *pRawDataset;
940 u8 *pCalBChans = NULL;
941 u16 pdGainOverlap_t2;
942 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
943 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
944 u16 numPiers, i, j;
945 int16_t tMinCalPower;
946 u16 numXpdGain, xpdMask;
947 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
948 u32 reg32, regOffset, regChainOffset;
949 int16_t modalIdx;
950
951 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
952 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
953
954 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
955 AR5416_EEP_MINOR_VER_2) {
956 pdGainOverlap_t2 =
957 pEepData->modalHeader[modalIdx].pdGainOverlap;
958 } else {
959 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
960 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
961 }
962
963 if (IS_CHAN_2GHZ(chan)) {
964 pCalBChans = pEepData->calFreqPier2G;
965 numPiers = AR5416_NUM_2G_CAL_PIERS;
966 } else {
967 pCalBChans = pEepData->calFreqPier5G;
968 numPiers = AR5416_NUM_5G_CAL_PIERS;
969 }
970
971 numXpdGain = 0;
972
973 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
974 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
975 if (numXpdGain >= AR5416_NUM_PD_GAINS)
976 break;
977 xpdGainValues[numXpdGain] =
978 (u16)(AR5416_PD_GAINS_IN_MASK - i);
979 numXpdGain++;
980 }
981 }
982
983 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
984 (numXpdGain - 1) & 0x3);
985 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
986 xpdGainValues[0]);
987 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
988 xpdGainValues[1]);
989 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
990 xpdGainValues[2]);
991
992 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
993 if (AR_SREV_5416_V20_OR_LATER(ah) &&
994 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) &&
995 (i != 0)) {
996 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
997 } else
998 regChainOffset = i * 0x1000;
999
1000 if (pEepData->baseEepHeader.txMask & (1 << i)) {
1001 if (IS_CHAN_2GHZ(chan))
1002 pRawDataset = pEepData->calPierData2G[i];
1003 else
1004 pRawDataset = pEepData->calPierData5G[i];
1005
1006 ath9k_hw_get_def_gain_boundaries_pdadcs(ah, chan,
1007 pRawDataset, pCalBChans,
1008 numPiers, pdGainOverlap_t2,
1009 &tMinCalPower, gainBoundaries,
1010 pdadcValues, numXpdGain);
1011
1012 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
1013 REG_WRITE(ah,
1014 AR_PHY_TPCRG5 + regChainOffset,
1015 SM(pdGainOverlap_t2,
1016 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
1017 | SM(gainBoundaries[0],
1018 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
1019 | SM(gainBoundaries[1],
1020 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
1021 | SM(gainBoundaries[2],
1022 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
1023 | SM(gainBoundaries[3],
1024 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
1025 }
1026
1027 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
1028 for (j = 0; j < 32; j++) {
1029 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
1030 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
1031 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
1032 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
1033 REG_WRITE(ah, regOffset, reg32);
1034
1035 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1036 "PDADC (%d,%4x): %4.4x %8.8x\n",
1037 i, regChainOffset, regOffset,
1038 reg32);
1039 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1040 "PDADC: Chain %d | PDADC %3d "
1041 "Value %3d | PDADC %3d Value %3d | "
1042 "PDADC %3d Value %3d | PDADC %3d "
1043 "Value %3d |\n",
1044 i, 4 * j, pdadcValues[4 * j],
1045 4 * j + 1, pdadcValues[4 * j + 1],
1046 4 * j + 2, pdadcValues[4 * j + 2],
1047 4 * j + 3,
1048 pdadcValues[4 * j + 3]);
1049
1050 regOffset += 4;
1051 }
1052 }
1053 }
1054
1055 *pTxPowerIndexOffset = 0;
1056
1057 return true;
1058 }
1059
1060 static bool ath9k_hw_set_4k_power_cal_table(struct ath_hal *ah,
1061 struct ath9k_channel *chan,
1062 int16_t *pTxPowerIndexOffset)
1063 {
1064 struct ath_hal_5416 *ahp = AH5416(ah);
1065 struct ar5416_eeprom_4k *pEepData = &ahp->ah_eeprom.map4k;
1066 struct cal_data_per_freq_4k *pRawDataset;
1067 u8 *pCalBChans = NULL;
1068 u16 pdGainOverlap_t2;
1069 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
1070 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
1071 u16 numPiers, i, j;
1072 int16_t tMinCalPower;
1073 u16 numXpdGain, xpdMask;
1074 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
1075 u32 reg32, regOffset, regChainOffset;
1076
1077 xpdMask = pEepData->modalHeader.xpdGain;
1078
1079 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1080 AR5416_EEP_MINOR_VER_2) {
1081 pdGainOverlap_t2 =
1082 pEepData->modalHeader.pdGainOverlap;
1083 } else {
1084 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
1085 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
1086 }
1087
1088 pCalBChans = pEepData->calFreqPier2G;
1089 numPiers = AR5416_NUM_2G_CAL_PIERS;
1090
1091 numXpdGain = 0;
1092
1093 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
1094 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
1095 if (numXpdGain >= AR5416_NUM_PD_GAINS)
1096 break;
1097 xpdGainValues[numXpdGain] =
1098 (u16)(AR5416_PD_GAINS_IN_MASK - i);
1099 numXpdGain++;
1100 }
1101 }
1102
1103 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
1104 (numXpdGain - 1) & 0x3);
1105 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
1106 xpdGainValues[0]);
1107 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
1108 xpdGainValues[1]);
1109 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
1110 xpdGainValues[2]);
1111
1112 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1113 if (AR_SREV_5416_V20_OR_LATER(ah) &&
1114 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) &&
1115 (i != 0)) {
1116 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1117 } else
1118 regChainOffset = i * 0x1000;
1119
1120 if (pEepData->baseEepHeader.txMask & (1 << i)) {
1121 pRawDataset = pEepData->calPierData2G[i];
1122
1123 ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan,
1124 pRawDataset, pCalBChans,
1125 numPiers, pdGainOverlap_t2,
1126 &tMinCalPower, gainBoundaries,
1127 pdadcValues, numXpdGain);
1128
1129 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
1130 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
1131 SM(pdGainOverlap_t2,
1132 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
1133 | SM(gainBoundaries[0],
1134 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
1135 | SM(gainBoundaries[1],
1136 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
1137 | SM(gainBoundaries[2],
1138 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
1139 | SM(gainBoundaries[3],
1140 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
1141 }
1142
1143 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
1144 for (j = 0; j < 32; j++) {
1145 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
1146 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
1147 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
1148 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
1149 REG_WRITE(ah, regOffset, reg32);
1150
1151 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1152 "PDADC (%d,%4x): %4.4x %8.8x\n",
1153 i, regChainOffset, regOffset,
1154 reg32);
1155 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1156 "PDADC: Chain %d | "
1157 "PDADC %3d Value %3d | "
1158 "PDADC %3d Value %3d | "
1159 "PDADC %3d Value %3d | "
1160 "PDADC %3d Value %3d |\n",
1161 i, 4 * j, pdadcValues[4 * j],
1162 4 * j + 1, pdadcValues[4 * j + 1],
1163 4 * j + 2, pdadcValues[4 * j + 2],
1164 4 * j + 3,
1165 pdadcValues[4 * j + 3]);
1166
1167 regOffset += 4;
1168 }
1169 }
1170 }
1171
1172 *pTxPowerIndexOffset = 0;
1173
1174 return true;
1175 }
1176
1177 static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hal *ah,
1178 struct ath9k_channel *chan,
1179 int16_t *ratesArray,
1180 u16 cfgCtl,
1181 u16 AntennaReduction,
1182 u16 twiceMaxRegulatoryPower,
1183 u16 powerLimit)
1184 {
1185 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
1186 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
1187
1188 struct ath_hal_5416 *ahp = AH5416(ah);
1189 struct ar5416_eeprom_def *pEepData = &ahp->ah_eeprom.def;
1190 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1191 static const u16 tpScaleReductionTable[5] =
1192 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
1193
1194 int i;
1195 int16_t twiceLargestAntenna;
1196 struct cal_ctl_data *rep;
1197 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
1198 0, { 0, 0, 0, 0}
1199 };
1200 struct cal_target_power_leg targetPowerOfdmExt = {
1201 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
1202 0, { 0, 0, 0, 0 }
1203 };
1204 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
1205 0, {0, 0, 0, 0}
1206 };
1207 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
1208 u16 ctlModesFor11a[] =
1209 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
1210 u16 ctlModesFor11g[] =
1211 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
1212 CTL_2GHT40
1213 };
1214 u16 numCtlModes, *pCtlMode, ctlMode, freq;
1215 struct chan_centers centers;
1216 int tx_chainmask;
1217 u16 twiceMinEdgePower;
1218
1219 tx_chainmask = ahp->ah_txchainmask;
1220
1221 ath9k_hw_get_channel_centers(ah, chan, &centers);
1222
1223 twiceLargestAntenna = max(
1224 pEepData->modalHeader
1225 [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
1226 pEepData->modalHeader
1227 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
1228
1229 twiceLargestAntenna = max((u8)twiceLargestAntenna,
1230 pEepData->modalHeader
1231 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
1232
1233 twiceLargestAntenna = (int16_t)min(AntennaReduction -
1234 twiceLargestAntenna, 0);
1235
1236 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
1237
1238 if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) {
1239 maxRegAllowedPower -=
1240 (tpScaleReductionTable[(ah->ah_tpScale)] * 2);
1241 }
1242
1243 scaledPower = min(powerLimit, maxRegAllowedPower);
1244
1245 switch (ar5416_get_ntxchains(tx_chainmask)) {
1246 case 1:
1247 break;
1248 case 2:
1249 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
1250 break;
1251 case 3:
1252 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
1253 break;
1254 }
1255
1256 scaledPower = max((u16)0, scaledPower);
1257
1258 if (IS_CHAN_2GHZ(chan)) {
1259 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
1260 SUB_NUM_CTL_MODES_AT_2G_40;
1261 pCtlMode = ctlModesFor11g;
1262
1263 ath9k_hw_get_legacy_target_powers(ah, chan,
1264 pEepData->calTargetPowerCck,
1265 AR5416_NUM_2G_CCK_TARGET_POWERS,
1266 &targetPowerCck, 4, false);
1267 ath9k_hw_get_legacy_target_powers(ah, chan,
1268 pEepData->calTargetPower2G,
1269 AR5416_NUM_2G_20_TARGET_POWERS,
1270 &targetPowerOfdm, 4, false);
1271 ath9k_hw_get_target_powers(ah, chan,
1272 pEepData->calTargetPower2GHT20,
1273 AR5416_NUM_2G_20_TARGET_POWERS,
1274 &targetPowerHt20, 8, false);
1275
1276 if (IS_CHAN_HT40(chan)) {
1277 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
1278 ath9k_hw_get_target_powers(ah, chan,
1279 pEepData->calTargetPower2GHT40,
1280 AR5416_NUM_2G_40_TARGET_POWERS,
1281 &targetPowerHt40, 8, true);
1282 ath9k_hw_get_legacy_target_powers(ah, chan,
1283 pEepData->calTargetPowerCck,
1284 AR5416_NUM_2G_CCK_TARGET_POWERS,
1285 &targetPowerCckExt, 4, true);
1286 ath9k_hw_get_legacy_target_powers(ah, chan,
1287 pEepData->calTargetPower2G,
1288 AR5416_NUM_2G_20_TARGET_POWERS,
1289 &targetPowerOfdmExt, 4, true);
1290 }
1291 } else {
1292 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
1293 SUB_NUM_CTL_MODES_AT_5G_40;
1294 pCtlMode = ctlModesFor11a;
1295
1296 ath9k_hw_get_legacy_target_powers(ah, chan,
1297 pEepData->calTargetPower5G,
1298 AR5416_NUM_5G_20_TARGET_POWERS,
1299 &targetPowerOfdm, 4, false);
1300 ath9k_hw_get_target_powers(ah, chan,
1301 pEepData->calTargetPower5GHT20,
1302 AR5416_NUM_5G_20_TARGET_POWERS,
1303 &targetPowerHt20, 8, false);
1304
1305 if (IS_CHAN_HT40(chan)) {
1306 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
1307 ath9k_hw_get_target_powers(ah, chan,
1308 pEepData->calTargetPower5GHT40,
1309 AR5416_NUM_5G_40_TARGET_POWERS,
1310 &targetPowerHt40, 8, true);
1311 ath9k_hw_get_legacy_target_powers(ah, chan,
1312 pEepData->calTargetPower5G,
1313 AR5416_NUM_5G_20_TARGET_POWERS,
1314 &targetPowerOfdmExt, 4, true);
1315 }
1316 }
1317
1318 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1319 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1320 (pCtlMode[ctlMode] == CTL_2GHT40);
1321 if (isHt40CtlMode)
1322 freq = centers.synth_center;
1323 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1324 freq = centers.ext_center;
1325 else
1326 freq = centers.ctl_center;
1327
1328 if (ar5416_get_eep_ver(ahp) == 14 && ar5416_get_eep_rev(ahp) <= 2)
1329 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1330
1331 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1332 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
1333 "EXT_ADDITIVE %d\n",
1334 ctlMode, numCtlModes, isHt40CtlMode,
1335 (pCtlMode[ctlMode] & EXT_ADDITIVE));
1336
1337 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1338 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1339 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
1340 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
1341 "chan %d\n",
1342 i, cfgCtl, pCtlMode[ctlMode],
1343 pEepData->ctlIndex[i], chan->channel);
1344
1345 if ((((cfgCtl & ~CTL_MODE_M) |
1346 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1347 pEepData->ctlIndex[i]) ||
1348 (((cfgCtl & ~CTL_MODE_M) |
1349 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1350 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1351 rep = &(pEepData->ctlData[i]);
1352
1353 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
1354 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
1355 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
1356
1357 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1358 " MATCH-EE_IDX %d: ch %d is2 %d "
1359 "2xMinEdge %d chainmask %d chains %d\n",
1360 i, freq, IS_CHAN_2GHZ(chan),
1361 twiceMinEdgePower, tx_chainmask,
1362 ar5416_get_ntxchains
1363 (tx_chainmask));
1364 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1365 twiceMaxEdgePower = min(twiceMaxEdgePower,
1366 twiceMinEdgePower);
1367 } else {
1368 twiceMaxEdgePower = twiceMinEdgePower;
1369 break;
1370 }
1371 }
1372 }
1373
1374 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1375
1376 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1377 " SEL-Min ctlMode %d pCtlMode %d "
1378 "2xMaxEdge %d sP %d minCtlPwr %d\n",
1379 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
1380 scaledPower, minCtlPower);
1381
1382 switch (pCtlMode[ctlMode]) {
1383 case CTL_11B:
1384 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1385 targetPowerCck.tPow2x[i] =
1386 min((u16)targetPowerCck.tPow2x[i],
1387 minCtlPower);
1388 }
1389 break;
1390 case CTL_11A:
1391 case CTL_11G:
1392 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1393 targetPowerOfdm.tPow2x[i] =
1394 min((u16)targetPowerOfdm.tPow2x[i],
1395 minCtlPower);
1396 }
1397 break;
1398 case CTL_5GHT20:
1399 case CTL_2GHT20:
1400 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1401 targetPowerHt20.tPow2x[i] =
1402 min((u16)targetPowerHt20.tPow2x[i],
1403 minCtlPower);
1404 }
1405 break;
1406 case CTL_11B_EXT:
1407 targetPowerCckExt.tPow2x[0] = min((u16)
1408 targetPowerCckExt.tPow2x[0],
1409 minCtlPower);
1410 break;
1411 case CTL_11A_EXT:
1412 case CTL_11G_EXT:
1413 targetPowerOfdmExt.tPow2x[0] = min((u16)
1414 targetPowerOfdmExt.tPow2x[0],
1415 minCtlPower);
1416 break;
1417 case CTL_5GHT40:
1418 case CTL_2GHT40:
1419 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1420 targetPowerHt40.tPow2x[i] =
1421 min((u16)targetPowerHt40.tPow2x[i],
1422 minCtlPower);
1423 }
1424 break;
1425 default:
1426 break;
1427 }
1428 }
1429
1430 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1431 ratesArray[rate18mb] = ratesArray[rate24mb] =
1432 targetPowerOfdm.tPow2x[0];
1433 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1434 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1435 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1436 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1437
1438 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1439 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1440
1441 if (IS_CHAN_2GHZ(chan)) {
1442 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1443 ratesArray[rate2s] = ratesArray[rate2l] =
1444 targetPowerCck.tPow2x[1];
1445 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1446 targetPowerCck.tPow2x[2];
1447 ;
1448 ratesArray[rate11s] = ratesArray[rate11l] =
1449 targetPowerCck.tPow2x[3];
1450 ;
1451 }
1452 if (IS_CHAN_HT40(chan)) {
1453 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1454 ratesArray[rateHt40_0 + i] =
1455 targetPowerHt40.tPow2x[i];
1456 }
1457 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1458 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1459 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1460 if (IS_CHAN_2GHZ(chan)) {
1461 ratesArray[rateExtCck] =
1462 targetPowerCckExt.tPow2x[0];
1463 }
1464 }
1465 return true;
1466 }
1467
1468 static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah,
1469 struct ath9k_channel *chan,
1470 int16_t *ratesArray,
1471 u16 cfgCtl,
1472 u16 AntennaReduction,
1473 u16 twiceMaxRegulatoryPower,
1474 u16 powerLimit)
1475 {
1476 struct ath_hal_5416 *ahp = AH5416(ah);
1477 struct ar5416_eeprom_4k *pEepData = &ahp->ah_eeprom.map4k;
1478 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1479 static const u16 tpScaleReductionTable[5] =
1480 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
1481
1482 int i;
1483 int16_t twiceLargestAntenna;
1484 struct cal_ctl_data_4k *rep;
1485 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
1486 0, { 0, 0, 0, 0}
1487 };
1488 struct cal_target_power_leg targetPowerOfdmExt = {
1489 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
1490 0, { 0, 0, 0, 0 }
1491 };
1492 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
1493 0, {0, 0, 0, 0}
1494 };
1495 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
1496 u16 ctlModesFor11g[] =
1497 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
1498 CTL_2GHT40
1499 };
1500 u16 numCtlModes, *pCtlMode, ctlMode, freq;
1501 struct chan_centers centers;
1502 int tx_chainmask;
1503 u16 twiceMinEdgePower;
1504
1505 tx_chainmask = ahp->ah_txchainmask;
1506
1507 ath9k_hw_get_channel_centers(ah, chan, &centers);
1508
1509 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
1510
1511 twiceLargestAntenna = (int16_t)min(AntennaReduction -
1512 twiceLargestAntenna, 0);
1513
1514 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
1515
1516 if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) {
1517 maxRegAllowedPower -=
1518 (tpScaleReductionTable[(ah->ah_tpScale)] * 2);
1519 }
1520
1521 scaledPower = min(powerLimit, maxRegAllowedPower);
1522 scaledPower = max((u16)0, scaledPower);
1523
1524 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
1525 pCtlMode = ctlModesFor11g;
1526
1527 ath9k_hw_get_legacy_target_powers(ah, chan,
1528 pEepData->calTargetPowerCck,
1529 AR5416_NUM_2G_CCK_TARGET_POWERS,
1530 &targetPowerCck, 4, false);
1531 ath9k_hw_get_legacy_target_powers(ah, chan,
1532 pEepData->calTargetPower2G,
1533 AR5416_NUM_2G_20_TARGET_POWERS,
1534 &targetPowerOfdm, 4, false);
1535 ath9k_hw_get_target_powers(ah, chan,
1536 pEepData->calTargetPower2GHT20,
1537 AR5416_NUM_2G_20_TARGET_POWERS,
1538 &targetPowerHt20, 8, false);
1539
1540 if (IS_CHAN_HT40(chan)) {
1541 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
1542 ath9k_hw_get_target_powers(ah, chan,
1543 pEepData->calTargetPower2GHT40,
1544 AR5416_NUM_2G_40_TARGET_POWERS,
1545 &targetPowerHt40, 8, true);
1546 ath9k_hw_get_legacy_target_powers(ah, chan,
1547 pEepData->calTargetPowerCck,
1548 AR5416_NUM_2G_CCK_TARGET_POWERS,
1549 &targetPowerCckExt, 4, true);
1550 ath9k_hw_get_legacy_target_powers(ah, chan,
1551 pEepData->calTargetPower2G,
1552 AR5416_NUM_2G_20_TARGET_POWERS,
1553 &targetPowerOfdmExt, 4, true);
1554 }
1555
1556 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1557 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1558 (pCtlMode[ctlMode] == CTL_2GHT40);
1559 if (isHt40CtlMode)
1560 freq = centers.synth_center;
1561 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1562 freq = centers.ext_center;
1563 else
1564 freq = centers.ctl_center;
1565
1566 if (ar5416_get_eep_ver(ahp) == 14 &&
1567 ar5416_get_eep_rev(ahp) <= 2)
1568 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1569
1570 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1571 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
1572 "EXT_ADDITIVE %d\n",
1573 ctlMode, numCtlModes, isHt40CtlMode,
1574 (pCtlMode[ctlMode] & EXT_ADDITIVE));
1575
1576 for (i = 0; (i < AR5416_NUM_CTLS) &&
1577 pEepData->ctlIndex[i]; i++) {
1578 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1579 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
1580 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
1581 "chan %d\n",
1582 i, cfgCtl, pCtlMode[ctlMode],
1583 pEepData->ctlIndex[i], chan->channel);
1584
1585 if ((((cfgCtl & ~CTL_MODE_M) |
1586 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1587 pEepData->ctlIndex[i]) ||
1588 (((cfgCtl & ~CTL_MODE_M) |
1589 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1590 ((pEepData->ctlIndex[i] & CTL_MODE_M) |
1591 SD_NO_CTL))) {
1592 rep = &(pEepData->ctlData[i]);
1593
1594 twiceMinEdgePower =
1595 ath9k_hw_get_max_edge_power(freq,
1596 rep->ctlEdges[ar5416_get_ntxchains
1597 (tx_chainmask) - 1],
1598 IS_CHAN_2GHZ(chan),
1599 AR5416_EEP4K_NUM_BAND_EDGES);
1600
1601 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1602 " MATCH-EE_IDX %d: ch %d is2 %d "
1603 "2xMinEdge %d chainmask %d chains %d\n",
1604 i, freq, IS_CHAN_2GHZ(chan),
1605 twiceMinEdgePower, tx_chainmask,
1606 ar5416_get_ntxchains
1607 (tx_chainmask));
1608 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1609 twiceMaxEdgePower =
1610 min(twiceMaxEdgePower,
1611 twiceMinEdgePower);
1612 } else {
1613 twiceMaxEdgePower = twiceMinEdgePower;
1614 break;
1615 }
1616 }
1617 }
1618
1619 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
1620
1621 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1622 " SEL-Min ctlMode %d pCtlMode %d "
1623 "2xMaxEdge %d sP %d minCtlPwr %d\n",
1624 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
1625 scaledPower, minCtlPower);
1626
1627 switch (pCtlMode[ctlMode]) {
1628 case CTL_11B:
1629 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x);
1630 i++) {
1631 targetPowerCck.tPow2x[i] =
1632 min((u16)targetPowerCck.tPow2x[i],
1633 minCtlPower);
1634 }
1635 break;
1636 case CTL_11G:
1637 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
1638 i++) {
1639 targetPowerOfdm.tPow2x[i] =
1640 min((u16)targetPowerOfdm.tPow2x[i],
1641 minCtlPower);
1642 }
1643 break;
1644 case CTL_2GHT20:
1645 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x);
1646 i++) {
1647 targetPowerHt20.tPow2x[i] =
1648 min((u16)targetPowerHt20.tPow2x[i],
1649 minCtlPower);
1650 }
1651 break;
1652 case CTL_11B_EXT:
1653 targetPowerCckExt.tPow2x[0] = min((u16)
1654 targetPowerCckExt.tPow2x[0],
1655 minCtlPower);
1656 break;
1657 case CTL_11G_EXT:
1658 targetPowerOfdmExt.tPow2x[0] = min((u16)
1659 targetPowerOfdmExt.tPow2x[0],
1660 minCtlPower);
1661 break;
1662 case CTL_2GHT40:
1663 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x);
1664 i++) {
1665 targetPowerHt40.tPow2x[i] =
1666 min((u16)targetPowerHt40.tPow2x[i],
1667 minCtlPower);
1668 }
1669 break;
1670 default:
1671 break;
1672 }
1673 }
1674
1675 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1676 ratesArray[rate18mb] = ratesArray[rate24mb] =
1677 targetPowerOfdm.tPow2x[0];
1678 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1679 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1680 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1681 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1682
1683 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1684 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1685
1686 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1687 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
1688 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
1689 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
1690
1691 if (IS_CHAN_HT40(chan)) {
1692 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1693 ratesArray[rateHt40_0 + i] =
1694 targetPowerHt40.tPow2x[i];
1695 }
1696 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1697 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1698 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1699 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
1700 }
1701 return true;
1702 }
1703
1704 static int ath9k_hw_def_set_txpower(struct ath_hal *ah,
1705 struct ath9k_channel *chan,
1706 u16 cfgCtl,
1707 u8 twiceAntennaReduction,
1708 u8 twiceMaxRegulatoryPower,
1709 u8 powerLimit)
1710 {
1711 struct ath_hal_5416 *ahp = AH5416(ah);
1712 struct ar5416_eeprom_def *pEepData = &ahp->ah_eeprom.def;
1713 struct modal_eep_header *pModal =
1714 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1715 int16_t ratesArray[Ar5416RateSize];
1716 int16_t txPowerIndexOffset = 0;
1717 u8 ht40PowerIncForPdadc = 2;
1718 int i;
1719
1720 memset(ratesArray, 0, sizeof(ratesArray));
1721
1722 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1723 AR5416_EEP_MINOR_VER_2) {
1724 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1725 }
1726
1727 if (!ath9k_hw_set_def_power_per_rate_table(ah, chan,
1728 &ratesArray[0], cfgCtl,
1729 twiceAntennaReduction,
1730 twiceMaxRegulatoryPower,
1731 powerLimit)) {
1732 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1733 "ath9k_hw_set_txpower: unable to set "
1734 "tx power per rate table\n");
1735 return -EIO;
1736 }
1737
1738 if (!ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset)) {
1739 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1740 "ath9k_hw_set_txpower: unable to set power table\n");
1741 return -EIO;
1742 }
1743
1744 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1745 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1746 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1747 ratesArray[i] = AR5416_MAX_RATE_POWER;
1748 }
1749
1750 if (AR_SREV_9280_10_OR_LATER(ah)) {
1751 for (i = 0; i < Ar5416RateSize; i++)
1752 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
1753 }
1754
1755 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1756 ATH9K_POW_SM(ratesArray[rate18mb], 24)
1757 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1758 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1759 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1760 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1761 ATH9K_POW_SM(ratesArray[rate54mb], 24)
1762 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1763 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1764 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1765
1766 if (IS_CHAN_2GHZ(chan)) {
1767 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1768 ATH9K_POW_SM(ratesArray[rate2s], 24)
1769 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1770 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1771 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1772 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1773 ATH9K_POW_SM(ratesArray[rate11s], 24)
1774 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1775 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1776 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1777 }
1778
1779 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1780 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1781 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1782 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1783 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1784 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1785 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1786 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1787 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1788 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1789
1790 if (IS_CHAN_HT40(chan)) {
1791 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1792 ATH9K_POW_SM(ratesArray[rateHt40_3] +
1793 ht40PowerIncForPdadc, 24)
1794 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1795 ht40PowerIncForPdadc, 16)
1796 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1797 ht40PowerIncForPdadc, 8)
1798 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1799 ht40PowerIncForPdadc, 0));
1800 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1801 ATH9K_POW_SM(ratesArray[rateHt40_7] +
1802 ht40PowerIncForPdadc, 24)
1803 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1804 ht40PowerIncForPdadc, 16)
1805 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1806 ht40PowerIncForPdadc, 8)
1807 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1808 ht40PowerIncForPdadc, 0));
1809
1810 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1811 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1812 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1813 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1814 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1815 }
1816
1817 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1818 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1819 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1820
1821 i = rate6mb;
1822
1823 if (IS_CHAN_HT40(chan))
1824 i = rateHt40_0;
1825 else if (IS_CHAN_HT20(chan))
1826 i = rateHt20_0;
1827
1828 if (AR_SREV_9280_10_OR_LATER(ah))
1829 ah->ah_maxPowerLevel =
1830 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
1831 else
1832 ah->ah_maxPowerLevel = ratesArray[i];
1833
1834 return 0;
1835 }
1836
1837 static int ath9k_hw_4k_set_txpower(struct ath_hal *ah,
1838 struct ath9k_channel *chan,
1839 u16 cfgCtl,
1840 u8 twiceAntennaReduction,
1841 u8 twiceMaxRegulatoryPower,
1842 u8 powerLimit)
1843 {
1844 struct ath_hal_5416 *ahp = AH5416(ah);
1845 struct ar5416_eeprom_4k *pEepData = &ahp->ah_eeprom.map4k;
1846 struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
1847 int16_t ratesArray[Ar5416RateSize];
1848 int16_t txPowerIndexOffset = 0;
1849 u8 ht40PowerIncForPdadc = 2;
1850 int i;
1851
1852 memset(ratesArray, 0, sizeof(ratesArray));
1853
1854 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1855 AR5416_EEP_MINOR_VER_2) {
1856 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1857 }
1858
1859 if (!ath9k_hw_set_4k_power_per_rate_table(ah, chan,
1860 &ratesArray[0], cfgCtl,
1861 twiceAntennaReduction,
1862 twiceMaxRegulatoryPower,
1863 powerLimit)) {
1864 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1865 "ath9k_hw_set_txpower: unable to set "
1866 "tx power per rate table\n");
1867 return -EIO;
1868 }
1869
1870 if (!ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset)) {
1871 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1872 "ath9k_hw_set_txpower: unable to set power table\n");
1873 return -EIO;
1874 }
1875
1876 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1877 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1878 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1879 ratesArray[i] = AR5416_MAX_RATE_POWER;
1880 }
1881
1882 if (AR_SREV_9280_10_OR_LATER(ah)) {
1883 for (i = 0; i < Ar5416RateSize; i++)
1884 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
1885 }
1886
1887 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1888 ATH9K_POW_SM(ratesArray[rate18mb], 24)
1889 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1890 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1891 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1892 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1893 ATH9K_POW_SM(ratesArray[rate54mb], 24)
1894 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1895 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1896 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1897
1898 if (IS_CHAN_2GHZ(chan)) {
1899 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1900 ATH9K_POW_SM(ratesArray[rate2s], 24)
1901 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1902 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1903 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1904 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1905 ATH9K_POW_SM(ratesArray[rate11s], 24)
1906 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1907 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1908 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1909 }
1910
1911 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1912 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1913 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1914 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1915 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1916 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1917 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1918 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1919 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1920 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1921
1922 if (IS_CHAN_HT40(chan)) {
1923 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1924 ATH9K_POW_SM(ratesArray[rateHt40_3] +
1925 ht40PowerIncForPdadc, 24)
1926 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1927 ht40PowerIncForPdadc, 16)
1928 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1929 ht40PowerIncForPdadc, 8)
1930 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1931 ht40PowerIncForPdadc, 0));
1932 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1933 ATH9K_POW_SM(ratesArray[rateHt40_7] +
1934 ht40PowerIncForPdadc, 24)
1935 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1936 ht40PowerIncForPdadc, 16)
1937 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1938 ht40PowerIncForPdadc, 8)
1939 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1940 ht40PowerIncForPdadc, 0));
1941
1942 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1943 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1944 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1945 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1946 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1947 }
1948
1949 i = rate6mb;
1950
1951 if (IS_CHAN_HT40(chan))
1952 i = rateHt40_0;
1953 else if (IS_CHAN_HT20(chan))
1954 i = rateHt20_0;
1955
1956 if (AR_SREV_9280_10_OR_LATER(ah))
1957 ah->ah_maxPowerLevel =
1958 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
1959 else
1960 ah->ah_maxPowerLevel = ratesArray[i];
1961
1962 return 0;
1963 }
1964
1965 static int (*ath9k_set_txpower[]) (struct ath_hal *,
1966 struct ath9k_channel *,
1967 u16, u8, u8, u8) = {
1968 ath9k_hw_def_set_txpower,
1969 ath9k_hw_4k_set_txpower
1970 };
1971
1972 int ath9k_hw_set_txpower(struct ath_hal *ah,
1973 struct ath9k_channel *chan,
1974 u16 cfgCtl,
1975 u8 twiceAntennaReduction,
1976 u8 twiceMaxRegulatoryPower,
1977 u8 powerLimit)
1978 {
1979 struct ath_hal_5416 *ahp = AH5416(ah);
1980
1981 return ath9k_set_txpower[ahp->ah_eep_map](ah, chan, cfgCtl,
1982 twiceAntennaReduction, twiceMaxRegulatoryPower,
1983 powerLimit);
1984 }
1985
1986 static void ath9k_hw_set_def_addac(struct ath_hal *ah,
1987 struct ath9k_channel *chan)
1988 {
1989 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
1990 struct modal_eep_header *pModal;
1991 struct ath_hal_5416 *ahp = AH5416(ah);
1992 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
1993 u8 biaslevel;
1994
1995 if (ah->ah_macVersion != AR_SREV_VERSION_9160)
1996 return;
1997
1998 if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7)
1999 return;
2000
2001 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
2002
2003 if (pModal->xpaBiasLvl != 0xff) {
2004 biaslevel = pModal->xpaBiasLvl;
2005 } else {
2006 u16 resetFreqBin, freqBin, freqCount = 0;
2007 struct chan_centers centers;
2008
2009 ath9k_hw_get_channel_centers(ah, chan, &centers);
2010
2011 resetFreqBin = FREQ2FBIN(centers.synth_center,
2012 IS_CHAN_2GHZ(chan));
2013 freqBin = XPA_LVL_FREQ(0) & 0xff;
2014 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
2015
2016 freqCount++;
2017
2018 while (freqCount < 3) {
2019 if (XPA_LVL_FREQ(freqCount) == 0x0)
2020 break;
2021
2022 freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
2023 if (resetFreqBin >= freqBin)
2024 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
2025 else
2026 break;
2027 freqCount++;
2028 }
2029 }
2030
2031 if (IS_CHAN_2GHZ(chan)) {
2032 INI_RA(&ahp->ah_iniAddac, 7, 1) = (INI_RA(&ahp->ah_iniAddac,
2033 7, 1) & (~0x18)) | biaslevel << 3;
2034 } else {
2035 INI_RA(&ahp->ah_iniAddac, 6, 1) = (INI_RA(&ahp->ah_iniAddac,
2036 6, 1) & (~0xc0)) | biaslevel << 6;
2037 }
2038 #undef XPA_LVL_FREQ
2039 }
2040
2041 static void ath9k_hw_set_4k_addac(struct ath_hal *ah,
2042 struct ath9k_channel *chan)
2043 {
2044 struct modal_eep_4k_header *pModal;
2045 struct ath_hal_5416 *ahp = AH5416(ah);
2046 struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k;
2047 u8 biaslevel;
2048
2049 if (ah->ah_macVersion != AR_SREV_VERSION_9160)
2050 return;
2051
2052 if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7)
2053 return;
2054
2055 pModal = &eep->modalHeader;
2056
2057 if (pModal->xpaBiasLvl != 0xff) {
2058 biaslevel = pModal->xpaBiasLvl;
2059 INI_RA(&ahp->ah_iniAddac, 7, 1) =
2060 (INI_RA(&ahp->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
2061 }
2062 }
2063
2064 static void (*ath9k_set_addac[]) (struct ath_hal *, struct ath9k_channel *) = {
2065 ath9k_hw_set_def_addac,
2066 ath9k_hw_set_4k_addac
2067 };
2068
2069 void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan)
2070 {
2071 struct ath_hal_5416 *ahp = AH5416(ah);
2072
2073 ath9k_set_addac[ahp->ah_eep_map](ah, chan);
2074 }
2075
2076
2077
2078 /* XXX: Clean me up, make me more legible */
2079 static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hal *ah,
2080 struct ath9k_channel *chan)
2081 {
2082 #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
2083 struct modal_eep_header *pModal;
2084 struct ath_hal_5416 *ahp = AH5416(ah);
2085 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
2086 int i, regChainOffset;
2087 u8 txRxAttenLocal;
2088 u16 ant_config;
2089
2090 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
2091
2092 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
2093
2094 ath9k_hw_get_eeprom_antenna_cfg(ah, chan, 0, &ant_config);
2095 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
2096
2097 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
2098 if (AR_SREV_9280(ah)) {
2099 if (i >= 2)
2100 break;
2101 }
2102
2103 if (AR_SREV_5416_V20_OR_LATER(ah) &&
2104 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5)
2105 && (i != 0))
2106 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
2107 else
2108 regChainOffset = i * 0x1000;
2109
2110 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
2111 pModal->antCtrlChain[i]);
2112
2113 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
2114 (REG_READ(ah,
2115 AR_PHY_TIMING_CTRL4(0) +
2116 regChainOffset) &
2117 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
2118 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
2119 SM(pModal->iqCalICh[i],
2120 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
2121 SM(pModal->iqCalQCh[i],
2122 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
2123
2124 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
2125 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
2126 txRxAttenLocal = pModal->txRxAttenCh[i];
2127 if (AR_SREV_9280_10_OR_LATER(ah)) {
2128 REG_RMW_FIELD(ah,
2129 AR_PHY_GAIN_2GHZ +
2130 regChainOffset,
2131 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
2132 pModal->
2133 bswMargin[i]);
2134 REG_RMW_FIELD(ah,
2135 AR_PHY_GAIN_2GHZ +
2136 regChainOffset,
2137 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
2138 pModal->
2139 bswAtten[i]);
2140 REG_RMW_FIELD(ah,
2141 AR_PHY_GAIN_2GHZ +
2142 regChainOffset,
2143 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
2144 pModal->
2145 xatten2Margin[i]);
2146 REG_RMW_FIELD(ah,
2147 AR_PHY_GAIN_2GHZ +
2148 regChainOffset,
2149 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
2150 pModal->
2151 xatten2Db[i]);
2152 } else {
2153 REG_WRITE(ah,
2154 AR_PHY_GAIN_2GHZ +
2155 regChainOffset,
2156 (REG_READ(ah,
2157 AR_PHY_GAIN_2GHZ +
2158 regChainOffset) &
2159 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
2160 | SM(pModal->
2161 bswMargin[i],
2162 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
2163 REG_WRITE(ah,
2164 AR_PHY_GAIN_2GHZ +
2165 regChainOffset,
2166 (REG_READ(ah,
2167 AR_PHY_GAIN_2GHZ +
2168 regChainOffset) &
2169 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
2170 | SM(pModal->bswAtten[i],
2171 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
2172 }
2173 }
2174 if (AR_SREV_9280_10_OR_LATER(ah)) {
2175 REG_RMW_FIELD(ah,
2176 AR_PHY_RXGAIN +
2177 regChainOffset,
2178 AR9280_PHY_RXGAIN_TXRX_ATTEN,
2179 txRxAttenLocal);
2180 REG_RMW_FIELD(ah,
2181 AR_PHY_RXGAIN +
2182 regChainOffset,
2183 AR9280_PHY_RXGAIN_TXRX_MARGIN,
2184 pModal->rxTxMarginCh[i]);
2185 } else {
2186 REG_WRITE(ah,
2187 AR_PHY_RXGAIN + regChainOffset,
2188 (REG_READ(ah,
2189 AR_PHY_RXGAIN +
2190 regChainOffset) &
2191 ~AR_PHY_RXGAIN_TXRX_ATTEN) |
2192 SM(txRxAttenLocal,
2193 AR_PHY_RXGAIN_TXRX_ATTEN));
2194 REG_WRITE(ah,
2195 AR_PHY_GAIN_2GHZ +
2196 regChainOffset,
2197 (REG_READ(ah,
2198 AR_PHY_GAIN_2GHZ +
2199 regChainOffset) &
2200 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
2201 SM(pModal->rxTxMarginCh[i],
2202 AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
2203 }
2204 }
2205 }
2206
2207 if (AR_SREV_9280_10_OR_LATER(ah)) {
2208 if (IS_CHAN_2GHZ(chan)) {
2209 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
2210 AR_AN_RF2G1_CH0_OB,
2211 AR_AN_RF2G1_CH0_OB_S,
2212 pModal->ob);
2213 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
2214 AR_AN_RF2G1_CH0_DB,
2215 AR_AN_RF2G1_CH0_DB_S,
2216 pModal->db);
2217 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
2218 AR_AN_RF2G1_CH1_OB,
2219 AR_AN_RF2G1_CH1_OB_S,
2220 pModal->ob_ch1);
2221 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
2222 AR_AN_RF2G1_CH1_DB,
2223 AR_AN_RF2G1_CH1_DB_S,
2224 pModal->db_ch1);
2225 } else {
2226 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
2227 AR_AN_RF5G1_CH0_OB5,
2228 AR_AN_RF5G1_CH0_OB5_S,
2229 pModal->ob);
2230 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
2231 AR_AN_RF5G1_CH0_DB5,
2232 AR_AN_RF5G1_CH0_DB5_S,
2233 pModal->db);
2234 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
2235 AR_AN_RF5G1_CH1_OB5,
2236 AR_AN_RF5G1_CH1_OB5_S,
2237 pModal->ob_ch1);
2238 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
2239 AR_AN_RF5G1_CH1_DB5,
2240 AR_AN_RF5G1_CH1_DB5_S,
2241 pModal->db_ch1);
2242 }
2243 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
2244 AR_AN_TOP2_XPABIAS_LVL,
2245 AR_AN_TOP2_XPABIAS_LVL_S,
2246 pModal->xpaBiasLvl);
2247 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
2248 AR_AN_TOP2_LOCALBIAS,
2249 AR_AN_TOP2_LOCALBIAS_S,
2250 pModal->local_bias);
2251 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "ForceXPAon: %d\n",
2252 pModal->force_xpaon);
2253 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
2254 pModal->force_xpaon);
2255 }
2256
2257 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
2258 pModal->switchSettling);
2259 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
2260 pModal->adcDesiredSize);
2261
2262 if (!AR_SREV_9280_10_OR_LATER(ah))
2263 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
2264 AR_PHY_DESIRED_SZ_PGA,
2265 pModal->pgaDesiredSize);
2266
2267 REG_WRITE(ah, AR_PHY_RF_CTL4,
2268 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
2269 | SM(pModal->txEndToXpaOff,
2270 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
2271 | SM(pModal->txFrameToXpaOn,
2272 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
2273 | SM(pModal->txFrameToXpaOn,
2274 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
2275
2276 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
2277 pModal->txEndToRxOn);
2278 if (AR_SREV_9280_10_OR_LATER(ah)) {
2279 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
2280 pModal->thresh62);
2281 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
2282 AR_PHY_EXT_CCA0_THRESH62,
2283 pModal->thresh62);
2284 } else {
2285 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
2286 pModal->thresh62);
2287 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
2288 AR_PHY_EXT_CCA_THRESH62,
2289 pModal->thresh62);
2290 }
2291
2292 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
2293 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
2294 AR_PHY_TX_END_DATA_START,
2295 pModal->txFrameToDataStart);
2296 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
2297 pModal->txFrameToPaOn);
2298 }
2299
2300 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
2301 if (IS_CHAN_HT40(chan))
2302 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
2303 AR_PHY_SETTLING_SWITCH,
2304 pModal->swSettleHt40);
2305 }
2306
2307 if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
2308 if (IS_CHAN_HT20(chan))
2309 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
2310 eep->baseEepHeader.dacLpMode);
2311 else if (eep->baseEepHeader.dacHiPwrMode_5G)
2312 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
2313 else
2314 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
2315 eep->baseEepHeader.dacLpMode);
2316
2317 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
2318 pModal->miscBits >> 2);
2319 }
2320
2321 return true;
2322 #undef AR5416_VER_MASK
2323 }
2324
2325 static bool ath9k_hw_eeprom_set_4k_board_values(struct ath_hal *ah,
2326 struct ath9k_channel *chan)
2327 {
2328 struct modal_eep_4k_header *pModal;
2329 struct ath_hal_5416 *ahp = AH5416(ah);
2330 struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k;
2331 int regChainOffset;
2332 u8 txRxAttenLocal;
2333 u16 ant_config = 0;
2334 u8 ob[5], db1[5], db2[5];
2335 u8 ant_div_control1, ant_div_control2;
2336 u32 regVal;
2337
2338
2339 pModal = &eep->modalHeader;
2340
2341 txRxAttenLocal = 23;
2342
2343 ath9k_hw_get_eeprom_antenna_cfg(ah, chan, 0, &ant_config);
2344 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
2345
2346 regChainOffset = 0;
2347 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
2348 pModal->antCtrlChain[0]);
2349
2350 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
2351 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
2352 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
2353 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
2354 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
2355 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
2356
2357 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
2358 AR5416_EEP_MINOR_VER_3) {
2359 txRxAttenLocal = pModal->txRxAttenCh[0];
2360 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
2361 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
2362 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
2363 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
2364 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
2365 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
2366 pModal->xatten2Margin[0]);
2367 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
2368 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
2369 }
2370
2371 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
2372 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
2373 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
2374 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
2375
2376 if (AR_SREV_9285_11(ah))
2377 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
2378
2379 /* Initialize Ant Diversity settings from EEPROM */
2380 if (pModal->version == 3) {
2381 ant_div_control1 = ((pModal->ob_234 >> 12) & 0xf);
2382 ant_div_control2 = ((pModal->db1_234 >> 12) & 0xf);
2383 regVal = REG_READ(ah, 0x99ac);
2384 regVal &= (~(0x7f000000));
2385 regVal |= ((ant_div_control1 & 0x1) << 24);
2386 regVal |= (((ant_div_control1 >> 1) & 0x1) << 29);
2387 regVal |= (((ant_div_control1 >> 2) & 0x1) << 30);
2388 regVal |= ((ant_div_control2 & 0x3) << 25);
2389 regVal |= (((ant_div_control2 >> 2) & 0x3) << 27);
2390 REG_WRITE(ah, 0x99ac, regVal);
2391 regVal = REG_READ(ah, 0x99ac);
2392 regVal = REG_READ(ah, 0xa208);
2393 regVal &= (~(0x1 << 13));
2394 regVal |= (((ant_div_control1 >> 3) & 0x1) << 13);
2395 REG_WRITE(ah, 0xa208, regVal);
2396 regVal = REG_READ(ah, 0xa208);
2397 }
2398
2399 if (pModal->version >= 2) {
2400 ob[0] = (pModal->ob_01 & 0xf);
2401 ob[1] = (pModal->ob_01 >> 4) & 0xf;
2402 ob[2] = (pModal->ob_234 & 0xf);
2403 ob[3] = ((pModal->ob_234 >> 4) & 0xf);
2404 ob[4] = ((pModal->ob_234 >> 8) & 0xf);
2405
2406 db1[0] = (pModal->db1_01 & 0xf);
2407 db1[1] = ((pModal->db1_01 >> 4) & 0xf);
2408 db1[2] = (pModal->db1_234 & 0xf);
2409 db1[3] = ((pModal->db1_234 >> 4) & 0xf);
2410 db1[4] = ((pModal->db1_234 >> 8) & 0xf);
2411
2412 db2[0] = (pModal->db2_01 & 0xf);
2413 db2[1] = ((pModal->db2_01 >> 4) & 0xf);
2414 db2[2] = (pModal->db2_234 & 0xf);
2415 db2[3] = ((pModal->db2_234 >> 4) & 0xf);
2416 db2[4] = ((pModal->db2_234 >> 8) & 0xf);
2417
2418 } else if (pModal->version == 1) {
2419
2420 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2421 "EEPROM Model version is set to 1 \n");
2422 ob[0] = (pModal->ob_01 & 0xf);
2423 ob[1] = ob[2] = ob[3] = ob[4] = (pModal->ob_01 >> 4) & 0xf;
2424 db1[0] = (pModal->db1_01 & 0xf);
2425 db1[1] = db1[2] = db1[3] =
2426 db1[4] = ((pModal->db1_01 >> 4) & 0xf);
2427 db2[0] = (pModal->db2_01 & 0xf);
2428 db2[1] = db2[2] = db2[3] =
2429 db2[4] = ((pModal->db2_01 >> 4) & 0xf);
2430 } else {
2431 int i;
2432 for (i = 0; i < 5; i++) {
2433 ob[i] = pModal->ob_01;
2434 db1[i] = pModal->db1_01;
2435 db2[i] = pModal->db1_01;
2436 }
2437 }
2438
2439 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2440 AR9285_AN_RF2G3_OB_0, AR9285_AN_RF2G3_OB_0_S, ob[0]);
2441 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2442 AR9285_AN_RF2G3_OB_1, AR9285_AN_RF2G3_OB_1_S, ob[1]);
2443 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2444 AR9285_AN_RF2G3_OB_2, AR9285_AN_RF2G3_OB_2_S, ob[2]);
2445 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2446 AR9285_AN_RF2G3_OB_3, AR9285_AN_RF2G3_OB_3_S, ob[3]);
2447 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2448 AR9285_AN_RF2G3_OB_4, AR9285_AN_RF2G3_OB_4_S, ob[4]);
2449
2450 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2451 AR9285_AN_RF2G3_DB1_0, AR9285_AN_RF2G3_DB1_0_S, db1[0]);
2452 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2453 AR9285_AN_RF2G3_DB1_1, AR9285_AN_RF2G3_DB1_1_S, db1[1]);
2454 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2455 AR9285_AN_RF2G3_DB1_2, AR9285_AN_RF2G3_DB1_2_S, db1[2]);
2456 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2457 AR9285_AN_RF2G4_DB1_3, AR9285_AN_RF2G4_DB1_3_S, db1[3]);
2458 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2459 AR9285_AN_RF2G4_DB1_4, AR9285_AN_RF2G4_DB1_4_S, db1[4]);
2460
2461 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2462 AR9285_AN_RF2G4_DB2_0, AR9285_AN_RF2G4_DB2_0_S, db2[0]);
2463 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2464 AR9285_AN_RF2G4_DB2_1, AR9285_AN_RF2G4_DB2_1_S, db2[1]);
2465 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2466 AR9285_AN_RF2G4_DB2_2, AR9285_AN_RF2G4_DB2_2_S, db2[2]);
2467 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2468 AR9285_AN_RF2G4_DB2_3, AR9285_AN_RF2G4_DB2_3_S, db2[3]);
2469 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2470 AR9285_AN_RF2G4_DB2_4, AR9285_AN_RF2G4_DB2_4_S, db2[4]);
2471
2472
2473 if (AR_SREV_9285_11(ah))
2474 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
2475
2476 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
2477 pModal->switchSettling);
2478 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
2479 pModal->adcDesiredSize);
2480
2481 REG_WRITE(ah, AR_PHY_RF_CTL4,
2482 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
2483 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
2484 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) |
2485 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
2486
2487 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
2488 pModal->txEndToRxOn);
2489 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
2490 pModal->thresh62);
2491 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
2492 pModal->thresh62);
2493
2494 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
2495 AR5416_EEP_MINOR_VER_2) {
2496 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
2497 pModal->txFrameToDataStart);
2498 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
2499 pModal->txFrameToPaOn);
2500 }
2501
2502 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
2503 AR5416_EEP_MINOR_VER_3) {
2504 if (IS_CHAN_HT40(chan))
2505 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
2506 AR_PHY_SETTLING_SWITCH,
2507 pModal->swSettleHt40);
2508 }
2509
2510 return true;
2511 }
2512
2513 static bool (*ath9k_eeprom_set_board_values[])(struct ath_hal *,
2514 struct ath9k_channel *) = {
2515 ath9k_hw_eeprom_set_def_board_values,
2516 ath9k_hw_eeprom_set_4k_board_values
2517 };
2518
2519 bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
2520 struct ath9k_channel *chan)
2521 {
2522 struct ath_hal_5416 *ahp = AH5416(ah);
2523
2524 return ath9k_eeprom_set_board_values[ahp->ah_eep_map](ah, chan);
2525 }
2526
2527 static int ath9k_hw_get_def_eeprom_antenna_cfg(struct ath_hal *ah,
2528 struct ath9k_channel *chan,
2529 u8 index, u16 *config)
2530 {
2531 struct ath_hal_5416 *ahp = AH5416(ah);
2532 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
2533 struct modal_eep_header *pModal =
2534 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
2535 struct base_eep_header *pBase = &eep->baseEepHeader;
2536
2537 switch (index) {
2538 case 0:
2539 *config = pModal->antCtrlCommon & 0xFFFF;
2540 return 0;
2541 case 1:
2542 if (pBase->version >= 0x0E0D) {
2543 if (pModal->useAnt1) {
2544 *config =
2545 ((pModal->antCtrlCommon & 0xFFFF0000) >> 16);
2546 return 0;
2547 }
2548 }
2549 break;
2550 default:
2551 break;
2552 }
2553
2554 return -EINVAL;
2555 }
2556
2557 static int ath9k_hw_get_4k_eeprom_antenna_cfg(struct ath_hal *ah,
2558 struct ath9k_channel *chan,
2559 u8 index, u16 *config)
2560 {
2561 struct ath_hal_5416 *ahp = AH5416(ah);
2562 struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k;
2563 struct modal_eep_4k_header *pModal = &eep->modalHeader;
2564
2565 switch (index) {
2566 case 0:
2567 *config = pModal->antCtrlCommon & 0xFFFF;
2568 return 0;
2569 default:
2570 break;
2571 }
2572
2573 return -EINVAL;
2574 }
2575
2576 static int (*ath9k_get_eeprom_antenna_cfg[])(struct ath_hal *,
2577 struct ath9k_channel *,
2578 u8, u16 *) = {
2579 ath9k_hw_get_def_eeprom_antenna_cfg,
2580 ath9k_hw_get_4k_eeprom_antenna_cfg
2581 };
2582
2583 int ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah,
2584 struct ath9k_channel *chan,
2585 u8 index, u16 *config)
2586 {
2587 struct ath_hal_5416 *ahp = AH5416(ah);
2588
2589 return ath9k_get_eeprom_antenna_cfg[ahp->ah_eep_map](ah, chan,
2590 index, config);
2591 }
2592
2593 static u8 ath9k_hw_get_4k_num_ant_config(struct ath_hal *ah,
2594 enum ieee80211_band freq_band)
2595 {
2596 return 1;
2597 }
2598
2599 static u8 ath9k_hw_get_def_num_ant_config(struct ath_hal *ah,
2600 enum ieee80211_band freq_band)
2601 {
2602 struct ath_hal_5416 *ahp = AH5416(ah);
2603 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
2604 struct modal_eep_header *pModal =
2605 &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]);
2606 struct base_eep_header *pBase = &eep->baseEepHeader;
2607 u8 num_ant_config;
2608
2609 num_ant_config = 1;
2610
2611 if (pBase->version >= 0x0E0D)
2612 if (pModal->useAnt1)
2613 num_ant_config += 1;
2614
2615 return num_ant_config;
2616 }
2617
2618 static u8 (*ath9k_get_num_ant_config[])(struct ath_hal *,
2619 enum ieee80211_band) = {
2620 ath9k_hw_get_def_num_ant_config,
2621 ath9k_hw_get_4k_num_ant_config
2622 };
2623
2624 u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah,
2625 enum ieee80211_band freq_band)
2626 {
2627 struct ath_hal_5416 *ahp = AH5416(ah);
2628
2629 return ath9k_get_num_ant_config[ahp->ah_eep_map](ah, freq_band);
2630 }
2631
2632 u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz)
2633 {
2634 #define EEP_MAP4K_SPURCHAN \
2635 (ahp->ah_eeprom.map4k.modalHeader.spurChans[i].spurChan)
2636 #define EEP_DEF_SPURCHAN \
2637 (ahp->ah_eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
2638 struct ath_hal_5416 *ahp = AH5416(ah);
2639 u16 spur_val = AR_NO_SPUR;
2640
2641 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2642 "Getting spur idx %d is2Ghz. %d val %x\n",
2643 i, is2GHz, ah->ah_config.spurchans[i][is2GHz]);
2644
2645 switch (ah->ah_config.spurmode) {
2646 case SPUR_DISABLE:
2647 break;
2648 case SPUR_ENABLE_IOCTL:
2649 spur_val = ah->ah_config.spurchans[i][is2GHz];
2650 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2651 "Getting spur val from new loc. %d\n", spur_val);
2652 break;
2653 case SPUR_ENABLE_EEPROM:
2654 if (ahp->ah_eep_map == EEP_MAP_4KBITS)
2655 spur_val = EEP_MAP4K_SPURCHAN;
2656 else
2657 spur_val = EEP_DEF_SPURCHAN;
2658 break;
2659
2660 }
2661
2662 return spur_val;
2663 #undef EEP_DEF_SPURCHAN
2664 #undef EEP_MAP4K_SPURCHAN
2665 }
2666
2667 static u32 ath9k_hw_get_eeprom_4k(struct ath_hal *ah,
2668 enum eeprom_param param)
2669 {
2670 struct ath_hal_5416 *ahp = AH5416(ah);
2671 struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k;
2672 struct modal_eep_4k_header *pModal = &eep->modalHeader;
2673 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
2674
2675 switch (param) {
2676 case EEP_NFTHRESH_2:
2677 return pModal[1].noiseFloorThreshCh[0];
2678 case AR_EEPROM_MAC(0):
2679 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
2680 case AR_EEPROM_MAC(1):
2681 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
2682 case AR_EEPROM_MAC(2):
2683 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
2684 case EEP_REG_0:
2685 return pBase->regDmn[0];
2686 case EEP_REG_1:
2687 return pBase->regDmn[1];
2688 case EEP_OP_CAP:
2689 return pBase->deviceCap;
2690 case EEP_OP_MODE:
2691 return pBase->opCapFlags;
2692 case EEP_RF_SILENT:
2693 return pBase->rfSilent;
2694 case EEP_OB_2:
2695 return pModal->ob_01;
2696 case EEP_DB_2:
2697 return pModal->db1_01;
2698 case EEP_MINOR_REV:
2699 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
2700 case EEP_TX_MASK:
2701 return pBase->txMask;
2702 case EEP_RX_MASK:
2703 return pBase->rxMask;
2704 default:
2705 return 0;
2706 }
2707 }
2708
2709 static u32 ath9k_hw_get_eeprom_def(struct ath_hal *ah,
2710 enum eeprom_param param)
2711 {
2712 #define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK)
2713 struct ath_hal_5416 *ahp = AH5416(ah);
2714 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
2715 struct modal_eep_header *pModal = eep->modalHeader;
2716 struct base_eep_header *pBase = &eep->baseEepHeader;
2717
2718 switch (param) {
2719 case EEP_NFTHRESH_5:
2720 return pModal[0].noiseFloorThreshCh[0];
2721 case EEP_NFTHRESH_2:
2722 return pModal[1].noiseFloorThreshCh[0];
2723 case AR_EEPROM_MAC(0):
2724 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
2725 case AR_EEPROM_MAC(1):
2726 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
2727 case AR_EEPROM_MAC(2):
2728 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
2729 case EEP_REG_0:
2730 return pBase->regDmn[0];
2731 case EEP_REG_1:
2732 return pBase->regDmn[1];
2733 case EEP_OP_CAP:
2734 return pBase->deviceCap;
2735 case EEP_OP_MODE:
2736 return pBase->opCapFlags;
2737 case EEP_RF_SILENT:
2738 return pBase->rfSilent;
2739 case EEP_OB_5:
2740 return pModal[0].ob;
2741 case EEP_DB_5:
2742 return pModal[0].db;
2743 case EEP_OB_2:
2744 return pModal[1].ob;
2745 case EEP_DB_2:
2746 return pModal[1].db;
2747 case EEP_MINOR_REV:
2748 return AR5416_VER_MASK;
2749 case EEP_TX_MASK:
2750 return pBase->txMask;
2751 case EEP_RX_MASK:
2752 return pBase->rxMask;
2753 case EEP_RXGAIN_TYPE:
2754 return pBase->rxGainType;
2755 case EEP_TXGAIN_TYPE:
2756 return pBase->txGainType;
2757 case EEP_DAC_HPWR_5G:
2758 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
2759 return pBase->dacHiPwrMode_5G;
2760 else
2761 return 0;
2762 default:
2763 return 0;
2764 }
2765 #undef AR5416_VER_MASK
2766 }
2767
2768 static u32 (*ath9k_get_eeprom[])(struct ath_hal *, enum eeprom_param) = {
2769 ath9k_hw_get_eeprom_def,
2770 ath9k_hw_get_eeprom_4k
2771 };
2772
2773 u32 ath9k_hw_get_eeprom(struct ath_hal *ah,
2774 enum eeprom_param param)
2775 {
2776 struct ath_hal_5416 *ahp = AH5416(ah);
2777
2778 return ath9k_get_eeprom[ahp->ah_eep_map](ah, param);
2779 }
2780
2781 int ath9k_hw_eeprom_attach(struct ath_hal *ah)
2782 {
2783 int status;
2784 struct ath_hal_5416 *ahp = AH5416(ah);
2785
2786 if (AR_SREV_9285(ah))
2787 ahp->ah_eep_map = EEP_MAP_4KBITS;
2788 else
2789 ahp->ah_eep_map = EEP_MAP_DEFAULT;
2790
2791 if (!ath9k_hw_fill_eeprom(ah))
2792 return -EIO;
2793
2794 status = ath9k_hw_check_eeprom(ah);
2795
2796 return status;
2797 }
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