arch/arm/plat-samsung/irq-vic-timer.c

   1 /* arch/arm/plat-samsung/irq-vic-timer.c
   2  *      originally part of arch/arm/plat-s3c64xx/irq.c
   3  *
   4  * Copyright 2008 Openmoko, Inc.
   5  * Copyright 2008 Simtec Electronics
   6  *      Ben Dooks <ben@simtec.co.uk>
   7  *      http://armlinux.simtec.co.uk/
   8  *
   9  * S3C64XX - Interrupt handling
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/irq.h>
  19 #include <linux/io.h>
  20
  21 #include <mach/map.h>
  22 #include <plat/cpu.h>
  23 #include <plat/irq-vic-timer.h>
  24 #include <plat/regs-timer.h>
  25
  26 #include <asm/mach/irq.h>
  27
  28 static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
  29 {
  30         struct irq_chip *chip = irq_get_chip(irq);
  31         chained_irq_enter(chip, desc);
  32         generic_handle_irq((int)desc->irq_data.handler_data);
  33         chained_irq_exit(chip, desc);
  34 }
  35
  36 /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
  37 static void s3c_irq_timer_ack(struct irq_data *d)
  38 {
  39         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  40         u32 mask = (1 << 5) << (d->irq - gc->irq_base);
  41
  42         irq_reg_writel(mask | gc->mask_cache, gc->reg_base);
  43 }
  44
  45 /**
  46  * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\
  47  * @num: Number of timers to initialize
  48  * @timer_irq: Base IRQ number to be used for the timers.
  49  *
  50  * Register the necessary IRQ chaining and support for the timer IRQs
  51  * chained of the VIC.
  52  */
  53 void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq)
  54 {
  55         unsigned int pirq[5] = { IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
  56                                  IRQ_TIMER3_VIC, IRQ_TIMER4_VIC };
  57         struct irq_chip_generic *s3c_tgc;
  58         struct irq_chip_type *ct;
  59         unsigned int i;
  60
  61 #ifdef CONFIG_ARCH_EXYNOS
  62         if (soc_is_exynos5250()) {
  63                 pirq[0] = EXYNOS5_IRQ_TIMER0_VIC;
  64                 pirq[1] = EXYNOS5_IRQ_TIMER1_VIC;
  65                 pirq[2] = EXYNOS5_IRQ_TIMER2_VIC;
  66                 pirq[3] = EXYNOS5_IRQ_TIMER3_VIC;
  67                 pirq[4] = EXYNOS5_IRQ_TIMER4_VIC;
  68         } else {
  69                 pirq[0] = EXYNOS4_IRQ_TIMER0_VIC;
  70                 pirq[1] = EXYNOS4_IRQ_TIMER1_VIC;
  71                 pirq[2] = EXYNOS4_IRQ_TIMER2_VIC;
  72                 pirq[3] = EXYNOS4_IRQ_TIMER3_VIC;
  73                 pirq[4] = EXYNOS4_IRQ_TIMER4_VIC;
  74         }
  75 #endif
  76         s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq,
  77                                          S3C64XX_TINT_CSTAT, handle_level_irq);
  78
  79         if (!s3c_tgc) {
  80                 pr_err("%s: irq_alloc_generic_chip for IRQ %d failed\n",
  81                        __func__, timer_irq);
  82                 return;
  83         }
  84
  85         ct = s3c_tgc->chip_types;
  86         ct->chip.irq_mask = irq_gc_mask_clr_bit;
  87         ct->chip.irq_unmask = irq_gc_mask_set_bit;
  88         ct->chip.irq_ack = s3c_irq_timer_ack;
  89         irq_setup_generic_chip(s3c_tgc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
  90                                IRQ_NOREQUEST | IRQ_NOPROBE, 0);
  91         /* Clear the upper bits of the mask_cache*/
  92         s3c_tgc->mask_cache &= 0x1f;
  93
  94         for (i = 0; i < num; i++, timer_irq++) {
  95                 irq_set_chained_handler(pirq[i], s3c_irq_demux_vic_timer);
  96                 irq_set_handler_data(pirq[i], (void *)timer_irq);
  97         }
  98 }