2 * linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon
4 * Heavily based on proc-arm926.S
5 * Maintainer: Assaf Hoffman <hoffman@marvell.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/linkage.h>
23 #include <linux/init.h>
24 #include <asm/assembler.h>
25 #include <asm/hwcap.h>
26 #include <asm/pgtable-hwdef.h>
27 #include <asm/pgtable.h>
29 #include <asm/ptrace.h>
30 #include "proc-macros.S"
33 * This is the maximum size of an area which will be invalidated
34 * using the single invalidate entry instructions. Anything larger
35 * than this, and we go for the whole cache.
37 * This value should be chosen such that we choose the cheapest
40 #define CACHE_DLIMIT 16384
43 * the cache line size of the I and D cache
45 #define CACHE_DLINESIZE 32
54 .word __cache_params_loc
57 * cpu_feroceon_proc_init()
59 ENTRY(cpu_feroceon_proc_init)
60 mrc p15, 0, r0, c0, c0, 1 @ read cache type register
61 ldr r1, __cache_params
63 tst r0, #(1 << 16) @ get way
64 mov r0, r0, lsr #18 @ get cache size order
65 movne r3, #((4 - 1) << 30) @ 4-way
68 mov r2, r2, lsl r0 @ actual cache size
69 movne r2, r2, lsr #2 @ turned into # of sets
75 * cpu_feroceon_proc_fin()
77 ENTRY(cpu_feroceon_proc_fin)
78 #if defined(CONFIG_CACHE_FEROCEON_L2) && \
79 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
81 mcr p15, 1, r0, c15, c9, 0 @ clean L2
82 mcr p15, 0, r0, c7, c10, 4 @ drain WB
85 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
86 bic r0, r0, #0x1000 @ ...i............
87 bic r0, r0, #0x000e @ ............wca.
88 mcr p15, 0, r0, c1, c0, 0 @ disable caches
92 * cpu_feroceon_reset(loc)
94 * Perform a soft reset of the system. Put the CPU into the
95 * same state as it would be if it had been reset, and branch
96 * to what would be the reset vector.
98 * loc: location to jump to for soft reset
101 ENTRY(cpu_feroceon_reset)
103 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
104 mcr p15, 0, ip, c7, c10, 4 @ drain WB
106 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
108 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
109 bic ip, ip, #0x000f @ ............wcam
110 bic ip, ip, #0x1100 @ ...i...s........
111 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
115 * cpu_feroceon_do_idle()
117 * Called with IRQs disabled
120 ENTRY(cpu_feroceon_do_idle)
122 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
123 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
127 * flush_user_cache_all()
129 * Clean and invalidate all cache entries in a particular
133 ENTRY(feroceon_flush_user_cache_all)
137 * flush_kern_cache_all()
139 * Clean and invalidate the entire cache.
141 ENTRY(feroceon_flush_kern_cache_all)
145 ldr r1, __cache_params
148 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
149 subs ip, ip, #(1 << 30) @ next way
151 subs r1, r1, #(1 << 5) @ next set
156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
157 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
161 * flush_user_cache_range(start, end, flags)
163 * Clean and invalidate a range of cache entries in the
164 * specified address range.
166 * - start - start address (inclusive)
167 * - end - end address (exclusive)
168 * - flags - vm_flags describing address space
171 ENTRY(feroceon_flush_user_cache_range)
172 sub r3, r1, r0 @ calculate total size
173 cmp r3, #CACHE_DLIMIT
174 bgt __flush_whole_cache
176 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
177 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
178 add r0, r0, #CACHE_DLINESIZE
179 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
180 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
181 add r0, r0, #CACHE_DLINESIZE
186 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
190 * coherent_kern_range(start, end)
192 * Ensure coherency between the Icache and the Dcache in the
193 * region described by start, end. If you have non-snooping
194 * Harvard caches, you need to implement this function.
196 * - start - virtual start address
197 * - end - virtual end address
200 ENTRY(feroceon_coherent_kern_range)
204 * coherent_user_range(start, end)
206 * Ensure coherency between the Icache and the Dcache in the
207 * region described by start, end. If you have non-snooping
208 * Harvard caches, you need to implement this function.
210 * - start - virtual start address
211 * - end - virtual end address
213 ENTRY(feroceon_coherent_user_range)
214 bic r0, r0, #CACHE_DLINESIZE - 1
215 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
216 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
217 add r0, r0, #CACHE_DLINESIZE
220 mcr p15, 0, r0, c7, c10, 4 @ drain WB
224 * flush_kern_dcache_area(void *addr, size_t size)
226 * Ensure no D cache aliasing occurs, either with itself or
229 * - addr - kernel address
230 * - size - region size
233 ENTRY(feroceon_flush_kern_dcache_area)
235 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
236 add r0, r0, #CACHE_DLINESIZE
240 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
241 mcr p15, 0, r0, c7, c10, 4 @ drain WB
245 ENTRY(feroceon_range_flush_kern_dcache_area)
247 add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive
248 orr r3, r2, #PSR_I_BIT
249 msr cpsr_c, r3 @ disable interrupts
250 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
251 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
252 msr cpsr_c, r2 @ restore interrupts
254 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
255 mcr p15, 0, r0, c7, c10, 4 @ drain WB
259 * dma_inv_range(start, end)
261 * Invalidate (discard) the specified virtual address range.
262 * May not write back any entries. If 'start' or 'end'
263 * are not cache line aligned, those lines must be written
266 * - start - virtual start address
267 * - end - virtual end address
272 feroceon_dma_inv_range:
273 tst r0, #CACHE_DLINESIZE - 1
274 bic r0, r0, #CACHE_DLINESIZE - 1
275 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
276 tst r1, #CACHE_DLINESIZE - 1
277 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
278 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
279 add r0, r0, #CACHE_DLINESIZE
282 mcr p15, 0, r0, c7, c10, 4 @ drain WB
286 feroceon_range_dma_inv_range:
288 tst r0, #CACHE_DLINESIZE - 1
289 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
290 tst r1, #CACHE_DLINESIZE - 1
291 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
293 subne r1, r1, #1 @ top address is inclusive
294 orr r3, r2, #PSR_I_BIT
295 msr cpsr_c, r3 @ disable interrupts
296 mcr p15, 5, r0, c15, c14, 0 @ D inv range start
297 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
298 msr cpsr_c, r2 @ restore interrupts
302 * dma_clean_range(start, end)
304 * Clean the specified virtual address range.
306 * - start - virtual start address
307 * - end - virtual end address
312 feroceon_dma_clean_range:
313 bic r0, r0, #CACHE_DLINESIZE - 1
314 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
315 add r0, r0, #CACHE_DLINESIZE
318 mcr p15, 0, r0, c7, c10, 4 @ drain WB
322 feroceon_range_dma_clean_range:
325 subne r1, r1, #1 @ top address is inclusive
326 orr r3, r2, #PSR_I_BIT
327 msr cpsr_c, r3 @ disable interrupts
328 mcr p15, 5, r0, c15, c13, 0 @ D clean range start
329 mcr p15, 5, r1, c15, c13, 1 @ D clean range top
330 msr cpsr_c, r2 @ restore interrupts
331 mcr p15, 0, r0, c7, c10, 4 @ drain WB
335 * dma_flush_range(start, end)
337 * Clean and invalidate the specified virtual address range.
339 * - start - virtual start address
340 * - end - virtual end address
343 ENTRY(feroceon_dma_flush_range)
344 bic r0, r0, #CACHE_DLINESIZE - 1
345 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
346 add r0, r0, #CACHE_DLINESIZE
349 mcr p15, 0, r0, c7, c10, 4 @ drain WB
353 ENTRY(feroceon_range_dma_flush_range)
356 subne r1, r1, #1 @ top address is inclusive
357 orr r3, r2, #PSR_I_BIT
358 msr cpsr_c, r3 @ disable interrupts
359 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
360 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
361 msr cpsr_c, r2 @ restore interrupts
362 mcr p15, 0, r0, c7, c10, 4 @ drain WB
366 * dma_map_area(start, size, dir)
367 * - start - kernel virtual start address
368 * - size - size of region
369 * - dir - DMA direction
371 ENTRY(feroceon_dma_map_area)
373 cmp r2, #DMA_TO_DEVICE
374 beq feroceon_dma_clean_range
375 bcs feroceon_dma_inv_range
376 b feroceon_dma_flush_range
377 ENDPROC(feroceon_dma_map_area)
380 * dma_map_area(start, size, dir)
381 * - start - kernel virtual start address
382 * - size - size of region
383 * - dir - DMA direction
385 ENTRY(feroceon_range_dma_map_area)
387 cmp r2, #DMA_TO_DEVICE
388 beq feroceon_range_dma_clean_range
389 bcs feroceon_range_dma_inv_range
390 b feroceon_range_dma_flush_range
391 ENDPROC(feroceon_range_dma_map_area)
394 * dma_unmap_area(start, size, dir)
395 * - start - kernel virtual start address
396 * - size - size of region
397 * - dir - DMA direction
399 ENTRY(feroceon_dma_unmap_area)
401 ENDPROC(feroceon_dma_unmap_area)
403 ENTRY(feroceon_cache_fns)
404 .long feroceon_flush_kern_cache_all
405 .long feroceon_flush_user_cache_all
406 .long feroceon_flush_user_cache_range
407 .long feroceon_coherent_kern_range
408 .long feroceon_coherent_user_range
409 .long feroceon_flush_kern_dcache_area
410 .long feroceon_dma_map_area
411 .long feroceon_dma_unmap_area
412 .long feroceon_dma_flush_range
414 ENTRY(feroceon_range_cache_fns)
415 .long feroceon_flush_kern_cache_all
416 .long feroceon_flush_user_cache_all
417 .long feroceon_flush_user_cache_range
418 .long feroceon_coherent_kern_range
419 .long feroceon_coherent_user_range
420 .long feroceon_range_flush_kern_dcache_area
421 .long feroceon_range_dma_map_area
422 .long feroceon_dma_unmap_area
423 .long feroceon_range_dma_flush_range
426 ENTRY(cpu_feroceon_dcache_clean_area)
427 #if defined(CONFIG_CACHE_FEROCEON_L2) && \
428 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
432 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
433 add r0, r0, #CACHE_DLINESIZE
434 subs r1, r1, #CACHE_DLINESIZE
436 #if defined(CONFIG_CACHE_FEROCEON_L2) && \
437 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
438 1: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry
439 add r2, r2, #CACHE_DLINESIZE
440 subs r3, r3, #CACHE_DLINESIZE
443 mcr p15, 0, r0, c7, c10, 4 @ drain WB
446 /* =============================== PageTable ============================== */
449 * cpu_feroceon_switch_mm(pgd)
451 * Set the translation base pointer to be as described by pgd.
453 * pgd: new page tables
456 ENTRY(cpu_feroceon_switch_mm)
459 * Note: we wish to call __flush_whole_cache but we need to preserve
460 * lr to do so. The only way without touching main memory is to
461 * use r2 which is normally used to test the VM_EXEC flag, and
462 * compensate locally for the skipped ops if it is not set.
464 mov r2, lr @ abuse r2 to preserve lr
465 bl __flush_whole_cache
466 @ if r2 contains the VM_EXEC bit then the next 2 ops are done already
468 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
469 mcreq p15, 0, ip, c7, c10, 4 @ drain WB
471 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
472 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
479 * cpu_feroceon_set_pte_ext(ptep, pte, ext)
481 * Set a PTE and flush it out
484 ENTRY(cpu_feroceon_set_pte_ext)
486 armv3_set_pte_ext wc_disable=0
488 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
489 #if defined(CONFIG_CACHE_FEROCEON_L2) && \
490 !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
491 mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry
493 mcr p15, 0, r0, c7, c10, 4 @ drain WB
499 .type __feroceon_setup, #function
502 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
503 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
505 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
508 adr r5, feroceon_crval
510 mrc p15, 0, r0, c1, c0 @ get control register v4
514 .size __feroceon_setup, . - __feroceon_setup
519 * .RVI UFRS BLDP WCAM
520 * .011 .001 ..11 0101
523 .type feroceon_crval, #object
525 crval clear=0x0000773f, mmuset=0x00003135, ucset=0x00001134
530 * Purpose : Function pointers used to access above functions - all calls
533 .type feroceon_processor_functions, #object
534 feroceon_processor_functions:
535 .word v5t_early_abort
537 .word cpu_feroceon_proc_init
538 .word cpu_feroceon_proc_fin
539 .word cpu_feroceon_reset
540 .word cpu_feroceon_do_idle
541 .word cpu_feroceon_dcache_clean_area
542 .word cpu_feroceon_switch_mm
543 .word cpu_feroceon_set_pte_ext
544 .size feroceon_processor_functions, . - feroceon_processor_functions
548 .type cpu_arch_name, #object
551 .size cpu_arch_name, . - cpu_arch_name
553 .type cpu_elf_name, #object
556 .size cpu_elf_name, . - cpu_elf_name
558 .type cpu_feroceon_name, #object
561 .size cpu_feroceon_name, . - cpu_feroceon_name
563 .type cpu_88fr531_name, #object
565 .asciz "Feroceon 88FR531-vd"
566 .size cpu_88fr531_name, . - cpu_88fr531_name
568 .type cpu_88fr571_name, #object
570 .asciz "Feroceon 88FR571-vd"
571 .size cpu_88fr571_name, . - cpu_88fr571_name
573 .type cpu_88fr131_name, #object
575 .asciz "Feroceon 88FR131"
576 .size cpu_88fr131_name, . - cpu_88fr131_name
580 .section ".proc.info.init", #alloc, #execinstr
582 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
583 .type __feroceon_old_id_proc_info,#object
584 __feroceon_old_id_proc_info:
587 .long PMD_TYPE_SECT | \
588 PMD_SECT_BUFFERABLE | \
589 PMD_SECT_CACHEABLE | \
591 PMD_SECT_AP_WRITE | \
593 .long PMD_TYPE_SECT | \
595 PMD_SECT_AP_WRITE | \
600 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
601 .long cpu_feroceon_name
602 .long feroceon_processor_functions
604 .long feroceon_user_fns
605 .long feroceon_cache_fns
606 .size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
609 .type __88fr531_proc_info,#object
613 .long PMD_TYPE_SECT | \
614 PMD_SECT_BUFFERABLE | \
615 PMD_SECT_CACHEABLE | \
617 PMD_SECT_AP_WRITE | \
619 .long PMD_TYPE_SECT | \
621 PMD_SECT_AP_WRITE | \
626 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
627 .long cpu_88fr531_name
628 .long feroceon_processor_functions
630 .long feroceon_user_fns
631 .long feroceon_cache_fns
632 .size __88fr531_proc_info, . - __88fr531_proc_info
634 .type __88fr571_proc_info,#object
638 .long PMD_TYPE_SECT | \
639 PMD_SECT_BUFFERABLE | \
640 PMD_SECT_CACHEABLE | \
642 PMD_SECT_AP_WRITE | \
644 .long PMD_TYPE_SECT | \
646 PMD_SECT_AP_WRITE | \
651 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
652 .long cpu_88fr571_name
653 .long feroceon_processor_functions
655 .long feroceon_user_fns
656 .long feroceon_range_cache_fns
657 .size __88fr571_proc_info, . - __88fr571_proc_info
659 .type __88fr131_proc_info,#object
663 .long PMD_TYPE_SECT | \
664 PMD_SECT_BUFFERABLE | \
665 PMD_SECT_CACHEABLE | \
667 PMD_SECT_AP_WRITE | \
669 .long PMD_TYPE_SECT | \
671 PMD_SECT_AP_WRITE | \
676 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
677 .long cpu_88fr131_name
678 .long feroceon_processor_functions
680 .long feroceon_user_fns
681 .long feroceon_range_cache_fns
682 .size __88fr131_proc_info, . - __88fr131_proc_info