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ARM: socfpga: Enable SMP for socfpga
[linux-2.6.git] / drivers / usb / otg / twl4030-usb.c
blobf0d2e7530cfea4ecb01bdec31411de4afd1e7097
1 /*
2 * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
3 *
4 * Copyright (C) 2004-2007 Texas Instruments
5 * Copyright (C) 2008 Nokia Corporation
6 * Contact: Felipe Balbi <felipe.balbi@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Current status:
23 * - HS USB ULPI mode works.
24 * - 3-pin mode support may be added in future.
25 */
26
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/platform_device.h>
31 #include <linux/spinlock.h>
32 #include <linux/workqueue.h>
33 #include <linux/io.h>
34 #include <linux/delay.h>
35 #include <linux/usb/otg.h>
36 #include <linux/usb/musb-omap.h>
37 #include <linux/usb/ulpi.h>
38 #include <linux/i2c/twl.h>
39 #include <linux/regulator/consumer.h>
40 #include <linux/err.h>
41 #include <linux/slab.h>
42
43 /* Register defines */
44
45 #define MCPC_CTRL 0x30
46 #define MCPC_CTRL_RTSOL (1 << 7)
47 #define MCPC_CTRL_EXTSWR (1 << 6)
48 #define MCPC_CTRL_EXTSWC (1 << 5)
49 #define MCPC_CTRL_VOICESW (1 << 4)
50 #define MCPC_CTRL_OUT64K (1 << 3)
51 #define MCPC_CTRL_RTSCTSSW (1 << 2)
52 #define MCPC_CTRL_HS_UART (1 << 0)
53
54 #define MCPC_IO_CTRL 0x33
55 #define MCPC_IO_CTRL_MICBIASEN (1 << 5)
56 #define MCPC_IO_CTRL_CTS_NPU (1 << 4)
57 #define MCPC_IO_CTRL_RXD_PU (1 << 3)
58 #define MCPC_IO_CTRL_TXDTYP (1 << 2)
59 #define MCPC_IO_CTRL_CTSTYP (1 << 1)
60 #define MCPC_IO_CTRL_RTSTYP (1 << 0)
61
62 #define MCPC_CTRL2 0x36
63 #define MCPC_CTRL2_MCPC_CK_EN (1 << 0)
64
65 #define OTHER_FUNC_CTRL 0x80
66 #define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4)
67 #define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2)
68
69 #define OTHER_IFC_CTRL 0x83
70 #define OTHER_IFC_CTRL_OE_INT_EN (1 << 6)
71 #define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5)
72 #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4)
73 #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT (1 << 3)
74 #define OTHER_IFC_CTRL_HIZ_ULPI (1 << 2)
75 #define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0)
76
77 #define OTHER_INT_EN_RISE 0x86
78 #define OTHER_INT_EN_FALL 0x89
79 #define OTHER_INT_STS 0x8C
80 #define OTHER_INT_LATCH 0x8D
81 #define OTHER_INT_VB_SESS_VLD (1 << 7)
82 #define OTHER_INT_DM_HI (1 << 6) /* not valid for "latch" reg */
83 #define OTHER_INT_DP_HI (1 << 5) /* not valid for "latch" reg */
84 #define OTHER_INT_BDIS_ACON (1 << 3) /* not valid for "fall" regs */
85 #define OTHER_INT_MANU (1 << 1)
86 #define OTHER_INT_ABNORMAL_STRESS (1 << 0)
87
88 #define ID_STATUS 0x96
89 #define ID_RES_FLOAT (1 << 4)
90 #define ID_RES_440K (1 << 3)
91 #define ID_RES_200K (1 << 2)
92 #define ID_RES_102K (1 << 1)
93 #define ID_RES_GND (1 << 0)
94
95 #define POWER_CTRL 0xAC
96 #define POWER_CTRL_OTG_ENAB (1 << 5)
97
98 #define OTHER_IFC_CTRL2 0xAF
99 #define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4)
100 #define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3)
101 #define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2)
102 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK (3 << 0) /* bits 0 and 1 */
103 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N (0 << 0)
104 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0)
105
106 #define REG_CTRL_EN 0xB2
107 #define REG_CTRL_ERROR 0xB5
108 #define ULPI_I2C_CONFLICT_INTEN (1 << 0)
109
110 #define OTHER_FUNC_CTRL2 0xB8
111 #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0)
112
113 /* following registers do not have separate _clr and _set registers */
114 #define VBUS_DEBOUNCE 0xC0
115 #define ID_DEBOUNCE 0xC1
116 #define VBAT_TIMER 0xD3
117 #define PHY_PWR_CTRL 0xFD
118 #define PHY_PWR_PHYPWD (1 << 0)
119 #define PHY_CLK_CTRL 0xFE
120 #define PHY_CLK_CTRL_CLOCKGATING_EN (1 << 2)
121 #define PHY_CLK_CTRL_CLK32K_EN (1 << 1)
122 #define REQ_PHY_DPLL_CLK (1 << 0)
123 #define PHY_CLK_CTRL_STS 0xFF
124 #define PHY_DPLL_CLK (1 << 0)
125
126 /* In module TWL4030_MODULE_PM_MASTER */
127 #define STS_HW_CONDITIONS 0x0F
128
129 /* In module TWL4030_MODULE_PM_RECEIVER */
130 #define VUSB_DEDICATED1 0x7D
131 #define VUSB_DEDICATED2 0x7E
132 #define VUSB1V5_DEV_GRP 0x71
133 #define VUSB1V5_TYPE 0x72
134 #define VUSB1V5_REMAP 0x73
135 #define VUSB1V8_DEV_GRP 0x74
136 #define VUSB1V8_TYPE 0x75
137 #define VUSB1V8_REMAP 0x76
138 #define VUSB3V1_DEV_GRP 0x77
139 #define VUSB3V1_TYPE 0x78
140 #define VUSB3V1_REMAP 0x79
141
142 /* In module TWL4030_MODULE_INTBR */
143 #define PMBR1 0x0D
144 #define GPIO_USB_4PIN_ULPI_2430C (3 << 0)
145
146 struct twl4030_usb {
147 struct usb_phy phy;
148 struct device *dev;
149
150 /* TWL4030 internal USB regulator supplies */
151 struct regulator *usb1v5;
152 struct regulator *usb1v8;
153 struct regulator *usb3v1;
154
155 /* for vbus reporting with irqs disabled */
156 spinlock_t lock;
157
158 /* pin configuration */
159 enum twl4030_usb_mode usb_mode;
160
161 int irq;
162 enum omap_musb_vbus_id_status linkstat;
163 bool vbus_supplied;
164 u8 asleep;
165 bool irq_enabled;
166 };
167
168 /* internal define on top of container_of */
169 #define phy_to_twl(x) container_of((x), struct twl4030_usb, phy)
170
171 /*-------------------------------------------------------------------------*/
172
173 static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
174 u8 module, u8 data, u8 address)
175 {
176 u8 check;
177
178 if ((twl_i2c_write_u8(module, data, address) >= 0) &&
179 (twl_i2c_read_u8(module, &check, address) >= 0) &&
180 (check == data))
181 return 0;
182 dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
183 1, module, address, check, data);
184
185 /* Failed once: Try again */
186 if ((twl_i2c_write_u8(module, data, address) >= 0) &&
187 (twl_i2c_read_u8(module, &check, address) >= 0) &&
188 (check == data))
189 return 0;
190 dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
191 2, module, address, check, data);
192
193 /* Failed again: Return error */
194 return -EBUSY;
195 }
196
197 #define twl4030_usb_write_verify(twl, address, data) \
198 twl4030_i2c_write_u8_verify(twl, TWL4030_MODULE_USB, (data), (address))
199
200 static inline int twl4030_usb_write(struct twl4030_usb *twl,
201 u8 address, u8 data)
202 {
203 int ret = 0;
204
205 ret = twl_i2c_write_u8(TWL4030_MODULE_USB, data, address);
206 if (ret < 0)
207 dev_dbg(twl->dev,
208 "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
209 return ret;
210 }
211
212 static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
213 {
214 u8 data;
215 int ret = 0;
216
217 ret = twl_i2c_read_u8(module, &data, address);
218 if (ret >= 0)
219 ret = data;
220 else
221 dev_dbg(twl->dev,
222 "TWL4030:readb[0x%x,0x%x] Error %d\n",
223 module, address, ret);
224
225 return ret;
226 }
227
228 static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
229 {
230 return twl4030_readb(twl, TWL4030_MODULE_USB, address);
231 }
232
233 /*-------------------------------------------------------------------------*/
234
235 static inline int
236 twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
237 {
238 return twl4030_usb_write(twl, ULPI_SET(reg), bits);
239 }
240
241 static inline int
242 twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
243 {
244 return twl4030_usb_write(twl, ULPI_CLR(reg), bits);
245 }
246
247 /*-------------------------------------------------------------------------*/
248
249 static enum omap_musb_vbus_id_status
250 twl4030_usb_linkstat(struct twl4030_usb *twl)
251 {
252 int status;
253 enum omap_musb_vbus_id_status linkstat = OMAP_MUSB_UNKNOWN;
254
255 twl->vbus_supplied = false;
256
257 /*
258 * For ID/VBUS sensing, see manual section 15.4.8 ...
259 * except when using only battery backup power, two
260 * comparators produce VBUS_PRES and ID_PRES signals,
261 * which don't match docs elsewhere. But ... BIT(7)
262 * and BIT(2) of STS_HW_CONDITIONS, respectively, do
263 * seem to match up. If either is true the USB_PRES
264 * signal is active, the OTG module is activated, and
265 * its interrupt may be raised (may wake the system).
266 */
267 status = twl4030_readb(twl, TWL4030_MODULE_PM_MASTER,
268 STS_HW_CONDITIONS);
269 if (status < 0)
270 dev_err(twl->dev, "USB link status err %d\n", status);
271 else if (status & (BIT(7) | BIT(2))) {
272 if (status & (BIT(7)))
273 twl->vbus_supplied = true;
274
275 if (status & BIT(2))
276 linkstat = OMAP_MUSB_ID_GROUND;
277 else
278 linkstat = OMAP_MUSB_VBUS_VALID;
279 } else {
280 if (twl->linkstat != OMAP_MUSB_UNKNOWN)
281 linkstat = OMAP_MUSB_VBUS_OFF;
282 }
283
284 dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
285 status, status, linkstat);
286
287 /* REVISIT this assumes host and peripheral controllers
288 * are registered, and that both are active...
289 */
290
291 spin_lock_irq(&twl->lock);
292 twl->linkstat = linkstat;
293 spin_unlock_irq(&twl->lock);
294
295 return linkstat;
296 }
297
298 static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
299 {
300 twl->usb_mode = mode;
301
302 switch (mode) {
303 case T2_USB_MODE_ULPI:
304 twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL,
305 ULPI_IFC_CTRL_CARKITMODE);
306 twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
307 twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL,
308 ULPI_FUNC_CTRL_XCVRSEL_MASK |
309 ULPI_FUNC_CTRL_OPMODE_MASK);
310 break;
311 case -1:
312 /* FIXME: power on defaults */
313 break;
314 default:
315 dev_err(twl->dev, "unsupported T2 transceiver mode %d\n",
316 mode);
317 break;
318 };
319 }
320
321 static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
322 {
323 unsigned long timeout;
324 int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
325
326 if (val >= 0) {
327 if (on) {
328 /* enable DPLL to access PHY registers over I2C */
329 val |= REQ_PHY_DPLL_CLK;
330 WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
331 (u8)val) < 0);
332
333 timeout = jiffies + HZ;
334 while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
335 PHY_DPLL_CLK)
336 && time_before(jiffies, timeout))
337 udelay(10);
338 if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
339 PHY_DPLL_CLK))
340 dev_err(twl->dev, "Timeout setting T2 HSUSB "
341 "PHY DPLL clock\n");
342 } else {
343 /* let ULPI control the DPLL clock */
344 val &= ~REQ_PHY_DPLL_CLK;
345 WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
346 (u8)val) < 0);
347 }
348 }
349 }
350
351 static void __twl4030_phy_power(struct twl4030_usb *twl, int on)
352 {
353 u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
354
355 if (on)
356 pwr &= ~PHY_PWR_PHYPWD;
357 else
358 pwr |= PHY_PWR_PHYPWD;
359
360 WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
361 }
362
363 static void twl4030_phy_power(struct twl4030_usb *twl, int on)
364 {
365 if (on) {
366 regulator_enable(twl->usb3v1);
367 regulator_enable(twl->usb1v8);
368 /*
369 * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
370 * in twl4030) resets the VUSB_DEDICATED2 register. This reset
371 * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
372 * SLEEP. We work around this by clearing the bit after usv3v1
373 * is re-activated. This ensures that VUSB3V1 is really active.
374 */
375 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0,
376 VUSB_DEDICATED2);
377 regulator_enable(twl->usb1v5);
378 __twl4030_phy_power(twl, 1);
379 twl4030_usb_write(twl, PHY_CLK_CTRL,
380 twl4030_usb_read(twl, PHY_CLK_CTRL) |
381 (PHY_CLK_CTRL_CLOCKGATING_EN |
382 PHY_CLK_CTRL_CLK32K_EN));
383 } else {
384 __twl4030_phy_power(twl, 0);
385 regulator_disable(twl->usb1v5);
386 regulator_disable(twl->usb1v8);
387 regulator_disable(twl->usb3v1);
388 }
389 }
390
391 static void twl4030_phy_suspend(struct twl4030_usb *twl, int controller_off)
392 {
393 if (twl->asleep)
394 return;
395
396 twl4030_phy_power(twl, 0);
397 twl->asleep = 1;
398 dev_dbg(twl->dev, "%s\n", __func__);
399 }
400
401 static void __twl4030_phy_resume(struct twl4030_usb *twl)
402 {
403 twl4030_phy_power(twl, 1);
404 twl4030_i2c_access(twl, 1);
405 twl4030_usb_set_mode(twl, twl->usb_mode);
406 if (twl->usb_mode == T2_USB_MODE_ULPI)
407 twl4030_i2c_access(twl, 0);
408 }
409
410 static void twl4030_phy_resume(struct twl4030_usb *twl)
411 {
412 if (!twl->asleep)
413 return;
414 __twl4030_phy_resume(twl);
415 twl->asleep = 0;
416 dev_dbg(twl->dev, "%s\n", __func__);
417 }
418
419 static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
420 {
421 /* Enable writing to power configuration registers */
422 twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER,
423 TWL4030_PM_MASTER_KEY_CFG1,
424 TWL4030_PM_MASTER_PROTECT_KEY);
425
426 twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER,
427 TWL4030_PM_MASTER_KEY_CFG2,
428 TWL4030_PM_MASTER_PROTECT_KEY);
429
430 /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/
431 /*twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/
432
433 /* input to VUSB3V1 LDO is from VBAT, not VBUS */
434 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
435
436 /* Initialize 3.1V regulator */
437 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP);
438
439 twl->usb3v1 = regulator_get(twl->dev, "usb3v1");
440 if (IS_ERR(twl->usb3v1))
441 return -ENODEV;
442
443 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
444
445 /* Initialize 1.5V regulator */
446 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP);
447
448 twl->usb1v5 = regulator_get(twl->dev, "usb1v5");
449 if (IS_ERR(twl->usb1v5))
450 goto fail1;
451
452 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
453
454 /* Initialize 1.8V regulator */
455 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP);
456
457 twl->usb1v8 = regulator_get(twl->dev, "usb1v8");
458 if (IS_ERR(twl->usb1v8))
459 goto fail2;
460
461 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
462
463 /* disable access to power configuration registers */
464 twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0,
465 TWL4030_PM_MASTER_PROTECT_KEY);
466
467 return 0;
468
469 fail2:
470 regulator_put(twl->usb1v5);
471 twl->usb1v5 = NULL;
472 fail1:
473 regulator_put(twl->usb3v1);
474 twl->usb3v1 = NULL;
475 return -ENODEV;
476 }
477
478 static ssize_t twl4030_usb_vbus_show(struct device *dev,
479 struct device_attribute *attr, char *buf)
480 {
481 struct twl4030_usb *twl = dev_get_drvdata(dev);
482 unsigned long flags;
483 int ret = -EINVAL;
484
485 spin_lock_irqsave(&twl->lock, flags);
486 ret = sprintf(buf, "%s\n",
487 twl->vbus_supplied ? "on" : "off");
488 spin_unlock_irqrestore(&twl->lock, flags);
489
490 return ret;
491 }
492 static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
493
494 static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
495 {
496 struct twl4030_usb *twl = _twl;
497 enum omap_musb_vbus_id_status status;
498
499 status = twl4030_usb_linkstat(twl);
500 if (status > 0) {
501 /* FIXME add a set_power() method so that B-devices can
502 * configure the charger appropriately. It's not always
503 * correct to consume VBUS power, and how much current to
504 * consume is a function of the USB configuration chosen
505 * by the host.
506 *
507 * REVISIT usb_gadget_vbus_connect(...) as needed, ditto
508 * its disconnect() sibling, when changing to/from the
509 * USB_LINK_VBUS state. musb_hdrc won't care until it
510 * starts to handle softconnect right.
511 */
512 if (status == OMAP_MUSB_VBUS_OFF ||
513 status == OMAP_MUSB_ID_FLOAT)
514 twl4030_phy_suspend(twl, 0);
515 else
516 twl4030_phy_resume(twl);
517
518 omap_musb_mailbox(twl->linkstat);
519 }
520 sysfs_notify(&twl->dev->kobj, NULL, "vbus");
521
522 return IRQ_HANDLED;
523 }
524
525 static void twl4030_usb_phy_init(struct twl4030_usb *twl)
526 {
527 enum omap_musb_vbus_id_status status;
528
529 status = twl4030_usb_linkstat(twl);
530 if (status > 0) {
531 if (status == OMAP_MUSB_VBUS_OFF ||
532 status == OMAP_MUSB_ID_FLOAT) {
533 __twl4030_phy_power(twl, 0);
534 twl->asleep = 1;
535 } else {
536 __twl4030_phy_resume(twl);
537 twl->asleep = 0;
538 }
539
540 omap_musb_mailbox(twl->linkstat);
541 }
542 sysfs_notify(&twl->dev->kobj, NULL, "vbus");
543 }
544
545 static int twl4030_set_suspend(struct usb_phy *x, int suspend)
546 {
547 struct twl4030_usb *twl = phy_to_twl(x);
548
549 if (suspend)
550 twl4030_phy_suspend(twl, 1);
551 else
552 twl4030_phy_resume(twl);
553
554 return 0;
555 }
556
557 static int twl4030_set_peripheral(struct usb_otg *otg,
558 struct usb_gadget *gadget)
559 {
560 if (!otg)
561 return -ENODEV;
562
563 otg->gadget = gadget;
564 if (!gadget)
565 otg->phy->state = OTG_STATE_UNDEFINED;
566
567 return 0;
568 }
569
570 static int twl4030_set_host(struct usb_otg *otg, struct usb_bus *host)
571 {
572 if (!otg)
573 return -ENODEV;
574
575 otg->host = host;
576 if (!host)
577 otg->phy->state = OTG_STATE_UNDEFINED;
578
579 return 0;
580 }
581
582 static int __devinit twl4030_usb_probe(struct platform_device *pdev)
583 {
584 struct twl4030_usb_data *pdata = pdev->dev.platform_data;
585 struct twl4030_usb *twl;
586 int status, err;
587 struct usb_otg *otg;
588 struct device_node *np = pdev->dev.of_node;
589
590 twl = devm_kzalloc(&pdev->dev, sizeof *twl, GFP_KERNEL);
591 if (!twl)
592 return -ENOMEM;
593
594 if (np)
595 of_property_read_u32(np, "usb_mode",
596 (enum twl4030_usb_mode *)&twl->usb_mode);
597 else if (pdata)
598 twl->usb_mode = pdata->usb_mode;
599 else {
600 dev_err(&pdev->dev, "twl4030 initialized without pdata\n");
601 return -EINVAL;
602 }
603
604 otg = devm_kzalloc(&pdev->dev, sizeof *otg, GFP_KERNEL);
605 if (!otg)
606 return -ENOMEM;
607
608 twl->dev = &pdev->dev;
609 twl->irq = platform_get_irq(pdev, 0);
610 twl->vbus_supplied = false;
611 twl->asleep = 1;
612 twl->linkstat = OMAP_MUSB_UNKNOWN;
613
614 twl->phy.dev = twl->dev;
615 twl->phy.label = "twl4030";
616 twl->phy.otg = otg;
617 twl->phy.set_suspend = twl4030_set_suspend;
618
619 otg->phy = &twl->phy;
620 otg->set_host = twl4030_set_host;
621 otg->set_peripheral = twl4030_set_peripheral;
622
623 /* init spinlock for workqueue */
624 spin_lock_init(&twl->lock);
625
626 err = twl4030_usb_ldo_init(twl);
627 if (err) {
628 dev_err(&pdev->dev, "ldo init failed\n");
629 return err;
630 }
631 usb_add_phy(&twl->phy, USB_PHY_TYPE_USB2);
632
633 platform_set_drvdata(pdev, twl);
634 if (device_create_file(&pdev->dev, &dev_attr_vbus))
635 dev_warn(&pdev->dev, "could not create sysfs file\n");
636
637 /* Our job is to use irqs and status from the power module
638 * to keep the transceiver disabled when nothing's connected.
639 *
640 * FIXME we actually shouldn't start enabling it until the
641 * USB controller drivers have said they're ready, by calling
642 * set_host() and/or set_peripheral() ... OTG_capable boards
643 * need both handles, otherwise just one suffices.
644 */
645 twl->irq_enabled = true;
646 status = request_threaded_irq(twl->irq, NULL, twl4030_usb_irq,
647 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
648 IRQF_ONESHOT, "twl4030_usb", twl);
649 if (status < 0) {
650 dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
651 twl->irq, status);
652 return status;
653 }
654
655 /* Power down phy or make it work according to
656 * current link state.
657 */
658 twl4030_usb_phy_init(twl);
659
660 dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
661 return 0;
662 }
663
664 static int __exit twl4030_usb_remove(struct platform_device *pdev)
665 {
666 struct twl4030_usb *twl = platform_get_drvdata(pdev);
667 int val;
668
669 free_irq(twl->irq, twl);
670 device_remove_file(twl->dev, &dev_attr_vbus);
671
672 /* set transceiver mode to power on defaults */
673 twl4030_usb_set_mode(twl, -1);
674
675 /* autogate 60MHz ULPI clock,
676 * clear dpll clock request for i2c access,
677 * disable 32KHz
678 */
679 val = twl4030_usb_read(twl, PHY_CLK_CTRL);
680 if (val >= 0) {
681 val |= PHY_CLK_CTRL_CLOCKGATING_EN;
682 val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
683 twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
684 }
685
686 /* disable complete OTG block */
687 twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
688
689 if (!twl->asleep)
690 twl4030_phy_power(twl, 0);
691 regulator_put(twl->usb1v5);
692 regulator_put(twl->usb1v8);
693 regulator_put(twl->usb3v1);
694
695 return 0;
696 }
697
698 #ifdef CONFIG_OF
699 static const struct of_device_id twl4030_usb_id_table[] = {
700 { .compatible = "ti,twl4030-usb" },
701 {}
702 };
703 MODULE_DEVICE_TABLE(of, twl4030_usb_id_table);
704 #endif
705
706 static struct platform_driver twl4030_usb_driver = {
707 .probe = twl4030_usb_probe,
708 .remove = __exit_p(twl4030_usb_remove),
709 .driver = {
710 .name = "twl4030_usb",
711 .owner = THIS_MODULE,
712 .of_match_table = of_match_ptr(twl4030_usb_id_table),
713 },
714 };
715
716 static int __init twl4030_usb_init(void)
717 {
718 return platform_driver_register(&twl4030_usb_driver);
719 }
720 subsys_initcall(twl4030_usb_init);
721
722 static void __exit twl4030_usb_exit(void)
723 {
724 platform_driver_unregister(&twl4030_usb_driver);
725 }
726 module_exit(twl4030_usb_exit);
727
728 MODULE_ALIAS("platform:twl4030_usb");
729 MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
730 MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
731 MODULE_LICENSE("GPL");
Linus' kernel tree