1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
32 #include <linux/types.h>
33 #include <linux/slab.h>
34 #include <linux/if_ether.h>
36 #include "e1000_mac.h"
37 #include "e1000_82575.h"
39 static s32
igb_get_invariants_82575(struct e1000_hw
*);
40 static s32
igb_acquire_phy_82575(struct e1000_hw
*);
41 static void igb_release_phy_82575(struct e1000_hw
*);
42 static s32
igb_acquire_nvm_82575(struct e1000_hw
*);
43 static void igb_release_nvm_82575(struct e1000_hw
*);
44 static s32
igb_check_for_link_82575(struct e1000_hw
*);
45 static s32
igb_get_cfg_done_82575(struct e1000_hw
*);
46 static s32
igb_init_hw_82575(struct e1000_hw
*);
47 static s32
igb_phy_hw_reset_sgmii_82575(struct e1000_hw
*);
48 static s32
igb_read_phy_reg_sgmii_82575(struct e1000_hw
*, u32
, u16
*);
49 static s32
igb_read_phy_reg_82580(struct e1000_hw
*, u32
, u16
*);
50 static s32
igb_write_phy_reg_82580(struct e1000_hw
*, u32
, u16
);
51 static s32
igb_reset_hw_82575(struct e1000_hw
*);
52 static s32
igb_reset_hw_82580(struct e1000_hw
*);
53 static s32
igb_set_d0_lplu_state_82575(struct e1000_hw
*, bool);
54 static s32
igb_setup_copper_link_82575(struct e1000_hw
*);
55 static s32
igb_setup_serdes_link_82575(struct e1000_hw
*);
56 static s32
igb_write_phy_reg_sgmii_82575(struct e1000_hw
*, u32
, u16
);
57 static void igb_clear_hw_cntrs_82575(struct e1000_hw
*);
58 static s32
igb_acquire_swfw_sync_82575(struct e1000_hw
*, u16
);
59 static s32
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw
*, u16
*,
61 static s32
igb_get_phy_id_82575(struct e1000_hw
*);
62 static void igb_release_swfw_sync_82575(struct e1000_hw
*, u16
);
63 static bool igb_sgmii_active_82575(struct e1000_hw
*);
64 static s32
igb_reset_init_script_82575(struct e1000_hw
*);
65 static s32
igb_read_mac_addr_82575(struct e1000_hw
*);
66 static s32
igb_set_pcie_completion_timeout(struct e1000_hw
*hw
);
68 static const u16 e1000_82580_rxpbs_table
[] =
69 { 36, 72, 144, 1, 2, 4, 8, 16,
71 #define E1000_82580_RXPBS_TABLE_SIZE \
72 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
74 static s32
igb_get_invariants_82575(struct e1000_hw
*hw
)
76 struct e1000_phy_info
*phy
= &hw
->phy
;
77 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
78 struct e1000_mac_info
*mac
= &hw
->mac
;
79 struct e1000_dev_spec_82575
* dev_spec
= &hw
->dev_spec
._82575
;
85 switch (hw
->device_id
) {
86 case E1000_DEV_ID_82575EB_COPPER
:
87 case E1000_DEV_ID_82575EB_FIBER_SERDES
:
88 case E1000_DEV_ID_82575GB_QUAD_COPPER
:
89 mac
->type
= e1000_82575
;
91 case E1000_DEV_ID_82576
:
92 case E1000_DEV_ID_82576_NS
:
93 case E1000_DEV_ID_82576_NS_SERDES
:
94 case E1000_DEV_ID_82576_FIBER
:
95 case E1000_DEV_ID_82576_SERDES
:
96 case E1000_DEV_ID_82576_QUAD_COPPER
:
97 case E1000_DEV_ID_82576_SERDES_QUAD
:
98 mac
->type
= e1000_82576
;
100 case E1000_DEV_ID_82580_COPPER
:
101 case E1000_DEV_ID_82580_FIBER
:
102 case E1000_DEV_ID_82580_SERDES
:
103 case E1000_DEV_ID_82580_SGMII
:
104 case E1000_DEV_ID_82580_COPPER_DUAL
:
105 mac
->type
= e1000_82580
;
108 return -E1000_ERR_MAC_INIT
;
114 * The 82575 uses bits 22:23 for link mode. The mode can be changed
115 * based on the EEPROM. We cannot rely upon device ID. There
116 * is no distinguishable difference between fiber and internal
117 * SerDes mode on the 82575. There can be an external PHY attached
118 * on the SGMII interface. For this, we'll set sgmii_active to true.
120 phy
->media_type
= e1000_media_type_copper
;
121 dev_spec
->sgmii_active
= false;
123 ctrl_ext
= rd32(E1000_CTRL_EXT
);
124 switch (ctrl_ext
& E1000_CTRL_EXT_LINK_MODE_MASK
) {
125 case E1000_CTRL_EXT_LINK_MODE_SGMII
:
126 dev_spec
->sgmii_active
= true;
127 ctrl_ext
|= E1000_CTRL_I2C_ENA
;
129 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX
:
130 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES
:
131 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
132 ctrl_ext
|= E1000_CTRL_I2C_ENA
;
135 ctrl_ext
&= ~E1000_CTRL_I2C_ENA
;
139 wr32(E1000_CTRL_EXT
, ctrl_ext
);
142 * if using i2c make certain the MDICNFG register is cleared to prevent
143 * communications from being misrouted to the mdic registers
145 if ((ctrl_ext
& E1000_CTRL_I2C_ENA
) && (hw
->mac
.type
== e1000_82580
))
146 wr32(E1000_MDICNFG
, 0);
148 /* Set mta register count */
149 mac
->mta_reg_count
= 128;
150 /* Set rar entry count */
151 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82575
;
152 if (mac
->type
== e1000_82576
)
153 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82576
;
154 if (mac
->type
== e1000_82580
)
155 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82580
;
157 if (mac
->type
== e1000_82580
)
158 mac
->ops
.reset_hw
= igb_reset_hw_82580
;
160 mac
->ops
.reset_hw
= igb_reset_hw_82575
;
161 /* Set if part includes ASF firmware */
162 mac
->asf_firmware_present
= true;
163 /* Set if manageability features are enabled. */
164 mac
->arc_subsystem_valid
=
165 (rd32(E1000_FWSM
) & E1000_FWSM_MODE_MASK
)
168 /* physical interface link setup */
169 mac
->ops
.setup_physical_interface
=
170 (hw
->phy
.media_type
== e1000_media_type_copper
)
171 ? igb_setup_copper_link_82575
172 : igb_setup_serdes_link_82575
;
174 /* NVM initialization */
175 eecd
= rd32(E1000_EECD
);
177 nvm
->opcode_bits
= 8;
179 switch (nvm
->override
) {
180 case e1000_nvm_override_spi_large
:
182 nvm
->address_bits
= 16;
184 case e1000_nvm_override_spi_small
:
186 nvm
->address_bits
= 8;
189 nvm
->page_size
= eecd
& E1000_EECD_ADDR_BITS
? 32 : 8;
190 nvm
->address_bits
= eecd
& E1000_EECD_ADDR_BITS
? 16 : 8;
194 nvm
->type
= e1000_nvm_eeprom_spi
;
196 size
= (u16
)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
197 E1000_EECD_SIZE_EX_SHIFT
);
200 * Added to a constant, "size" becomes the left-shift value
201 * for setting word_size.
203 size
+= NVM_WORD_SIZE_BASE_SHIFT
;
205 /* EEPROM access above 16k is unsupported */
208 nvm
->word_size
= 1 << size
;
210 /* if 82576 then initialize mailbox parameters */
211 if (mac
->type
== e1000_82576
)
212 igb_init_mbx_params_pf(hw
);
214 /* setup PHY parameters */
215 if (phy
->media_type
!= e1000_media_type_copper
) {
216 phy
->type
= e1000_phy_none
;
220 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
221 phy
->reset_delay_us
= 100;
223 /* PHY function pointers */
224 if (igb_sgmii_active_82575(hw
)) {
225 phy
->ops
.reset
= igb_phy_hw_reset_sgmii_82575
;
226 phy
->ops
.read_reg
= igb_read_phy_reg_sgmii_82575
;
227 phy
->ops
.write_reg
= igb_write_phy_reg_sgmii_82575
;
228 } else if (hw
->mac
.type
== e1000_82580
) {
229 phy
->ops
.reset
= igb_phy_hw_reset
;
230 phy
->ops
.read_reg
= igb_read_phy_reg_82580
;
231 phy
->ops
.write_reg
= igb_write_phy_reg_82580
;
233 phy
->ops
.reset
= igb_phy_hw_reset
;
234 phy
->ops
.read_reg
= igb_read_phy_reg_igp
;
235 phy
->ops
.write_reg
= igb_write_phy_reg_igp
;
239 hw
->bus
.func
= (rd32(E1000_STATUS
) & E1000_STATUS_FUNC_MASK
) >>
240 E1000_STATUS_FUNC_SHIFT
;
242 /* Set phy->phy_addr and phy->id. */
243 ret_val
= igb_get_phy_id_82575(hw
);
247 /* Verify phy id and set remaining function pointers */
249 case M88E1111_I_PHY_ID
:
250 phy
->type
= e1000_phy_m88
;
251 phy
->ops
.get_phy_info
= igb_get_phy_info_m88
;
252 phy
->ops
.get_cable_length
= igb_get_cable_length_m88
;
253 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_m88
;
255 case IGP03E1000_E_PHY_ID
:
256 phy
->type
= e1000_phy_igp_3
;
257 phy
->ops
.get_phy_info
= igb_get_phy_info_igp
;
258 phy
->ops
.get_cable_length
= igb_get_cable_length_igp_2
;
259 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_igp
;
260 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82575
;
261 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state
;
263 case I82580_I_PHY_ID
:
264 phy
->type
= e1000_phy_82580
;
265 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_82580
;
266 phy
->ops
.get_cable_length
= igb_get_cable_length_82580
;
267 phy
->ops
.get_phy_info
= igb_get_phy_info_82580
;
270 return -E1000_ERR_PHY
;
277 * igb_acquire_phy_82575 - Acquire rights to access PHY
278 * @hw: pointer to the HW structure
280 * Acquire access rights to the correct PHY. This is a
281 * function pointer entry point called by the api module.
283 static s32
igb_acquire_phy_82575(struct e1000_hw
*hw
)
285 u16 mask
= E1000_SWFW_PHY0_SM
;
287 if (hw
->bus
.func
== E1000_FUNC_1
)
288 mask
= E1000_SWFW_PHY1_SM
;
290 return igb_acquire_swfw_sync_82575(hw
, mask
);
294 * igb_release_phy_82575 - Release rights to access PHY
295 * @hw: pointer to the HW structure
297 * A wrapper to release access rights to the correct PHY. This is a
298 * function pointer entry point called by the api module.
300 static void igb_release_phy_82575(struct e1000_hw
*hw
)
302 u16 mask
= E1000_SWFW_PHY0_SM
;
304 if (hw
->bus
.func
== E1000_FUNC_1
)
305 mask
= E1000_SWFW_PHY1_SM
;
307 igb_release_swfw_sync_82575(hw
, mask
);
311 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
312 * @hw: pointer to the HW structure
313 * @offset: register offset to be read
314 * @data: pointer to the read data
316 * Reads the PHY register at offset using the serial gigabit media independent
317 * interface and stores the retrieved information in data.
319 static s32
igb_read_phy_reg_sgmii_82575(struct e1000_hw
*hw
, u32 offset
,
322 s32 ret_val
= -E1000_ERR_PARAM
;
324 if (offset
> E1000_MAX_SGMII_PHY_REG_ADDR
) {
325 hw_dbg("PHY Address %u is out of range\n", offset
);
329 ret_val
= hw
->phy
.ops
.acquire(hw
);
333 ret_val
= igb_read_phy_reg_i2c(hw
, offset
, data
);
335 hw
->phy
.ops
.release(hw
);
342 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
343 * @hw: pointer to the HW structure
344 * @offset: register offset to write to
345 * @data: data to write at register offset
347 * Writes the data to PHY register at the offset using the serial gigabit
348 * media independent interface.
350 static s32
igb_write_phy_reg_sgmii_82575(struct e1000_hw
*hw
, u32 offset
,
353 s32 ret_val
= -E1000_ERR_PARAM
;
356 if (offset
> E1000_MAX_SGMII_PHY_REG_ADDR
) {
357 hw_dbg("PHY Address %d is out of range\n", offset
);
361 ret_val
= hw
->phy
.ops
.acquire(hw
);
365 ret_val
= igb_write_phy_reg_i2c(hw
, offset
, data
);
367 hw
->phy
.ops
.release(hw
);
374 * igb_get_phy_id_82575 - Retrieve PHY addr and id
375 * @hw: pointer to the HW structure
377 * Retrieves the PHY address and ID for both PHY's which do and do not use
380 static s32
igb_get_phy_id_82575(struct e1000_hw
*hw
)
382 struct e1000_phy_info
*phy
= &hw
->phy
;
388 * For SGMII PHYs, we try the list of possible addresses until
389 * we find one that works. For non-SGMII PHYs
390 * (e.g. integrated copper PHYs), an address of 1 should
391 * work. The result of this function should mean phy->phy_addr
392 * and phy->id are set correctly.
394 if (!(igb_sgmii_active_82575(hw
))) {
396 ret_val
= igb_get_phy_id(hw
);
400 /* Power on sgmii phy if it is disabled */
401 ctrl_ext
= rd32(E1000_CTRL_EXT
);
402 wr32(E1000_CTRL_EXT
, ctrl_ext
& ~E1000_CTRL_EXT_SDP3_DATA
);
407 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
408 * Therefore, we need to test 1-7
410 for (phy
->addr
= 1; phy
->addr
< 8; phy
->addr
++) {
411 ret_val
= igb_read_phy_reg_sgmii_82575(hw
, PHY_ID1
, &phy_id
);
413 hw_dbg("Vendor ID 0x%08X read at address %u\n",
416 * At the time of this writing, The M88 part is
417 * the only supported SGMII PHY product.
419 if (phy_id
== M88_VENDOR
)
422 hw_dbg("PHY address %u was unreadable\n", phy
->addr
);
426 /* A valid PHY type couldn't be found. */
427 if (phy
->addr
== 8) {
429 ret_val
= -E1000_ERR_PHY
;
432 ret_val
= igb_get_phy_id(hw
);
435 /* restore previous sfp cage power state */
436 wr32(E1000_CTRL_EXT
, ctrl_ext
);
443 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
444 * @hw: pointer to the HW structure
446 * Resets the PHY using the serial gigabit media independent interface.
448 static s32
igb_phy_hw_reset_sgmii_82575(struct e1000_hw
*hw
)
453 * This isn't a true "hard" reset, but is the only reset
454 * available to us at this time.
457 hw_dbg("Soft resetting SGMII attached PHY...\n");
460 * SFP documentation requires the following to configure the SPF module
461 * to work on SGMII. No further documentation is given.
463 ret_val
= hw
->phy
.ops
.write_reg(hw
, 0x1B, 0x8084);
467 ret_val
= igb_phy_sw_reset(hw
);
474 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
475 * @hw: pointer to the HW structure
476 * @active: true to enable LPLU, false to disable
478 * Sets the LPLU D0 state according to the active flag. When
479 * activating LPLU this function also disables smart speed
480 * and vice versa. LPLU will not be activated unless the
481 * device autonegotiation advertisement meets standards of
482 * either 10 or 10/100 or 10/100/1000 at all duplexes.
483 * This is a function pointer entry point only called by
484 * PHY setup routines.
486 static s32
igb_set_d0_lplu_state_82575(struct e1000_hw
*hw
, bool active
)
488 struct e1000_phy_info
*phy
= &hw
->phy
;
492 ret_val
= phy
->ops
.read_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
497 data
|= IGP02E1000_PM_D0_LPLU
;
498 ret_val
= phy
->ops
.write_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
503 /* When LPLU is enabled, we should disable SmartSpeed */
504 ret_val
= phy
->ops
.read_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
506 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
507 ret_val
= phy
->ops
.write_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
512 data
&= ~IGP02E1000_PM_D0_LPLU
;
513 ret_val
= phy
->ops
.write_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
516 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
517 * during Dx states where the power conservation is most
518 * important. During driver activity we should enable
519 * SmartSpeed, so performance is maintained.
521 if (phy
->smart_speed
== e1000_smart_speed_on
) {
522 ret_val
= phy
->ops
.read_reg(hw
,
523 IGP01E1000_PHY_PORT_CONFIG
, &data
);
527 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
528 ret_val
= phy
->ops
.write_reg(hw
,
529 IGP01E1000_PHY_PORT_CONFIG
, data
);
532 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
533 ret_val
= phy
->ops
.read_reg(hw
,
534 IGP01E1000_PHY_PORT_CONFIG
, &data
);
538 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
539 ret_val
= phy
->ops
.write_reg(hw
,
540 IGP01E1000_PHY_PORT_CONFIG
, data
);
551 * igb_acquire_nvm_82575 - Request for access to EEPROM
552 * @hw: pointer to the HW structure
554 * Acquire the necessary semaphores for exclusive access to the EEPROM.
555 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
556 * Return successful if access grant bit set, else clear the request for
557 * EEPROM access and return -E1000_ERR_NVM (-1).
559 static s32
igb_acquire_nvm_82575(struct e1000_hw
*hw
)
563 ret_val
= igb_acquire_swfw_sync_82575(hw
, E1000_SWFW_EEP_SM
);
567 ret_val
= igb_acquire_nvm(hw
);
570 igb_release_swfw_sync_82575(hw
, E1000_SWFW_EEP_SM
);
577 * igb_release_nvm_82575 - Release exclusive access to EEPROM
578 * @hw: pointer to the HW structure
580 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
581 * then release the semaphores acquired.
583 static void igb_release_nvm_82575(struct e1000_hw
*hw
)
586 igb_release_swfw_sync_82575(hw
, E1000_SWFW_EEP_SM
);
590 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
591 * @hw: pointer to the HW structure
592 * @mask: specifies which semaphore to acquire
594 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
595 * will also specify which port we're acquiring the lock for.
597 static s32
igb_acquire_swfw_sync_82575(struct e1000_hw
*hw
, u16 mask
)
601 u32 fwmask
= mask
<< 16;
603 s32 i
= 0, timeout
= 200; /* FIXME: find real value to use here */
605 while (i
< timeout
) {
606 if (igb_get_hw_semaphore(hw
)) {
607 ret_val
= -E1000_ERR_SWFW_SYNC
;
611 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
612 if (!(swfw_sync
& (fwmask
| swmask
)))
616 * Firmware currently using resource (fwmask)
617 * or other software thread using resource (swmask)
619 igb_put_hw_semaphore(hw
);
625 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
626 ret_val
= -E1000_ERR_SWFW_SYNC
;
631 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
633 igb_put_hw_semaphore(hw
);
640 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
641 * @hw: pointer to the HW structure
642 * @mask: specifies which semaphore to acquire
644 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
645 * will also specify which port we're releasing the lock for.
647 static void igb_release_swfw_sync_82575(struct e1000_hw
*hw
, u16 mask
)
651 while (igb_get_hw_semaphore(hw
) != 0);
654 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
656 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
658 igb_put_hw_semaphore(hw
);
662 * igb_get_cfg_done_82575 - Read config done bit
663 * @hw: pointer to the HW structure
665 * Read the management control register for the config done bit for
666 * completion status. NOTE: silicon which is EEPROM-less will fail trying
667 * to read the config done bit, so an error is *ONLY* logged and returns
668 * 0. If we were to return with error, EEPROM-less silicon
669 * would not be able to be reset or change link.
671 static s32
igb_get_cfg_done_82575(struct e1000_hw
*hw
)
673 s32 timeout
= PHY_CFG_TIMEOUT
;
675 u32 mask
= E1000_NVM_CFG_DONE_PORT_0
;
677 if (hw
->bus
.func
== 1)
678 mask
= E1000_NVM_CFG_DONE_PORT_1
;
679 else if (hw
->bus
.func
== E1000_FUNC_2
)
680 mask
= E1000_NVM_CFG_DONE_PORT_2
;
681 else if (hw
->bus
.func
== E1000_FUNC_3
)
682 mask
= E1000_NVM_CFG_DONE_PORT_3
;
685 if (rd32(E1000_EEMNGCTL
) & mask
)
691 hw_dbg("MNG configuration cycle has not completed.\n");
693 /* If EEPROM is not marked present, init the PHY manually */
694 if (((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0) &&
695 (hw
->phy
.type
== e1000_phy_igp_3
))
696 igb_phy_init_script_igp3(hw
);
702 * igb_check_for_link_82575 - Check for link
703 * @hw: pointer to the HW structure
705 * If sgmii is enabled, then use the pcs register to determine link, otherwise
706 * use the generic interface for determining link.
708 static s32
igb_check_for_link_82575(struct e1000_hw
*hw
)
713 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
714 ret_val
= igb_get_pcs_speed_and_duplex_82575(hw
, &speed
,
717 * Use this flag to determine if link needs to be checked or
718 * not. If we have link clear the flag so that we do not
719 * continue to check for link.
721 hw
->mac
.get_link_status
= !hw
->mac
.serdes_has_link
;
723 ret_val
= igb_check_for_copper_link(hw
);
730 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
731 * @hw: pointer to the HW structure
732 * @speed: stores the current speed
733 * @duplex: stores the current duplex
735 * Using the physical coding sub-layer (PCS), retrieve the current speed and
736 * duplex, then store the values in the pointers provided.
738 static s32
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw
*hw
, u16
*speed
,
741 struct e1000_mac_info
*mac
= &hw
->mac
;
744 /* Set up defaults for the return values of this function */
745 mac
->serdes_has_link
= false;
750 * Read the PCS Status register for link state. For non-copper mode,
751 * the status register is not accurate. The PCS status register is
754 pcs
= rd32(E1000_PCS_LSTAT
);
757 * The link up bit determines when link is up on autoneg. The sync ok
758 * gets set once both sides sync up and agree upon link. Stable link
759 * can be determined by checking for both link up and link sync ok
761 if ((pcs
& E1000_PCS_LSTS_LINK_OK
) && (pcs
& E1000_PCS_LSTS_SYNK_OK
)) {
762 mac
->serdes_has_link
= true;
764 /* Detect and store PCS speed */
765 if (pcs
& E1000_PCS_LSTS_SPEED_1000
) {
767 } else if (pcs
& E1000_PCS_LSTS_SPEED_100
) {
773 /* Detect and store PCS duplex */
774 if (pcs
& E1000_PCS_LSTS_DUPLEX_FULL
) {
775 *duplex
= FULL_DUPLEX
;
777 *duplex
= HALF_DUPLEX
;
785 * igb_shutdown_serdes_link_82575 - Remove link during power down
786 * @hw: pointer to the HW structure
788 * In the case of fiber serdes, shut down optics and PCS on driver unload
789 * when management pass thru is not enabled.
791 void igb_shutdown_serdes_link_82575(struct e1000_hw
*hw
)
796 if (hw
->phy
.media_type
!= e1000_media_type_internal_serdes
||
797 igb_sgmii_active_82575(hw
))
800 if (hw
->bus
.func
== E1000_FUNC_0
)
801 hw
->nvm
.ops
.read(hw
, NVM_INIT_CONTROL3_PORT_A
, 1, &eeprom_data
);
802 else if (hw
->mac
.type
== e1000_82580
)
803 hw
->nvm
.ops
.read(hw
, NVM_INIT_CONTROL3_PORT_A
+
804 NVM_82580_LAN_FUNC_OFFSET(hw
->bus
.func
), 1,
806 else if (hw
->bus
.func
== E1000_FUNC_1
)
807 hw
->nvm
.ops
.read(hw
, NVM_INIT_CONTROL3_PORT_B
, 1, &eeprom_data
);
810 * If APM is not enabled in the EEPROM and management interface is
811 * not enabled, then power down.
813 if (!(eeprom_data
& E1000_NVM_APME_82575
) &&
814 !igb_enable_mng_pass_thru(hw
)) {
815 /* Disable PCS to turn off link */
816 reg
= rd32(E1000_PCS_CFG0
);
817 reg
&= ~E1000_PCS_CFG_PCS_EN
;
818 wr32(E1000_PCS_CFG0
, reg
);
820 /* shutdown the laser */
821 reg
= rd32(E1000_CTRL_EXT
);
822 reg
|= E1000_CTRL_EXT_SDP3_DATA
;
823 wr32(E1000_CTRL_EXT
, reg
);
825 /* flush the write to verify completion */
834 * igb_reset_hw_82575 - Reset hardware
835 * @hw: pointer to the HW structure
837 * This resets the hardware into a known state. This is a
838 * function pointer entry point called by the api module.
840 static s32
igb_reset_hw_82575(struct e1000_hw
*hw
)
846 * Prevent the PCI-E bus from sticking if there is no TLP connection
847 * on the last TLP read/write transaction when MAC is reset.
849 ret_val
= igb_disable_pcie_master(hw
);
851 hw_dbg("PCI-E Master disable polling has failed.\n");
853 /* set the completion timeout for interface */
854 ret_val
= igb_set_pcie_completion_timeout(hw
);
856 hw_dbg("PCI-E Set completion timeout has failed.\n");
859 hw_dbg("Masking off all interrupts\n");
860 wr32(E1000_IMC
, 0xffffffff);
863 wr32(E1000_TCTL
, E1000_TCTL_PSP
);
868 ctrl
= rd32(E1000_CTRL
);
870 hw_dbg("Issuing a global reset to MAC\n");
871 wr32(E1000_CTRL
, ctrl
| E1000_CTRL_RST
);
873 ret_val
= igb_get_auto_rd_done(hw
);
876 * When auto config read does not complete, do not
877 * return with an error. This can happen in situations
878 * where there is no eeprom and prevents getting link.
880 hw_dbg("Auto Read Done did not complete\n");
883 /* If EEPROM is not present, run manual init scripts */
884 if ((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0)
885 igb_reset_init_script_82575(hw
);
887 /* Clear any pending interrupt events. */
888 wr32(E1000_IMC
, 0xffffffff);
889 icr
= rd32(E1000_ICR
);
891 /* Install any alternate MAC address into RAR0 */
892 ret_val
= igb_check_alt_mac_addr(hw
);
898 * igb_init_hw_82575 - Initialize hardware
899 * @hw: pointer to the HW structure
901 * This inits the hardware readying it for operation.
903 static s32
igb_init_hw_82575(struct e1000_hw
*hw
)
905 struct e1000_mac_info
*mac
= &hw
->mac
;
907 u16 i
, rar_count
= mac
->rar_entry_count
;
909 /* Initialize identification LED */
910 ret_val
= igb_id_led_init(hw
);
912 hw_dbg("Error initializing identification LED\n");
913 /* This is not fatal and we should not stop init due to this */
916 /* Disabling VLAN filtering */
917 hw_dbg("Initializing the IEEE VLAN\n");
920 /* Setup the receive address */
921 igb_init_rx_addrs(hw
, rar_count
);
923 /* Zero out the Multicast HASH table */
924 hw_dbg("Zeroing the MTA\n");
925 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
926 array_wr32(E1000_MTA
, i
, 0);
928 /* Zero out the Unicast HASH table */
929 hw_dbg("Zeroing the UTA\n");
930 for (i
= 0; i
< mac
->uta_reg_count
; i
++)
931 array_wr32(E1000_UTA
, i
, 0);
933 /* Setup link and flow control */
934 ret_val
= igb_setup_link(hw
);
937 * Clear all of the statistics registers (clear on read). It is
938 * important that we do this after we have tried to establish link
939 * because the symbol error count will increment wildly if there
942 igb_clear_hw_cntrs_82575(hw
);
948 * igb_setup_copper_link_82575 - Configure copper link settings
949 * @hw: pointer to the HW structure
951 * Configures the link for auto-neg or forced speed and duplex. Then we check
952 * for link, once link is established calls to configure collision distance
953 * and flow control are called.
955 static s32
igb_setup_copper_link_82575(struct e1000_hw
*hw
)
960 ctrl
= rd32(E1000_CTRL
);
961 ctrl
|= E1000_CTRL_SLU
;
962 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
963 wr32(E1000_CTRL
, ctrl
);
965 ret_val
= igb_setup_serdes_link_82575(hw
);
969 if (igb_sgmii_active_82575(hw
) && !hw
->phy
.reset_disable
) {
970 /* allow time for SFP cage time to power up phy */
973 ret_val
= hw
->phy
.ops
.reset(hw
);
975 hw_dbg("Error resetting the PHY.\n");
979 switch (hw
->phy
.type
) {
981 ret_val
= igb_copper_link_setup_m88(hw
);
983 case e1000_phy_igp_3
:
984 ret_val
= igb_copper_link_setup_igp(hw
);
986 case e1000_phy_82580
:
987 ret_val
= igb_copper_link_setup_82580(hw
);
990 ret_val
= -E1000_ERR_PHY
;
997 ret_val
= igb_setup_copper_link(hw
);
1003 * igb_setup_serdes_link_82575 - Setup link for serdes
1004 * @hw: pointer to the HW structure
1006 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1007 * used on copper connections where the serialized gigabit media independent
1008 * interface (sgmii), or serdes fiber is being used. Configures the link
1009 * for auto-negotiation or forces speed/duplex.
1011 static s32
igb_setup_serdes_link_82575(struct e1000_hw
*hw
)
1013 u32 ctrl_ext
, ctrl_reg
, reg
;
1016 if ((hw
->phy
.media_type
!= e1000_media_type_internal_serdes
) &&
1017 !igb_sgmii_active_82575(hw
))
1021 * On the 82575, SerDes loopback mode persists until it is
1022 * explicitly turned off or a power cycle is performed. A read to
1023 * the register does not indicate its status. Therefore, we ensure
1024 * loopback mode is disabled during initialization.
1026 wr32(E1000_SCTL
, E1000_SCTL_DISABLE_SERDES_LOOPBACK
);
1028 /* power on the sfp cage if present */
1029 ctrl_ext
= rd32(E1000_CTRL_EXT
);
1030 ctrl_ext
&= ~E1000_CTRL_EXT_SDP3_DATA
;
1031 wr32(E1000_CTRL_EXT
, ctrl_ext
);
1033 ctrl_reg
= rd32(E1000_CTRL
);
1034 ctrl_reg
|= E1000_CTRL_SLU
;
1036 if (hw
->mac
.type
== e1000_82575
|| hw
->mac
.type
== e1000_82576
) {
1037 /* set both sw defined pins */
1038 ctrl_reg
|= E1000_CTRL_SWDPIN0
| E1000_CTRL_SWDPIN1
;
1040 /* Set switch control to serdes energy detect */
1041 reg
= rd32(E1000_CONNSW
);
1042 reg
|= E1000_CONNSW_ENRGSRC
;
1043 wr32(E1000_CONNSW
, reg
);
1046 reg
= rd32(E1000_PCS_LCTL
);
1048 /* default pcs_autoneg to the same setting as mac autoneg */
1049 pcs_autoneg
= hw
->mac
.autoneg
;
1051 switch (ctrl_ext
& E1000_CTRL_EXT_LINK_MODE_MASK
) {
1052 case E1000_CTRL_EXT_LINK_MODE_SGMII
:
1053 /* sgmii mode lets the phy handle forcing speed/duplex */
1055 /* autoneg time out should be disabled for SGMII mode */
1056 reg
&= ~(E1000_PCS_LCTL_AN_TIMEOUT
);
1058 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX
:
1059 /* disable PCS autoneg and support parallel detect only */
1060 pcs_autoneg
= false;
1063 * non-SGMII modes only supports a speed of 1000/Full for the
1064 * link so it is best to just force the MAC and let the pcs
1065 * link either autoneg or be forced to 1000/Full
1067 ctrl_reg
|= E1000_CTRL_SPD_1000
| E1000_CTRL_FRCSPD
|
1068 E1000_CTRL_FD
| E1000_CTRL_FRCDPX
;
1070 /* set speed of 1000/Full if speed/duplex is forced */
1071 reg
|= E1000_PCS_LCTL_FSV_1000
| E1000_PCS_LCTL_FDV_FULL
;
1075 wr32(E1000_CTRL
, ctrl_reg
);
1078 * New SerDes mode allows for forcing speed or autonegotiating speed
1079 * at 1gb. Autoneg should be default set by most drivers. This is the
1080 * mode that will be compatible with older link partners and switches.
1081 * However, both are supported by the hardware and some drivers/tools.
1083 reg
&= ~(E1000_PCS_LCTL_AN_ENABLE
| E1000_PCS_LCTL_FLV_LINK_UP
|
1084 E1000_PCS_LCTL_FSD
| E1000_PCS_LCTL_FORCE_LINK
);
1087 * We force flow control to prevent the CTRL register values from being
1088 * overwritten by the autonegotiated flow control values
1090 reg
|= E1000_PCS_LCTL_FORCE_FCTRL
;
1093 /* Set PCS register for autoneg */
1094 reg
|= E1000_PCS_LCTL_AN_ENABLE
| /* Enable Autoneg */
1095 E1000_PCS_LCTL_AN_RESTART
; /* Restart autoneg */
1096 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg
);
1098 /* Set PCS register for forced link */
1099 reg
|= E1000_PCS_LCTL_FSD
| /* Force Speed */
1100 E1000_PCS_LCTL_FORCE_LINK
| /* Force Link */
1101 E1000_PCS_LCTL_FLV_LINK_UP
; /* Force link value up */
1103 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg
);
1106 wr32(E1000_PCS_LCTL
, reg
);
1108 if (!igb_sgmii_active_82575(hw
))
1109 igb_force_mac_fc(hw
);
1115 * igb_sgmii_active_82575 - Return sgmii state
1116 * @hw: pointer to the HW structure
1118 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1119 * which can be enabled for use in the embedded applications. Simply
1120 * return the current state of the sgmii interface.
1122 static bool igb_sgmii_active_82575(struct e1000_hw
*hw
)
1124 struct e1000_dev_spec_82575
*dev_spec
= &hw
->dev_spec
._82575
;
1125 return dev_spec
->sgmii_active
;
1129 * igb_reset_init_script_82575 - Inits HW defaults after reset
1130 * @hw: pointer to the HW structure
1132 * Inits recommended HW defaults after a reset when there is no EEPROM
1133 * detected. This is only for the 82575.
1135 static s32
igb_reset_init_script_82575(struct e1000_hw
*hw
)
1137 if (hw
->mac
.type
== e1000_82575
) {
1138 hw_dbg("Running reset init script for 82575\n");
1139 /* SerDes configuration via SERDESCTRL */
1140 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x00, 0x0C);
1141 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x01, 0x78);
1142 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x1B, 0x23);
1143 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x23, 0x15);
1145 /* CCM configuration via CCMCTL register */
1146 igb_write_8bit_ctrl_reg(hw
, E1000_CCMCTL
, 0x14, 0x00);
1147 igb_write_8bit_ctrl_reg(hw
, E1000_CCMCTL
, 0x10, 0x00);
1149 /* PCIe lanes configuration */
1150 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x00, 0xEC);
1151 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x61, 0xDF);
1152 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x34, 0x05);
1153 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x2F, 0x81);
1155 /* PCIe PLL Configuration */
1156 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x02, 0x47);
1157 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x14, 0x00);
1158 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x10, 0x00);
1165 * igb_read_mac_addr_82575 - Read device MAC address
1166 * @hw: pointer to the HW structure
1168 static s32
igb_read_mac_addr_82575(struct e1000_hw
*hw
)
1173 * If there's an alternate MAC address place it in RAR0
1174 * so that it will override the Si installed default perm
1177 ret_val
= igb_check_alt_mac_addr(hw
);
1181 ret_val
= igb_read_mac_addr(hw
);
1188 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1189 * @hw: pointer to the HW structure
1191 * Clears the hardware counters by reading the counter registers.
1193 static void igb_clear_hw_cntrs_82575(struct e1000_hw
*hw
)
1195 igb_clear_hw_cntrs_base(hw
);
1201 rd32(E1000_PRC1023
);
1202 rd32(E1000_PRC1522
);
1207 rd32(E1000_PTC1023
);
1208 rd32(E1000_PTC1522
);
1210 rd32(E1000_ALGNERRC
);
1213 rd32(E1000_CEXTERR
);
1224 rd32(E1000_ICRXPTC
);
1225 rd32(E1000_ICRXATC
);
1226 rd32(E1000_ICTXPTC
);
1227 rd32(E1000_ICTXATC
);
1228 rd32(E1000_ICTXQEC
);
1229 rd32(E1000_ICTXQMTC
);
1230 rd32(E1000_ICRXDMTC
);
1237 rd32(E1000_HTCBDPC
);
1242 rd32(E1000_LENERRS
);
1244 /* This register should not be read in copper configurations */
1245 if (hw
->phy
.media_type
== e1000_media_type_internal_serdes
||
1246 igb_sgmii_active_82575(hw
))
1251 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1252 * @hw: pointer to the HW structure
1254 * After rx enable if managability is enabled then there is likely some
1255 * bad data at the start of the fifo and possibly in the DMA fifo. This
1256 * function clears the fifos and flushes any packets that came in as rx was
1259 void igb_rx_fifo_flush_82575(struct e1000_hw
*hw
)
1261 u32 rctl
, rlpml
, rxdctl
[4], rfctl
, temp_rctl
, rx_enabled
;
1264 if (hw
->mac
.type
!= e1000_82575
||
1265 !(rd32(E1000_MANC
) & E1000_MANC_RCV_TCO_EN
))
1268 /* Disable all RX queues */
1269 for (i
= 0; i
< 4; i
++) {
1270 rxdctl
[i
] = rd32(E1000_RXDCTL(i
));
1271 wr32(E1000_RXDCTL(i
),
1272 rxdctl
[i
] & ~E1000_RXDCTL_QUEUE_ENABLE
);
1274 /* Poll all queues to verify they have shut down */
1275 for (ms_wait
= 0; ms_wait
< 10; ms_wait
++) {
1278 for (i
= 0; i
< 4; i
++)
1279 rx_enabled
|= rd32(E1000_RXDCTL(i
));
1280 if (!(rx_enabled
& E1000_RXDCTL_QUEUE_ENABLE
))
1285 hw_dbg("Queue disable timed out after 10ms\n");
1287 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1288 * incoming packets are rejected. Set enable and wait 2ms so that
1289 * any packet that was coming in as RCTL.EN was set is flushed
1291 rfctl
= rd32(E1000_RFCTL
);
1292 wr32(E1000_RFCTL
, rfctl
& ~E1000_RFCTL_LEF
);
1294 rlpml
= rd32(E1000_RLPML
);
1295 wr32(E1000_RLPML
, 0);
1297 rctl
= rd32(E1000_RCTL
);
1298 temp_rctl
= rctl
& ~(E1000_RCTL_EN
| E1000_RCTL_SBP
);
1299 temp_rctl
|= E1000_RCTL_LPE
;
1301 wr32(E1000_RCTL
, temp_rctl
);
1302 wr32(E1000_RCTL
, temp_rctl
| E1000_RCTL_EN
);
1306 /* Enable RX queues that were previously enabled and restore our
1309 for (i
= 0; i
< 4; i
++)
1310 wr32(E1000_RXDCTL(i
), rxdctl
[i
]);
1311 wr32(E1000_RCTL
, rctl
);
1314 wr32(E1000_RLPML
, rlpml
);
1315 wr32(E1000_RFCTL
, rfctl
);
1317 /* Flush receive errors generated by workaround */
1324 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1325 * @hw: pointer to the HW structure
1327 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1328 * however the hardware default for these parts is 500us to 1ms which is less
1329 * than the 10ms recommended by the pci-e spec. To address this we need to
1330 * increase the value to either 10ms to 200ms for capability version 1 config,
1331 * or 16ms to 55ms for version 2.
1333 static s32
igb_set_pcie_completion_timeout(struct e1000_hw
*hw
)
1335 u32 gcr
= rd32(E1000_GCR
);
1339 /* only take action if timeout value is defaulted to 0 */
1340 if (gcr
& E1000_GCR_CMPL_TMOUT_MASK
)
1344 * if capababilities version is type 1 we can write the
1345 * timeout of 10ms to 200ms through the GCR register
1347 if (!(gcr
& E1000_GCR_CAP_VER2
)) {
1348 gcr
|= E1000_GCR_CMPL_TMOUT_10ms
;
1353 * for version 2 capabilities we need to write the config space
1354 * directly in order to set the completion timeout value for
1357 ret_val
= igb_read_pcie_cap_reg(hw
, PCIE_DEVICE_CONTROL2
,
1362 pcie_devctl2
|= PCIE_DEVICE_CONTROL2_16ms
;
1364 ret_val
= igb_write_pcie_cap_reg(hw
, PCIE_DEVICE_CONTROL2
,
1367 /* disable completion timeout resend */
1368 gcr
&= ~E1000_GCR_CMPL_TMOUT_RESEND
;
1370 wr32(E1000_GCR
, gcr
);
1375 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1376 * @hw: pointer to the hardware struct
1377 * @enable: state to enter, either enabled or disabled
1379 * enables/disables L2 switch loopback functionality.
1381 void igb_vmdq_set_loopback_pf(struct e1000_hw
*hw
, bool enable
)
1383 u32 dtxswc
= rd32(E1000_DTXSWC
);
1386 dtxswc
|= E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
1388 dtxswc
&= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
1390 wr32(E1000_DTXSWC
, dtxswc
);
1394 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1395 * @hw: pointer to the hardware struct
1396 * @enable: state to enter, either enabled or disabled
1398 * enables/disables replication of packets across multiple pools.
1400 void igb_vmdq_set_replication_pf(struct e1000_hw
*hw
, bool enable
)
1402 u32 vt_ctl
= rd32(E1000_VT_CTL
);
1405 vt_ctl
|= E1000_VT_CTL_VM_REPL_EN
;
1407 vt_ctl
&= ~E1000_VT_CTL_VM_REPL_EN
;
1409 wr32(E1000_VT_CTL
, vt_ctl
);
1413 * igb_read_phy_reg_82580 - Read 82580 MDI control register
1414 * @hw: pointer to the HW structure
1415 * @offset: register offset to be read
1416 * @data: pointer to the read data
1418 * Reads the MDI control register in the PHY at offset and stores the
1419 * information read to data.
1421 static s32
igb_read_phy_reg_82580(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
1427 ret_val
= hw
->phy
.ops
.acquire(hw
);
1432 * We config the phy address in MDICNFG register now. Same bits
1433 * as before. The values in MDIC can be written but will be
1434 * ignored. This allows us to call the old function after
1435 * configuring the PHY address in the new register
1437 mdicnfg
= (hw
->phy
.addr
<< E1000_MDIC_PHY_SHIFT
);
1438 wr32(E1000_MDICNFG
, mdicnfg
);
1440 ret_val
= igb_read_phy_reg_mdic(hw
, offset
, data
);
1442 hw
->phy
.ops
.release(hw
);
1449 * igb_write_phy_reg_82580 - Write 82580 MDI control register
1450 * @hw: pointer to the HW structure
1451 * @offset: register offset to write to
1452 * @data: data to write to register at offset
1454 * Writes data to MDI control register in the PHY at offset.
1456 static s32
igb_write_phy_reg_82580(struct e1000_hw
*hw
, u32 offset
, u16 data
)
1462 ret_val
= hw
->phy
.ops
.acquire(hw
);
1467 * We config the phy address in MDICNFG register now. Same bits
1468 * as before. The values in MDIC can be written but will be
1469 * ignored. This allows us to call the old function after
1470 * configuring the PHY address in the new register
1472 mdicnfg
= (hw
->phy
.addr
<< E1000_MDIC_PHY_SHIFT
);
1473 wr32(E1000_MDICNFG
, mdicnfg
);
1475 ret_val
= igb_write_phy_reg_mdic(hw
, offset
, data
);
1477 hw
->phy
.ops
.release(hw
);
1484 * igb_reset_hw_82580 - Reset hardware
1485 * @hw: pointer to the HW structure
1487 * This resets function or entire device (all ports, etc.)
1490 static s32
igb_reset_hw_82580(struct e1000_hw
*hw
)
1493 /* BH SW mailbox bit in SW_FW_SYNC */
1494 u16 swmbsw_mask
= E1000_SW_SYNCH_MB
;
1496 bool global_device_reset
= hw
->dev_spec
._82575
.global_device_reset
;
1499 hw
->dev_spec
._82575
.global_device_reset
= false;
1501 /* Get current control state. */
1502 ctrl
= rd32(E1000_CTRL
);
1505 * Prevent the PCI-E bus from sticking if there is no TLP connection
1506 * on the last TLP read/write transaction when MAC is reset.
1508 ret_val
= igb_disable_pcie_master(hw
);
1510 hw_dbg("PCI-E Master disable polling has failed.\n");
1512 hw_dbg("Masking off all interrupts\n");
1513 wr32(E1000_IMC
, 0xffffffff);
1514 wr32(E1000_RCTL
, 0);
1515 wr32(E1000_TCTL
, E1000_TCTL_PSP
);
1520 /* Determine whether or not a global dev reset is requested */
1521 if (global_device_reset
&&
1522 igb_acquire_swfw_sync_82575(hw
, swmbsw_mask
))
1523 global_device_reset
= false;
1525 if (global_device_reset
&&
1526 !(rd32(E1000_STATUS
) & E1000_STAT_DEV_RST_SET
))
1527 ctrl
|= E1000_CTRL_DEV_RST
;
1529 ctrl
|= E1000_CTRL_RST
;
1531 wr32(E1000_CTRL
, ctrl
);
1533 /* Add delay to insure DEV_RST has time to complete */
1534 if (global_device_reset
)
1537 ret_val
= igb_get_auto_rd_done(hw
);
1540 * When auto config read does not complete, do not
1541 * return with an error. This can happen in situations
1542 * where there is no eeprom and prevents getting link.
1544 hw_dbg("Auto Read Done did not complete\n");
1547 /* If EEPROM is not present, run manual init scripts */
1548 if ((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0)
1549 igb_reset_init_script_82575(hw
);
1551 /* clear global device reset status bit */
1552 wr32(E1000_STATUS
, E1000_STAT_DEV_RST_SET
);
1554 /* Clear any pending interrupt events. */
1555 wr32(E1000_IMC
, 0xffffffff);
1556 icr
= rd32(E1000_ICR
);
1558 /* Install any alternate MAC address into RAR0 */
1559 ret_val
= igb_check_alt_mac_addr(hw
);
1561 /* Release semaphore */
1562 if (global_device_reset
)
1563 igb_release_swfw_sync_82575(hw
, swmbsw_mask
);
1569 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
1570 * @data: data received by reading RXPBS register
1572 * The 82580 uses a table based approach for packet buffer allocation sizes.
1573 * This function converts the retrieved value into the correct table value
1574 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
1575 * 0x0 36 72 144 1 2 4 8 16
1576 * 0x8 35 70 140 rsv rsv rsv rsv rsv
1578 u16
igb_rxpbs_adjust_82580(u32 data
)
1582 if (data
< E1000_82580_RXPBS_TABLE_SIZE
)
1583 ret_val
= e1000_82580_rxpbs_table
[data
];
1588 static struct e1000_mac_operations e1000_mac_ops_82575
= {
1589 .init_hw
= igb_init_hw_82575
,
1590 .check_for_link
= igb_check_for_link_82575
,
1591 .rar_set
= igb_rar_set
,
1592 .read_mac_addr
= igb_read_mac_addr_82575
,
1593 .get_speed_and_duplex
= igb_get_speed_and_duplex_copper
,
1596 static struct e1000_phy_operations e1000_phy_ops_82575
= {
1597 .acquire
= igb_acquire_phy_82575
,
1598 .get_cfg_done
= igb_get_cfg_done_82575
,
1599 .release
= igb_release_phy_82575
,
1602 static struct e1000_nvm_operations e1000_nvm_ops_82575
= {
1603 .acquire
= igb_acquire_nvm_82575
,
1604 .read
= igb_read_nvm_eerd
,
1605 .release
= igb_release_nvm_82575
,
1606 .write
= igb_write_nvm_spi
,
1609 const struct e1000_info e1000_82575_info
= {
1610 .get_invariants
= igb_get_invariants_82575
,
1611 .mac_ops
= &e1000_mac_ops_82575
,
1612 .phy_ops
= &e1000_phy_ops_82575
,
1613 .nvm_ops
= &e1000_nvm_ops_82575
,