1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
35 #include "intel_drv.h"
37 #include <linux/console.h>
38 #include "drm_crtc_helper.h"
40 static int i915_modeset
= -1;
41 module_param_named(modeset
, i915_modeset
, int, 0400);
43 unsigned int i915_fbpercrtc
= 0;
44 module_param_named(fbpercrtc
, i915_fbpercrtc
, int, 0400);
46 int i915_panel_ignore_lid
= 0;
47 module_param_named(panel_ignore_lid
, i915_panel_ignore_lid
, int, 0600);
49 unsigned int i915_powersave
= 1;
50 module_param_named(powersave
, i915_powersave
, int, 0600);
52 unsigned int i915_semaphores
= 0;
53 module_param_named(semaphores
, i915_semaphores
, int, 0600);
55 unsigned int i915_enable_rc6
= 0;
56 module_param_named(i915_enable_rc6
, i915_enable_rc6
, int, 0600);
58 unsigned int i915_enable_fbc
= 1;
59 module_param_named(i915_enable_fbc
, i915_enable_fbc
, int, 0600);
61 unsigned int i915_lvds_downclock
= 0;
62 module_param_named(lvds_downclock
, i915_lvds_downclock
, int, 0400);
64 unsigned int i915_panel_use_ssc
= 1;
65 module_param_named(lvds_use_ssc
, i915_panel_use_ssc
, int, 0600);
67 int i915_vbt_sdvo_panel_type
= -1;
68 module_param_named(vbt_sdvo_panel_type
, i915_vbt_sdvo_panel_type
, int, 0600);
70 static bool i915_try_reset
= true;
71 module_param_named(reset
, i915_try_reset
, bool, 0600);
73 bool i915_enable_hangcheck
= true;
74 module_param_named(enable_hangcheck
, i915_enable_hangcheck
, bool, 0644);
76 static struct drm_driver driver
;
77 extern int intel_agp_enabled
;
79 #define INTEL_VGA_DEVICE(id, info) { \
80 .class = PCI_CLASS_DISPLAY_VGA << 8, \
81 .class_mask = 0xff0000, \
84 .subvendor = PCI_ANY_ID, \
85 .subdevice = PCI_ANY_ID, \
86 .driver_data = (unsigned long) info }
88 static const struct intel_device_info intel_i830_info
= {
89 .gen
= 2, .is_mobile
= 1, .cursor_needs_physical
= 1,
90 .has_overlay
= 1, .overlay_needs_physical
= 1,
93 static const struct intel_device_info intel_845g_info
= {
95 .has_overlay
= 1, .overlay_needs_physical
= 1,
98 static const struct intel_device_info intel_i85x_info
= {
99 .gen
= 2, .is_i85x
= 1, .is_mobile
= 1,
100 .cursor_needs_physical
= 1,
101 .has_overlay
= 1, .overlay_needs_physical
= 1,
104 static const struct intel_device_info intel_i865g_info
= {
106 .has_overlay
= 1, .overlay_needs_physical
= 1,
109 static const struct intel_device_info intel_i915g_info
= {
110 .gen
= 3, .is_i915g
= 1, .cursor_needs_physical
= 1,
111 .has_overlay
= 1, .overlay_needs_physical
= 1,
113 static const struct intel_device_info intel_i915gm_info
= {
114 .gen
= 3, .is_mobile
= 1,
115 .cursor_needs_physical
= 1,
116 .has_overlay
= 1, .overlay_needs_physical
= 1,
119 static const struct intel_device_info intel_i945g_info
= {
120 .gen
= 3, .has_hotplug
= 1, .cursor_needs_physical
= 1,
121 .has_overlay
= 1, .overlay_needs_physical
= 1,
123 static const struct intel_device_info intel_i945gm_info
= {
124 .gen
= 3, .is_i945gm
= 1, .is_mobile
= 1,
125 .has_hotplug
= 1, .cursor_needs_physical
= 1,
126 .has_overlay
= 1, .overlay_needs_physical
= 1,
130 static const struct intel_device_info intel_i965g_info
= {
131 .gen
= 4, .is_broadwater
= 1,
136 static const struct intel_device_info intel_i965gm_info
= {
137 .gen
= 4, .is_crestline
= 1,
138 .is_mobile
= 1, .has_fbc
= 1, .has_hotplug
= 1,
143 static const struct intel_device_info intel_g33_info
= {
144 .gen
= 3, .is_g33
= 1,
145 .need_gfx_hws
= 1, .has_hotplug
= 1,
149 static const struct intel_device_info intel_g45_info
= {
150 .gen
= 4, .is_g4x
= 1, .need_gfx_hws
= 1,
151 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
155 static const struct intel_device_info intel_gm45_info
= {
156 .gen
= 4, .is_g4x
= 1,
157 .is_mobile
= 1, .need_gfx_hws
= 1, .has_fbc
= 1,
158 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
163 static const struct intel_device_info intel_pineview_info
= {
164 .gen
= 3, .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1,
165 .need_gfx_hws
= 1, .has_hotplug
= 1,
169 static const struct intel_device_info intel_ironlake_d_info
= {
171 .need_gfx_hws
= 1, .has_pipe_cxsr
= 1, .has_hotplug
= 1,
175 static const struct intel_device_info intel_ironlake_m_info
= {
176 .gen
= 5, .is_mobile
= 1,
177 .need_gfx_hws
= 1, .has_hotplug
= 1,
182 static const struct intel_device_info intel_sandybridge_d_info
= {
184 .need_gfx_hws
= 1, .has_hotplug
= 1,
189 static const struct intel_device_info intel_sandybridge_m_info
= {
190 .gen
= 6, .is_mobile
= 1,
191 .need_gfx_hws
= 1, .has_hotplug
= 1,
197 static const struct intel_device_info intel_ivybridge_d_info
= {
198 .is_ivybridge
= 1, .gen
= 7,
199 .need_gfx_hws
= 1, .has_hotplug
= 1,
204 static const struct intel_device_info intel_ivybridge_m_info
= {
205 .is_ivybridge
= 1, .gen
= 7, .is_mobile
= 1,
206 .need_gfx_hws
= 1, .has_hotplug
= 1,
207 .has_fbc
= 0, /* FBC is not enabled on Ivybridge mobile yet */
212 static const struct pci_device_id pciidlist
[] = { /* aka */
213 INTEL_VGA_DEVICE(0x3577, &intel_i830_info
), /* I830_M */
214 INTEL_VGA_DEVICE(0x2562, &intel_845g_info
), /* 845_G */
215 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info
), /* I855_GM */
216 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info
),
217 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info
), /* I865_G */
218 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info
), /* I915_G */
219 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info
), /* E7221_G */
220 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info
), /* I915_GM */
221 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info
), /* I945_G */
222 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info
), /* I945_GM */
223 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info
), /* I945_GME */
224 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info
), /* I946_GZ */
225 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info
), /* G35_G */
226 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info
), /* I965_Q */
227 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info
), /* I965_G */
228 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info
), /* Q35_G */
229 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info
), /* G33_G */
230 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info
), /* Q33_G */
231 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info
), /* I965_GM */
232 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info
), /* I965_GME */
233 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info
), /* GM45_G */
234 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info
), /* IGD_E_G */
235 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info
), /* Q45_G */
236 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info
), /* G45_G */
237 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info
), /* G41_G */
238 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info
), /* B43_G */
239 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info
), /* B43_G.1 */
240 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info
),
241 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info
),
242 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info
),
243 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info
),
244 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info
),
245 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info
),
246 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info
),
247 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info
),
248 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info
),
249 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info
),
250 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info
),
251 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info
), /* GT1 mobile */
252 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info
), /* GT2 mobile */
253 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info
), /* GT1 desktop */
254 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info
), /* GT2 desktop */
255 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info
), /* GT1 server */
259 #if defined(CONFIG_DRM_I915_KMS)
260 MODULE_DEVICE_TABLE(pci
, pciidlist
);
263 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
264 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
265 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
266 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
268 void intel_detect_pch (struct drm_device
*dev
)
270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
274 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
275 * make graphics device passthrough work easy for VMM, that only
276 * need to expose ISA bridge to let driver know the real hardware
277 * underneath. This is a requirement from virtualization team.
279 pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, NULL
);
281 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
283 id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
285 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
286 dev_priv
->pch_type
= PCH_IBX
;
287 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
288 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
289 dev_priv
->pch_type
= PCH_CPT
;
290 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
291 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
292 /* PantherPoint is CPT compatible */
293 dev_priv
->pch_type
= PCH_CPT
;
294 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
301 static void __gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
)
306 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
309 I915_WRITE_NOTRACE(FORCEWAKE
, 1);
310 POSTING_READ(FORCEWAKE
);
313 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1) == 0)
318 * Generally this is called implicitly by the register read function. However,
319 * if some sequence requires the GT to not power down then this function should
320 * be called at the beginning of the sequence followed by a call to
321 * gen6_gt_force_wake_put() at the end of the sequence.
323 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
)
325 WARN_ON(!mutex_is_locked(&dev_priv
->dev
->struct_mutex
));
327 /* Forcewake is atomic in case we get in here without the lock */
328 if (atomic_add_return(1, &dev_priv
->forcewake_count
) == 1)
329 __gen6_gt_force_wake_get(dev_priv
);
332 static void __gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
)
334 I915_WRITE_NOTRACE(FORCEWAKE
, 0);
335 POSTING_READ(FORCEWAKE
);
339 * see gen6_gt_force_wake_get()
341 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
)
343 WARN_ON(!mutex_is_locked(&dev_priv
->dev
->struct_mutex
));
345 if (atomic_dec_and_test(&dev_priv
->forcewake_count
))
346 __gen6_gt_force_wake_put(dev_priv
);
349 void __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
)
352 u32 fifo
= I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES
);
353 while (fifo
< 20 && loop
--) {
355 fifo
= I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES
);
359 static int i915_drm_freeze(struct drm_device
*dev
)
361 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
363 drm_kms_helper_poll_disable(dev
);
365 pci_save_state(dev
->pdev
);
367 /* If KMS is active, we do the leavevt stuff here */
368 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
369 int error
= i915_gem_idle(dev
);
371 dev_err(&dev
->pdev
->dev
,
372 "GEM idle failed, resume might fail\n");
375 drm_irq_uninstall(dev
);
378 i915_save_state(dev
);
380 intel_opregion_fini(dev
);
382 /* Modeset on resume, not lid events */
383 dev_priv
->modeset_on_lid
= 0;
388 int i915_suspend(struct drm_device
*dev
, pm_message_t state
)
392 if (!dev
|| !dev
->dev_private
) {
393 DRM_ERROR("dev: %p\n", dev
);
394 DRM_ERROR("DRM not initialized, aborting suspend.\n");
398 if (state
.event
== PM_EVENT_PRETHAW
)
402 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
405 error
= i915_drm_freeze(dev
);
409 if (state
.event
== PM_EVENT_SUSPEND
) {
410 /* Shut down the device */
411 pci_disable_device(dev
->pdev
);
412 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
418 static int i915_drm_thaw(struct drm_device
*dev
)
420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
423 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
424 mutex_lock(&dev
->struct_mutex
);
425 i915_gem_restore_gtt_mappings(dev
);
426 mutex_unlock(&dev
->struct_mutex
);
429 i915_restore_state(dev
);
430 intel_opregion_setup(dev
);
432 /* KMS EnterVT equivalent */
433 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
434 mutex_lock(&dev
->struct_mutex
);
435 dev_priv
->mm
.suspended
= 0;
437 error
= i915_gem_init_ringbuffer(dev
);
438 mutex_unlock(&dev
->struct_mutex
);
440 drm_mode_config_reset(dev
);
441 drm_irq_install(dev
);
443 /* Resume the modeset for every activated CRTC */
444 drm_helper_resume_force_mode(dev
);
446 if (IS_IRONLAKE_M(dev
))
447 ironlake_enable_rc6(dev
);
450 intel_opregion_init(dev
);
452 dev_priv
->modeset_on_lid
= 0;
457 int i915_resume(struct drm_device
*dev
)
461 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
464 if (pci_enable_device(dev
->pdev
))
467 pci_set_master(dev
->pdev
);
469 ret
= i915_drm_thaw(dev
);
473 drm_kms_helper_poll_enable(dev
);
477 static int i8xx_do_reset(struct drm_device
*dev
, u8 flags
)
479 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
484 I915_WRITE(D_STATE
, I915_READ(D_STATE
) | DSTATE_GFX_RESET_I830
);
485 POSTING_READ(D_STATE
);
487 if (IS_I830(dev
) || IS_845G(dev
)) {
488 I915_WRITE(DEBUG_RESET_I830
,
489 DEBUG_RESET_DISPLAY
|
492 POSTING_READ(DEBUG_RESET_I830
);
495 I915_WRITE(DEBUG_RESET_I830
, 0);
496 POSTING_READ(DEBUG_RESET_I830
);
501 I915_WRITE(D_STATE
, I915_READ(D_STATE
) & ~DSTATE_GFX_RESET_I830
);
502 POSTING_READ(D_STATE
);
507 static int i965_reset_complete(struct drm_device
*dev
)
510 pci_read_config_byte(dev
->pdev
, I965_GDRST
, &gdrst
);
514 static int i965_do_reset(struct drm_device
*dev
, u8 flags
)
519 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
520 * well as the reset bit (GR/bit 0). Setting the GR bit
521 * triggers the reset; when done, the hardware will clear it.
523 pci_read_config_byte(dev
->pdev
, I965_GDRST
, &gdrst
);
524 pci_write_config_byte(dev
->pdev
, I965_GDRST
, gdrst
| flags
| 0x1);
526 return wait_for(i965_reset_complete(dev
), 500);
529 static int ironlake_do_reset(struct drm_device
*dev
, u8 flags
)
531 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
532 u32 gdrst
= I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
);
533 I915_WRITE(MCHBAR_MIRROR_BASE
+ ILK_GDSR
, gdrst
| flags
| 0x1);
534 return wait_for(I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
) & 0x1, 500);
537 static int gen6_do_reset(struct drm_device
*dev
, u8 flags
)
539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
541 I915_WRITE(GEN6_GDRST
, GEN6_GRDOM_FULL
);
542 return wait_for((I915_READ(GEN6_GDRST
) & GEN6_GRDOM_FULL
) == 0, 500);
546 * i965_reset - reset chip after a hang
547 * @dev: drm device to reset
548 * @flags: reset domains
550 * Reset the chip. Useful if a hang is detected. Returns zero on successful
551 * reset or otherwise an error code.
553 * Procedure is fairly simple:
554 * - reset the chip using the reset reg
555 * - re-init context state
556 * - re-init hardware status page
557 * - re-init ring buffer
558 * - re-init interrupt state
561 int i915_reset(struct drm_device
*dev
, u8 flags
)
563 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
565 * We really should only reset the display subsystem if we actually
568 bool need_display
= true;
574 if (!mutex_trylock(&dev
->struct_mutex
))
580 if (get_seconds() - dev_priv
->last_gpu_reset
< 5) {
581 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
582 } else switch (INTEL_INFO(dev
)->gen
) {
585 ret
= gen6_do_reset(dev
, flags
);
586 /* If reset with a user forcewake, try to restore */
587 if (atomic_read(&dev_priv
->forcewake_count
))
588 __gen6_gt_force_wake_get(dev_priv
);
591 ret
= ironlake_do_reset(dev
, flags
);
594 ret
= i965_do_reset(dev
, flags
);
597 ret
= i8xx_do_reset(dev
, flags
);
600 dev_priv
->last_gpu_reset
= get_seconds();
602 DRM_ERROR("Failed to reset chip.\n");
603 mutex_unlock(&dev
->struct_mutex
);
607 /* Ok, now get things going again... */
610 * Everything depends on having the GTT running, so we need to start
611 * there. Fortunately we don't need to do this unless we reset the
612 * chip at a PCI level.
614 * Next we need to restore the context, but we don't use those
617 * Ring buffer needs to be re-initialized in the KMS case, or if X
618 * was running at the time of the reset (i.e. we weren't VT
621 if (drm_core_check_feature(dev
, DRIVER_MODESET
) ||
622 !dev_priv
->mm
.suspended
) {
623 dev_priv
->mm
.suspended
= 0;
625 dev_priv
->ring
[RCS
].init(&dev_priv
->ring
[RCS
]);
627 dev_priv
->ring
[VCS
].init(&dev_priv
->ring
[VCS
]);
629 dev_priv
->ring
[BCS
].init(&dev_priv
->ring
[BCS
]);
631 mutex_unlock(&dev
->struct_mutex
);
632 drm_irq_uninstall(dev
);
633 drm_mode_config_reset(dev
);
634 drm_irq_install(dev
);
635 mutex_lock(&dev
->struct_mutex
);
638 mutex_unlock(&dev
->struct_mutex
);
641 * Perform a full modeset as on later generations, e.g. Ironlake, we may
642 * need to retrain the display link and cannot just restore the register
646 mutex_lock(&dev
->mode_config
.mutex
);
647 drm_helper_resume_force_mode(dev
);
648 mutex_unlock(&dev
->mode_config
.mutex
);
656 i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
658 /* Only bind to function 0 of the device. Early generations
659 * used function 1 as a placeholder for multi-head. This causes
660 * us confusion instead, especially on the systems where both
661 * functions have the same PCI-ID!
663 if (PCI_FUNC(pdev
->devfn
))
666 return drm_get_pci_dev(pdev
, ent
, &driver
);
670 i915_pci_remove(struct pci_dev
*pdev
)
672 struct drm_device
*dev
= pci_get_drvdata(pdev
);
677 static int i915_pm_suspend(struct device
*dev
)
679 struct pci_dev
*pdev
= to_pci_dev(dev
);
680 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
683 if (!drm_dev
|| !drm_dev
->dev_private
) {
684 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
688 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
691 error
= i915_drm_freeze(drm_dev
);
695 pci_disable_device(pdev
);
696 pci_set_power_state(pdev
, PCI_D3hot
);
701 static int i915_pm_resume(struct device
*dev
)
703 struct pci_dev
*pdev
= to_pci_dev(dev
);
704 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
706 return i915_resume(drm_dev
);
709 static int i915_pm_freeze(struct device
*dev
)
711 struct pci_dev
*pdev
= to_pci_dev(dev
);
712 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
714 if (!drm_dev
|| !drm_dev
->dev_private
) {
715 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
719 return i915_drm_freeze(drm_dev
);
722 static int i915_pm_thaw(struct device
*dev
)
724 struct pci_dev
*pdev
= to_pci_dev(dev
);
725 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
727 return i915_drm_thaw(drm_dev
);
730 static int i915_pm_poweroff(struct device
*dev
)
732 struct pci_dev
*pdev
= to_pci_dev(dev
);
733 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
735 return i915_drm_freeze(drm_dev
);
738 static const struct dev_pm_ops i915_pm_ops
= {
739 .suspend
= i915_pm_suspend
,
740 .resume
= i915_pm_resume
,
741 .freeze
= i915_pm_freeze
,
742 .thaw
= i915_pm_thaw
,
743 .poweroff
= i915_pm_poweroff
,
744 .restore
= i915_pm_resume
,
747 static struct vm_operations_struct i915_gem_vm_ops
= {
748 .fault
= i915_gem_fault
,
749 .open
= drm_gem_vm_open
,
750 .close
= drm_gem_vm_close
,
753 static struct drm_driver driver
= {
754 /* don't use mtrr's here, the Xserver or user space app should
755 * deal with them for intel hardware.
758 DRIVER_USE_AGP
| DRIVER_REQUIRE_AGP
| /* DRIVER_USE_MTRR |*/
759 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
,
760 .load
= i915_driver_load
,
761 .unload
= i915_driver_unload
,
762 .open
= i915_driver_open
,
763 .lastclose
= i915_driver_lastclose
,
764 .preclose
= i915_driver_preclose
,
765 .postclose
= i915_driver_postclose
,
767 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
768 .suspend
= i915_suspend
,
769 .resume
= i915_resume
,
771 .device_is_agp
= i915_driver_device_is_agp
,
772 .reclaim_buffers
= drm_core_reclaim_buffers
,
773 .master_create
= i915_master_create
,
774 .master_destroy
= i915_master_destroy
,
775 #if defined(CONFIG_DEBUG_FS)
776 .debugfs_init
= i915_debugfs_init
,
777 .debugfs_cleanup
= i915_debugfs_cleanup
,
779 .gem_init_object
= i915_gem_init_object
,
780 .gem_free_object
= i915_gem_free_object
,
781 .gem_vm_ops
= &i915_gem_vm_ops
,
782 .dumb_create
= i915_gem_dumb_create
,
783 .dumb_map_offset
= i915_gem_mmap_gtt
,
784 .dumb_destroy
= i915_gem_dumb_destroy
,
785 .ioctls
= i915_ioctls
,
787 .owner
= THIS_MODULE
,
789 .release
= drm_release
,
790 .unlocked_ioctl
= drm_ioctl
,
791 .mmap
= drm_gem_mmap
,
793 .fasync
= drm_fasync
,
796 .compat_ioctl
= i915_compat_ioctl
,
798 .llseek
= noop_llseek
,
804 .major
= DRIVER_MAJOR
,
805 .minor
= DRIVER_MINOR
,
806 .patchlevel
= DRIVER_PATCHLEVEL
,
809 static struct pci_driver i915_pci_driver
= {
811 .id_table
= pciidlist
,
812 .probe
= i915_pci_probe
,
813 .remove
= i915_pci_remove
,
814 .driver
.pm
= &i915_pm_ops
,
817 static int __init
i915_init(void)
819 if (!intel_agp_enabled
) {
820 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
824 driver
.num_ioctls
= i915_max_ioctl
;
827 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
828 * explicitly disabled with the module pararmeter.
830 * Otherwise, just follow the parameter (defaulting to off).
832 * Allow optional vga_text_mode_force boot option to override
833 * the default behavior.
835 #if defined(CONFIG_DRM_I915_KMS)
836 if (i915_modeset
!= 0)
837 driver
.driver_features
|= DRIVER_MODESET
;
839 if (i915_modeset
== 1)
840 driver
.driver_features
|= DRIVER_MODESET
;
842 #ifdef CONFIG_VGA_CONSOLE
843 if (vgacon_text_force() && i915_modeset
== -1)
844 driver
.driver_features
&= ~DRIVER_MODESET
;
847 if (!(driver
.driver_features
& DRIVER_MODESET
))
848 driver
.get_vblank_timestamp
= NULL
;
850 return drm_pci_init(&driver
, &i915_pci_driver
);
853 static void __exit
i915_exit(void)
855 drm_pci_exit(&driver
, &i915_pci_driver
);
858 module_init(i915_init
);
859 module_exit(i915_exit
);
861 MODULE_AUTHOR(DRIVER_AUTHOR
);
862 MODULE_DESCRIPTION(DRIVER_DESC
);
863 MODULE_LICENSE("GPL and additional rights");