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e1000e: 82579 intermittently disabled during S0->Sx
[linux-2.6.git] / drivers / net / e1000e / ich8lan.c
blobdcd5db5e34e5d6577667a25af28622c8146622af
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
55 * 82579LM Gigabit Network Connection
56 * 82579V Gigabit Network Connection
57 */
58
59 #include "e1000.h"
60
61 #define ICH_FLASH_GFPREG 0x0000
62 #define ICH_FLASH_HSFSTS 0x0004
63 #define ICH_FLASH_HSFCTL 0x0006
64 #define ICH_FLASH_FADDR 0x0008
65 #define ICH_FLASH_FDATA0 0x0010
66 #define ICH_FLASH_PR0 0x0074
67
68 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
71 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
72 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
73
74 #define ICH_CYCLE_READ 0
75 #define ICH_CYCLE_WRITE 2
76 #define ICH_CYCLE_ERASE 3
77
78 #define FLASH_GFPREG_BASE_MASK 0x1FFF
79 #define FLASH_SECTOR_ADDR_SHIFT 12
80
81 #define ICH_FLASH_SEG_SIZE_256 256
82 #define ICH_FLASH_SEG_SIZE_4K 4096
83 #define ICH_FLASH_SEG_SIZE_8K 8192
84 #define ICH_FLASH_SEG_SIZE_64K 65536
85
86
87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
88 /* FW established a valid mode */
89 #define E1000_ICH_FWSM_FW_VALID 0x00008000
90
91 #define E1000_ICH_MNG_IAMT_MODE 0x2
92
93 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
94 (ID_LED_DEF1_OFF2 << 8) | \
95 (ID_LED_DEF1_ON2 << 4) | \
96 (ID_LED_DEF1_DEF2))
97
98 #define E1000_ICH_NVM_SIG_WORD 0x13
99 #define E1000_ICH_NVM_SIG_MASK 0xC000
100 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
101 #define E1000_ICH_NVM_SIG_VALUE 0x80
102
103 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
104
105 #define E1000_FEXTNVM_SW_CONFIG 1
106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
107
108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
111
112 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
113
114 #define E1000_ICH_RAR_ENTRIES 7
115
116 #define PHY_PAGE_SHIFT 5
117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
118 ((reg) & MAX_PHY_REG_ADDRESS))
119 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
120 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
121
122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
124 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
125
126 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
127
128 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
129
130 /* SMBus Address Phy Register */
131 #define HV_SMB_ADDR PHY_REG(768, 26)
132 #define HV_SMB_ADDR_MASK 0x007F
133 #define HV_SMB_ADDR_PEC_EN 0x0200
134 #define HV_SMB_ADDR_VALID 0x0080
135
136 /* PHY Power Management Control */
137 #define HV_PM_CTRL PHY_REG(770, 17)
138
139 /* PHY Low Power Idle Control */
140 #define I82579_LPI_CTRL PHY_REG(772, 20)
141 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000
142
143 /* EMI Registers */
144 #define I82579_EMI_ADDR 0x10
145 #define I82579_EMI_DATA 0x11
146 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
147
148 /* Strapping Option Register - RO */
149 #define E1000_STRAP 0x0000C
150 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
151 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
152
153 /* OEM Bits Phy Register */
154 #define HV_OEM_BITS PHY_REG(768, 25)
155 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
156 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
157 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
158
159 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
160 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
161
162 /* KMRN Mode Control */
163 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
164 #define HV_KMRN_MDIO_SLOW 0x0400
165
166 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
167 /* Offset 04h HSFSTS */
168 union ich8_hws_flash_status {
169 struct ich8_hsfsts {
170 u16 flcdone :1; /* bit 0 Flash Cycle Done */
171 u16 flcerr :1; /* bit 1 Flash Cycle Error */
172 u16 dael :1; /* bit 2 Direct Access error Log */
173 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
174 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
175 u16 reserved1 :2; /* bit 13:6 Reserved */
176 u16 reserved2 :6; /* bit 13:6 Reserved */
177 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
178 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
179 } hsf_status;
180 u16 regval;
181 };
182
183 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
184 /* Offset 06h FLCTL */
185 union ich8_hws_flash_ctrl {
186 struct ich8_hsflctl {
187 u16 flcgo :1; /* 0 Flash Cycle Go */
188 u16 flcycle :2; /* 2:1 Flash Cycle */
189 u16 reserved :5; /* 7:3 Reserved */
190 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
191 u16 flockdn :6; /* 15:10 Reserved */
192 } hsf_ctrl;
193 u16 regval;
194 };
195
196 /* ICH Flash Region Access Permissions */
197 union ich8_hws_flash_regacc {
198 struct ich8_flracc {
199 u32 grra :8; /* 0:7 GbE region Read Access */
200 u32 grwa :8; /* 8:15 GbE region Write Access */
201 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
202 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
203 } hsf_flregacc;
204 u16 regval;
205 };
206
207 /* ICH Flash Protected Region */
208 union ich8_flash_protected_range {
209 struct ich8_pr {
210 u32 base:13; /* 0:12 Protected Range Base */
211 u32 reserved1:2; /* 13:14 Reserved */
212 u32 rpe:1; /* 15 Read Protection Enable */
213 u32 limit:13; /* 16:28 Protected Range Limit */
214 u32 reserved2:2; /* 29:30 Reserved */
215 u32 wpe:1; /* 31 Write Protection Enable */
216 } range;
217 u32 regval;
218 };
219
220 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
221 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
222 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
223 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
224 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
225 u32 offset, u8 byte);
226 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
227 u8 *data);
228 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
229 u16 *data);
230 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
231 u8 size, u16 *data);
232 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
233 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
234 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
235 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
236 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
237 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
238 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
239 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
240 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
241 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
242 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
243 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
244 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
245 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
246 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
247 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
248 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
249 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
250 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
251 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
252
253 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
254 {
255 return readw(hw->flash_address + reg);
256 }
257
258 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
259 {
260 return readl(hw->flash_address + reg);
261 }
262
263 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
264 {
265 writew(val, hw->flash_address + reg);
266 }
267
268 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
269 {
270 writel(val, hw->flash_address + reg);
271 }
272
273 #define er16flash(reg) __er16flash(hw, (reg))
274 #define er32flash(reg) __er32flash(hw, (reg))
275 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
276 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
277
278 static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)
279 {
280 u32 ctrl;
281
282 ctrl = er32(CTRL);
283 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
284 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
285 ew32(CTRL, ctrl);
286 udelay(10);
287 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
288 ew32(CTRL, ctrl);
289 }
290
291 /**
292 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
293 * @hw: pointer to the HW structure
294 *
295 * Initialize family-specific PHY parameters and function pointers.
296 **/
297 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
298 {
299 struct e1000_phy_info *phy = &hw->phy;
300 u32 fwsm;
301 s32 ret_val = 0;
302
303 phy->addr = 1;
304 phy->reset_delay_us = 100;
305
306 phy->ops.read_reg = e1000_read_phy_reg_hv;
307 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
308 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
309 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
310 phy->ops.write_reg = e1000_write_phy_reg_hv;
311 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
312 phy->ops.power_up = e1000_power_up_phy_copper;
313 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
314 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
315
316 /*
317 * The MAC-PHY interconnect may still be in SMBus mode
318 * after Sx->S0. If the manageability engine (ME) is
319 * disabled, then toggle the LANPHYPC Value bit to force
320 * the interconnect to PCIe mode.
321 */
322 fwsm = er32(FWSM);
323 if (!(fwsm & E1000_ICH_FWSM_FW_VALID) && !e1000_check_reset_block(hw)) {
324 e1000_toggle_lanphypc_value_ich8lan(hw);
325 msleep(50);
326
327 /*
328 * Gate automatic PHY configuration by hardware on
329 * non-managed 82579
330 */
331 if (hw->mac.type == e1000_pch2lan)
332 e1000_gate_hw_phy_config_ich8lan(hw, true);
333 }
334
335 /*
336 * Reset the PHY before any access to it. Doing so, ensures that
337 * the PHY is in a known good state before we read/write PHY registers.
338 * The generic reset is sufficient here, because we haven't determined
339 * the PHY type yet.
340 */
341 ret_val = e1000e_phy_hw_reset_generic(hw);
342 if (ret_val)
343 goto out;
344
345 /* Ungate automatic PHY configuration on non-managed 82579 */
346 if ((hw->mac.type == e1000_pch2lan) &&
347 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
348 usleep_range(10000, 20000);
349 e1000_gate_hw_phy_config_ich8lan(hw, false);
350 }
351
352 phy->id = e1000_phy_unknown;
353 switch (hw->mac.type) {
354 default:
355 ret_val = e1000e_get_phy_id(hw);
356 if (ret_val)
357 goto out;
358 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
359 break;
360 /* fall-through */
361 case e1000_pch2lan:
362 /*
363 * In case the PHY needs to be in mdio slow mode,
364 * set slow mode and try to get the PHY id again.
365 */
366 ret_val = e1000_set_mdio_slow_mode_hv(hw);
367 if (ret_val)
368 goto out;
369 ret_val = e1000e_get_phy_id(hw);
370 if (ret_val)
371 goto out;
372 break;
373 }
374 phy->type = e1000e_get_phy_type_from_id(phy->id);
375
376 switch (phy->type) {
377 case e1000_phy_82577:
378 case e1000_phy_82579:
379 phy->ops.check_polarity = e1000_check_polarity_82577;
380 phy->ops.force_speed_duplex =
381 e1000_phy_force_speed_duplex_82577;
382 phy->ops.get_cable_length = e1000_get_cable_length_82577;
383 phy->ops.get_info = e1000_get_phy_info_82577;
384 phy->ops.commit = e1000e_phy_sw_reset;
385 break;
386 case e1000_phy_82578:
387 phy->ops.check_polarity = e1000_check_polarity_m88;
388 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
389 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
390 phy->ops.get_info = e1000e_get_phy_info_m88;
391 break;
392 default:
393 ret_val = -E1000_ERR_PHY;
394 break;
395 }
396
397 out:
398 return ret_val;
399 }
400
401 /**
402 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
403 * @hw: pointer to the HW structure
404 *
405 * Initialize family-specific PHY parameters and function pointers.
406 **/
407 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
408 {
409 struct e1000_phy_info *phy = &hw->phy;
410 s32 ret_val;
411 u16 i = 0;
412
413 phy->addr = 1;
414 phy->reset_delay_us = 100;
415
416 phy->ops.power_up = e1000_power_up_phy_copper;
417 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
418
419 /*
420 * We may need to do this twice - once for IGP and if that fails,
421 * we'll set BM func pointers and try again
422 */
423 ret_val = e1000e_determine_phy_address(hw);
424 if (ret_val) {
425 phy->ops.write_reg = e1000e_write_phy_reg_bm;
426 phy->ops.read_reg = e1000e_read_phy_reg_bm;
427 ret_val = e1000e_determine_phy_address(hw);
428 if (ret_val) {
429 e_dbg("Cannot determine PHY addr. Erroring out\n");
430 return ret_val;
431 }
432 }
433
434 phy->id = 0;
435 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
436 (i++ < 100)) {
437 usleep_range(1000, 2000);
438 ret_val = e1000e_get_phy_id(hw);
439 if (ret_val)
440 return ret_val;
441 }
442
443 /* Verify phy id */
444 switch (phy->id) {
445 case IGP03E1000_E_PHY_ID:
446 phy->type = e1000_phy_igp_3;
447 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
448 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
449 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
450 phy->ops.get_info = e1000e_get_phy_info_igp;
451 phy->ops.check_polarity = e1000_check_polarity_igp;
452 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
453 break;
454 case IFE_E_PHY_ID:
455 case IFE_PLUS_E_PHY_ID:
456 case IFE_C_E_PHY_ID:
457 phy->type = e1000_phy_ife;
458 phy->autoneg_mask = E1000_ALL_NOT_GIG;
459 phy->ops.get_info = e1000_get_phy_info_ife;
460 phy->ops.check_polarity = e1000_check_polarity_ife;
461 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
462 break;
463 case BME1000_E_PHY_ID:
464 phy->type = e1000_phy_bm;
465 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
466 phy->ops.read_reg = e1000e_read_phy_reg_bm;
467 phy->ops.write_reg = e1000e_write_phy_reg_bm;
468 phy->ops.commit = e1000e_phy_sw_reset;
469 phy->ops.get_info = e1000e_get_phy_info_m88;
470 phy->ops.check_polarity = e1000_check_polarity_m88;
471 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
472 break;
473 default:
474 return -E1000_ERR_PHY;
475 break;
476 }
477
478 return 0;
479 }
480
481 /**
482 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
483 * @hw: pointer to the HW structure
484 *
485 * Initialize family-specific NVM parameters and function
486 * pointers.
487 **/
488 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
489 {
490 struct e1000_nvm_info *nvm = &hw->nvm;
491 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
492 u32 gfpreg, sector_base_addr, sector_end_addr;
493 u16 i;
494
495 /* Can't read flash registers if the register set isn't mapped. */
496 if (!hw->flash_address) {
497 e_dbg("ERROR: Flash registers not mapped\n");
498 return -E1000_ERR_CONFIG;
499 }
500
501 nvm->type = e1000_nvm_flash_sw;
502
503 gfpreg = er32flash(ICH_FLASH_GFPREG);
504
505 /*
506 * sector_X_addr is a "sector"-aligned address (4096 bytes)
507 * Add 1 to sector_end_addr since this sector is included in
508 * the overall size.
509 */
510 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
511 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
512
513 /* flash_base_addr is byte-aligned */
514 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
515
516 /*
517 * find total size of the NVM, then cut in half since the total
518 * size represents two separate NVM banks.
519 */
520 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
521 << FLASH_SECTOR_ADDR_SHIFT;
522 nvm->flash_bank_size /= 2;
523 /* Adjust to word count */
524 nvm->flash_bank_size /= sizeof(u16);
525
526 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
527
528 /* Clear shadow ram */
529 for (i = 0; i < nvm->word_size; i++) {
530 dev_spec->shadow_ram[i].modified = false;
531 dev_spec->shadow_ram[i].value = 0xFFFF;
532 }
533
534 return 0;
535 }
536
537 /**
538 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
539 * @hw: pointer to the HW structure
540 *
541 * Initialize family-specific MAC parameters and function
542 * pointers.
543 **/
544 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
545 {
546 struct e1000_hw *hw = &adapter->hw;
547 struct e1000_mac_info *mac = &hw->mac;
548
549 /* Set media type function pointer */
550 hw->phy.media_type = e1000_media_type_copper;
551
552 /* Set mta register count */
553 mac->mta_reg_count = 32;
554 /* Set rar entry count */
555 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
556 if (mac->type == e1000_ich8lan)
557 mac->rar_entry_count--;
558 /* FWSM register */
559 mac->has_fwsm = true;
560 /* ARC subsystem not supported */
561 mac->arc_subsystem_valid = false;
562 /* Adaptive IFS supported */
563 mac->adaptive_ifs = true;
564
565 /* LED operations */
566 switch (mac->type) {
567 case e1000_ich8lan:
568 case e1000_ich9lan:
569 case e1000_ich10lan:
570 /* check management mode */
571 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
572 /* ID LED init */
573 mac->ops.id_led_init = e1000e_id_led_init;
574 /* blink LED */
575 mac->ops.blink_led = e1000e_blink_led_generic;
576 /* setup LED */
577 mac->ops.setup_led = e1000e_setup_led_generic;
578 /* cleanup LED */
579 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
580 /* turn on/off LED */
581 mac->ops.led_on = e1000_led_on_ich8lan;
582 mac->ops.led_off = e1000_led_off_ich8lan;
583 break;
584 case e1000_pchlan:
585 case e1000_pch2lan:
586 /* check management mode */
587 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
588 /* ID LED init */
589 mac->ops.id_led_init = e1000_id_led_init_pchlan;
590 /* setup LED */
591 mac->ops.setup_led = e1000_setup_led_pchlan;
592 /* cleanup LED */
593 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
594 /* turn on/off LED */
595 mac->ops.led_on = e1000_led_on_pchlan;
596 mac->ops.led_off = e1000_led_off_pchlan;
597 break;
598 default:
599 break;
600 }
601
602 /* Enable PCS Lock-loss workaround for ICH8 */
603 if (mac->type == e1000_ich8lan)
604 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
605
606 /* Gate automatic PHY configuration by hardware on managed 82579 */
607 if ((mac->type == e1000_pch2lan) &&
608 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
609 e1000_gate_hw_phy_config_ich8lan(hw, true);
610
611 return 0;
612 }
613
614 /**
615 * e1000_set_eee_pchlan - Enable/disable EEE support
616 * @hw: pointer to the HW structure
617 *
618 * Enable/disable EEE based on setting in dev_spec structure. The bits in
619 * the LPI Control register will remain set only if/when link is up.
620 **/
621 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
622 {
623 s32 ret_val = 0;
624 u16 phy_reg;
625
626 if (hw->phy.type != e1000_phy_82579)
627 goto out;
628
629 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
630 if (ret_val)
631 goto out;
632
633 if (hw->dev_spec.ich8lan.eee_disable)
634 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
635 else
636 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
637
638 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
639 out:
640 return ret_val;
641 }
642
643 /**
644 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
645 * @hw: pointer to the HW structure
646 *
647 * Checks to see of the link status of the hardware has changed. If a
648 * change in link status has been detected, then we read the PHY registers
649 * to get the current speed/duplex if link exists.
650 **/
651 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
652 {
653 struct e1000_mac_info *mac = &hw->mac;
654 s32 ret_val;
655 bool link;
656
657 /*
658 * We only want to go out to the PHY registers to see if Auto-Neg
659 * has completed and/or if our link status has changed. The
660 * get_link_status flag is set upon receiving a Link Status
661 * Change or Rx Sequence Error interrupt.
662 */
663 if (!mac->get_link_status) {
664 ret_val = 0;
665 goto out;
666 }
667
668 /*
669 * First we want to see if the MII Status Register reports
670 * link. If so, then we want to get the current speed/duplex
671 * of the PHY.
672 */
673 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
674 if (ret_val)
675 goto out;
676
677 if (hw->mac.type == e1000_pchlan) {
678 ret_val = e1000_k1_gig_workaround_hv(hw, link);
679 if (ret_val)
680 goto out;
681 }
682
683 if (!link)
684 goto out; /* No link detected */
685
686 mac->get_link_status = false;
687
688 if (hw->phy.type == e1000_phy_82578) {
689 ret_val = e1000_link_stall_workaround_hv(hw);
690 if (ret_val)
691 goto out;
692 }
693
694 if (hw->mac.type == e1000_pch2lan) {
695 ret_val = e1000_k1_workaround_lv(hw);
696 if (ret_val)
697 goto out;
698 }
699
700 /*
701 * Check if there was DownShift, must be checked
702 * immediately after link-up
703 */
704 e1000e_check_downshift(hw);
705
706 /* Enable/Disable EEE after link up */
707 ret_val = e1000_set_eee_pchlan(hw);
708 if (ret_val)
709 goto out;
710
711 /*
712 * If we are forcing speed/duplex, then we simply return since
713 * we have already determined whether we have link or not.
714 */
715 if (!mac->autoneg) {
716 ret_val = -E1000_ERR_CONFIG;
717 goto out;
718 }
719
720 /*
721 * Auto-Neg is enabled. Auto Speed Detection takes care
722 * of MAC speed/duplex configuration. So we only need to
723 * configure Collision Distance in the MAC.
724 */
725 e1000e_config_collision_dist(hw);
726
727 /*
728 * Configure Flow Control now that Auto-Neg has completed.
729 * First, we need to restore the desired flow control
730 * settings because we may have had to re-autoneg with a
731 * different link partner.
732 */
733 ret_val = e1000e_config_fc_after_link_up(hw);
734 if (ret_val)
735 e_dbg("Error configuring flow control\n");
736
737 out:
738 return ret_val;
739 }
740
741 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
742 {
743 struct e1000_hw *hw = &adapter->hw;
744 s32 rc;
745
746 rc = e1000_init_mac_params_ich8lan(adapter);
747 if (rc)
748 return rc;
749
750 rc = e1000_init_nvm_params_ich8lan(hw);
751 if (rc)
752 return rc;
753
754 switch (hw->mac.type) {
755 case e1000_ich8lan:
756 case e1000_ich9lan:
757 case e1000_ich10lan:
758 rc = e1000_init_phy_params_ich8lan(hw);
759 break;
760 case e1000_pchlan:
761 case e1000_pch2lan:
762 rc = e1000_init_phy_params_pchlan(hw);
763 break;
764 default:
765 break;
766 }
767 if (rc)
768 return rc;
769
770 /*
771 * Disable Jumbo Frame support on parts with Intel 10/100 PHY or
772 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
773 */
774 if ((adapter->hw.phy.type == e1000_phy_ife) ||
775 ((adapter->hw.mac.type >= e1000_pch2lan) &&
776 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
777 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
778 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
779
780 hw->mac.ops.blink_led = NULL;
781 }
782
783 if ((adapter->hw.mac.type == e1000_ich8lan) &&
784 (adapter->hw.phy.type == e1000_phy_igp_3))
785 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
786
787 /* Disable EEE by default until IEEE802.3az spec is finalized */
788 if (adapter->flags2 & FLAG2_HAS_EEE)
789 adapter->hw.dev_spec.ich8lan.eee_disable = true;
790
791 return 0;
792 }
793
794 static DEFINE_MUTEX(nvm_mutex);
795
796 /**
797 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
798 * @hw: pointer to the HW structure
799 *
800 * Acquires the mutex for performing NVM operations.
801 **/
802 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
803 {
804 mutex_lock(&nvm_mutex);
805
806 return 0;
807 }
808
809 /**
810 * e1000_release_nvm_ich8lan - Release NVM mutex
811 * @hw: pointer to the HW structure
812 *
813 * Releases the mutex used while performing NVM operations.
814 **/
815 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
816 {
817 mutex_unlock(&nvm_mutex);
818 }
819
820 static DEFINE_MUTEX(swflag_mutex);
821
822 /**
823 * e1000_acquire_swflag_ich8lan - Acquire software control flag
824 * @hw: pointer to the HW structure
825 *
826 * Acquires the software control flag for performing PHY and select
827 * MAC CSR accesses.
828 **/
829 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
830 {
831 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
832 s32 ret_val = 0;
833
834 mutex_lock(&swflag_mutex);
835
836 while (timeout) {
837 extcnf_ctrl = er32(EXTCNF_CTRL);
838 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
839 break;
840
841 mdelay(1);
842 timeout--;
843 }
844
845 if (!timeout) {
846 e_dbg("SW/FW/HW has locked the resource for too long.\n");
847 ret_val = -E1000_ERR_CONFIG;
848 goto out;
849 }
850
851 timeout = SW_FLAG_TIMEOUT;
852
853 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
854 ew32(EXTCNF_CTRL, extcnf_ctrl);
855
856 while (timeout) {
857 extcnf_ctrl = er32(EXTCNF_CTRL);
858 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
859 break;
860
861 mdelay(1);
862 timeout--;
863 }
864
865 if (!timeout) {
866 e_dbg("Failed to acquire the semaphore.\n");
867 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
868 ew32(EXTCNF_CTRL, extcnf_ctrl);
869 ret_val = -E1000_ERR_CONFIG;
870 goto out;
871 }
872
873 out:
874 if (ret_val)
875 mutex_unlock(&swflag_mutex);
876
877 return ret_val;
878 }
879
880 /**
881 * e1000_release_swflag_ich8lan - Release software control flag
882 * @hw: pointer to the HW structure
883 *
884 * Releases the software control flag for performing PHY and select
885 * MAC CSR accesses.
886 **/
887 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
888 {
889 u32 extcnf_ctrl;
890
891 extcnf_ctrl = er32(EXTCNF_CTRL);
892 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
893 ew32(EXTCNF_CTRL, extcnf_ctrl);
894
895 mutex_unlock(&swflag_mutex);
896 }
897
898 /**
899 * e1000_check_mng_mode_ich8lan - Checks management mode
900 * @hw: pointer to the HW structure
901 *
902 * This checks if the adapter has any manageability enabled.
903 * This is a function pointer entry point only called by read/write
904 * routines for the PHY and NVM parts.
905 **/
906 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
907 {
908 u32 fwsm;
909
910 fwsm = er32(FWSM);
911 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
912 ((fwsm & E1000_FWSM_MODE_MASK) ==
913 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
914 }
915
916 /**
917 * e1000_check_mng_mode_pchlan - Checks management mode
918 * @hw: pointer to the HW structure
919 *
920 * This checks if the adapter has iAMT enabled.
921 * This is a function pointer entry point only called by read/write
922 * routines for the PHY and NVM parts.
923 **/
924 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
925 {
926 u32 fwsm;
927
928 fwsm = er32(FWSM);
929 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
930 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
931 }
932
933 /**
934 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
935 * @hw: pointer to the HW structure
936 *
937 * Checks if firmware is blocking the reset of the PHY.
938 * This is a function pointer entry point only called by
939 * reset routines.
940 **/
941 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
942 {
943 u32 fwsm;
944
945 fwsm = er32(FWSM);
946
947 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
948 }
949
950 /**
951 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
952 * @hw: pointer to the HW structure
953 *
954 * Assumes semaphore already acquired.
955 *
956 **/
957 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
958 {
959 u16 phy_data;
960 u32 strap = er32(STRAP);
961 s32 ret_val = 0;
962
963 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
964
965 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
966 if (ret_val)
967 goto out;
968
969 phy_data &= ~HV_SMB_ADDR_MASK;
970 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
971 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
972 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
973
974 out:
975 return ret_val;
976 }
977
978 /**
979 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
980 * @hw: pointer to the HW structure
981 *
982 * SW should configure the LCD from the NVM extended configuration region
983 * as a workaround for certain parts.
984 **/
985 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
986 {
987 struct e1000_phy_info *phy = &hw->phy;
988 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
989 s32 ret_val = 0;
990 u16 word_addr, reg_data, reg_addr, phy_page = 0;
991
992 /*
993 * Initialize the PHY from the NVM on ICH platforms. This
994 * is needed due to an issue where the NVM configuration is
995 * not properly autoloaded after power transitions.
996 * Therefore, after each PHY reset, we will load the
997 * configuration data out of the NVM manually.
998 */
999 switch (hw->mac.type) {
1000 case e1000_ich8lan:
1001 if (phy->type != e1000_phy_igp_3)
1002 return ret_val;
1003
1004 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1005 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1006 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1007 break;
1008 }
1009 /* Fall-thru */
1010 case e1000_pchlan:
1011 case e1000_pch2lan:
1012 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1013 break;
1014 default:
1015 return ret_val;
1016 }
1017
1018 ret_val = hw->phy.ops.acquire(hw);
1019 if (ret_val)
1020 return ret_val;
1021
1022 data = er32(FEXTNVM);
1023 if (!(data & sw_cfg_mask))
1024 goto out;
1025
1026 /*
1027 * Make sure HW does not configure LCD from PHY
1028 * extended configuration before SW configuration
1029 */
1030 data = er32(EXTCNF_CTRL);
1031 if (!(hw->mac.type == e1000_pch2lan)) {
1032 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
1033 goto out;
1034 }
1035
1036 cnf_size = er32(EXTCNF_SIZE);
1037 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1038 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1039 if (!cnf_size)
1040 goto out;
1041
1042 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1043 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1044
1045 if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1046 (hw->mac.type == e1000_pchlan)) ||
1047 (hw->mac.type == e1000_pch2lan)) {
1048 /*
1049 * HW configures the SMBus address and LEDs when the
1050 * OEM and LCD Write Enable bits are set in the NVM.
1051 * When both NVM bits are cleared, SW will configure
1052 * them instead.
1053 */
1054 ret_val = e1000_write_smbus_addr(hw);
1055 if (ret_val)
1056 goto out;
1057
1058 data = er32(LEDCTL);
1059 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1060 (u16)data);
1061 if (ret_val)
1062 goto out;
1063 }
1064
1065 /* Configure LCD from extended configuration region. */
1066
1067 /* cnf_base_addr is in DWORD */
1068 word_addr = (u16)(cnf_base_addr << 1);
1069
1070 for (i = 0; i < cnf_size; i++) {
1071 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1072 &reg_data);
1073 if (ret_val)
1074 goto out;
1075
1076 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1077 1, &reg_addr);
1078 if (ret_val)
1079 goto out;
1080
1081 /* Save off the PHY page for future writes. */
1082 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1083 phy_page = reg_data;
1084 continue;
1085 }
1086
1087 reg_addr &= PHY_REG_MASK;
1088 reg_addr |= phy_page;
1089
1090 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1091 reg_data);
1092 if (ret_val)
1093 goto out;
1094 }
1095
1096 out:
1097 hw->phy.ops.release(hw);
1098 return ret_val;
1099 }
1100
1101 /**
1102 * e1000_k1_gig_workaround_hv - K1 Si workaround
1103 * @hw: pointer to the HW structure
1104 * @link: link up bool flag
1105 *
1106 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1107 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1108 * If link is down, the function will restore the default K1 setting located
1109 * in the NVM.
1110 **/
1111 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1112 {
1113 s32 ret_val = 0;
1114 u16 status_reg = 0;
1115 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1116
1117 if (hw->mac.type != e1000_pchlan)
1118 goto out;
1119
1120 /* Wrap the whole flow with the sw flag */
1121 ret_val = hw->phy.ops.acquire(hw);
1122 if (ret_val)
1123 goto out;
1124
1125 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1126 if (link) {
1127 if (hw->phy.type == e1000_phy_82578) {
1128 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1129 &status_reg);
1130 if (ret_val)
1131 goto release;
1132
1133 status_reg &= BM_CS_STATUS_LINK_UP |
1134 BM_CS_STATUS_RESOLVED |
1135 BM_CS_STATUS_SPEED_MASK;
1136
1137 if (status_reg == (BM_CS_STATUS_LINK_UP |
1138 BM_CS_STATUS_RESOLVED |
1139 BM_CS_STATUS_SPEED_1000))
1140 k1_enable = false;
1141 }
1142
1143 if (hw->phy.type == e1000_phy_82577) {
1144 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1145 &status_reg);
1146 if (ret_val)
1147 goto release;
1148
1149 status_reg &= HV_M_STATUS_LINK_UP |
1150 HV_M_STATUS_AUTONEG_COMPLETE |
1151 HV_M_STATUS_SPEED_MASK;
1152
1153 if (status_reg == (HV_M_STATUS_LINK_UP |
1154 HV_M_STATUS_AUTONEG_COMPLETE |
1155 HV_M_STATUS_SPEED_1000))
1156 k1_enable = false;
1157 }
1158
1159 /* Link stall fix for link up */
1160 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1161 0x0100);
1162 if (ret_val)
1163 goto release;
1164
1165 } else {
1166 /* Link stall fix for link down */
1167 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1168 0x4100);
1169 if (ret_val)
1170 goto release;
1171 }
1172
1173 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1174
1175 release:
1176 hw->phy.ops.release(hw);
1177 out:
1178 return ret_val;
1179 }
1180
1181 /**
1182 * e1000_configure_k1_ich8lan - Configure K1 power state
1183 * @hw: pointer to the HW structure
1184 * @enable: K1 state to configure
1185 *
1186 * Configure the K1 power state based on the provided parameter.
1187 * Assumes semaphore already acquired.
1188 *
1189 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1190 **/
1191 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1192 {
1193 s32 ret_val = 0;
1194 u32 ctrl_reg = 0;
1195 u32 ctrl_ext = 0;
1196 u32 reg = 0;
1197 u16 kmrn_reg = 0;
1198
1199 ret_val = e1000e_read_kmrn_reg_locked(hw,
1200 E1000_KMRNCTRLSTA_K1_CONFIG,
1201 &kmrn_reg);
1202 if (ret_val)
1203 goto out;
1204
1205 if (k1_enable)
1206 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1207 else
1208 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1209
1210 ret_val = e1000e_write_kmrn_reg_locked(hw,
1211 E1000_KMRNCTRLSTA_K1_CONFIG,
1212 kmrn_reg);
1213 if (ret_val)
1214 goto out;
1215
1216 udelay(20);
1217 ctrl_ext = er32(CTRL_EXT);
1218 ctrl_reg = er32(CTRL);
1219
1220 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1221 reg |= E1000_CTRL_FRCSPD;
1222 ew32(CTRL, reg);
1223
1224 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1225 udelay(20);
1226 ew32(CTRL, ctrl_reg);
1227 ew32(CTRL_EXT, ctrl_ext);
1228 udelay(20);
1229
1230 out:
1231 return ret_val;
1232 }
1233
1234 /**
1235 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1236 * @hw: pointer to the HW structure
1237 * @d0_state: boolean if entering d0 or d3 device state
1238 *
1239 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1240 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1241 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1242 **/
1243 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1244 {
1245 s32 ret_val = 0;
1246 u32 mac_reg;
1247 u16 oem_reg;
1248
1249 if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1250 return ret_val;
1251
1252 ret_val = hw->phy.ops.acquire(hw);
1253 if (ret_val)
1254 return ret_val;
1255
1256 if (!(hw->mac.type == e1000_pch2lan)) {
1257 mac_reg = er32(EXTCNF_CTRL);
1258 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1259 goto out;
1260 }
1261
1262 mac_reg = er32(FEXTNVM);
1263 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1264 goto out;
1265
1266 mac_reg = er32(PHY_CTRL);
1267
1268 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1269 if (ret_val)
1270 goto out;
1271
1272 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1273
1274 if (d0_state) {
1275 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1276 oem_reg |= HV_OEM_BITS_GBE_DIS;
1277
1278 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1279 oem_reg |= HV_OEM_BITS_LPLU;
1280 } else {
1281 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1282 oem_reg |= HV_OEM_BITS_GBE_DIS;
1283
1284 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1285 oem_reg |= HV_OEM_BITS_LPLU;
1286 }
1287 /* Restart auto-neg to activate the bits */
1288 if (!e1000_check_reset_block(hw))
1289 oem_reg |= HV_OEM_BITS_RESTART_AN;
1290 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1291
1292 out:
1293 hw->phy.ops.release(hw);
1294
1295 return ret_val;
1296 }
1297
1298
1299 /**
1300 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1301 * @hw: pointer to the HW structure
1302 **/
1303 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1304 {
1305 s32 ret_val;
1306 u16 data;
1307
1308 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1309 if (ret_val)
1310 return ret_val;
1311
1312 data |= HV_KMRN_MDIO_SLOW;
1313
1314 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1315
1316 return ret_val;
1317 }
1318
1319 /**
1320 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1321 * done after every PHY reset.
1322 **/
1323 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1324 {
1325 s32 ret_val = 0;
1326 u16 phy_data;
1327
1328 if (hw->mac.type != e1000_pchlan)
1329 return ret_val;
1330
1331 /* Set MDIO slow mode before any other MDIO access */
1332 if (hw->phy.type == e1000_phy_82577) {
1333 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1334 if (ret_val)
1335 goto out;
1336 }
1337
1338 if (((hw->phy.type == e1000_phy_82577) &&
1339 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1340 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1341 /* Disable generation of early preamble */
1342 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1343 if (ret_val)
1344 return ret_val;
1345
1346 /* Preamble tuning for SSC */
1347 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1348 if (ret_val)
1349 return ret_val;
1350 }
1351
1352 if (hw->phy.type == e1000_phy_82578) {
1353 /*
1354 * Return registers to default by doing a soft reset then
1355 * writing 0x3140 to the control register.
1356 */
1357 if (hw->phy.revision < 2) {
1358 e1000e_phy_sw_reset(hw);
1359 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1360 }
1361 }
1362
1363 /* Select page 0 */
1364 ret_val = hw->phy.ops.acquire(hw);
1365 if (ret_val)
1366 return ret_val;
1367
1368 hw->phy.addr = 1;
1369 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1370 hw->phy.ops.release(hw);
1371 if (ret_val)
1372 goto out;
1373
1374 /*
1375 * Configure the K1 Si workaround during phy reset assuming there is
1376 * link so that it disables K1 if link is in 1Gbps.
1377 */
1378 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1379 if (ret_val)
1380 goto out;
1381
1382 /* Workaround for link disconnects on a busy hub in half duplex */
1383 ret_val = hw->phy.ops.acquire(hw);
1384 if (ret_val)
1385 goto out;
1386 ret_val = hw->phy.ops.read_reg_locked(hw,
1387 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1388 &phy_data);
1389 if (ret_val)
1390 goto release;
1391 ret_val = hw->phy.ops.write_reg_locked(hw,
1392 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1393 phy_data & 0x00FF);
1394 release:
1395 hw->phy.ops.release(hw);
1396 out:
1397 return ret_val;
1398 }
1399
1400 /**
1401 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1402 * @hw: pointer to the HW structure
1403 **/
1404 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1405 {
1406 u32 mac_reg;
1407 u16 i;
1408
1409 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1410 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1411 mac_reg = er32(RAL(i));
1412 e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
1413 e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
1414 mac_reg = er32(RAH(i));
1415 e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
1416 e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
1417 }
1418 }
1419
1420 /**
1421 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1422 * with 82579 PHY
1423 * @hw: pointer to the HW structure
1424 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
1425 **/
1426 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1427 {
1428 s32 ret_val = 0;
1429 u16 phy_reg, data;
1430 u32 mac_reg;
1431 u16 i;
1432
1433 if (hw->mac.type != e1000_pch2lan)
1434 goto out;
1435
1436 /* disable Rx path while enabling/disabling workaround */
1437 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1438 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1439 if (ret_val)
1440 goto out;
1441
1442 if (enable) {
1443 /*
1444 * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1445 * SHRAL/H) and initial CRC values to the MAC
1446 */
1447 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1448 u8 mac_addr[ETH_ALEN] = {0};
1449 u32 addr_high, addr_low;
1450
1451 addr_high = er32(RAH(i));
1452 if (!(addr_high & E1000_RAH_AV))
1453 continue;
1454 addr_low = er32(RAL(i));
1455 mac_addr[0] = (addr_low & 0xFF);
1456 mac_addr[1] = ((addr_low >> 8) & 0xFF);
1457 mac_addr[2] = ((addr_low >> 16) & 0xFF);
1458 mac_addr[3] = ((addr_low >> 24) & 0xFF);
1459 mac_addr[4] = (addr_high & 0xFF);
1460 mac_addr[5] = ((addr_high >> 8) & 0xFF);
1461
1462 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1463 }
1464
1465 /* Write Rx addresses to the PHY */
1466 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1467
1468 /* Enable jumbo frame workaround in the MAC */
1469 mac_reg = er32(FFLT_DBG);
1470 mac_reg &= ~(1 << 14);
1471 mac_reg |= (7 << 15);
1472 ew32(FFLT_DBG, mac_reg);
1473
1474 mac_reg = er32(RCTL);
1475 mac_reg |= E1000_RCTL_SECRC;
1476 ew32(RCTL, mac_reg);
1477
1478 ret_val = e1000e_read_kmrn_reg(hw,
1479 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1480 &data);
1481 if (ret_val)
1482 goto out;
1483 ret_val = e1000e_write_kmrn_reg(hw,
1484 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1485 data | (1 << 0));
1486 if (ret_val)
1487 goto out;
1488 ret_val = e1000e_read_kmrn_reg(hw,
1489 E1000_KMRNCTRLSTA_HD_CTRL,
1490 &data);
1491 if (ret_val)
1492 goto out;
1493 data &= ~(0xF << 8);
1494 data |= (0xB << 8);
1495 ret_val = e1000e_write_kmrn_reg(hw,
1496 E1000_KMRNCTRLSTA_HD_CTRL,
1497 data);
1498 if (ret_val)
1499 goto out;
1500
1501 /* Enable jumbo frame workaround in the PHY */
1502 e1e_rphy(hw, PHY_REG(769, 23), &data);
1503 data &= ~(0x7F << 5);
1504 data |= (0x37 << 5);
1505 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1506 if (ret_val)
1507 goto out;
1508 e1e_rphy(hw, PHY_REG(769, 16), &data);
1509 data &= ~(1 << 13);
1510 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1511 if (ret_val)
1512 goto out;
1513 e1e_rphy(hw, PHY_REG(776, 20), &data);
1514 data &= ~(0x3FF << 2);
1515 data |= (0x1A << 2);
1516 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1517 if (ret_val)
1518 goto out;
1519 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
1520 if (ret_val)
1521 goto out;
1522 e1e_rphy(hw, HV_PM_CTRL, &data);
1523 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1524 if (ret_val)
1525 goto out;
1526 } else {
1527 /* Write MAC register values back to h/w defaults */
1528 mac_reg = er32(FFLT_DBG);
1529 mac_reg &= ~(0xF << 14);
1530 ew32(FFLT_DBG, mac_reg);
1531
1532 mac_reg = er32(RCTL);
1533 mac_reg &= ~E1000_RCTL_SECRC;
1534 ew32(RCTL, mac_reg);
1535
1536 ret_val = e1000e_read_kmrn_reg(hw,
1537 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1538 &data);
1539 if (ret_val)
1540 goto out;
1541 ret_val = e1000e_write_kmrn_reg(hw,
1542 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1543 data & ~(1 << 0));
1544 if (ret_val)
1545 goto out;
1546 ret_val = e1000e_read_kmrn_reg(hw,
1547 E1000_KMRNCTRLSTA_HD_CTRL,
1548 &data);
1549 if (ret_val)
1550 goto out;
1551 data &= ~(0xF << 8);
1552 data |= (0xB << 8);
1553 ret_val = e1000e_write_kmrn_reg(hw,
1554 E1000_KMRNCTRLSTA_HD_CTRL,
1555 data);
1556 if (ret_val)
1557 goto out;
1558
1559 /* Write PHY register values back to h/w defaults */
1560 e1e_rphy(hw, PHY_REG(769, 23), &data);
1561 data &= ~(0x7F << 5);
1562 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1563 if (ret_val)
1564 goto out;
1565 e1e_rphy(hw, PHY_REG(769, 16), &data);
1566 data |= (1 << 13);
1567 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1568 if (ret_val)
1569 goto out;
1570 e1e_rphy(hw, PHY_REG(776, 20), &data);
1571 data &= ~(0x3FF << 2);
1572 data |= (0x8 << 2);
1573 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1574 if (ret_val)
1575 goto out;
1576 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1577 if (ret_val)
1578 goto out;
1579 e1e_rphy(hw, HV_PM_CTRL, &data);
1580 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1581 if (ret_val)
1582 goto out;
1583 }
1584
1585 /* re-enable Rx path after enabling/disabling workaround */
1586 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1587
1588 out:
1589 return ret_val;
1590 }
1591
1592 /**
1593 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1594 * done after every PHY reset.
1595 **/
1596 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1597 {
1598 s32 ret_val = 0;
1599
1600 if (hw->mac.type != e1000_pch2lan)
1601 goto out;
1602
1603 /* Set MDIO slow mode before any other MDIO access */
1604 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1605
1606 out:
1607 return ret_val;
1608 }
1609
1610 /**
1611 * e1000_k1_gig_workaround_lv - K1 Si workaround
1612 * @hw: pointer to the HW structure
1613 *
1614 * Workaround to set the K1 beacon duration for 82579 parts
1615 **/
1616 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1617 {
1618 s32 ret_val = 0;
1619 u16 status_reg = 0;
1620 u32 mac_reg;
1621
1622 if (hw->mac.type != e1000_pch2lan)
1623 goto out;
1624
1625 /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1626 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1627 if (ret_val)
1628 goto out;
1629
1630 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1631 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1632 mac_reg = er32(FEXTNVM4);
1633 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1634
1635 if (status_reg & HV_M_STATUS_SPEED_1000)
1636 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1637 else
1638 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1639
1640 ew32(FEXTNVM4, mac_reg);
1641 }
1642
1643 out:
1644 return ret_val;
1645 }
1646
1647 /**
1648 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1649 * @hw: pointer to the HW structure
1650 * @gate: boolean set to true to gate, false to ungate
1651 *
1652 * Gate/ungate the automatic PHY configuration via hardware; perform
1653 * the configuration via software instead.
1654 **/
1655 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1656 {
1657 u32 extcnf_ctrl;
1658
1659 if (hw->mac.type != e1000_pch2lan)
1660 return;
1661
1662 extcnf_ctrl = er32(EXTCNF_CTRL);
1663
1664 if (gate)
1665 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1666 else
1667 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1668
1669 ew32(EXTCNF_CTRL, extcnf_ctrl);
1670 return;
1671 }
1672
1673 /**
1674 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1675 * @hw: pointer to the HW structure
1676 *
1677 * Check the appropriate indication the MAC has finished configuring the
1678 * PHY after a software reset.
1679 **/
1680 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1681 {
1682 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1683
1684 /* Wait for basic configuration completes before proceeding */
1685 do {
1686 data = er32(STATUS);
1687 data &= E1000_STATUS_LAN_INIT_DONE;
1688 udelay(100);
1689 } while ((!data) && --loop);
1690
1691 /*
1692 * If basic configuration is incomplete before the above loop
1693 * count reaches 0, loading the configuration from NVM will
1694 * leave the PHY in a bad state possibly resulting in no link.
1695 */
1696 if (loop == 0)
1697 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1698
1699 /* Clear the Init Done bit for the next init event */
1700 data = er32(STATUS);
1701 data &= ~E1000_STATUS_LAN_INIT_DONE;
1702 ew32(STATUS, data);
1703 }
1704
1705 /**
1706 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1707 * @hw: pointer to the HW structure
1708 **/
1709 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1710 {
1711 s32 ret_val = 0;
1712 u16 reg;
1713
1714 if (e1000_check_reset_block(hw))
1715 goto out;
1716
1717 /* Allow time for h/w to get to quiescent state after reset */
1718 usleep_range(10000, 20000);
1719
1720 /* Perform any necessary post-reset workarounds */
1721 switch (hw->mac.type) {
1722 case e1000_pchlan:
1723 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1724 if (ret_val)
1725 goto out;
1726 break;
1727 case e1000_pch2lan:
1728 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1729 if (ret_val)
1730 goto out;
1731 break;
1732 default:
1733 break;
1734 }
1735
1736 /* Dummy read to clear the phy wakeup bit after lcd reset */
1737 if (hw->mac.type >= e1000_pchlan)
1738 e1e_rphy(hw, BM_WUC, &reg);
1739
1740 /* Configure the LCD with the extended configuration region in NVM */
1741 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1742 if (ret_val)
1743 goto out;
1744
1745 /* Configure the LCD with the OEM bits in NVM */
1746 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1747
1748 if (hw->mac.type == e1000_pch2lan) {
1749 /* Ungate automatic PHY configuration on non-managed 82579 */
1750 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1751 usleep_range(10000, 20000);
1752 e1000_gate_hw_phy_config_ich8lan(hw, false);
1753 }
1754
1755 /* Set EEE LPI Update Timer to 200usec */
1756 ret_val = hw->phy.ops.acquire(hw);
1757 if (ret_val)
1758 goto out;
1759 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1760 I82579_LPI_UPDATE_TIMER);
1761 if (ret_val)
1762 goto release;
1763 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
1764 0x1387);
1765 release:
1766 hw->phy.ops.release(hw);
1767 }
1768
1769 out:
1770 return ret_val;
1771 }
1772
1773 /**
1774 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1775 * @hw: pointer to the HW structure
1776 *
1777 * Resets the PHY
1778 * This is a function pointer entry point called by drivers
1779 * or other shared routines.
1780 **/
1781 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1782 {
1783 s32 ret_val = 0;
1784
1785 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1786 if ((hw->mac.type == e1000_pch2lan) &&
1787 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1788 e1000_gate_hw_phy_config_ich8lan(hw, true);
1789
1790 ret_val = e1000e_phy_hw_reset_generic(hw);
1791 if (ret_val)
1792 goto out;
1793
1794 ret_val = e1000_post_phy_reset_ich8lan(hw);
1795
1796 out:
1797 return ret_val;
1798 }
1799
1800 /**
1801 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1802 * @hw: pointer to the HW structure
1803 * @active: true to enable LPLU, false to disable
1804 *
1805 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1806 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1807 * the phy speed. This function will manually set the LPLU bit and restart
1808 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1809 * since it configures the same bit.
1810 **/
1811 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1812 {
1813 s32 ret_val = 0;
1814 u16 oem_reg;
1815
1816 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1817 if (ret_val)
1818 goto out;
1819
1820 if (active)
1821 oem_reg |= HV_OEM_BITS_LPLU;
1822 else
1823 oem_reg &= ~HV_OEM_BITS_LPLU;
1824
1825 oem_reg |= HV_OEM_BITS_RESTART_AN;
1826 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1827
1828 out:
1829 return ret_val;
1830 }
1831
1832 /**
1833 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1834 * @hw: pointer to the HW structure
1835 * @active: true to enable LPLU, false to disable
1836 *
1837 * Sets the LPLU D0 state according to the active flag. When
1838 * activating LPLU this function also disables smart speed
1839 * and vice versa. LPLU will not be activated unless the
1840 * device autonegotiation advertisement meets standards of
1841 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1842 * This is a function pointer entry point only called by
1843 * PHY setup routines.
1844 **/
1845 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1846 {
1847 struct e1000_phy_info *phy = &hw->phy;
1848 u32 phy_ctrl;
1849 s32 ret_val = 0;
1850 u16 data;
1851
1852 if (phy->type == e1000_phy_ife)
1853 return ret_val;
1854
1855 phy_ctrl = er32(PHY_CTRL);
1856
1857 if (active) {
1858 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1859 ew32(PHY_CTRL, phy_ctrl);
1860
1861 if (phy->type != e1000_phy_igp_3)
1862 return 0;
1863
1864 /*
1865 * Call gig speed drop workaround on LPLU before accessing
1866 * any PHY registers
1867 */
1868 if (hw->mac.type == e1000_ich8lan)
1869 e1000e_gig_downshift_workaround_ich8lan(hw);
1870
1871 /* When LPLU is enabled, we should disable SmartSpeed */
1872 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1873 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1874 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1875 if (ret_val)
1876 return ret_val;
1877 } else {
1878 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1879 ew32(PHY_CTRL, phy_ctrl);
1880
1881 if (phy->type != e1000_phy_igp_3)
1882 return 0;
1883
1884 /*
1885 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1886 * during Dx states where the power conservation is most
1887 * important. During driver activity we should enable
1888 * SmartSpeed, so performance is maintained.
1889 */
1890 if (phy->smart_speed == e1000_smart_speed_on) {
1891 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1892 &data);
1893 if (ret_val)
1894 return ret_val;
1895
1896 data |= IGP01E1000_PSCFR_SMART_SPEED;
1897 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1898 data);
1899 if (ret_val)
1900 return ret_val;
1901 } else if (phy->smart_speed == e1000_smart_speed_off) {
1902 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1903 &data);
1904 if (ret_val)
1905 return ret_val;
1906
1907 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1908 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1909 data);
1910 if (ret_val)
1911 return ret_val;
1912 }
1913 }
1914
1915 return 0;
1916 }
1917
1918 /**
1919 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1920 * @hw: pointer to the HW structure
1921 * @active: true to enable LPLU, false to disable
1922 *
1923 * Sets the LPLU D3 state according to the active flag. When
1924 * activating LPLU this function also disables smart speed
1925 * and vice versa. LPLU will not be activated unless the
1926 * device autonegotiation advertisement meets standards of
1927 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1928 * This is a function pointer entry point only called by
1929 * PHY setup routines.
1930 **/
1931 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1932 {
1933 struct e1000_phy_info *phy = &hw->phy;
1934 u32 phy_ctrl;
1935 s32 ret_val;
1936 u16 data;
1937
1938 phy_ctrl = er32(PHY_CTRL);
1939
1940 if (!active) {
1941 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1942 ew32(PHY_CTRL, phy_ctrl);
1943
1944 if (phy->type != e1000_phy_igp_3)
1945 return 0;
1946
1947 /*
1948 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1949 * during Dx states where the power conservation is most
1950 * important. During driver activity we should enable
1951 * SmartSpeed, so performance is maintained.
1952 */
1953 if (phy->smart_speed == e1000_smart_speed_on) {
1954 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1955 &data);
1956 if (ret_val)
1957 return ret_val;
1958
1959 data |= IGP01E1000_PSCFR_SMART_SPEED;
1960 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1961 data);
1962 if (ret_val)
1963 return ret_val;
1964 } else if (phy->smart_speed == e1000_smart_speed_off) {
1965 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1966 &data);
1967 if (ret_val)
1968 return ret_val;
1969
1970 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1971 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1972 data);
1973 if (ret_val)
1974 return ret_val;
1975 }
1976 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1977 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1978 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1979 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1980 ew32(PHY_CTRL, phy_ctrl);
1981
1982 if (phy->type != e1000_phy_igp_3)
1983 return 0;
1984
1985 /*
1986 * Call gig speed drop workaround on LPLU before accessing
1987 * any PHY registers
1988 */
1989 if (hw->mac.type == e1000_ich8lan)
1990 e1000e_gig_downshift_workaround_ich8lan(hw);
1991
1992 /* When LPLU is enabled, we should disable SmartSpeed */
1993 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1994 if (ret_val)
1995 return ret_val;
1996
1997 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1998 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1999 }
2000
2001 return 0;
2002 }
2003
2004 /**
2005 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2006 * @hw: pointer to the HW structure
2007 * @bank: pointer to the variable that returns the active bank
2008 *
2009 * Reads signature byte from the NVM using the flash access registers.
2010 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2011 **/
2012 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2013 {
2014 u32 eecd;
2015 struct e1000_nvm_info *nvm = &hw->nvm;
2016 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2017 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2018 u8 sig_byte = 0;
2019 s32 ret_val = 0;
2020
2021 switch (hw->mac.type) {
2022 case e1000_ich8lan:
2023 case e1000_ich9lan:
2024 eecd = er32(EECD);
2025 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2026 E1000_EECD_SEC1VAL_VALID_MASK) {
2027 if (eecd & E1000_EECD_SEC1VAL)
2028 *bank = 1;
2029 else
2030 *bank = 0;
2031
2032 return 0;
2033 }
2034 e_dbg("Unable to determine valid NVM bank via EEC - "
2035 "reading flash signature\n");
2036 /* fall-thru */
2037 default:
2038 /* set bank to 0 in case flash read fails */
2039 *bank = 0;
2040
2041 /* Check bank 0 */
2042 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2043 &sig_byte);
2044 if (ret_val)
2045 return ret_val;
2046 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2047 E1000_ICH_NVM_SIG_VALUE) {
2048 *bank = 0;
2049 return 0;
2050 }
2051
2052 /* Check bank 1 */
2053 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2054 bank1_offset,
2055 &sig_byte);
2056 if (ret_val)
2057 return ret_val;
2058 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2059 E1000_ICH_NVM_SIG_VALUE) {
2060 *bank = 1;
2061 return 0;
2062 }
2063
2064 e_dbg("ERROR: No valid NVM bank present\n");
2065 return -E1000_ERR_NVM;
2066 }
2067
2068 return 0;
2069 }
2070
2071 /**
2072 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
2073 * @hw: pointer to the HW structure
2074 * @offset: The offset (in bytes) of the word(s) to read.
2075 * @words: Size of data to read in words
2076 * @data: Pointer to the word(s) to read at offset.
2077 *
2078 * Reads a word(s) from the NVM using the flash access registers.
2079 **/
2080 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2081 u16 *data)
2082 {
2083 struct e1000_nvm_info *nvm = &hw->nvm;
2084 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2085 u32 act_offset;
2086 s32 ret_val = 0;
2087 u32 bank = 0;
2088 u16 i, word;
2089
2090 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2091 (words == 0)) {
2092 e_dbg("nvm parameter(s) out of bounds\n");
2093 ret_val = -E1000_ERR_NVM;
2094 goto out;
2095 }
2096
2097 nvm->ops.acquire(hw);
2098
2099 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2100 if (ret_val) {
2101 e_dbg("Could not detect valid bank, assuming bank 0\n");
2102 bank = 0;
2103 }
2104
2105 act_offset = (bank) ? nvm->flash_bank_size : 0;
2106 act_offset += offset;
2107
2108 ret_val = 0;
2109 for (i = 0; i < words; i++) {
2110 if ((dev_spec->shadow_ram) &&
2111 (dev_spec->shadow_ram[offset+i].modified)) {
2112 data[i] = dev_spec->shadow_ram[offset+i].value;
2113 } else {
2114 ret_val = e1000_read_flash_word_ich8lan(hw,
2115 act_offset + i,
2116 &word);
2117 if (ret_val)
2118 break;
2119 data[i] = word;
2120 }
2121 }
2122
2123 nvm->ops.release(hw);
2124
2125 out:
2126 if (ret_val)
2127 e_dbg("NVM read error: %d\n", ret_val);
2128
2129 return ret_val;
2130 }
2131
2132 /**
2133 * e1000_flash_cycle_init_ich8lan - Initialize flash
2134 * @hw: pointer to the HW structure
2135 *
2136 * This function does initial flash setup so that a new read/write/erase cycle
2137 * can be started.
2138 **/
2139 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2140 {
2141 union ich8_hws_flash_status hsfsts;
2142 s32 ret_val = -E1000_ERR_NVM;
2143
2144 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2145
2146 /* Check if the flash descriptor is valid */
2147 if (hsfsts.hsf_status.fldesvalid == 0) {
2148 e_dbg("Flash descriptor invalid. "
2149 "SW Sequencing must be used.\n");
2150 return -E1000_ERR_NVM;
2151 }
2152
2153 /* Clear FCERR and DAEL in hw status by writing 1 */
2154 hsfsts.hsf_status.flcerr = 1;
2155 hsfsts.hsf_status.dael = 1;
2156
2157 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2158
2159 /*
2160 * Either we should have a hardware SPI cycle in progress
2161 * bit to check against, in order to start a new cycle or
2162 * FDONE bit should be changed in the hardware so that it
2163 * is 1 after hardware reset, which can then be used as an
2164 * indication whether a cycle is in progress or has been
2165 * completed.
2166 */
2167
2168 if (hsfsts.hsf_status.flcinprog == 0) {
2169 /*
2170 * There is no cycle running at present,
2171 * so we can start a cycle.
2172 * Begin by setting Flash Cycle Done.
2173 */
2174 hsfsts.hsf_status.flcdone = 1;
2175 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2176 ret_val = 0;
2177 } else {
2178 s32 i = 0;
2179
2180 /*
2181 * Otherwise poll for sometime so the current
2182 * cycle has a chance to end before giving up.
2183 */
2184 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2185 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2186 if (hsfsts.hsf_status.flcinprog == 0) {
2187 ret_val = 0;
2188 break;
2189 }
2190 udelay(1);
2191 }
2192 if (ret_val == 0) {
2193 /*
2194 * Successful in waiting for previous cycle to timeout,
2195 * now set the Flash Cycle Done.
2196 */
2197 hsfsts.hsf_status.flcdone = 1;
2198 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2199 } else {
2200 e_dbg("Flash controller busy, cannot get access\n");
2201 }
2202 }
2203
2204 return ret_val;
2205 }
2206
2207 /**
2208 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2209 * @hw: pointer to the HW structure
2210 * @timeout: maximum time to wait for completion
2211 *
2212 * This function starts a flash cycle and waits for its completion.
2213 **/
2214 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2215 {
2216 union ich8_hws_flash_ctrl hsflctl;
2217 union ich8_hws_flash_status hsfsts;
2218 s32 ret_val = -E1000_ERR_NVM;
2219 u32 i = 0;
2220
2221 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2222 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2223 hsflctl.hsf_ctrl.flcgo = 1;
2224 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2225
2226 /* wait till FDONE bit is set to 1 */
2227 do {
2228 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2229 if (hsfsts.hsf_status.flcdone == 1)
2230 break;
2231 udelay(1);
2232 } while (i++ < timeout);
2233
2234 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2235 return 0;
2236
2237 return ret_val;
2238 }
2239
2240 /**
2241 * e1000_read_flash_word_ich8lan - Read word from flash
2242 * @hw: pointer to the HW structure
2243 * @offset: offset to data location
2244 * @data: pointer to the location for storing the data
2245 *
2246 * Reads the flash word at offset into data. Offset is converted
2247 * to bytes before read.
2248 **/
2249 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2250 u16 *data)
2251 {
2252 /* Must convert offset into bytes. */
2253 offset <<= 1;
2254
2255 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2256 }
2257
2258 /**
2259 * e1000_read_flash_byte_ich8lan - Read byte from flash
2260 * @hw: pointer to the HW structure
2261 * @offset: The offset of the byte to read.
2262 * @data: Pointer to a byte to store the value read.
2263 *
2264 * Reads a single byte from the NVM using the flash access registers.
2265 **/
2266 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2267 u8 *data)
2268 {
2269 s32 ret_val;
2270 u16 word = 0;
2271
2272 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2273 if (ret_val)
2274 return ret_val;
2275
2276 *data = (u8)word;
2277
2278 return 0;
2279 }
2280
2281 /**
2282 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
2283 * @hw: pointer to the HW structure
2284 * @offset: The offset (in bytes) of the byte or word to read.
2285 * @size: Size of data to read, 1=byte 2=word
2286 * @data: Pointer to the word to store the value read.
2287 *
2288 * Reads a byte or word from the NVM using the flash access registers.
2289 **/
2290 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2291 u8 size, u16 *data)
2292 {
2293 union ich8_hws_flash_status hsfsts;
2294 union ich8_hws_flash_ctrl hsflctl;
2295 u32 flash_linear_addr;
2296 u32 flash_data = 0;
2297 s32 ret_val = -E1000_ERR_NVM;
2298 u8 count = 0;
2299
2300 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2301 return -E1000_ERR_NVM;
2302
2303 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2304 hw->nvm.flash_base_addr;
2305
2306 do {
2307 udelay(1);
2308 /* Steps */
2309 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2310 if (ret_val != 0)
2311 break;
2312
2313 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2314 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2315 hsflctl.hsf_ctrl.fldbcount = size - 1;
2316 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2317 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2318
2319 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2320
2321 ret_val = e1000_flash_cycle_ich8lan(hw,
2322 ICH_FLASH_READ_COMMAND_TIMEOUT);
2323
2324 /*
2325 * Check if FCERR is set to 1, if set to 1, clear it
2326 * and try the whole sequence a few more times, else
2327 * read in (shift in) the Flash Data0, the order is
2328 * least significant byte first msb to lsb
2329 */
2330 if (ret_val == 0) {
2331 flash_data = er32flash(ICH_FLASH_FDATA0);
2332 if (size == 1)
2333 *data = (u8)(flash_data & 0x000000FF);
2334 else if (size == 2)
2335 *data = (u16)(flash_data & 0x0000FFFF);
2336 break;
2337 } else {
2338 /*
2339 * If we've gotten here, then things are probably
2340 * completely hosed, but if the error condition is
2341 * detected, it won't hurt to give it another try...
2342 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2343 */
2344 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2345 if (hsfsts.hsf_status.flcerr == 1) {
2346 /* Repeat for some time before giving up. */
2347 continue;
2348 } else if (hsfsts.hsf_status.flcdone == 0) {
2349 e_dbg("Timeout error - flash cycle "
2350 "did not complete.\n");
2351 break;
2352 }
2353 }
2354 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2355
2356 return ret_val;
2357 }
2358
2359 /**
2360 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2361 * @hw: pointer to the HW structure
2362 * @offset: The offset (in bytes) of the word(s) to write.
2363 * @words: Size of data to write in words
2364 * @data: Pointer to the word(s) to write at offset.
2365 *
2366 * Writes a byte or word to the NVM using the flash access registers.
2367 **/
2368 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2369 u16 *data)
2370 {
2371 struct e1000_nvm_info *nvm = &hw->nvm;
2372 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2373 u16 i;
2374
2375 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2376 (words == 0)) {
2377 e_dbg("nvm parameter(s) out of bounds\n");
2378 return -E1000_ERR_NVM;
2379 }
2380
2381 nvm->ops.acquire(hw);
2382
2383 for (i = 0; i < words; i++) {
2384 dev_spec->shadow_ram[offset+i].modified = true;
2385 dev_spec->shadow_ram[offset+i].value = data[i];
2386 }
2387
2388 nvm->ops.release(hw);
2389
2390 return 0;
2391 }
2392
2393 /**
2394 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2395 * @hw: pointer to the HW structure
2396 *
2397 * The NVM checksum is updated by calling the generic update_nvm_checksum,
2398 * which writes the checksum to the shadow ram. The changes in the shadow
2399 * ram are then committed to the EEPROM by processing each bank at a time
2400 * checking for the modified bit and writing only the pending changes.
2401 * After a successful commit, the shadow ram is cleared and is ready for
2402 * future writes.
2403 **/
2404 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2405 {
2406 struct e1000_nvm_info *nvm = &hw->nvm;
2407 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2408 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2409 s32 ret_val;
2410 u16 data;
2411
2412 ret_val = e1000e_update_nvm_checksum_generic(hw);
2413 if (ret_val)
2414 goto out;
2415
2416 if (nvm->type != e1000_nvm_flash_sw)
2417 goto out;
2418
2419 nvm->ops.acquire(hw);
2420
2421 /*
2422 * We're writing to the opposite bank so if we're on bank 1,
2423 * write to bank 0 etc. We also need to erase the segment that
2424 * is going to be written
2425 */
2426 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2427 if (ret_val) {
2428 e_dbg("Could not detect valid bank, assuming bank 0\n");
2429 bank = 0;
2430 }
2431
2432 if (bank == 0) {
2433 new_bank_offset = nvm->flash_bank_size;
2434 old_bank_offset = 0;
2435 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2436 if (ret_val)
2437 goto release;
2438 } else {
2439 old_bank_offset = nvm->flash_bank_size;
2440 new_bank_offset = 0;
2441 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2442 if (ret_val)
2443 goto release;
2444 }
2445
2446 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2447 /*
2448 * Determine whether to write the value stored
2449 * in the other NVM bank or a modified value stored
2450 * in the shadow RAM
2451 */
2452 if (dev_spec->shadow_ram[i].modified) {
2453 data = dev_spec->shadow_ram[i].value;
2454 } else {
2455 ret_val = e1000_read_flash_word_ich8lan(hw, i +
2456 old_bank_offset,
2457 &data);
2458 if (ret_val)
2459 break;
2460 }
2461
2462 /*
2463 * If the word is 0x13, then make sure the signature bits
2464 * (15:14) are 11b until the commit has completed.
2465 * This will allow us to write 10b which indicates the
2466 * signature is valid. We want to do this after the write
2467 * has completed so that we don't mark the segment valid
2468 * while the write is still in progress
2469 */
2470 if (i == E1000_ICH_NVM_SIG_WORD)
2471 data |= E1000_ICH_NVM_SIG_MASK;
2472
2473 /* Convert offset to bytes. */
2474 act_offset = (i + new_bank_offset) << 1;
2475
2476 udelay(100);
2477 /* Write the bytes to the new bank. */
2478 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2479 act_offset,
2480 (u8)data);
2481 if (ret_val)
2482 break;
2483
2484 udelay(100);
2485 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2486 act_offset + 1,
2487 (u8)(data >> 8));
2488 if (ret_val)
2489 break;
2490 }
2491
2492 /*
2493 * Don't bother writing the segment valid bits if sector
2494 * programming failed.
2495 */
2496 if (ret_val) {
2497 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2498 e_dbg("Flash commit failed.\n");
2499 goto release;
2500 }
2501
2502 /*
2503 * Finally validate the new segment by setting bit 15:14
2504 * to 10b in word 0x13 , this can be done without an
2505 * erase as well since these bits are 11 to start with
2506 * and we need to change bit 14 to 0b
2507 */
2508 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2509 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2510 if (ret_val)
2511 goto release;
2512
2513 data &= 0xBFFF;
2514 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2515 act_offset * 2 + 1,
2516 (u8)(data >> 8));
2517 if (ret_val)
2518 goto release;
2519
2520 /*
2521 * And invalidate the previously valid segment by setting
2522 * its signature word (0x13) high_byte to 0b. This can be
2523 * done without an erase because flash erase sets all bits
2524 * to 1's. We can write 1's to 0's without an erase
2525 */
2526 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2527 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2528 if (ret_val)
2529 goto release;
2530
2531 /* Great! Everything worked, we can now clear the cached entries. */
2532 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2533 dev_spec->shadow_ram[i].modified = false;
2534 dev_spec->shadow_ram[i].value = 0xFFFF;
2535 }
2536
2537 release:
2538 nvm->ops.release(hw);
2539
2540 /*
2541 * Reload the EEPROM, or else modifications will not appear
2542 * until after the next adapter reset.
2543 */
2544 if (!ret_val) {
2545 e1000e_reload_nvm(hw);
2546 usleep_range(10000, 20000);
2547 }
2548
2549 out:
2550 if (ret_val)
2551 e_dbg("NVM update error: %d\n", ret_val);
2552
2553 return ret_val;
2554 }
2555
2556 /**
2557 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2558 * @hw: pointer to the HW structure
2559 *
2560 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2561 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2562 * calculated, in which case we need to calculate the checksum and set bit 6.
2563 **/
2564 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2565 {
2566 s32 ret_val;
2567 u16 data;
2568
2569 /*
2570 * Read 0x19 and check bit 6. If this bit is 0, the checksum
2571 * needs to be fixed. This bit is an indication that the NVM
2572 * was prepared by OEM software and did not calculate the
2573 * checksum...a likely scenario.
2574 */
2575 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2576 if (ret_val)
2577 return ret_val;
2578
2579 if ((data & 0x40) == 0) {
2580 data |= 0x40;
2581 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2582 if (ret_val)
2583 return ret_val;
2584 ret_val = e1000e_update_nvm_checksum(hw);
2585 if (ret_val)
2586 return ret_val;
2587 }
2588
2589 return e1000e_validate_nvm_checksum_generic(hw);
2590 }
2591
2592 /**
2593 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2594 * @hw: pointer to the HW structure
2595 *
2596 * To prevent malicious write/erase of the NVM, set it to be read-only
2597 * so that the hardware ignores all write/erase cycles of the NVM via
2598 * the flash control registers. The shadow-ram copy of the NVM will
2599 * still be updated, however any updates to this copy will not stick
2600 * across driver reloads.
2601 **/
2602 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2603 {
2604 struct e1000_nvm_info *nvm = &hw->nvm;
2605 union ich8_flash_protected_range pr0;
2606 union ich8_hws_flash_status hsfsts;
2607 u32 gfpreg;
2608
2609 nvm->ops.acquire(hw);
2610
2611 gfpreg = er32flash(ICH_FLASH_GFPREG);
2612
2613 /* Write-protect GbE Sector of NVM */
2614 pr0.regval = er32flash(ICH_FLASH_PR0);
2615 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2616 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2617 pr0.range.wpe = true;
2618 ew32flash(ICH_FLASH_PR0, pr0.regval);
2619
2620 /*
2621 * Lock down a subset of GbE Flash Control Registers, e.g.
2622 * PR0 to prevent the write-protection from being lifted.
2623 * Once FLOCKDN is set, the registers protected by it cannot
2624 * be written until FLOCKDN is cleared by a hardware reset.
2625 */
2626 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2627 hsfsts.hsf_status.flockdn = true;
2628 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2629
2630 nvm->ops.release(hw);
2631 }
2632
2633 /**
2634 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2635 * @hw: pointer to the HW structure
2636 * @offset: The offset (in bytes) of the byte/word to read.
2637 * @size: Size of data to read, 1=byte 2=word
2638 * @data: The byte(s) to write to the NVM.
2639 *
2640 * Writes one/two bytes to the NVM using the flash access registers.
2641 **/
2642 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2643 u8 size, u16 data)
2644 {
2645 union ich8_hws_flash_status hsfsts;
2646 union ich8_hws_flash_ctrl hsflctl;
2647 u32 flash_linear_addr;
2648 u32 flash_data = 0;
2649 s32 ret_val;
2650 u8 count = 0;
2651
2652 if (size < 1 || size > 2 || data > size * 0xff ||
2653 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2654 return -E1000_ERR_NVM;
2655
2656 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2657 hw->nvm.flash_base_addr;
2658
2659 do {
2660 udelay(1);
2661 /* Steps */
2662 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2663 if (ret_val)
2664 break;
2665
2666 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2667 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2668 hsflctl.hsf_ctrl.fldbcount = size -1;
2669 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2670 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2671
2672 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2673
2674 if (size == 1)
2675 flash_data = (u32)data & 0x00FF;
2676 else
2677 flash_data = (u32)data;
2678
2679 ew32flash(ICH_FLASH_FDATA0, flash_data);
2680
2681 /*
2682 * check if FCERR is set to 1 , if set to 1, clear it
2683 * and try the whole sequence a few more times else done
2684 */
2685 ret_val = e1000_flash_cycle_ich8lan(hw,
2686 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2687 if (!ret_val)
2688 break;
2689
2690 /*
2691 * If we're here, then things are most likely
2692 * completely hosed, but if the error condition
2693 * is detected, it won't hurt to give it another
2694 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2695 */
2696 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2697 if (hsfsts.hsf_status.flcerr == 1)
2698 /* Repeat for some time before giving up. */
2699 continue;
2700 if (hsfsts.hsf_status.flcdone == 0) {
2701 e_dbg("Timeout error - flash cycle "
2702 "did not complete.");
2703 break;
2704 }
2705 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2706
2707 return ret_val;
2708 }
2709
2710 /**
2711 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2712 * @hw: pointer to the HW structure
2713 * @offset: The index of the byte to read.
2714 * @data: The byte to write to the NVM.
2715 *
2716 * Writes a single byte to the NVM using the flash access registers.
2717 **/
2718 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2719 u8 data)
2720 {
2721 u16 word = (u16)data;
2722
2723 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2724 }
2725
2726 /**
2727 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2728 * @hw: pointer to the HW structure
2729 * @offset: The offset of the byte to write.
2730 * @byte: The byte to write to the NVM.
2731 *
2732 * Writes a single byte to the NVM using the flash access registers.
2733 * Goes through a retry algorithm before giving up.
2734 **/
2735 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2736 u32 offset, u8 byte)
2737 {
2738 s32 ret_val;
2739 u16 program_retries;
2740
2741 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2742 if (!ret_val)
2743 return ret_val;
2744
2745 for (program_retries = 0; program_retries < 100; program_retries++) {
2746 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2747 udelay(100);
2748 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2749 if (!ret_val)
2750 break;
2751 }
2752 if (program_retries == 100)
2753 return -E1000_ERR_NVM;
2754
2755 return 0;
2756 }
2757
2758 /**
2759 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2760 * @hw: pointer to the HW structure
2761 * @bank: 0 for first bank, 1 for second bank, etc.
2762 *
2763 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2764 * bank N is 4096 * N + flash_reg_addr.
2765 **/
2766 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2767 {
2768 struct e1000_nvm_info *nvm = &hw->nvm;
2769 union ich8_hws_flash_status hsfsts;
2770 union ich8_hws_flash_ctrl hsflctl;
2771 u32 flash_linear_addr;
2772 /* bank size is in 16bit words - adjust to bytes */
2773 u32 flash_bank_size = nvm->flash_bank_size * 2;
2774 s32 ret_val;
2775 s32 count = 0;
2776 s32 j, iteration, sector_size;
2777
2778 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2779
2780 /*
2781 * Determine HW Sector size: Read BERASE bits of hw flash status
2782 * register
2783 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2784 * consecutive sectors. The start index for the nth Hw sector
2785 * can be calculated as = bank * 4096 + n * 256
2786 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2787 * The start index for the nth Hw sector can be calculated
2788 * as = bank * 4096
2789 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2790 * (ich9 only, otherwise error condition)
2791 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2792 */
2793 switch (hsfsts.hsf_status.berasesz) {
2794 case 0:
2795 /* Hw sector size 256 */
2796 sector_size = ICH_FLASH_SEG_SIZE_256;
2797 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2798 break;
2799 case 1:
2800 sector_size = ICH_FLASH_SEG_SIZE_4K;
2801 iteration = 1;
2802 break;
2803 case 2:
2804 sector_size = ICH_FLASH_SEG_SIZE_8K;
2805 iteration = 1;
2806 break;
2807 case 3:
2808 sector_size = ICH_FLASH_SEG_SIZE_64K;
2809 iteration = 1;
2810 break;
2811 default:
2812 return -E1000_ERR_NVM;
2813 }
2814
2815 /* Start with the base address, then add the sector offset. */
2816 flash_linear_addr = hw->nvm.flash_base_addr;
2817 flash_linear_addr += (bank) ? flash_bank_size : 0;
2818
2819 for (j = 0; j < iteration ; j++) {
2820 do {
2821 /* Steps */
2822 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2823 if (ret_val)
2824 return ret_val;
2825
2826 /*
2827 * Write a value 11 (block Erase) in Flash
2828 * Cycle field in hw flash control
2829 */
2830 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2831 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2832 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2833
2834 /*
2835 * Write the last 24 bits of an index within the
2836 * block into Flash Linear address field in Flash
2837 * Address.
2838 */
2839 flash_linear_addr += (j * sector_size);
2840 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2841
2842 ret_val = e1000_flash_cycle_ich8lan(hw,
2843 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2844 if (ret_val == 0)
2845 break;
2846
2847 /*
2848 * Check if FCERR is set to 1. If 1,
2849 * clear it and try the whole sequence
2850 * a few more times else Done
2851 */
2852 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2853 if (hsfsts.hsf_status.flcerr == 1)
2854 /* repeat for some time before giving up */
2855 continue;
2856 else if (hsfsts.hsf_status.flcdone == 0)
2857 return ret_val;
2858 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2859 }
2860
2861 return 0;
2862 }
2863
2864 /**
2865 * e1000_valid_led_default_ich8lan - Set the default LED settings
2866 * @hw: pointer to the HW structure
2867 * @data: Pointer to the LED settings
2868 *
2869 * Reads the LED default settings from the NVM to data. If the NVM LED
2870 * settings is all 0's or F's, set the LED default to a valid LED default
2871 * setting.
2872 **/
2873 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2874 {
2875 s32 ret_val;
2876
2877 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2878 if (ret_val) {
2879 e_dbg("NVM Read Error\n");
2880 return ret_val;
2881 }
2882
2883 if (*data == ID_LED_RESERVED_0000 ||
2884 *data == ID_LED_RESERVED_FFFF)
2885 *data = ID_LED_DEFAULT_ICH8LAN;
2886
2887 return 0;
2888 }
2889
2890 /**
2891 * e1000_id_led_init_pchlan - store LED configurations
2892 * @hw: pointer to the HW structure
2893 *
2894 * PCH does not control LEDs via the LEDCTL register, rather it uses
2895 * the PHY LED configuration register.
2896 *
2897 * PCH also does not have an "always on" or "always off" mode which
2898 * complicates the ID feature. Instead of using the "on" mode to indicate
2899 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2900 * use "link_up" mode. The LEDs will still ID on request if there is no
2901 * link based on logic in e1000_led_[on|off]_pchlan().
2902 **/
2903 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2904 {
2905 struct e1000_mac_info *mac = &hw->mac;
2906 s32 ret_val;
2907 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2908 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2909 u16 data, i, temp, shift;
2910
2911 /* Get default ID LED modes */
2912 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2913 if (ret_val)
2914 goto out;
2915
2916 mac->ledctl_default = er32(LEDCTL);
2917 mac->ledctl_mode1 = mac->ledctl_default;
2918 mac->ledctl_mode2 = mac->ledctl_default;
2919
2920 for (i = 0; i < 4; i++) {
2921 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2922 shift = (i * 5);
2923 switch (temp) {
2924 case ID_LED_ON1_DEF2:
2925 case ID_LED_ON1_ON2:
2926 case ID_LED_ON1_OFF2:
2927 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2928 mac->ledctl_mode1 |= (ledctl_on << shift);
2929 break;
2930 case ID_LED_OFF1_DEF2:
2931 case ID_LED_OFF1_ON2:
2932 case ID_LED_OFF1_OFF2:
2933 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2934 mac->ledctl_mode1 |= (ledctl_off << shift);
2935 break;
2936 default:
2937 /* Do nothing */
2938 break;
2939 }
2940 switch (temp) {
2941 case ID_LED_DEF1_ON2:
2942 case ID_LED_ON1_ON2:
2943 case ID_LED_OFF1_ON2:
2944 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2945 mac->ledctl_mode2 |= (ledctl_on << shift);
2946 break;
2947 case ID_LED_DEF1_OFF2:
2948 case ID_LED_ON1_OFF2:
2949 case ID_LED_OFF1_OFF2:
2950 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2951 mac->ledctl_mode2 |= (ledctl_off << shift);
2952 break;
2953 default:
2954 /* Do nothing */
2955 break;
2956 }
2957 }
2958
2959 out:
2960 return ret_val;
2961 }
2962
2963 /**
2964 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2965 * @hw: pointer to the HW structure
2966 *
2967 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2968 * register, so the the bus width is hard coded.
2969 **/
2970 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2971 {
2972 struct e1000_bus_info *bus = &hw->bus;
2973 s32 ret_val;
2974
2975 ret_val = e1000e_get_bus_info_pcie(hw);
2976
2977 /*
2978 * ICH devices are "PCI Express"-ish. They have
2979 * a configuration space, but do not contain
2980 * PCI Express Capability registers, so bus width
2981 * must be hardcoded.
2982 */
2983 if (bus->width == e1000_bus_width_unknown)
2984 bus->width = e1000_bus_width_pcie_x1;
2985
2986 return ret_val;
2987 }
2988
2989 /**
2990 * e1000_reset_hw_ich8lan - Reset the hardware
2991 * @hw: pointer to the HW structure
2992 *
2993 * Does a full reset of the hardware which includes a reset of the PHY and
2994 * MAC.
2995 **/
2996 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2997 {
2998 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2999 u16 reg;
3000 u32 ctrl, kab;
3001 s32 ret_val;
3002
3003 /*
3004 * Prevent the PCI-E bus from sticking if there is no TLP connection
3005 * on the last TLP read/write transaction when MAC is reset.
3006 */
3007 ret_val = e1000e_disable_pcie_master(hw);
3008 if (ret_val)
3009 e_dbg("PCI-E Master disable polling has failed.\n");
3010
3011 e_dbg("Masking off all interrupts\n");
3012 ew32(IMC, 0xffffffff);
3013
3014 /*
3015 * Disable the Transmit and Receive units. Then delay to allow
3016 * any pending transactions to complete before we hit the MAC
3017 * with the global reset.
3018 */
3019 ew32(RCTL, 0);
3020 ew32(TCTL, E1000_TCTL_PSP);
3021 e1e_flush();
3022
3023 usleep_range(10000, 20000);
3024
3025 /* Workaround for ICH8 bit corruption issue in FIFO memory */
3026 if (hw->mac.type == e1000_ich8lan) {
3027 /* Set Tx and Rx buffer allocation to 8k apiece. */
3028 ew32(PBA, E1000_PBA_8K);
3029 /* Set Packet Buffer Size to 16k. */
3030 ew32(PBS, E1000_PBS_16K);
3031 }
3032
3033 if (hw->mac.type == e1000_pchlan) {
3034 /* Save the NVM K1 bit setting*/
3035 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
3036 if (ret_val)
3037 return ret_val;
3038
3039 if (reg & E1000_NVM_K1_ENABLE)
3040 dev_spec->nvm_k1_enabled = true;
3041 else
3042 dev_spec->nvm_k1_enabled = false;
3043 }
3044
3045 ctrl = er32(CTRL);
3046
3047 if (!e1000_check_reset_block(hw)) {
3048 /*
3049 * Full-chip reset requires MAC and PHY reset at the same
3050 * time to make sure the interface between MAC and the
3051 * external PHY is reset.
3052 */
3053 ctrl |= E1000_CTRL_PHY_RST;
3054
3055 /*
3056 * Gate automatic PHY configuration by hardware on
3057 * non-managed 82579
3058 */
3059 if ((hw->mac.type == e1000_pch2lan) &&
3060 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3061 e1000_gate_hw_phy_config_ich8lan(hw, true);
3062 }
3063 ret_val = e1000_acquire_swflag_ich8lan(hw);
3064 e_dbg("Issuing a global reset to ich8lan\n");
3065 ew32(CTRL, (ctrl | E1000_CTRL_RST));
3066 msleep(20);
3067
3068 if (!ret_val)
3069 e1000_release_swflag_ich8lan(hw);
3070
3071 if (ctrl & E1000_CTRL_PHY_RST) {
3072 ret_val = hw->phy.ops.get_cfg_done(hw);
3073 if (ret_val)
3074 goto out;
3075
3076 ret_val = e1000_post_phy_reset_ich8lan(hw);
3077 if (ret_val)
3078 goto out;
3079 }
3080
3081 /*
3082 * For PCH, this write will make sure that any noise
3083 * will be detected as a CRC error and be dropped rather than show up
3084 * as a bad packet to the DMA engine.
3085 */
3086 if (hw->mac.type == e1000_pchlan)
3087 ew32(CRC_OFFSET, 0x65656565);
3088
3089 ew32(IMC, 0xffffffff);
3090 er32(ICR);
3091
3092 kab = er32(KABGTXD);
3093 kab |= E1000_KABGTXD_BGSQLBIAS;
3094 ew32(KABGTXD, kab);
3095
3096 out:
3097 return ret_val;
3098 }
3099
3100 /**
3101 * e1000_init_hw_ich8lan - Initialize the hardware
3102 * @hw: pointer to the HW structure
3103 *
3104 * Prepares the hardware for transmit and receive by doing the following:
3105 * - initialize hardware bits
3106 * - initialize LED identification
3107 * - setup receive address registers
3108 * - setup flow control
3109 * - setup transmit descriptors
3110 * - clear statistics
3111 **/
3112 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3113 {
3114 struct e1000_mac_info *mac = &hw->mac;
3115 u32 ctrl_ext, txdctl, snoop;
3116 s32 ret_val;
3117 u16 i;
3118
3119 e1000_initialize_hw_bits_ich8lan(hw);
3120
3121 /* Initialize identification LED */
3122 ret_val = mac->ops.id_led_init(hw);
3123 if (ret_val)
3124 e_dbg("Error initializing identification LED\n");
3125 /* This is not fatal and we should not stop init due to this */
3126
3127 /* Setup the receive address. */
3128 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3129
3130 /* Zero out the Multicast HASH table */
3131 e_dbg("Zeroing the MTA\n");
3132 for (i = 0; i < mac->mta_reg_count; i++)
3133 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3134
3135 /*
3136 * The 82578 Rx buffer will stall if wakeup is enabled in host and
3137 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
3138 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3139 */
3140 if (hw->phy.type == e1000_phy_82578) {
3141 e1e_rphy(hw, BM_WUC, &i);
3142 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3143 if (ret_val)
3144 return ret_val;
3145 }
3146
3147 /* Setup link and flow control */
3148 ret_val = e1000_setup_link_ich8lan(hw);
3149
3150 /* Set the transmit descriptor write-back policy for both queues */
3151 txdctl = er32(TXDCTL(0));
3152 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3153 E1000_TXDCTL_FULL_TX_DESC_WB;
3154 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3155 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3156 ew32(TXDCTL(0), txdctl);
3157 txdctl = er32(TXDCTL(1));
3158 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3159 E1000_TXDCTL_FULL_TX_DESC_WB;
3160 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3161 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3162 ew32(TXDCTL(1), txdctl);
3163
3164 /*
3165 * ICH8 has opposite polarity of no_snoop bits.
3166 * By default, we should use snoop behavior.
3167 */
3168 if (mac->type == e1000_ich8lan)
3169 snoop = PCIE_ICH8_SNOOP_ALL;
3170 else
3171 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3172 e1000e_set_pcie_no_snoop(hw, snoop);
3173
3174 ctrl_ext = er32(CTRL_EXT);
3175 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3176 ew32(CTRL_EXT, ctrl_ext);
3177
3178 /*
3179 * Clear all of the statistics registers (clear on read). It is
3180 * important that we do this after we have tried to establish link
3181 * because the symbol error count will increment wildly if there
3182 * is no link.
3183 */
3184 e1000_clear_hw_cntrs_ich8lan(hw);
3185
3186 return 0;
3187 }
3188 /**
3189 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3190 * @hw: pointer to the HW structure
3191 *
3192 * Sets/Clears required hardware bits necessary for correctly setting up the
3193 * hardware for transmit and receive.
3194 **/
3195 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3196 {
3197 u32 reg;
3198
3199 /* Extended Device Control */
3200 reg = er32(CTRL_EXT);
3201 reg |= (1 << 22);
3202 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3203 if (hw->mac.type >= e1000_pchlan)
3204 reg |= E1000_CTRL_EXT_PHYPDEN;
3205 ew32(CTRL_EXT, reg);
3206
3207 /* Transmit Descriptor Control 0 */
3208 reg = er32(TXDCTL(0));
3209 reg |= (1 << 22);
3210 ew32(TXDCTL(0), reg);
3211
3212 /* Transmit Descriptor Control 1 */
3213 reg = er32(TXDCTL(1));
3214 reg |= (1 << 22);
3215 ew32(TXDCTL(1), reg);
3216
3217 /* Transmit Arbitration Control 0 */
3218 reg = er32(TARC(0));
3219 if (hw->mac.type == e1000_ich8lan)
3220 reg |= (1 << 28) | (1 << 29);
3221 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3222 ew32(TARC(0), reg);
3223
3224 /* Transmit Arbitration Control 1 */
3225 reg = er32(TARC(1));
3226 if (er32(TCTL) & E1000_TCTL_MULR)
3227 reg &= ~(1 << 28);
3228 else
3229 reg |= (1 << 28);
3230 reg |= (1 << 24) | (1 << 26) | (1 << 30);
3231 ew32(TARC(1), reg);
3232
3233 /* Device Status */
3234 if (hw->mac.type == e1000_ich8lan) {
3235 reg = er32(STATUS);
3236 reg &= ~(1 << 31);
3237 ew32(STATUS, reg);
3238 }
3239
3240 /*
3241 * work-around descriptor data corruption issue during nfs v2 udp
3242 * traffic, just disable the nfs filtering capability
3243 */
3244 reg = er32(RFCTL);
3245 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3246 ew32(RFCTL, reg);
3247 }
3248
3249 /**
3250 * e1000_setup_link_ich8lan - Setup flow control and link settings
3251 * @hw: pointer to the HW structure
3252 *
3253 * Determines which flow control settings to use, then configures flow
3254 * control. Calls the appropriate media-specific link configuration
3255 * function. Assuming the adapter has a valid link partner, a valid link
3256 * should be established. Assumes the hardware has previously been reset
3257 * and the transmitter and receiver are not enabled.
3258 **/
3259 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3260 {
3261 s32 ret_val;
3262
3263 if (e1000_check_reset_block(hw))
3264 return 0;
3265
3266 /*
3267 * ICH parts do not have a word in the NVM to determine
3268 * the default flow control setting, so we explicitly
3269 * set it to full.
3270 */
3271 if (hw->fc.requested_mode == e1000_fc_default) {
3272 /* Workaround h/w hang when Tx flow control enabled */
3273 if (hw->mac.type == e1000_pchlan)
3274 hw->fc.requested_mode = e1000_fc_rx_pause;
3275 else
3276 hw->fc.requested_mode = e1000_fc_full;
3277 }
3278
3279 /*
3280 * Save off the requested flow control mode for use later. Depending
3281 * on the link partner's capabilities, we may or may not use this mode.
3282 */
3283 hw->fc.current_mode = hw->fc.requested_mode;
3284
3285 e_dbg("After fix-ups FlowControl is now = %x\n",
3286 hw->fc.current_mode);
3287
3288 /* Continue to configure the copper link. */
3289 ret_val = e1000_setup_copper_link_ich8lan(hw);
3290 if (ret_val)
3291 return ret_val;
3292
3293 ew32(FCTTV, hw->fc.pause_time);
3294 if ((hw->phy.type == e1000_phy_82578) ||
3295 (hw->phy.type == e1000_phy_82579) ||
3296 (hw->phy.type == e1000_phy_82577)) {
3297 ew32(FCRTV_PCH, hw->fc.refresh_time);
3298
3299 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3300 hw->fc.pause_time);
3301 if (ret_val)
3302 return ret_val;
3303 }
3304
3305 return e1000e_set_fc_watermarks(hw);
3306 }
3307
3308 /**
3309 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3310 * @hw: pointer to the HW structure
3311 *
3312 * Configures the kumeran interface to the PHY to wait the appropriate time
3313 * when polling the PHY, then call the generic setup_copper_link to finish
3314 * configuring the copper link.
3315 **/
3316 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3317 {
3318 u32 ctrl;
3319 s32 ret_val;
3320 u16 reg_data;
3321
3322 ctrl = er32(CTRL);
3323 ctrl |= E1000_CTRL_SLU;
3324 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3325 ew32(CTRL, ctrl);
3326
3327 /*
3328 * Set the mac to wait the maximum time between each iteration
3329 * and increase the max iterations when polling the phy;
3330 * this fixes erroneous timeouts at 10Mbps.
3331 */
3332 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3333 if (ret_val)
3334 return ret_val;
3335 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3336 &reg_data);
3337 if (ret_val)
3338 return ret_val;
3339 reg_data |= 0x3F;
3340 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3341 reg_data);
3342 if (ret_val)
3343 return ret_val;
3344
3345 switch (hw->phy.type) {
3346 case e1000_phy_igp_3:
3347 ret_val = e1000e_copper_link_setup_igp(hw);
3348 if (ret_val)
3349 return ret_val;
3350 break;
3351 case e1000_phy_bm:
3352 case e1000_phy_82578:
3353 ret_val = e1000e_copper_link_setup_m88(hw);
3354 if (ret_val)
3355 return ret_val;
3356 break;
3357 case e1000_phy_82577:
3358 case e1000_phy_82579:
3359 ret_val = e1000_copper_link_setup_82577(hw);
3360 if (ret_val)
3361 return ret_val;
3362 break;
3363 case e1000_phy_ife:
3364 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3365 if (ret_val)
3366 return ret_val;
3367
3368 reg_data &= ~IFE_PMC_AUTO_MDIX;
3369
3370 switch (hw->phy.mdix) {
3371 case 1:
3372 reg_data &= ~IFE_PMC_FORCE_MDIX;
3373 break;
3374 case 2:
3375 reg_data |= IFE_PMC_FORCE_MDIX;
3376 break;
3377 case 0:
3378 default:
3379 reg_data |= IFE_PMC_AUTO_MDIX;
3380 break;
3381 }
3382 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3383 if (ret_val)
3384 return ret_val;
3385 break;
3386 default:
3387 break;
3388 }
3389 return e1000e_setup_copper_link(hw);
3390 }
3391
3392 /**
3393 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3394 * @hw: pointer to the HW structure
3395 * @speed: pointer to store current link speed
3396 * @duplex: pointer to store the current link duplex
3397 *
3398 * Calls the generic get_speed_and_duplex to retrieve the current link
3399 * information and then calls the Kumeran lock loss workaround for links at
3400 * gigabit speeds.
3401 **/
3402 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3403 u16 *duplex)
3404 {
3405 s32 ret_val;
3406
3407 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3408 if (ret_val)
3409 return ret_val;
3410
3411 if ((hw->mac.type == e1000_ich8lan) &&
3412 (hw->phy.type == e1000_phy_igp_3) &&
3413 (*speed == SPEED_1000)) {
3414 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3415 }
3416
3417 return ret_val;
3418 }
3419
3420 /**
3421 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3422 * @hw: pointer to the HW structure
3423 *
3424 * Work-around for 82566 Kumeran PCS lock loss:
3425 * On link status change (i.e. PCI reset, speed change) and link is up and
3426 * speed is gigabit-
3427 * 0) if workaround is optionally disabled do nothing
3428 * 1) wait 1ms for Kumeran link to come up
3429 * 2) check Kumeran Diagnostic register PCS lock loss bit
3430 * 3) if not set the link is locked (all is good), otherwise...
3431 * 4) reset the PHY
3432 * 5) repeat up to 10 times
3433 * Note: this is only called for IGP3 copper when speed is 1gb.
3434 **/
3435 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3436 {
3437 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3438 u32 phy_ctrl;
3439 s32 ret_val;
3440 u16 i, data;
3441 bool link;
3442
3443 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3444 return 0;
3445
3446 /*
3447 * Make sure link is up before proceeding. If not just return.
3448 * Attempting this while link is negotiating fouled up link
3449 * stability
3450 */
3451 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3452 if (!link)
3453 return 0;
3454
3455 for (i = 0; i < 10; i++) {
3456 /* read once to clear */
3457 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3458 if (ret_val)
3459 return ret_val;
3460 /* and again to get new status */
3461 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3462 if (ret_val)
3463 return ret_val;
3464
3465 /* check for PCS lock */
3466 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3467 return 0;
3468
3469 /* Issue PHY reset */
3470 e1000_phy_hw_reset(hw);
3471 mdelay(5);
3472 }
3473 /* Disable GigE link negotiation */
3474 phy_ctrl = er32(PHY_CTRL);
3475 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3476 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3477 ew32(PHY_CTRL, phy_ctrl);
3478
3479 /*
3480 * Call gig speed drop workaround on Gig disable before accessing
3481 * any PHY registers
3482 */
3483 e1000e_gig_downshift_workaround_ich8lan(hw);
3484
3485 /* unable to acquire PCS lock */
3486 return -E1000_ERR_PHY;
3487 }
3488
3489 /**
3490 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3491 * @hw: pointer to the HW structure
3492 * @state: boolean value used to set the current Kumeran workaround state
3493 *
3494 * If ICH8, set the current Kumeran workaround state (enabled - true
3495 * /disabled - false).
3496 **/
3497 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3498 bool state)
3499 {
3500 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3501
3502 if (hw->mac.type != e1000_ich8lan) {
3503 e_dbg("Workaround applies to ICH8 only.\n");
3504 return;
3505 }
3506
3507 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3508 }
3509
3510 /**
3511 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3512 * @hw: pointer to the HW structure
3513 *
3514 * Workaround for 82566 power-down on D3 entry:
3515 * 1) disable gigabit link
3516 * 2) write VR power-down enable
3517 * 3) read it back
3518 * Continue if successful, else issue LCD reset and repeat
3519 **/
3520 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3521 {
3522 u32 reg;
3523 u16 data;
3524 u8 retry = 0;
3525
3526 if (hw->phy.type != e1000_phy_igp_3)
3527 return;
3528
3529 /* Try the workaround twice (if needed) */
3530 do {
3531 /* Disable link */
3532 reg = er32(PHY_CTRL);
3533 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3534 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3535 ew32(PHY_CTRL, reg);
3536
3537 /*
3538 * Call gig speed drop workaround on Gig disable before
3539 * accessing any PHY registers
3540 */
3541 if (hw->mac.type == e1000_ich8lan)
3542 e1000e_gig_downshift_workaround_ich8lan(hw);
3543
3544 /* Write VR power-down enable */
3545 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3546 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3547 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3548
3549 /* Read it back and test */
3550 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3551 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3552 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3553 break;
3554
3555 /* Issue PHY reset and repeat at most one more time */
3556 reg = er32(CTRL);
3557 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3558 retry++;
3559 } while (retry);
3560 }
3561
3562 /**
3563 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3564 * @hw: pointer to the HW structure
3565 *
3566 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3567 * LPLU, Gig disable, MDIC PHY reset):
3568 * 1) Set Kumeran Near-end loopback
3569 * 2) Clear Kumeran Near-end loopback
3570 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3571 **/
3572 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3573 {
3574 s32 ret_val;
3575 u16 reg_data;
3576
3577 if ((hw->mac.type != e1000_ich8lan) ||
3578 (hw->phy.type != e1000_phy_igp_3))
3579 return;
3580
3581 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3582 &reg_data);
3583 if (ret_val)
3584 return;
3585 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3586 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3587 reg_data);
3588 if (ret_val)
3589 return;
3590 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3591 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3592 reg_data);
3593 }
3594
3595 /**
3596 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
3597 * @hw: pointer to the HW structure
3598 *
3599 * During S0 to Sx transition, it is possible the link remains at gig
3600 * instead of negotiating to a lower speed. Before going to Sx, set
3601 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3602 * to a lower speed. For PCH and newer parts, the OEM bits PHY register
3603 * (LED, GbE disable and LPLU configurations) also needs to be written.
3604 **/
3605 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
3606 {
3607 u32 phy_ctrl;
3608 s32 ret_val;
3609
3610 phy_ctrl = er32(PHY_CTRL);
3611 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3612 ew32(PHY_CTRL, phy_ctrl);
3613
3614 if (hw->mac.type >= e1000_pchlan) {
3615 e1000_oem_bits_config_ich8lan(hw, false);
3616 ret_val = hw->phy.ops.acquire(hw);
3617 if (ret_val)
3618 return;
3619 e1000_write_smbus_addr(hw);
3620 hw->phy.ops.release(hw);
3621 }
3622 }
3623
3624 /**
3625 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
3626 * @hw: pointer to the HW structure
3627 *
3628 * During Sx to S0 transitions on non-managed devices or managed devices
3629 * on which PHY resets are not blocked, if the PHY registers cannot be
3630 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
3631 * the PHY.
3632 **/
3633 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
3634 {
3635 u32 fwsm;
3636
3637 if (hw->mac.type != e1000_pch2lan)
3638 return;
3639
3640 fwsm = er32(FWSM);
3641 if (!(fwsm & E1000_ICH_FWSM_FW_VALID) || !e1000_check_reset_block(hw)) {
3642 u16 phy_id1, phy_id2;
3643 s32 ret_val;
3644
3645 ret_val = hw->phy.ops.acquire(hw);
3646 if (ret_val) {
3647 e_dbg("Failed to acquire PHY semaphore in resume\n");
3648 return;
3649 }
3650
3651 /* Test access to the PHY registers by reading the ID regs */
3652 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1);
3653 if (ret_val)
3654 goto release;
3655 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2);
3656 if (ret_val)
3657 goto release;
3658
3659 if (hw->phy.id == ((u32)(phy_id1 << 16) |
3660 (u32)(phy_id2 & PHY_REVISION_MASK)))
3661 goto release;
3662
3663 e1000_toggle_lanphypc_value_ich8lan(hw);
3664
3665 hw->phy.ops.release(hw);
3666 msleep(50);
3667 e1000_phy_hw_reset(hw);
3668 msleep(50);
3669 return;
3670 }
3671
3672 release:
3673 hw->phy.ops.release(hw);
3674
3675 return;
3676 }
3677
3678 /**
3679 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3680 * @hw: pointer to the HW structure
3681 *
3682 * Return the LED back to the default configuration.
3683 **/
3684 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3685 {
3686 if (hw->phy.type == e1000_phy_ife)
3687 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3688
3689 ew32(LEDCTL, hw->mac.ledctl_default);
3690 return 0;
3691 }
3692
3693 /**
3694 * e1000_led_on_ich8lan - Turn LEDs on
3695 * @hw: pointer to the HW structure
3696 *
3697 * Turn on the LEDs.
3698 **/
3699 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3700 {
3701 if (hw->phy.type == e1000_phy_ife)
3702 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3703 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3704
3705 ew32(LEDCTL, hw->mac.ledctl_mode2);
3706 return 0;
3707 }
3708
3709 /**
3710 * e1000_led_off_ich8lan - Turn LEDs off
3711 * @hw: pointer to the HW structure
3712 *
3713 * Turn off the LEDs.
3714 **/
3715 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3716 {
3717 if (hw->phy.type == e1000_phy_ife)
3718 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3719 (IFE_PSCL_PROBE_MODE |
3720 IFE_PSCL_PROBE_LEDS_OFF));
3721
3722 ew32(LEDCTL, hw->mac.ledctl_mode1);
3723 return 0;
3724 }
3725
3726 /**
3727 * e1000_setup_led_pchlan - Configures SW controllable LED
3728 * @hw: pointer to the HW structure
3729 *
3730 * This prepares the SW controllable LED for use.
3731 **/
3732 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3733 {
3734 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
3735 }
3736
3737 /**
3738 * e1000_cleanup_led_pchlan - Restore the default LED operation
3739 * @hw: pointer to the HW structure
3740 *
3741 * Return the LED back to the default configuration.
3742 **/
3743 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3744 {
3745 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
3746 }
3747
3748 /**
3749 * e1000_led_on_pchlan - Turn LEDs on
3750 * @hw: pointer to the HW structure
3751 *
3752 * Turn on the LEDs.
3753 **/
3754 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3755 {
3756 u16 data = (u16)hw->mac.ledctl_mode2;
3757 u32 i, led;
3758
3759 /*
3760 * If no link, then turn LED on by setting the invert bit
3761 * for each LED that's mode is "link_up" in ledctl_mode2.
3762 */
3763 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3764 for (i = 0; i < 3; i++) {
3765 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3766 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3767 E1000_LEDCTL_MODE_LINK_UP)
3768 continue;
3769 if (led & E1000_PHY_LED0_IVRT)
3770 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3771 else
3772 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3773 }
3774 }
3775
3776 return e1e_wphy(hw, HV_LED_CONFIG, data);
3777 }
3778
3779 /**
3780 * e1000_led_off_pchlan - Turn LEDs off
3781 * @hw: pointer to the HW structure
3782 *
3783 * Turn off the LEDs.
3784 **/
3785 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3786 {
3787 u16 data = (u16)hw->mac.ledctl_mode1;
3788 u32 i, led;
3789
3790 /*
3791 * If no link, then turn LED off by clearing the invert bit
3792 * for each LED that's mode is "link_up" in ledctl_mode1.
3793 */
3794 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3795 for (i = 0; i < 3; i++) {
3796 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3797 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3798 E1000_LEDCTL_MODE_LINK_UP)
3799 continue;
3800 if (led & E1000_PHY_LED0_IVRT)
3801 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3802 else
3803 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3804 }
3805 }
3806
3807 return e1e_wphy(hw, HV_LED_CONFIG, data);
3808 }
3809
3810 /**
3811 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3812 * @hw: pointer to the HW structure
3813 *
3814 * Read appropriate register for the config done bit for completion status
3815 * and configure the PHY through s/w for EEPROM-less parts.
3816 *
3817 * NOTE: some silicon which is EEPROM-less will fail trying to read the
3818 * config done bit, so only an error is logged and continues. If we were
3819 * to return with error, EEPROM-less silicon would not be able to be reset
3820 * or change link.
3821 **/
3822 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3823 {
3824 s32 ret_val = 0;
3825 u32 bank = 0;
3826 u32 status;
3827
3828 e1000e_get_cfg_done(hw);
3829
3830 /* Wait for indication from h/w that it has completed basic config */
3831 if (hw->mac.type >= e1000_ich10lan) {
3832 e1000_lan_init_done_ich8lan(hw);
3833 } else {
3834 ret_val = e1000e_get_auto_rd_done(hw);
3835 if (ret_val) {
3836 /*
3837 * When auto config read does not complete, do not
3838 * return with an error. This can happen in situations
3839 * where there is no eeprom and prevents getting link.
3840 */
3841 e_dbg("Auto Read Done did not complete\n");
3842 ret_val = 0;
3843 }
3844 }
3845
3846 /* Clear PHY Reset Asserted bit */
3847 status = er32(STATUS);
3848 if (status & E1000_STATUS_PHYRA)
3849 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3850 else
3851 e_dbg("PHY Reset Asserted not set - needs delay\n");
3852
3853 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3854 if (hw->mac.type <= e1000_ich9lan) {
3855 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3856 (hw->phy.type == e1000_phy_igp_3)) {
3857 e1000e_phy_init_script_igp3(hw);
3858 }
3859 } else {
3860 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3861 /* Maybe we should do a basic PHY config */
3862 e_dbg("EEPROM not present\n");
3863 ret_val = -E1000_ERR_CONFIG;
3864 }
3865 }
3866
3867 return ret_val;
3868 }
3869
3870 /**
3871 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3872 * @hw: pointer to the HW structure
3873 *
3874 * In the case of a PHY power down to save power, or to turn off link during a
3875 * driver unload, or wake on lan is not enabled, remove the link.
3876 **/
3877 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3878 {
3879 /* If the management interface is not enabled, then power down */
3880 if (!(hw->mac.ops.check_mng_mode(hw) ||
3881 hw->phy.ops.check_reset_block(hw)))
3882 e1000_power_down_phy_copper(hw);
3883 }
3884
3885 /**
3886 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3887 * @hw: pointer to the HW structure
3888 *
3889 * Clears hardware counters specific to the silicon family and calls
3890 * clear_hw_cntrs_generic to clear all general purpose counters.
3891 **/
3892 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3893 {
3894 u16 phy_data;
3895
3896 e1000e_clear_hw_cntrs_base(hw);
3897
3898 er32(ALGNERRC);
3899 er32(RXERRC);
3900 er32(TNCRS);
3901 er32(CEXTERR);
3902 er32(TSCTC);
3903 er32(TSCTFC);
3904
3905 er32(MGTPRC);
3906 er32(MGTPDC);
3907 er32(MGTPTC);
3908
3909 er32(IAC);
3910 er32(ICRXOC);
3911
3912 /* Clear PHY statistics registers */
3913 if ((hw->phy.type == e1000_phy_82578) ||
3914 (hw->phy.type == e1000_phy_82579) ||
3915 (hw->phy.type == e1000_phy_82577)) {
3916 e1e_rphy(hw, HV_SCC_UPPER, &phy_data);
3917 e1e_rphy(hw, HV_SCC_LOWER, &phy_data);
3918 e1e_rphy(hw, HV_ECOL_UPPER, &phy_data);
3919 e1e_rphy(hw, HV_ECOL_LOWER, &phy_data);
3920 e1e_rphy(hw, HV_MCC_UPPER, &phy_data);
3921 e1e_rphy(hw, HV_MCC_LOWER, &phy_data);
3922 e1e_rphy(hw, HV_LATECOL_UPPER, &phy_data);
3923 e1e_rphy(hw, HV_LATECOL_LOWER, &phy_data);
3924 e1e_rphy(hw, HV_COLC_UPPER, &phy_data);
3925 e1e_rphy(hw, HV_COLC_LOWER, &phy_data);
3926 e1e_rphy(hw, HV_DC_UPPER, &phy_data);
3927 e1e_rphy(hw, HV_DC_LOWER, &phy_data);
3928 e1e_rphy(hw, HV_TNCRS_UPPER, &phy_data);
3929 e1e_rphy(hw, HV_TNCRS_LOWER, &phy_data);
3930 }
3931 }
3932
3933 static struct e1000_mac_operations ich8_mac_ops = {
3934 .id_led_init = e1000e_id_led_init,
3935 /* check_mng_mode dependent on mac type */
3936 .check_for_link = e1000_check_for_copper_link_ich8lan,
3937 /* cleanup_led dependent on mac type */
3938 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3939 .get_bus_info = e1000_get_bus_info_ich8lan,
3940 .set_lan_id = e1000_set_lan_id_single_port,
3941 .get_link_up_info = e1000_get_link_up_info_ich8lan,
3942 /* led_on dependent on mac type */
3943 /* led_off dependent on mac type */
3944 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
3945 .reset_hw = e1000_reset_hw_ich8lan,
3946 .init_hw = e1000_init_hw_ich8lan,
3947 .setup_link = e1000_setup_link_ich8lan,
3948 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3949 /* id_led_init dependent on mac type */
3950 };
3951
3952 static struct e1000_phy_operations ich8_phy_ops = {
3953 .acquire = e1000_acquire_swflag_ich8lan,
3954 .check_reset_block = e1000_check_reset_block_ich8lan,
3955 .commit = NULL,
3956 .get_cfg_done = e1000_get_cfg_done_ich8lan,
3957 .get_cable_length = e1000e_get_cable_length_igp_2,
3958 .read_reg = e1000e_read_phy_reg_igp,
3959 .release = e1000_release_swflag_ich8lan,
3960 .reset = e1000_phy_hw_reset_ich8lan,
3961 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3962 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
3963 .write_reg = e1000e_write_phy_reg_igp,
3964 };
3965
3966 static struct e1000_nvm_operations ich8_nvm_ops = {
3967 .acquire = e1000_acquire_nvm_ich8lan,
3968 .read = e1000_read_nvm_ich8lan,
3969 .release = e1000_release_nvm_ich8lan,
3970 .update = e1000_update_nvm_checksum_ich8lan,
3971 .valid_led_default = e1000_valid_led_default_ich8lan,
3972 .validate = e1000_validate_nvm_checksum_ich8lan,
3973 .write = e1000_write_nvm_ich8lan,
3974 };
3975
3976 struct e1000_info e1000_ich8_info = {
3977 .mac = e1000_ich8lan,
3978 .flags = FLAG_HAS_WOL
3979 | FLAG_IS_ICH
3980 | FLAG_RX_CSUM_ENABLED
3981 | FLAG_HAS_CTRLEXT_ON_LOAD
3982 | FLAG_HAS_AMT
3983 | FLAG_HAS_FLASH
3984 | FLAG_APME_IN_WUC,
3985 .pba = 8,
3986 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
3987 .get_variants = e1000_get_variants_ich8lan,
3988 .mac_ops = &ich8_mac_ops,
3989 .phy_ops = &ich8_phy_ops,
3990 .nvm_ops = &ich8_nvm_ops,
3991 };
3992
3993 struct e1000_info e1000_ich9_info = {
3994 .mac = e1000_ich9lan,
3995 .flags = FLAG_HAS_JUMBO_FRAMES
3996 | FLAG_IS_ICH
3997 | FLAG_HAS_WOL
3998 | FLAG_RX_CSUM_ENABLED
3999 | FLAG_HAS_CTRLEXT_ON_LOAD
4000 | FLAG_HAS_AMT
4001 | FLAG_HAS_ERT
4002 | FLAG_HAS_FLASH
4003 | FLAG_APME_IN_WUC,
4004 .pba = 10,
4005 .max_hw_frame_size = DEFAULT_JUMBO,
4006 .get_variants = e1000_get_variants_ich8lan,
4007 .mac_ops = &ich8_mac_ops,
4008 .phy_ops = &ich8_phy_ops,
4009 .nvm_ops = &ich8_nvm_ops,
4010 };
4011
4012 struct e1000_info e1000_ich10_info = {
4013 .mac = e1000_ich10lan,
4014 .flags = FLAG_HAS_JUMBO_FRAMES
4015 | FLAG_IS_ICH
4016 | FLAG_HAS_WOL
4017 | FLAG_RX_CSUM_ENABLED
4018 | FLAG_HAS_CTRLEXT_ON_LOAD
4019 | FLAG_HAS_AMT
4020 | FLAG_HAS_ERT
4021 | FLAG_HAS_FLASH
4022 | FLAG_APME_IN_WUC,
4023 .pba = 10,
4024 .max_hw_frame_size = DEFAULT_JUMBO,
4025 .get_variants = e1000_get_variants_ich8lan,
4026 .mac_ops = &ich8_mac_ops,
4027 .phy_ops = &ich8_phy_ops,
4028 .nvm_ops = &ich8_nvm_ops,
4029 };
4030
4031 struct e1000_info e1000_pch_info = {
4032 .mac = e1000_pchlan,
4033 .flags = FLAG_IS_ICH
4034 | FLAG_HAS_WOL
4035 | FLAG_RX_CSUM_ENABLED
4036 | FLAG_HAS_CTRLEXT_ON_LOAD
4037 | FLAG_HAS_AMT
4038 | FLAG_HAS_FLASH
4039 | FLAG_HAS_JUMBO_FRAMES
4040 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4041 | FLAG_APME_IN_WUC,
4042 .flags2 = FLAG2_HAS_PHY_STATS,
4043 .pba = 26,
4044 .max_hw_frame_size = 4096,
4045 .get_variants = e1000_get_variants_ich8lan,
4046 .mac_ops = &ich8_mac_ops,
4047 .phy_ops = &ich8_phy_ops,
4048 .nvm_ops = &ich8_nvm_ops,
4049 };
4050
4051 struct e1000_info e1000_pch2_info = {
4052 .mac = e1000_pch2lan,
4053 .flags = FLAG_IS_ICH
4054 | FLAG_HAS_WOL
4055 | FLAG_RX_CSUM_ENABLED
4056 | FLAG_HAS_CTRLEXT_ON_LOAD
4057 | FLAG_HAS_AMT
4058 | FLAG_HAS_FLASH
4059 | FLAG_HAS_JUMBO_FRAMES
4060 | FLAG_APME_IN_WUC,
4061 .flags2 = FLAG2_HAS_PHY_STATS
4062 | FLAG2_HAS_EEE,
4063 .pba = 26,
4064 .max_hw_frame_size = DEFAULT_JUMBO,
4065 .get_variants = e1000_get_variants_ich8lan,
4066 .mac_ops = &ich8_mac_ops,
4067 .phy_ops = &ich8_phy_ops,
4068 .nvm_ops = &ich8_nvm_ops,
4069 };
Linus' kernel tree