drivers/media/video/cx18/cx18-driver.h

   1 /*
   2  *  cx18 driver internal defines and structures
   3  *
   4  *  Derived from ivtv-driver.h
   5  *
   6  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program; if not, write to the Free Software
  20  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  21  *  02111-1307  USA
  22  */
  23
  24 #ifndef CX18_DRIVER_H
  25 #define CX18_DRIVER_H
  26
  27 #include <linux/version.h>
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/init.h>
  31 #include <linux/delay.h>
  32 #include <linux/sched.h>
  33 #include <linux/fs.h>
  34 #include <linux/pci.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/spinlock.h>
  37 #include <linux/i2c.h>
  38 #include <linux/i2c-algo-bit.h>
  39 #include <linux/list.h>
  40 #include <linux/unistd.h>
  41 #include <linux/byteorder/swab.h>
  42 #include <linux/pagemap.h>
  43 #include <linux/workqueue.h>
  44 #include <linux/mutex.h>
  45
  46 #include <linux/dvb/video.h>
  47 #include <linux/dvb/audio.h>
  48 #include <media/v4l2-common.h>
  49 #include <media/tuner.h>
  50 #include "cx18-mailbox.h"
  51 #include "cx18-av-core.h"
  52 #include "cx23418.h"
  53
  54 /* DVB */
  55 #include "demux.h"
  56 #include "dmxdev.h"
  57 #include "dvb_demux.h"
  58 #include "dvb_frontend.h"
  59 #include "dvb_net.h"
  60 #include "dvbdev.h"
  61
  62 #ifndef CONFIG_PCI
  63 #  error "This driver requires kernel PCI support."
  64 #endif
  65
  66 #define CX18_MEM_OFFSET 0x00000000
  67 #define CX18_MEM_SIZE   0x04000000
  68 #define CX18_REG_OFFSET 0x02000000
  69
  70 /* Maximum cx18 driver instances. */
  71 #define CX18_MAX_CARDS 32
  72
  73 /* Supported cards */
  74 #define CX18_CARD_HVR_1600_ESMT       0 /* Hauppauge HVR 1600 (ESMT memory) */
  75 #define CX18_CARD_HVR_1600_SAMSUNG    1 /* Hauppauge HVR 1600 (Samsung memory) */
  76 #define CX18_CARD_COMPRO_H900         2 /* Compro VideoMate H900 */
  77 #define CX18_CARD_YUAN_MPC718         3 /* Yuan MPC718 */
  78 #define CX18_CARD_LAST                3
  79
  80 #define CX18_ENC_STREAM_TYPE_MPG  0
  81 #define CX18_ENC_STREAM_TYPE_TS   1
  82 #define CX18_ENC_STREAM_TYPE_YUV  2
  83 #define CX18_ENC_STREAM_TYPE_VBI  3
  84 #define CX18_ENC_STREAM_TYPE_PCM  4
  85 #define CX18_ENC_STREAM_TYPE_IDX  5
  86 #define CX18_ENC_STREAM_TYPE_RAD  6
  87 #define CX18_MAX_STREAMS          7
  88
  89 /* system vendor and device IDs */
  90 #define PCI_VENDOR_ID_CX      0x14f1
  91 #define PCI_DEVICE_ID_CX23418 0x5b7a
  92
  93 /* subsystem vendor ID */
  94 #define CX18_PCI_ID_HAUPPAUGE           0x0070
  95 #define CX18_PCI_ID_COMPRO              0x185b
  96 #define CX18_PCI_ID_YUAN                0x12ab
  97
  98 /* ======================================================================== */
  99 /* ========================== START USER SETTABLE DMA VARIABLES =========== */
 100 /* ======================================================================== */
 101
 102 /* DMA Buffers, Default size in MB allocated */
 103 #define CX18_DEFAULT_ENC_TS_BUFFERS  1
 104 #define CX18_DEFAULT_ENC_MPG_BUFFERS 2
 105 #define CX18_DEFAULT_ENC_IDX_BUFFERS 1
 106 #define CX18_DEFAULT_ENC_YUV_BUFFERS 2
 107 #define CX18_DEFAULT_ENC_VBI_BUFFERS 1
 108 #define CX18_DEFAULT_ENC_PCM_BUFFERS 1
 109
 110 /* i2c stuff */
 111 #define I2C_CLIENTS_MAX 16
 112
 113 /* debugging */
 114
 115 /* Flag to turn on high volume debugging */
 116 #define CX18_DBGFLG_WARN  (1 << 0)
 117 #define CX18_DBGFLG_INFO  (1 << 1)
 118 #define CX18_DBGFLG_API   (1 << 2)
 119 #define CX18_DBGFLG_DMA   (1 << 3)
 120 #define CX18_DBGFLG_IOCTL (1 << 4)
 121 #define CX18_DBGFLG_FILE  (1 << 5)
 122 #define CX18_DBGFLG_I2C   (1 << 6)
 123 #define CX18_DBGFLG_IRQ   (1 << 7)
 124 /* Flag to turn on high volume debugging */
 125 #define CX18_DBGFLG_HIGHVOL (1 << 8)
 126
 127 /* NOTE: extra space before comma in 'cx->num , ## args' is required for
 128    gcc-2.95, otherwise it won't compile. */
 129 #define CX18_DEBUG(x, type, fmt, args...) \
 130         do { \
 131                 if ((x) & cx18_debug) \
 132                         printk(KERN_INFO "cx18-%d " type ": " fmt, cx->num , ## args); \
 133         } while (0)
 134 #define CX18_DEBUG_WARN(fmt, args...)  CX18_DEBUG(CX18_DBGFLG_WARN, "warning", fmt , ## args)
 135 #define CX18_DEBUG_INFO(fmt, args...)  CX18_DEBUG(CX18_DBGFLG_INFO, "info", fmt , ## args)
 136 #define CX18_DEBUG_API(fmt, args...)   CX18_DEBUG(CX18_DBGFLG_API, "api", fmt , ## args)
 137 #define CX18_DEBUG_DMA(fmt, args...)   CX18_DEBUG(CX18_DBGFLG_DMA, "dma", fmt , ## args)
 138 #define CX18_DEBUG_IOCTL(fmt, args...) CX18_DEBUG(CX18_DBGFLG_IOCTL, "ioctl", fmt , ## args)
 139 #define CX18_DEBUG_FILE(fmt, args...)  CX18_DEBUG(CX18_DBGFLG_FILE, "file", fmt , ## args)
 140 #define CX18_DEBUG_I2C(fmt, args...)   CX18_DEBUG(CX18_DBGFLG_I2C, "i2c", fmt , ## args)
 141 #define CX18_DEBUG_IRQ(fmt, args...)   CX18_DEBUG(CX18_DBGFLG_IRQ, "irq", fmt , ## args)
 142
 143 #define CX18_DEBUG_HIGH_VOL(x, type, fmt, args...) \
 144         do { \
 145                 if (((x) & cx18_debug) && (cx18_debug & CX18_DBGFLG_HIGHVOL)) \
 146                         printk(KERN_INFO "cx18%d " type ": " fmt, cx->num , ## args); \
 147         } while (0)
 148 #define CX18_DEBUG_HI_WARN(fmt, args...)  CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_WARN, "warning", fmt , ## args)
 149 #define CX18_DEBUG_HI_INFO(fmt, args...)  CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_INFO, "info", fmt , ## args)
 150 #define CX18_DEBUG_HI_API(fmt, args...)   CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_API, "api", fmt , ## args)
 151 #define CX18_DEBUG_HI_DMA(fmt, args...)   CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_DMA, "dma", fmt , ## args)
 152 #define CX18_DEBUG_HI_IOCTL(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_IOCTL, "ioctl", fmt , ## args)
 153 #define CX18_DEBUG_HI_FILE(fmt, args...)  CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_FILE, "file", fmt , ## args)
 154 #define CX18_DEBUG_HI_I2C(fmt, args...)   CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_I2C, "i2c", fmt , ## args)
 155 #define CX18_DEBUG_HI_IRQ(fmt, args...)   CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_IRQ, "irq", fmt , ## args)
 156
 157 /* Standard kernel messages */
 158 #define CX18_ERR(fmt, args...)      printk(KERN_ERR  "cx18-%d: " fmt, cx->num , ## args)
 159 #define CX18_WARN(fmt, args...)     printk(KERN_WARNING "cx18-%d: " fmt, cx->num , ## args)
 160 #define CX18_INFO(fmt, args...)     printk(KERN_INFO "cx18-%d: " fmt, cx->num , ## args)
 161
 162 /* Values for CX18_API_DEC_PLAYBACK_SPEED mpeg_frame_type_mask parameter: */
 163 #define MPEG_FRAME_TYPE_IFRAME 1
 164 #define MPEG_FRAME_TYPE_IFRAME_PFRAME 3
 165 #define MPEG_FRAME_TYPE_ALL 7
 166
 167 #define CX18_MAX_PGM_INDEX (400)
 168
 169 extern int cx18_debug;
 170
 171
 172 struct cx18_options {
 173         int megabytes[CX18_MAX_STREAMS]; /* Size in megabytes of each stream */
 174         int cardtype;           /* force card type on load */
 175         int tuner;              /* set tuner on load */
 176         int radio;              /* enable/disable radio */
 177 };
 178
 179 /* per-buffer bit flags */
 180 #define CX18_F_B_NEED_BUF_SWAP  0       /* this buffer should be byte swapped */
 181
 182 /* per-stream, s_flags */
 183 #define CX18_F_S_CLAIMED        3       /* this stream is claimed */
 184 #define CX18_F_S_STREAMING      4       /* the fw is decoding/encoding this stream */
 185 #define CX18_F_S_INTERNAL_USE   5       /* this stream is used internally (sliced VBI processing) */
 186 #define CX18_F_S_STREAMOFF      7       /* signal end of stream EOS */
 187 #define CX18_F_S_APPL_IO        8       /* this stream is used read/written by an application */
 188
 189 /* per-cx18, i_flags */
 190 #define CX18_F_I_LOADED_FW      0       /* Loaded the firmware the first time */
 191 #define CX18_F_I_EOS            4       /* End of encoder stream reached */
 192 #define CX18_F_I_RADIO_USER     5       /* The radio tuner is selected */
 193 #define CX18_F_I_ENC_PAUSED     13      /* the encoder is paused */
 194 #define CX18_F_I_INITED         21      /* set after first open */
 195 #define CX18_F_I_FAILED         22      /* set if first open failed */
 196
 197 /* These are the VBI types as they appear in the embedded VBI private packets. */
 198 #define CX18_SLICED_TYPE_TELETEXT_B     (1)
 199 #define CX18_SLICED_TYPE_CAPTION_525    (4)
 200 #define CX18_SLICED_TYPE_WSS_625        (5)
 201 #define CX18_SLICED_TYPE_VPS            (7)
 202
 203 struct cx18_buffer {
 204         struct list_head list;
 205         dma_addr_t dma_handle;
 206         u32 id;
 207         unsigned long b_flags;
 208         char *buf;
 209
 210         u32 bytesused;
 211         u32 readpos;
 212 };
 213
 214 struct cx18_queue {
 215         struct list_head list;
 216         u32 buffers;
 217         u32 length;
 218         u32 bytesused;
 219 };
 220
 221 struct cx18_dvb {
 222         struct dmx_frontend hw_frontend;
 223         struct dmx_frontend mem_frontend;
 224         struct dmxdev dmxdev;
 225         struct dvb_adapter dvb_adapter;
 226         struct dvb_demux demux;
 227         struct dvb_frontend *fe;
 228         struct dvb_net dvbnet;
 229         int enabled;
 230         int feeding;
 231
 232         struct mutex feedlock;
 233
 234 };
 235
 236 struct cx18;     /* forward reference */
 237 struct cx18_scb; /* forward reference */
 238
 239 struct cx18_stream {
 240         /* These first four fields are always set, even if the stream
 241            is not actually created. */
 242         struct video_device *v4l2dev;   /* NULL when stream not created */
 243         struct cx18 *cx;                /* for ease of use */
 244         const char *name;               /* name of the stream */
 245         int type;                       /* stream type */
 246         u32 handle;                     /* task handle */
 247         unsigned mdl_offset;
 248
 249         u32 id;
 250         spinlock_t qlock;       /* locks access to the queues */
 251         unsigned long s_flags;  /* status flags, see above */
 252         int dma;                /* can be PCI_DMA_TODEVICE,
 253                                    PCI_DMA_FROMDEVICE or
 254                                    PCI_DMA_NONE */
 255         u64 dma_pts;
 256         wait_queue_head_t waitq;
 257
 258         /* Buffer Stats */
 259         u32 buffers;
 260         u32 buf_size;
 261         u32 buffers_stolen;
 262
 263         /* Buffer Queues */
 264         struct cx18_queue q_free;       /* free buffers */
 265         struct cx18_queue q_full;       /* full buffers */
 266         struct cx18_queue q_io;         /* waiting for I/O */
 267
 268         /* DVB / Digital Transport */
 269         struct cx18_dvb dvb;
 270 };
 271
 272 struct cx18_open_id {
 273         u32 open_id;
 274         int type;
 275         enum v4l2_priority prio;
 276         struct cx18 *cx;
 277 };
 278
 279 /* forward declaration of struct defined in cx18-cards.h */
 280 struct cx18_card;
 281
 282
 283 #define CX18_VBI_FRAMES 32
 284
 285 /* VBI data */
 286 struct vbi_info {
 287         u32 enc_size;
 288         u32 frame;
 289         u8 cc_data_odd[256];
 290         u8 cc_data_even[256];
 291         int cc_pos;
 292         u8 cc_no_update;
 293         u8 vps[5];
 294         u8 vps_found;
 295         int wss;
 296         u8 wss_found;
 297         u8 wss_no_update;
 298         u32 raw_decoder_line_size;
 299         u8 raw_decoder_sav_odd_field;
 300         u8 raw_decoder_sav_even_field;
 301         u32 sliced_decoder_line_size;
 302         u8 sliced_decoder_sav_odd_field;
 303         u8 sliced_decoder_sav_even_field;
 304         struct v4l2_format in;
 305         /* convenience pointer to sliced struct in vbi_in union */
 306         struct v4l2_sliced_vbi_format *sliced_in;
 307         u32 service_set_in;
 308         int insert_mpeg;
 309
 310         /* Buffer for the maximum of 2 * 18 * packet_size sliced VBI lines.
 311            One for /dev/vbi0 and one for /dev/vbi8 */
 312         struct v4l2_sliced_vbi_data sliced_data[36];
 313
 314         /* Buffer for VBI data inserted into MPEG stream.
 315            The first byte is a dummy byte that's never used.
 316            The next 16 bytes contain the MPEG header for the VBI data,
 317            the remainder is the actual VBI data.
 318            The max size accepted by the MPEG VBI reinsertion turns out
 319            to be 1552 bytes, which happens to be 4 + (1 + 42) * (2 * 18) bytes,
 320            where 4 is a four byte header, 42 is the max sliced VBI payload, 1 is
 321            a single line header byte and 2 * 18 is the number of VBI lines per frame.
 322
 323            However, it seems that the data must be 1K aligned, so we have to
 324            pad the data until the 1 or 2 K boundary.
 325
 326            This pointer array will allocate 2049 bytes to store each VBI frame. */
 327         u8 *sliced_mpeg_data[CX18_VBI_FRAMES];
 328         u32 sliced_mpeg_size[CX18_VBI_FRAMES];
 329         struct cx18_buffer sliced_mpeg_buf;
 330         u32 inserted_frame;
 331
 332         u32 start[2], count;
 333         u32 raw_size;
 334         u32 sliced_size;
 335 };
 336
 337 /* Per cx23418, per I2C bus private algo callback data */
 338 struct cx18_i2c_algo_callback_data {
 339         struct cx18 *cx;
 340         int bus_index;   /* 0 or 1 for the cx23418's 1st or 2nd I2C bus */
 341 };
 342
 343 /* Struct to hold info about cx18 cards */
 344 struct cx18 {
 345         int num;                /* board number, -1 during init! */
 346         char name[8];           /* board name for printk and interrupts (e.g. 'cx180') */
 347         struct pci_dev *dev;    /* PCI device */
 348         const struct cx18_card *card;   /* card information */
 349         const char *card_name;  /* full name of the card */
 350         const struct cx18_card_tuner_i2c *card_i2c; /* i2c addresses to probe for tuner */
 351         u8 is_50hz;
 352         u8 is_60hz;
 353         u8 is_out_50hz;
 354         u8 is_out_60hz;
 355         u8 nof_inputs;          /* number of video inputs */
 356         u8 nof_audio_inputs;    /* number of audio inputs */
 357         u16 buffer_id;          /* buffer ID counter */
 358         u32 v4l2_cap;           /* V4L2 capabilities of card */
 359         u32 hw_flags;           /* Hardware description of the board */
 360         unsigned mdl_offset;
 361         struct cx18_scb __iomem *scb;   /* pointer to SCB */
 362
 363         struct cx18_av_state av_state;
 364
 365         /* codec settings */
 366         struct cx2341x_mpeg_params params;
 367         u32 filter_mode;
 368         u32 temporal_strength;
 369         u32 spatial_strength;
 370
 371         /* dualwatch */
 372         unsigned long dualwatch_jiffies;
 373         u16 dualwatch_stereo_mode;
 374
 375         /* Digitizer type */
 376         int digitizer;          /* 0x00EF = saa7114 0x00FO = saa7115 0x0106 = mic */
 377
 378         struct mutex serialize_lock;    /* mutex used to serialize open/close/start/stop/ioctl operations */
 379         struct cx18_options options;    /* User options */
 380         int stream_buf_size[CX18_MAX_STREAMS]; /* Stream buffer size */
 381         struct cx18_stream streams[CX18_MAX_STREAMS];   /* Stream data */
 382         unsigned long i_flags;  /* global cx18 flags */
 383         atomic_t ana_capturing; /* count number of active analog capture streams */
 384         atomic_t tot_capturing; /* total count number of active capture streams */
 385         spinlock_t lock;        /* lock access to this struct */
 386         int search_pack_header;
 387
 388         spinlock_t dma_reg_lock; /* lock access to DMA engine registers */
 389
 390         int open_id;            /* incremented each time an open occurs, used as
 391                                    unique ID. Starts at 1, so 0 can be used as
 392                                    uninitialized value in the stream->id. */
 393
 394         u32 base_addr;
 395         struct v4l2_prio_state prio;
 396
 397         u8 card_rev;
 398         void __iomem *enc_mem, *reg_mem;
 399
 400         struct vbi_info vbi;
 401
 402         u32 pgm_info_offset;
 403         u32 pgm_info_num;
 404         u32 pgm_info_write_idx;
 405         u32 pgm_info_read_idx;
 406         struct v4l2_enc_idx_entry pgm_info[CX18_MAX_PGM_INDEX];
 407
 408         u64 mpg_data_received;
 409         u64 vbi_data_inserted;
 410
 411         wait_queue_head_t mb_apu_waitq;
 412         wait_queue_head_t mb_cpu_waitq;
 413         wait_queue_head_t mb_epu_waitq;
 414         wait_queue_head_t mb_hpu_waitq;
 415         wait_queue_head_t cap_w;
 416         /* when the current DMA is finished this queue is woken up */
 417         wait_queue_head_t dma_waitq;
 418
 419         /* i2c */
 420         struct i2c_adapter i2c_adap[2];
 421         struct i2c_algo_bit_data i2c_algo[2];
 422         struct cx18_i2c_algo_callback_data i2c_algo_cb_data[2];
 423         struct i2c_client i2c_client[2];
 424         struct mutex i2c_bus_lock[2];
 425         struct i2c_client *i2c_clients[I2C_CLIENTS_MAX];
 426
 427         /* gpio */
 428         u32 gpio_dir;
 429         u32 gpio_val;
 430
 431         /* v4l2 and User settings */
 432
 433         /* codec settings */
 434         u32 audio_input;
 435         u32 active_input;
 436         u32 active_output;
 437         v4l2_std_id std;
 438         v4l2_std_id tuner_std;  /* The norm of the tuner (fixed) */
 439 };
 440
 441 /* Globals */
 442 extern struct cx18 *cx18_cards[];
 443 extern int cx18_cards_active;
 444 extern int cx18_first_minor;
 445 extern spinlock_t cx18_cards_lock;
 446
 447 /*==============Prototypes==================*/
 448
 449 /* Return non-zero if a signal is pending */
 450 int cx18_msleep_timeout(unsigned int msecs, int intr);
 451
 452 /* Read Hauppauge eeprom */
 453 struct tveeprom; /* forward reference */
 454 void cx18_read_eeprom(struct cx18 *cx, struct tveeprom *tv);
 455
 456 /* First-open initialization: load firmware, etc. */
 457 int cx18_init_on_first_open(struct cx18 *cx);
 458
 459 /* This is a PCI post thing, where if the pci register is not read, then
 460    the write doesn't always take effect right away. By reading back the
 461    register any pending PCI writes will be performed (in order), and so
 462    you can be sure that the writes are guaranteed to be done.
 463
 464    Rarely needed, only in some timing sensitive cases.
 465    Apparently if this is not done some motherboards seem
 466    to kill the firmware and get into the broken state until computer is
 467    rebooted. */
 468 #define write_sync(val, reg) \
 469         do { writel(val, reg); readl(reg); } while (0)
 470
 471 #define read_reg(reg) readl(cx->reg_mem + (reg))
 472 #define write_reg(val, reg) writel(val, cx->reg_mem + (reg))
 473 #define write_reg_sync(val, reg) \
 474         do { write_reg(val, reg); read_reg(reg); } while (0)
 475
 476 #define read_enc(addr) readl(cx->enc_mem + (u32)(addr))
 477 #define write_enc(val, addr) writel(val, cx->enc_mem + (u32)(addr))
 478 #define write_enc_sync(val, addr) \
 479         do { write_enc(val, addr); read_enc(addr); } while (0)
 480
 481 #define sw1_irq_enable(val) do { \
 482         write_reg(val, SW1_INT_STATUS); \
 483         write_reg(read_reg(SW1_INT_ENABLE_PCI) | (val), SW1_INT_ENABLE_PCI); \
 484 } while (0)
 485
 486 #define sw1_irq_disable(val) \
 487         write_reg(read_reg(SW1_INT_ENABLE_PCI) & ~(val), SW1_INT_ENABLE_PCI);
 488
 489 #define sw2_irq_enable(val) do { \
 490         write_reg(val, SW2_INT_STATUS); \
 491         write_reg(read_reg(SW2_INT_ENABLE_PCI) | (val), SW2_INT_ENABLE_PCI); \
 492 } while (0)
 493
 494 #define sw2_irq_disable(val) \
 495         write_reg(read_reg(SW2_INT_ENABLE_PCI) & ~(val), SW2_INT_ENABLE_PCI);
 496
 497 #define setup_page(addr) do { \
 498     u32 val = read_reg(0xD000F8) & ~0x1f00; \
 499     write_reg(val | (((addr) >> 17) & 0x1f00), 0xD000F8); \
 500 } while (0)
 501
 502 #endif /* CX18_DRIVER_H */