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ALSA: oxygen: allow to dump codec registers
[linux-2.6.git] / sound / pci / oxygen / oxygen_lib.c
blobe581e7ab216cc6e2e310a11b9e59587dcec26432
1 /*
2 * C-Media CMI8788 driver - main driver module
3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 *
6 *
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
9 *
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/mutex.h>
23 #include <linux/pci.h>
24 #include <linux/slab.h>
25 #include <sound/ac97_codec.h>
26 #include <sound/asoundef.h>
27 #include <sound/core.h>
28 #include <sound/info.h>
29 #include <sound/mpu401.h>
30 #include <sound/pcm.h>
31 #include "oxygen.h"
32 #include "cm9780.h"
33
34 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
35 MODULE_DESCRIPTION("C-Media CMI8788 helper library");
36 MODULE_LICENSE("GPL v2");
37
38 #define DRIVER "oxygen"
39
40 static inline int oxygen_uart_input_ready(struct oxygen *chip)
41 {
42 return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY);
43 }
44
45 static void oxygen_read_uart(struct oxygen *chip)
46 {
47 if (unlikely(!oxygen_uart_input_ready(chip))) {
48 /* no data, but read it anyway to clear the interrupt */
49 oxygen_read8(chip, OXYGEN_MPU401);
50 return;
51 }
52 do {
53 u8 data = oxygen_read8(chip, OXYGEN_MPU401);
54 if (data == MPU401_ACK)
55 continue;
56 if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input))
57 chip->uart_input_count = 0;
58 chip->uart_input[chip->uart_input_count++] = data;
59 } while (oxygen_uart_input_ready(chip));
60 if (chip->model.uart_input)
61 chip->model.uart_input(chip);
62 }
63
64 static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
65 {
66 struct oxygen *chip = dev_id;
67 unsigned int status, clear, elapsed_streams, i;
68
69 status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
70 if (!status)
71 return IRQ_NONE;
72
73 spin_lock(&chip->reg_lock);
74
75 clear = status & (OXYGEN_CHANNEL_A |
76 OXYGEN_CHANNEL_B |
77 OXYGEN_CHANNEL_C |
78 OXYGEN_CHANNEL_SPDIF |
79 OXYGEN_CHANNEL_MULTICH |
80 OXYGEN_CHANNEL_AC97 |
81 OXYGEN_INT_SPDIF_IN_DETECT |
82 OXYGEN_INT_GPIO |
83 OXYGEN_INT_AC97);
84 if (clear) {
85 if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
86 chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
87 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
88 chip->interrupt_mask & ~clear);
89 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
90 chip->interrupt_mask);
91 }
92
93 elapsed_streams = status & chip->pcm_running;
94
95 spin_unlock(&chip->reg_lock);
96
97 for (i = 0; i < PCM_COUNT; ++i)
98 if ((elapsed_streams & (1 << i)) && chip->streams[i])
99 snd_pcm_period_elapsed(chip->streams[i]);
100
101 if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
102 spin_lock(&chip->reg_lock);
103 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
104 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
105 OXYGEN_SPDIF_RATE_INT)) {
106 /* write the interrupt bit(s) to clear */
107 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
108 schedule_work(&chip->spdif_input_bits_work);
109 }
110 spin_unlock(&chip->reg_lock);
111 }
112
113 if (status & OXYGEN_INT_GPIO)
114 schedule_work(&chip->gpio_work);
115
116 if (status & OXYGEN_INT_MIDI) {
117 if (chip->midi)
118 snd_mpu401_uart_interrupt(0, chip->midi->private_data);
119 else
120 oxygen_read_uart(chip);
121 }
122
123 if (status & OXYGEN_INT_AC97)
124 wake_up(&chip->ac97_waitqueue);
125
126 return IRQ_HANDLED;
127 }
128
129 static void oxygen_spdif_input_bits_changed(struct work_struct *work)
130 {
131 struct oxygen *chip = container_of(work, struct oxygen,
132 spdif_input_bits_work);
133 u32 reg;
134
135 /*
136 * This function gets called when there is new activity on the SPDIF
137 * input, or when we lose lock on the input signal, or when the rate
138 * changes.
139 */
140 msleep(1);
141 spin_lock_irq(&chip->reg_lock);
142 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
143 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
144 OXYGEN_SPDIF_LOCK_STATUS))
145 == OXYGEN_SPDIF_SENSE_STATUS) {
146 /*
147 * If we detect activity on the SPDIF input but cannot lock to
148 * a signal, the clock bit is likely to be wrong.
149 */
150 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
151 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
152 spin_unlock_irq(&chip->reg_lock);
153 msleep(1);
154 spin_lock_irq(&chip->reg_lock);
155 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
156 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
157 OXYGEN_SPDIF_LOCK_STATUS))
158 == OXYGEN_SPDIF_SENSE_STATUS) {
159 /* nothing detected with either clock; give up */
160 if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
161 == OXYGEN_SPDIF_IN_CLOCK_192) {
162 /*
163 * Reset clock to <= 96 kHz because this is
164 * more likely to be received next time.
165 */
166 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
167 reg |= OXYGEN_SPDIF_IN_CLOCK_96;
168 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
169 }
170 }
171 }
172 spin_unlock_irq(&chip->reg_lock);
173
174 if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
175 spin_lock_irq(&chip->reg_lock);
176 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
177 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
178 chip->interrupt_mask);
179 spin_unlock_irq(&chip->reg_lock);
180
181 /*
182 * We don't actually know that any channel status bits have
183 * changed, but let's send a notification just to be sure.
184 */
185 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
186 &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
187 }
188 }
189
190 static void oxygen_gpio_changed(struct work_struct *work)
191 {
192 struct oxygen *chip = container_of(work, struct oxygen, gpio_work);
193
194 if (chip->model.gpio_changed)
195 chip->model.gpio_changed(chip);
196 }
197
198 #ifdef CONFIG_PROC_FS
199 static void oxygen_proc_read(struct snd_info_entry *entry,
200 struct snd_info_buffer *buffer)
201 {
202 struct oxygen *chip = entry->private_data;
203 int i, j;
204
205 snd_iprintf(buffer, "CMI8788:\n");
206 for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) {
207 snd_iprintf(buffer, "%02x:", i);
208 for (j = 0; j < 0x10; ++j)
209 snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
210 snd_iprintf(buffer, "\n");
211 }
212 if (mutex_lock_interruptible(&chip->mutex) < 0)
213 return;
214 if (chip->has_ac97_0) {
215 snd_iprintf(buffer, "\nAC97:\n");
216 for (i = 0; i < 0x80; i += 0x10) {
217 snd_iprintf(buffer, "%02x:", i);
218 for (j = 0; j < 0x10; j += 2)
219 snd_iprintf(buffer, " %04x",
220 oxygen_read_ac97(chip, 0, i + j));
221 snd_iprintf(buffer, "\n");
222 }
223 }
224 if (chip->has_ac97_1) {
225 snd_iprintf(buffer, "\nAC97 2:\n");
226 for (i = 0; i < 0x80; i += 0x10) {
227 snd_iprintf(buffer, "%02x:", i);
228 for (j = 0; j < 0x10; j += 2)
229 snd_iprintf(buffer, " %04x",
230 oxygen_read_ac97(chip, 1, i + j));
231 snd_iprintf(buffer, "\n");
232 }
233 }
234 mutex_unlock(&chip->mutex);
235 if (chip->model.dump_registers)
236 chip->model.dump_registers(chip, buffer);
237 }
238
239 static void oxygen_proc_init(struct oxygen *chip)
240 {
241 struct snd_info_entry *entry;
242
243 if (!snd_card_proc_new(chip->card, "oxygen", &entry))
244 snd_info_set_text_ops(entry, chip, oxygen_proc_read);
245 }
246 #else
247 #define oxygen_proc_init(chip)
248 #endif
249
250 static const struct pci_device_id *
251 oxygen_search_pci_id(struct oxygen *chip, const struct pci_device_id ids[])
252 {
253 u16 subdevice;
254
255 /*
256 * Make sure the EEPROM pins are available, i.e., not used for SPI.
257 * (This function is called before we initialize or use SPI.)
258 */
259 oxygen_clear_bits8(chip, OXYGEN_FUNCTION,
260 OXYGEN_FUNCTION_ENABLE_SPI_4_5);
261 /*
262 * Read the subsystem device ID directly from the EEPROM, because the
263 * chip didn't if the first EEPROM word was overwritten.
264 */
265 subdevice = oxygen_read_eeprom(chip, 2);
266 /* use default ID if EEPROM is missing */
267 if (subdevice == 0xffff && oxygen_read_eeprom(chip, 1) == 0xffff)
268 subdevice = 0x8788;
269 /*
270 * We use only the subsystem device ID for searching because it is
271 * unique even without the subsystem vendor ID, which may have been
272 * overwritten in the EEPROM.
273 */
274 for (; ids->vendor; ++ids)
275 if (ids->subdevice == subdevice &&
276 ids->driver_data != BROKEN_EEPROM_DRIVER_DATA)
277 return ids;
278 return NULL;
279 }
280
281 static void oxygen_restore_eeprom(struct oxygen *chip,
282 const struct pci_device_id *id)
283 {
284 u16 eeprom_id;
285
286 eeprom_id = oxygen_read_eeprom(chip, 0);
287 if (eeprom_id != OXYGEN_EEPROM_ID &&
288 (eeprom_id != 0xffff || id->subdevice != 0x8788)) {
289 /*
290 * This function gets called only when a known card model has
291 * been detected, i.e., we know there is a valid subsystem
292 * product ID at index 2 in the EEPROM. Therefore, we have
293 * been able to deduce the correct subsystem vendor ID, and
294 * this is enough information to restore the original EEPROM
295 * contents.
296 */
297 oxygen_write_eeprom(chip, 1, id->subvendor);
298 oxygen_write_eeprom(chip, 0, OXYGEN_EEPROM_ID);
299
300 oxygen_set_bits8(chip, OXYGEN_MISC,
301 OXYGEN_MISC_WRITE_PCI_SUBID);
302 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID,
303 id->subvendor);
304 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_ID,
305 id->subdevice);
306 oxygen_clear_bits8(chip, OXYGEN_MISC,
307 OXYGEN_MISC_WRITE_PCI_SUBID);
308
309 snd_printk(KERN_INFO "EEPROM ID restored\n");
310 }
311 }
312
313 static void configure_pcie_bridge(struct pci_dev *pci)
314 {
315 enum { PEX811X, PI7C9X110 };
316 static const struct pci_device_id bridge_ids[] = {
317 { PCI_VDEVICE(PLX, 0x8111), .driver_data = PEX811X },
318 { PCI_VDEVICE(PLX, 0x8112), .driver_data = PEX811X },
319 { PCI_DEVICE(0x12d8, 0xe110), .driver_data = PI7C9X110 },
320 { }
321 };
322 struct pci_dev *bridge;
323 const struct pci_device_id *id;
324 u32 tmp;
325
326 if (!pci->bus || !pci->bus->self)
327 return;
328 bridge = pci->bus->self;
329
330 id = pci_match_id(bridge_ids, bridge);
331 if (!id)
332 return;
333
334 switch (id->driver_data) {
335 case PEX811X: /* PLX PEX8111/PEX8112 PCIe/PCI bridge */
336 pci_read_config_dword(bridge, 0x48, &tmp);
337 tmp |= 1; /* enable blind prefetching */
338 tmp |= 1 << 11; /* enable beacon generation */
339 pci_write_config_dword(bridge, 0x48, tmp);
340
341 pci_write_config_dword(bridge, 0x84, 0x0c);
342 pci_read_config_dword(bridge, 0x88, &tmp);
343 tmp &= ~(7 << 27);
344 tmp |= 2 << 27; /* set prefetch size to 128 bytes */
345 pci_write_config_dword(bridge, 0x88, tmp);
346 break;
347
348 case PI7C9X110: /* Pericom PI7C9X110 PCIe/PCI bridge */
349 pci_read_config_dword(bridge, 0x40, &tmp);
350 tmp |= 1; /* park the PCI arbiter to the sound chip */
351 pci_write_config_dword(bridge, 0x40, tmp);
352 break;
353 }
354 }
355
356 static void oxygen_init(struct oxygen *chip)
357 {
358 unsigned int i;
359
360 chip->dac_routing = 1;
361 for (i = 0; i < 8; ++i)
362 chip->dac_volume[i] = chip->model.dac_volume_min;
363 chip->dac_mute = 1;
364 chip->spdif_playback_enable = 1;
365 chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
366 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
367 chip->spdif_pcm_bits = chip->spdif_bits;
368
369 if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2)
370 chip->revision = 2;
371 else
372 chip->revision = 1;
373
374 if (chip->revision == 1)
375 oxygen_set_bits8(chip, OXYGEN_MISC,
376 OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
377
378 i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
379 chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
380 chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
381
382 oxygen_write8_masked(chip, OXYGEN_FUNCTION,
383 OXYGEN_FUNCTION_RESET_CODEC |
384 chip->model.function_flags,
385 OXYGEN_FUNCTION_RESET_CODEC |
386 OXYGEN_FUNCTION_2WIRE_SPI_MASK |
387 OXYGEN_FUNCTION_ENABLE_SPI_4_5);
388 oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
389 oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
390 oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
391 OXYGEN_PLAY_CHANNELS_2 |
392 OXYGEN_DMA_A_BURST_8 |
393 OXYGEN_DMA_MULTICH_BURST_8);
394 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
395 oxygen_write8_masked(chip, OXYGEN_MISC,
396 chip->model.misc_flags,
397 OXYGEN_MISC_WRITE_PCI_SUBID |
398 OXYGEN_MISC_REC_C_FROM_SPDIF |
399 OXYGEN_MISC_REC_B_FROM_AC97 |
400 OXYGEN_MISC_REC_A_FROM_MULTICH |
401 OXYGEN_MISC_MIDI);
402 oxygen_write8(chip, OXYGEN_REC_FORMAT,
403 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
404 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
405 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
406 oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
407 (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
408 (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
409 oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
410 oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
411 OXYGEN_RATE_48000 | chip->model.dac_i2s_format |
412 OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
413 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
414 if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
415 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
416 OXYGEN_RATE_48000 | chip->model.adc_i2s_format |
417 OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
418 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
419 else
420 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
421 OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
422 if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 |
423 CAPTURE_2_FROM_I2S_2))
424 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
425 OXYGEN_RATE_48000 | chip->model.adc_i2s_format |
426 OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
427 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
428 else
429 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
430 OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
431 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
432 OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
433 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
434 OXYGEN_SPDIF_OUT_ENABLE |
435 OXYGEN_SPDIF_LOOPBACK);
436 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
437 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
438 OXYGEN_SPDIF_SENSE_MASK |
439 OXYGEN_SPDIF_LOCK_MASK |
440 OXYGEN_SPDIF_RATE_MASK |
441 OXYGEN_SPDIF_LOCK_PAR |
442 OXYGEN_SPDIF_IN_CLOCK_96,
443 OXYGEN_SPDIF_SENSE_MASK |
444 OXYGEN_SPDIF_LOCK_MASK |
445 OXYGEN_SPDIF_RATE_MASK |
446 OXYGEN_SPDIF_SENSE_PAR |
447 OXYGEN_SPDIF_LOCK_PAR |
448 OXYGEN_SPDIF_IN_CLOCK_MASK);
449 else
450 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
451 OXYGEN_SPDIF_SENSE_MASK |
452 OXYGEN_SPDIF_LOCK_MASK |
453 OXYGEN_SPDIF_RATE_MASK);
454 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
455 oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
456 OXYGEN_2WIRE_LENGTH_8 |
457 OXYGEN_2WIRE_INTERRUPT_MASK |
458 OXYGEN_2WIRE_SPEED_STANDARD);
459 oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
460 oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
461 oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
462 oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
463 OXYGEN_PLAY_MULTICH_I2S_DAC |
464 OXYGEN_PLAY_SPDIF_SPDIF |
465 (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
466 (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
467 (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
468 (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
469 oxygen_write8(chip, OXYGEN_REC_ROUTING,
470 OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
471 OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
472 OXYGEN_REC_C_ROUTE_SPDIF);
473 oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
474 oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
475 (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
476 (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
477 (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
478 (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
479
480 if (chip->has_ac97_0 | chip->has_ac97_1)
481 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
482 OXYGEN_AC97_INT_READ_DONE |
483 OXYGEN_AC97_INT_WRITE_DONE);
484 else
485 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
486 oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
487 oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
488 if (!(chip->has_ac97_0 | chip->has_ac97_1))
489 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
490 OXYGEN_AC97_CLOCK_DISABLE);
491 if (!chip->has_ac97_0) {
492 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
493 OXYGEN_AC97_NO_CODEC_0);
494 } else {
495 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
496 msleep(1);
497 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
498 CM9780_GPIO0IO | CM9780_GPIO1IO);
499 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
500 CM9780_BSTSEL | CM9780_STRO_MIC |
501 CM9780_MIX2FR | CM9780_PCBSW);
502 oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
503 CM9780_RSOE | CM9780_CBOE |
504 CM9780_SSOE | CM9780_FROE |
505 CM9780_MIC2MIC | CM9780_LI2LI);
506 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
507 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
508 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
509 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
510 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
511 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
512 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
513 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
514 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
515 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
516 oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS,
517 CM9780_GPO0);
518 /* power down unused ADCs and DACs */
519 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
520 AC97_PD_PR0 | AC97_PD_PR1);
521 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
522 AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
523 }
524 if (chip->has_ac97_1) {
525 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
526 OXYGEN_AC97_CODEC1_SLOT3 |
527 OXYGEN_AC97_CODEC1_SLOT4);
528 oxygen_write_ac97(chip, 1, AC97_RESET, 0);
529 msleep(1);
530 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
531 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
532 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
533 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
534 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
535 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
536 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
537 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
538 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
539 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
540 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000);
541 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
542 }
543 }
544
545 static void oxygen_shutdown(struct oxygen *chip)
546 {
547 spin_lock_irq(&chip->reg_lock);
548 chip->interrupt_mask = 0;
549 chip->pcm_running = 0;
550 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
551 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
552 spin_unlock_irq(&chip->reg_lock);
553 }
554
555 static void oxygen_card_free(struct snd_card *card)
556 {
557 struct oxygen *chip = card->private_data;
558
559 oxygen_shutdown(chip);
560 if (chip->irq >= 0)
561 free_irq(chip->irq, chip);
562 flush_scheduled_work();
563 chip->model.cleanup(chip);
564 kfree(chip->model_data);
565 mutex_destroy(&chip->mutex);
566 pci_release_regions(chip->pci);
567 pci_disable_device(chip->pci);
568 }
569
570 int oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
571 struct module *owner,
572 const struct pci_device_id *ids,
573 int (*get_model)(struct oxygen *chip,
574 const struct pci_device_id *id
575 )
576 )
577 {
578 struct snd_card *card;
579 struct oxygen *chip;
580 const struct pci_device_id *pci_id;
581 int err;
582
583 err = snd_card_create(index, id, owner, sizeof(*chip), &card);
584 if (err < 0)
585 return err;
586
587 chip = card->private_data;
588 chip->card = card;
589 chip->pci = pci;
590 chip->irq = -1;
591 spin_lock_init(&chip->reg_lock);
592 mutex_init(&chip->mutex);
593 INIT_WORK(&chip->spdif_input_bits_work,
594 oxygen_spdif_input_bits_changed);
595 INIT_WORK(&chip->gpio_work, oxygen_gpio_changed);
596 init_waitqueue_head(&chip->ac97_waitqueue);
597
598 err = pci_enable_device(pci);
599 if (err < 0)
600 goto err_card;
601
602 err = pci_request_regions(pci, DRIVER);
603 if (err < 0) {
604 snd_printk(KERN_ERR "cannot reserve PCI resources\n");
605 goto err_pci_enable;
606 }
607
608 if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
609 pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) {
610 snd_printk(KERN_ERR "invalid PCI I/O range\n");
611 err = -ENXIO;
612 goto err_pci_regions;
613 }
614 chip->addr = pci_resource_start(pci, 0);
615
616 pci_id = oxygen_search_pci_id(chip, ids);
617 if (!pci_id) {
618 err = -ENODEV;
619 goto err_pci_regions;
620 }
621 oxygen_restore_eeprom(chip, pci_id);
622 err = get_model(chip, pci_id);
623 if (err < 0)
624 goto err_pci_regions;
625
626 if (chip->model.model_data_size) {
627 chip->model_data = kzalloc(chip->model.model_data_size,
628 GFP_KERNEL);
629 if (!chip->model_data) {
630 err = -ENOMEM;
631 goto err_pci_regions;
632 }
633 }
634
635 pci_set_master(pci);
636 snd_card_set_dev(card, &pci->dev);
637 card->private_free = oxygen_card_free;
638
639 configure_pcie_bridge(pci);
640 oxygen_init(chip);
641 chip->model.init(chip);
642
643 err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
644 DRIVER, chip);
645 if (err < 0) {
646 snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq);
647 goto err_card;
648 }
649 chip->irq = pci->irq;
650
651 strcpy(card->driver, chip->model.chip);
652 strcpy(card->shortname, chip->model.shortname);
653 sprintf(card->longname, "%s (rev %u) at %#lx, irq %i",
654 chip->model.longname, chip->revision, chip->addr, chip->irq);
655 strcpy(card->mixername, chip->model.chip);
656 snd_component_add(card, chip->model.chip);
657
658 err = oxygen_pcm_init(chip);
659 if (err < 0)
660 goto err_card;
661
662 err = oxygen_mixer_init(chip);
663 if (err < 0)
664 goto err_card;
665
666 if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) {
667 unsigned int info_flags = MPU401_INFO_INTEGRATED;
668 if (chip->model.device_config & MIDI_OUTPUT)
669 info_flags |= MPU401_INFO_OUTPUT;
670 if (chip->model.device_config & MIDI_INPUT)
671 info_flags |= MPU401_INFO_INPUT;
672 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
673 chip->addr + OXYGEN_MPU401,
674 info_flags, 0, 0,
675 &chip->midi);
676 if (err < 0)
677 goto err_card;
678 }
679
680 oxygen_proc_init(chip);
681
682 spin_lock_irq(&chip->reg_lock);
683 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
684 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
685 if (chip->has_ac97_0 | chip->has_ac97_1)
686 chip->interrupt_mask |= OXYGEN_INT_AC97;
687 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
688 spin_unlock_irq(&chip->reg_lock);
689
690 err = snd_card_register(card);
691 if (err < 0)
692 goto err_card;
693
694 pci_set_drvdata(pci, card);
695 return 0;
696
697 err_pci_regions:
698 pci_release_regions(pci);
699 err_pci_enable:
700 pci_disable_device(pci);
701 err_card:
702 snd_card_free(card);
703 return err;
704 }
705 EXPORT_SYMBOL(oxygen_pci_probe);
706
707 void oxygen_pci_remove(struct pci_dev *pci)
708 {
709 snd_card_free(pci_get_drvdata(pci));
710 pci_set_drvdata(pci, NULL);
711 }
712 EXPORT_SYMBOL(oxygen_pci_remove);
713
714 #ifdef CONFIG_PM
715 int oxygen_pci_suspend(struct pci_dev *pci, pm_message_t state)
716 {
717 struct snd_card *card = pci_get_drvdata(pci);
718 struct oxygen *chip = card->private_data;
719 unsigned int i, saved_interrupt_mask;
720
721 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
722
723 for (i = 0; i < PCM_COUNT; ++i)
724 if (chip->streams[i])
725 snd_pcm_suspend(chip->streams[i]);
726
727 if (chip->model.suspend)
728 chip->model.suspend(chip);
729
730 spin_lock_irq(&chip->reg_lock);
731 saved_interrupt_mask = chip->interrupt_mask;
732 chip->interrupt_mask = 0;
733 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
734 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
735 spin_unlock_irq(&chip->reg_lock);
736
737 synchronize_irq(chip->irq);
738 flush_scheduled_work();
739 chip->interrupt_mask = saved_interrupt_mask;
740
741 pci_disable_device(pci);
742 pci_save_state(pci);
743 pci_set_power_state(pci, pci_choose_state(pci, state));
744 return 0;
745 }
746 EXPORT_SYMBOL(oxygen_pci_suspend);
747
748 static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = {
749 0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff,
750 0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000
751 };
752 static const u32 ac97_registers_to_restore[2][0x40 / 32] = {
753 { 0x18284fa2, 0x03060000 },
754 { 0x00007fa6, 0x00200000 }
755 };
756
757 static inline int is_bit_set(const u32 *bitmap, unsigned int bit)
758 {
759 return bitmap[bit / 32] & (1 << (bit & 31));
760 }
761
762 static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec)
763 {
764 unsigned int i;
765
766 oxygen_write_ac97(chip, codec, AC97_RESET, 0);
767 msleep(1);
768 for (i = 1; i < 0x40; ++i)
769 if (is_bit_set(ac97_registers_to_restore[codec], i))
770 oxygen_write_ac97(chip, codec, i * 2,
771 chip->saved_ac97_registers[codec][i]);
772 }
773
774 int oxygen_pci_resume(struct pci_dev *pci)
775 {
776 struct snd_card *card = pci_get_drvdata(pci);
777 struct oxygen *chip = card->private_data;
778 unsigned int i;
779
780 pci_set_power_state(pci, PCI_D0);
781 pci_restore_state(pci);
782 if (pci_enable_device(pci) < 0) {
783 snd_printk(KERN_ERR "cannot reenable device");
784 snd_card_disconnect(card);
785 return -EIO;
786 }
787 pci_set_master(pci);
788
789 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
790 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
791 for (i = 0; i < OXYGEN_IO_SIZE; ++i)
792 if (is_bit_set(registers_to_restore, i))
793 oxygen_write8(chip, i, chip->saved_registers._8[i]);
794 if (chip->has_ac97_0)
795 oxygen_restore_ac97(chip, 0);
796 if (chip->has_ac97_1)
797 oxygen_restore_ac97(chip, 1);
798
799 if (chip->model.resume)
800 chip->model.resume(chip);
801
802 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
803
804 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
805 return 0;
806 }
807 EXPORT_SYMBOL(oxygen_pci_resume);
808 #endif /* CONFIG_PM */
809
810 void oxygen_pci_shutdown(struct pci_dev *pci)
811 {
812 struct snd_card *card = pci_get_drvdata(pci);
813 struct oxygen *chip = card->private_data;
814
815 oxygen_shutdown(chip);
816 chip->model.cleanup(chip);
817 }
818 EXPORT_SYMBOL(oxygen_pci_shutdown);
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