1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
35 #include <linux/interrupt.h>
37 #include <linux/tcp.h>
38 #include <linux/pkt_sched.h>
39 #include <linux/ipv6.h>
40 #include <linux/slab.h>
41 #include <net/checksum.h>
42 #include <net/ip6_checksum.h>
43 #include <linux/ethtool.h>
44 #include <linux/if_vlan.h>
45 #include <linux/prefetch.h>
46 #include <scsi/fc/fc_fcoe.h>
49 #include "ixgbe_common.h"
50 #include "ixgbe_dcb_82599.h"
51 #include "ixgbe_sriov.h"
53 char ixgbe_driver_name
[] = "ixgbe";
54 static const char ixgbe_driver_string
[] =
55 "Intel(R) 10 Gigabit PCI Express Network Driver";
60 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
61 __stringify(BUILD) "-k" __stringify(KFIX)
62 const char ixgbe_driver_version
[] = DRV_VERSION
;
63 static const char ixgbe_copyright
[] =
64 "Copyright (c) 1999-2011 Intel Corporation.";
66 static const struct ixgbe_info
*ixgbe_info_tbl
[] = {
67 [board_82598
] = &ixgbe_82598_info
,
68 [board_82599
] = &ixgbe_82599_info
,
69 [board_X540
] = &ixgbe_X540_info
,
72 /* ixgbe_pci_tbl - PCI Device ID Table
74 * Wildcard entries (PCI_ANY_ID) should come last
75 * Last entry must be all 0s
77 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
78 * Class, Class Mask, private data (not used) }
80 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl
) = {
81 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598
),
83 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_DUAL_PORT
),
85 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_SINGLE_PORT
),
87 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT
),
89 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT2
),
91 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_CX4
),
93 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_CX4_DUAL_PORT
),
95 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_DA_DUAL_PORT
),
97 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
),
99 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_XF_LR
),
101 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_SFP_LOM
),
103 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_BX
),
105 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4
),
107 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_XAUI_LOM
),
109 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KR
),
111 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP
),
113 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_EM
),
115 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4_MEZZ
),
117 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_CX4
),
119 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_BACKPLANE_FCOE
),
121 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_FCOE
),
123 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_T3_LOM
),
125 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_COMBO_BACKPLANE
),
127 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_X540T
),
129 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_SF2
),
131 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_LS
),
134 /* required last entry */
137 MODULE_DEVICE_TABLE(pci
, ixgbe_pci_tbl
);
139 #ifdef CONFIG_IXGBE_DCA
140 static int ixgbe_notify_dca(struct notifier_block
*, unsigned long event
,
142 static struct notifier_block dca_notifier
= {
143 .notifier_call
= ixgbe_notify_dca
,
149 #ifdef CONFIG_PCI_IOV
150 static unsigned int max_vfs
;
151 module_param(max_vfs
, uint
, 0);
152 MODULE_PARM_DESC(max_vfs
,
153 "Maximum number of virtual functions to allocate per physical function");
154 #endif /* CONFIG_PCI_IOV */
156 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
157 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
158 MODULE_LICENSE("GPL");
159 MODULE_VERSION(DRV_VERSION
);
161 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
163 static inline void ixgbe_disable_sriov(struct ixgbe_adapter
*adapter
)
165 struct ixgbe_hw
*hw
= &adapter
->hw
;
170 #ifdef CONFIG_PCI_IOV
171 /* disable iov and allow time for transactions to clear */
172 pci_disable_sriov(adapter
->pdev
);
175 /* turn off device IOV mode */
176 gcr
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
177 gcr
&= ~(IXGBE_GCR_EXT_SRIOV
);
178 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr
);
179 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
180 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
181 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
183 /* set default pool back to 0 */
184 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
185 vmdctl
&= ~IXGBE_VT_CTL_POOL_MASK
;
186 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
);
188 /* take a breather then clean up driver data */
191 kfree(adapter
->vfinfo
);
192 adapter
->vfinfo
= NULL
;
194 adapter
->num_vfs
= 0;
195 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
198 static void ixgbe_service_event_schedule(struct ixgbe_adapter
*adapter
)
200 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
) &&
201 !test_and_set_bit(__IXGBE_SERVICE_SCHED
, &adapter
->state
))
202 schedule_work(&adapter
->service_task
);
205 static void ixgbe_service_event_complete(struct ixgbe_adapter
*adapter
)
207 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED
, &adapter
->state
));
209 /* flush memory to make sure state is correct before next watchog */
210 smp_mb__before_clear_bit();
211 clear_bit(__IXGBE_SERVICE_SCHED
, &adapter
->state
);
214 struct ixgbe_reg_info
{
219 static const struct ixgbe_reg_info ixgbe_reg_info_tbl
[] = {
221 /* General Registers */
222 {IXGBE_CTRL
, "CTRL"},
223 {IXGBE_STATUS
, "STATUS"},
224 {IXGBE_CTRL_EXT
, "CTRL_EXT"},
226 /* Interrupt Registers */
227 {IXGBE_EICR
, "EICR"},
230 {IXGBE_SRRCTL(0), "SRRCTL"},
231 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
232 {IXGBE_RDLEN(0), "RDLEN"},
233 {IXGBE_RDH(0), "RDH"},
234 {IXGBE_RDT(0), "RDT"},
235 {IXGBE_RXDCTL(0), "RXDCTL"},
236 {IXGBE_RDBAL(0), "RDBAL"},
237 {IXGBE_RDBAH(0), "RDBAH"},
240 {IXGBE_TDBAL(0), "TDBAL"},
241 {IXGBE_TDBAH(0), "TDBAH"},
242 {IXGBE_TDLEN(0), "TDLEN"},
243 {IXGBE_TDH(0), "TDH"},
244 {IXGBE_TDT(0), "TDT"},
245 {IXGBE_TXDCTL(0), "TXDCTL"},
247 /* List Terminator */
253 * ixgbe_regdump - register printout routine
255 static void ixgbe_regdump(struct ixgbe_hw
*hw
, struct ixgbe_reg_info
*reginfo
)
261 switch (reginfo
->ofs
) {
262 case IXGBE_SRRCTL(0):
263 for (i
= 0; i
< 64; i
++)
264 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_SRRCTL(i
));
266 case IXGBE_DCA_RXCTRL(0):
267 for (i
= 0; i
< 64; i
++)
268 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(i
));
271 for (i
= 0; i
< 64; i
++)
272 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDLEN(i
));
275 for (i
= 0; i
< 64; i
++)
276 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDH(i
));
279 for (i
= 0; i
< 64; i
++)
280 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDT(i
));
282 case IXGBE_RXDCTL(0):
283 for (i
= 0; i
< 64; i
++)
284 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
287 for (i
= 0; i
< 64; i
++)
288 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAL(i
));
291 for (i
= 0; i
< 64; i
++)
292 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAH(i
));
295 for (i
= 0; i
< 64; i
++)
296 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAL(i
));
299 for (i
= 0; i
< 64; i
++)
300 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAH(i
));
303 for (i
= 0; i
< 64; i
++)
304 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDLEN(i
));
307 for (i
= 0; i
< 64; i
++)
308 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDH(i
));
311 for (i
= 0; i
< 64; i
++)
312 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDT(i
));
314 case IXGBE_TXDCTL(0):
315 for (i
= 0; i
< 64; i
++)
316 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TXDCTL(i
));
319 pr_info("%-15s %08x\n", reginfo
->name
,
320 IXGBE_READ_REG(hw
, reginfo
->ofs
));
324 for (i
= 0; i
< 8; i
++) {
325 snprintf(rname
, 16, "%s[%d-%d]", reginfo
->name
, i
*8, i
*8+7);
326 pr_err("%-15s", rname
);
327 for (j
= 0; j
< 8; j
++)
328 pr_cont(" %08x", regs
[i
*8+j
]);
335 * ixgbe_dump - Print registers, tx-rings and rx-rings
337 static void ixgbe_dump(struct ixgbe_adapter
*adapter
)
339 struct net_device
*netdev
= adapter
->netdev
;
340 struct ixgbe_hw
*hw
= &adapter
->hw
;
341 struct ixgbe_reg_info
*reginfo
;
343 struct ixgbe_ring
*tx_ring
;
344 struct ixgbe_tx_buffer
*tx_buffer_info
;
345 union ixgbe_adv_tx_desc
*tx_desc
;
346 struct my_u0
{ u64 a
; u64 b
; } *u0
;
347 struct ixgbe_ring
*rx_ring
;
348 union ixgbe_adv_rx_desc
*rx_desc
;
349 struct ixgbe_rx_buffer
*rx_buffer_info
;
353 if (!netif_msg_hw(adapter
))
356 /* Print netdevice Info */
358 dev_info(&adapter
->pdev
->dev
, "Net device Info\n");
359 pr_info("Device Name state "
360 "trans_start last_rx\n");
361 pr_info("%-15s %016lX %016lX %016lX\n",
368 /* Print Registers */
369 dev_info(&adapter
->pdev
->dev
, "Register Dump\n");
370 pr_info(" Register Name Value\n");
371 for (reginfo
= (struct ixgbe_reg_info
*)ixgbe_reg_info_tbl
;
372 reginfo
->name
; reginfo
++) {
373 ixgbe_regdump(hw
, reginfo
);
376 /* Print TX Ring Summary */
377 if (!netdev
|| !netif_running(netdev
))
380 dev_info(&adapter
->pdev
->dev
, "TX Rings Summary\n");
381 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
382 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
383 tx_ring
= adapter
->tx_ring
[n
];
385 &tx_ring
->tx_buffer_info
[tx_ring
->next_to_clean
];
386 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
387 n
, tx_ring
->next_to_use
, tx_ring
->next_to_clean
,
388 (u64
)tx_buffer_info
->dma
,
389 tx_buffer_info
->length
,
390 tx_buffer_info
->next_to_watch
,
391 (u64
)tx_buffer_info
->time_stamp
);
395 if (!netif_msg_tx_done(adapter
))
396 goto rx_ring_summary
;
398 dev_info(&adapter
->pdev
->dev
, "TX Rings Dump\n");
400 /* Transmit Descriptor Formats
402 * Advanced Transmit Descriptor
403 * +--------------------------------------------------------------+
404 * 0 | Buffer Address [63:0] |
405 * +--------------------------------------------------------------+
406 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
407 * +--------------------------------------------------------------+
408 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
411 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
412 tx_ring
= adapter
->tx_ring
[n
];
413 pr_info("------------------------------------\n");
414 pr_info("TX QUEUE INDEX = %d\n", tx_ring
->queue_index
);
415 pr_info("------------------------------------\n");
416 pr_info("T [desc] [address 63:0 ] "
417 "[PlPOIdStDDt Ln] [bi->dma ] "
418 "leng ntw timestamp bi->skb\n");
420 for (i
= 0; tx_ring
->desc
&& (i
< tx_ring
->count
); i
++) {
421 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
422 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
423 u0
= (struct my_u0
*)tx_desc
;
424 pr_info("T [0x%03X] %016llX %016llX %016llX"
425 " %04X %3X %016llX %p", i
,
428 (u64
)tx_buffer_info
->dma
,
429 tx_buffer_info
->length
,
430 tx_buffer_info
->next_to_watch
,
431 (u64
)tx_buffer_info
->time_stamp
,
432 tx_buffer_info
->skb
);
433 if (i
== tx_ring
->next_to_use
&&
434 i
== tx_ring
->next_to_clean
)
436 else if (i
== tx_ring
->next_to_use
)
438 else if (i
== tx_ring
->next_to_clean
)
443 if (netif_msg_pktdata(adapter
) &&
444 tx_buffer_info
->dma
!= 0)
445 print_hex_dump(KERN_INFO
, "",
446 DUMP_PREFIX_ADDRESS
, 16, 1,
447 phys_to_virt(tx_buffer_info
->dma
),
448 tx_buffer_info
->length
, true);
452 /* Print RX Rings Summary */
454 dev_info(&adapter
->pdev
->dev
, "RX Rings Summary\n");
455 pr_info("Queue [NTU] [NTC]\n");
456 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
457 rx_ring
= adapter
->rx_ring
[n
];
458 pr_info("%5d %5X %5X\n",
459 n
, rx_ring
->next_to_use
, rx_ring
->next_to_clean
);
463 if (!netif_msg_rx_status(adapter
))
466 dev_info(&adapter
->pdev
->dev
, "RX Rings Dump\n");
468 /* Advanced Receive Descriptor (Read) Format
470 * +-----------------------------------------------------+
471 * 0 | Packet Buffer Address [63:1] |A0/NSE|
472 * +----------------------------------------------+------+
473 * 8 | Header Buffer Address [63:1] | DD |
474 * +-----------------------------------------------------+
477 * Advanced Receive Descriptor (Write-Back) Format
479 * 63 48 47 32 31 30 21 20 16 15 4 3 0
480 * +------------------------------------------------------+
481 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
482 * | Checksum Ident | | | | Type | Type |
483 * +------------------------------------------------------+
484 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
485 * +------------------------------------------------------+
486 * 63 48 47 32 31 20 19 0
488 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
489 rx_ring
= adapter
->rx_ring
[n
];
490 pr_info("------------------------------------\n");
491 pr_info("RX QUEUE INDEX = %d\n", rx_ring
->queue_index
);
492 pr_info("------------------------------------\n");
493 pr_info("R [desc] [ PktBuf A0] "
494 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
495 "<-- Adv Rx Read format\n");
496 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
497 "[vl er S cks ln] ---------------- [bi->skb] "
498 "<-- Adv Rx Write-Back format\n");
500 for (i
= 0; i
< rx_ring
->count
; i
++) {
501 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
502 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
503 u0
= (struct my_u0
*)rx_desc
;
504 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
505 if (staterr
& IXGBE_RXD_STAT_DD
) {
506 /* Descriptor Done */
507 pr_info("RWB[0x%03X] %016llX "
508 "%016llX ---------------- %p", i
,
511 rx_buffer_info
->skb
);
513 pr_info("R [0x%03X] %016llX "
514 "%016llX %016llX %p", i
,
517 (u64
)rx_buffer_info
->dma
,
518 rx_buffer_info
->skb
);
520 if (netif_msg_pktdata(adapter
)) {
521 print_hex_dump(KERN_INFO
, "",
522 DUMP_PREFIX_ADDRESS
, 16, 1,
523 phys_to_virt(rx_buffer_info
->dma
),
524 rx_ring
->rx_buf_len
, true);
526 if (rx_ring
->rx_buf_len
527 < IXGBE_RXBUFFER_2048
)
528 print_hex_dump(KERN_INFO
, "",
529 DUMP_PREFIX_ADDRESS
, 16, 1,
531 rx_buffer_info
->page_dma
+
532 rx_buffer_info
->page_offset
538 if (i
== rx_ring
->next_to_use
)
540 else if (i
== rx_ring
->next_to_clean
)
552 static void ixgbe_release_hw_control(struct ixgbe_adapter
*adapter
)
556 /* Let firmware take over control of h/w */
557 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
558 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
559 ctrl_ext
& ~IXGBE_CTRL_EXT_DRV_LOAD
);
562 static void ixgbe_get_hw_control(struct ixgbe_adapter
*adapter
)
566 /* Let firmware know the driver has taken over */
567 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
568 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
569 ctrl_ext
| IXGBE_CTRL_EXT_DRV_LOAD
);
573 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
574 * @adapter: pointer to adapter struct
575 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
576 * @queue: queue to map the corresponding interrupt to
577 * @msix_vector: the vector to map to the corresponding queue
580 static void ixgbe_set_ivar(struct ixgbe_adapter
*adapter
, s8 direction
,
581 u8 queue
, u8 msix_vector
)
584 struct ixgbe_hw
*hw
= &adapter
->hw
;
585 switch (hw
->mac
.type
) {
586 case ixgbe_mac_82598EB
:
587 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
590 index
= (((direction
* 64) + queue
) >> 2) & 0x1F;
591 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
592 ivar
&= ~(0xFF << (8 * (queue
& 0x3)));
593 ivar
|= (msix_vector
<< (8 * (queue
& 0x3)));
594 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
596 case ixgbe_mac_82599EB
:
598 if (direction
== -1) {
600 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
601 index
= ((queue
& 1) * 8);
602 ivar
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_IVAR_MISC
);
603 ivar
&= ~(0xFF << index
);
604 ivar
|= (msix_vector
<< index
);
605 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_IVAR_MISC
, ivar
);
608 /* tx or rx causes */
609 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
610 index
= ((16 * (queue
& 1)) + (8 * direction
));
611 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(queue
>> 1));
612 ivar
&= ~(0xFF << index
);
613 ivar
|= (msix_vector
<< index
);
614 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(queue
>> 1), ivar
);
622 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter
*adapter
,
627 switch (adapter
->hw
.mac
.type
) {
628 case ixgbe_mac_82598EB
:
629 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
630 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS
, mask
);
632 case ixgbe_mac_82599EB
:
634 mask
= (qmask
& 0xFFFFFFFF);
635 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(0), mask
);
636 mask
= (qmask
>> 32);
637 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(1), mask
);
644 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring
*tx_ring
,
645 struct ixgbe_tx_buffer
*tx_buffer_info
)
647 if (tx_buffer_info
->dma
) {
648 if (tx_buffer_info
->mapped_as_page
)
649 dma_unmap_page(tx_ring
->dev
,
651 tx_buffer_info
->length
,
654 dma_unmap_single(tx_ring
->dev
,
656 tx_buffer_info
->length
,
658 tx_buffer_info
->dma
= 0;
660 if (tx_buffer_info
->skb
) {
661 dev_kfree_skb_any(tx_buffer_info
->skb
);
662 tx_buffer_info
->skb
= NULL
;
664 tx_buffer_info
->time_stamp
= 0;
665 /* tx_buffer_info must be completely set up in the transmit path */
668 static void ixgbe_update_xoff_received(struct ixgbe_adapter
*adapter
)
670 struct ixgbe_hw
*hw
= &adapter
->hw
;
671 struct ixgbe_hw_stats
*hwstats
= &adapter
->stats
;
676 if ((hw
->fc
.current_mode
== ixgbe_fc_full
) ||
677 (hw
->fc
.current_mode
== ixgbe_fc_rx_pause
)) {
678 switch (hw
->mac
.type
) {
679 case ixgbe_mac_82598EB
:
680 data
= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
683 data
= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
685 hwstats
->lxoffrxc
+= data
;
687 /* refill credits (no tx hang) if we received xoff */
691 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
692 clear_bit(__IXGBE_HANG_CHECK_ARMED
,
693 &adapter
->tx_ring
[i
]->state
);
695 } else if (!(adapter
->dcb_cfg
.pfc_mode_enable
))
698 /* update stats for each tc, only valid with PFC enabled */
699 for (i
= 0; i
< MAX_TX_PACKET_BUFFERS
; i
++) {
700 switch (hw
->mac
.type
) {
701 case ixgbe_mac_82598EB
:
702 xoff
[i
] = IXGBE_READ_REG(hw
, IXGBE_PXOFFRXC(i
));
705 xoff
[i
] = IXGBE_READ_REG(hw
, IXGBE_PXOFFRXCNT(i
));
707 hwstats
->pxoffrxc
[i
] += xoff
[i
];
710 /* disarm tx queues that have received xoff frames */
711 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
712 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[i
];
713 u8 tc
= tx_ring
->dcb_tc
;
716 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &tx_ring
->state
);
720 static u64
ixgbe_get_tx_completed(struct ixgbe_ring
*ring
)
722 return ring
->tx_stats
.completed
;
725 static u64
ixgbe_get_tx_pending(struct ixgbe_ring
*ring
)
727 struct ixgbe_adapter
*adapter
= netdev_priv(ring
->netdev
);
728 struct ixgbe_hw
*hw
= &adapter
->hw
;
730 u32 head
= IXGBE_READ_REG(hw
, IXGBE_TDH(ring
->reg_idx
));
731 u32 tail
= IXGBE_READ_REG(hw
, IXGBE_TDT(ring
->reg_idx
));
734 return (head
< tail
) ?
735 tail
- head
: (tail
+ ring
->count
- head
);
740 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring
*tx_ring
)
742 u32 tx_done
= ixgbe_get_tx_completed(tx_ring
);
743 u32 tx_done_old
= tx_ring
->tx_stats
.tx_done_old
;
744 u32 tx_pending
= ixgbe_get_tx_pending(tx_ring
);
747 clear_check_for_tx_hang(tx_ring
);
750 * Check for a hung queue, but be thorough. This verifies
751 * that a transmit has been completed since the previous
752 * check AND there is at least one packet pending. The
753 * ARMED bit is set to indicate a potential hang. The
754 * bit is cleared if a pause frame is received to remove
755 * false hang detection due to PFC or 802.3x frames. By
756 * requiring this to fail twice we avoid races with
757 * pfc clearing the ARMED bit and conditions where we
758 * run the check_tx_hang logic with a transmit completion
759 * pending but without time to complete it yet.
761 if ((tx_done_old
== tx_done
) && tx_pending
) {
762 /* make sure it is true for two checks in a row */
763 ret
= test_and_set_bit(__IXGBE_HANG_CHECK_ARMED
,
766 /* update completed stats and continue */
767 tx_ring
->tx_stats
.tx_done_old
= tx_done
;
768 /* reset the countdown */
769 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &tx_ring
->state
);
775 #define IXGBE_MAX_TXD_PWR 14
776 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
778 /* Tx Descriptors needed, worst case */
779 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
780 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
781 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
782 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
785 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
786 * @adapter: driver private struct
788 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter
*adapter
)
791 /* Do the reset outside of interrupt context */
792 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
793 adapter
->flags2
|= IXGBE_FLAG2_RESET_REQUESTED
;
794 ixgbe_service_event_schedule(adapter
);
799 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
800 * @q_vector: structure containing interrupt and ring information
801 * @tx_ring: tx ring to clean
803 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector
*q_vector
,
804 struct ixgbe_ring
*tx_ring
)
806 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
807 union ixgbe_adv_tx_desc
*tx_desc
, *eop_desc
;
808 struct ixgbe_tx_buffer
*tx_buffer_info
;
809 unsigned int total_bytes
= 0, total_packets
= 0;
810 u16 i
, eop
, count
= 0;
812 i
= tx_ring
->next_to_clean
;
813 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
814 eop_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
816 while ((eop_desc
->wb
.status
& cpu_to_le32(IXGBE_TXD_STAT_DD
)) &&
817 (count
< tx_ring
->work_limit
)) {
818 bool cleaned
= false;
819 rmb(); /* read buffer_info after eop_desc */
820 for ( ; !cleaned
; count
++) {
821 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
822 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
824 tx_desc
->wb
.status
= 0;
825 cleaned
= (i
== eop
);
828 if (i
== tx_ring
->count
)
831 if (cleaned
&& tx_buffer_info
->skb
) {
832 total_bytes
+= tx_buffer_info
->bytecount
;
833 total_packets
+= tx_buffer_info
->gso_segs
;
836 ixgbe_unmap_and_free_tx_resource(tx_ring
,
840 tx_ring
->tx_stats
.completed
++;
841 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
842 eop_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
845 tx_ring
->next_to_clean
= i
;
846 tx_ring
->total_bytes
+= total_bytes
;
847 tx_ring
->total_packets
+= total_packets
;
848 u64_stats_update_begin(&tx_ring
->syncp
);
849 tx_ring
->stats
.packets
+= total_packets
;
850 tx_ring
->stats
.bytes
+= total_bytes
;
851 u64_stats_update_end(&tx_ring
->syncp
);
853 if (check_for_tx_hang(tx_ring
) && ixgbe_check_tx_hang(tx_ring
)) {
854 /* schedule immediate reset if we believe we hung */
855 struct ixgbe_hw
*hw
= &adapter
->hw
;
856 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
857 e_err(drv
, "Detected Tx Unit Hang\n"
859 " TDH, TDT <%x>, <%x>\n"
860 " next_to_use <%x>\n"
861 " next_to_clean <%x>\n"
862 "tx_buffer_info[next_to_clean]\n"
863 " time_stamp <%lx>\n"
865 tx_ring
->queue_index
,
866 IXGBE_READ_REG(hw
, IXGBE_TDH(tx_ring
->reg_idx
)),
867 IXGBE_READ_REG(hw
, IXGBE_TDT(tx_ring
->reg_idx
)),
868 tx_ring
->next_to_use
, eop
,
869 tx_ring
->tx_buffer_info
[eop
].time_stamp
, jiffies
);
871 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
874 "tx hang %d detected on queue %d, resetting adapter\n",
875 adapter
->tx_timeout_count
+ 1, tx_ring
->queue_index
);
877 /* schedule immediate reset if we believe we hung */
878 ixgbe_tx_timeout_reset(adapter
);
880 /* the adapter is about to reset, no point in enabling stuff */
884 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
885 if (unlikely(count
&& netif_carrier_ok(tx_ring
->netdev
) &&
886 (IXGBE_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
887 /* Make sure that anybody stopping the queue after this
888 * sees the new next_to_clean.
891 if (__netif_subqueue_stopped(tx_ring
->netdev
, tx_ring
->queue_index
) &&
892 !test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
893 netif_wake_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
894 ++tx_ring
->tx_stats
.restart_queue
;
898 return count
< tx_ring
->work_limit
;
901 #ifdef CONFIG_IXGBE_DCA
902 static void ixgbe_update_rx_dca(struct ixgbe_adapter
*adapter
,
903 struct ixgbe_ring
*rx_ring
,
906 struct ixgbe_hw
*hw
= &adapter
->hw
;
908 u8 reg_idx
= rx_ring
->reg_idx
;
910 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(reg_idx
));
911 switch (hw
->mac
.type
) {
912 case ixgbe_mac_82598EB
:
913 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK
;
914 rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
916 case ixgbe_mac_82599EB
:
918 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599
;
919 rxctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
920 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
);
925 rxctrl
|= IXGBE_DCA_RXCTRL_DESC_DCA_EN
;
926 rxctrl
|= IXGBE_DCA_RXCTRL_HEAD_DCA_EN
;
927 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN
);
928 IXGBE_WRITE_REG(hw
, IXGBE_DCA_RXCTRL(reg_idx
), rxctrl
);
931 static void ixgbe_update_tx_dca(struct ixgbe_adapter
*adapter
,
932 struct ixgbe_ring
*tx_ring
,
935 struct ixgbe_hw
*hw
= &adapter
->hw
;
937 u8 reg_idx
= tx_ring
->reg_idx
;
939 switch (hw
->mac
.type
) {
940 case ixgbe_mac_82598EB
:
941 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(reg_idx
));
942 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK
;
943 txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
944 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
945 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(reg_idx
), txctrl
);
947 case ixgbe_mac_82599EB
:
949 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(reg_idx
));
950 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599
;
951 txctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
952 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
);
953 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
954 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(reg_idx
), txctrl
);
961 static void ixgbe_update_dca(struct ixgbe_q_vector
*q_vector
)
963 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
968 if (q_vector
->cpu
== cpu
)
971 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
972 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
973 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[r_idx
], cpu
);
974 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
978 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
979 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
980 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[r_idx
], cpu
);
981 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
990 static void ixgbe_setup_dca(struct ixgbe_adapter
*adapter
)
995 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
998 /* always use CB2 mode, difference is masked in the CB driver */
999 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 2);
1001 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
1002 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1006 for (i
= 0; i
< num_q_vectors
; i
++) {
1007 adapter
->q_vector
[i
]->cpu
= -1;
1008 ixgbe_update_dca(adapter
->q_vector
[i
]);
1012 static int __ixgbe_notify_dca(struct device
*dev
, void *data
)
1014 struct ixgbe_adapter
*adapter
= dev_get_drvdata(dev
);
1015 unsigned long event
= *(unsigned long *)data
;
1017 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
1021 case DCA_PROVIDER_ADD
:
1022 /* if we're already enabled, don't do it again */
1023 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1025 if (dca_add_requester(dev
) == 0) {
1026 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
1027 ixgbe_setup_dca(adapter
);
1030 /* Fall Through since DCA is disabled. */
1031 case DCA_PROVIDER_REMOVE
:
1032 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
1033 dca_remove_requester(dev
);
1034 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
1035 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
1042 #endif /* CONFIG_IXGBE_DCA */
1044 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc
*rx_desc
,
1045 struct sk_buff
*skb
)
1047 skb
->rxhash
= le32_to_cpu(rx_desc
->wb
.lower
.hi_dword
.rss
);
1051 * ixgbe_receive_skb - Send a completed packet up the stack
1052 * @adapter: board private structure
1053 * @skb: packet to send up
1054 * @status: hardware indication of status of receive
1055 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1056 * @rx_desc: rx descriptor
1058 static void ixgbe_receive_skb(struct ixgbe_q_vector
*q_vector
,
1059 struct sk_buff
*skb
, u8 status
,
1060 struct ixgbe_ring
*ring
,
1061 union ixgbe_adv_rx_desc
*rx_desc
)
1063 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1064 struct napi_struct
*napi
= &q_vector
->napi
;
1065 bool is_vlan
= (status
& IXGBE_RXD_STAT_VP
);
1066 u16 tag
= le16_to_cpu(rx_desc
->wb
.upper
.vlan
);
1068 if (is_vlan
&& (tag
& VLAN_VID_MASK
))
1069 __vlan_hwaccel_put_tag(skb
, tag
);
1071 if (!(adapter
->flags
& IXGBE_FLAG_IN_NETPOLL
))
1072 napi_gro_receive(napi
, skb
);
1078 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1079 * @adapter: address of board private structure
1080 * @status_err: hardware indication of status of receive
1081 * @skb: skb currently being received and modified
1083 static inline void ixgbe_rx_checksum(struct ixgbe_adapter
*adapter
,
1084 union ixgbe_adv_rx_desc
*rx_desc
,
1085 struct sk_buff
*skb
)
1087 u32 status_err
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1089 skb_checksum_none_assert(skb
);
1091 /* Rx csum disabled */
1092 if (!(adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
))
1095 /* if IP and error */
1096 if ((status_err
& IXGBE_RXD_STAT_IPCS
) &&
1097 (status_err
& IXGBE_RXDADV_ERR_IPE
)) {
1098 adapter
->hw_csum_rx_error
++;
1102 if (!(status_err
& IXGBE_RXD_STAT_L4CS
))
1105 if (status_err
& IXGBE_RXDADV_ERR_TCPE
) {
1106 u16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1109 * 82599 errata, UDP frames with a 0 checksum can be marked as
1112 if ((pkt_info
& IXGBE_RXDADV_PKTTYPE_UDP
) &&
1113 (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
1116 adapter
->hw_csum_rx_error
++;
1120 /* It must be a TCP or UDP packet with a valid checksum */
1121 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1124 static inline void ixgbe_release_rx_desc(struct ixgbe_ring
*rx_ring
, u32 val
)
1127 * Force memory writes to complete before letting h/w
1128 * know there are new descriptors to fetch. (Only
1129 * applicable for weak-ordered memory model archs,
1133 writel(val
, rx_ring
->tail
);
1137 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1138 * @rx_ring: ring to place buffers on
1139 * @cleaned_count: number of buffers to replace
1141 void ixgbe_alloc_rx_buffers(struct ixgbe_ring
*rx_ring
, u16 cleaned_count
)
1143 union ixgbe_adv_rx_desc
*rx_desc
;
1144 struct ixgbe_rx_buffer
*bi
;
1145 struct sk_buff
*skb
;
1146 u16 i
= rx_ring
->next_to_use
;
1148 /* do nothing if no valid netdev defined */
1149 if (!rx_ring
->netdev
)
1152 while (cleaned_count
--) {
1153 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1154 bi
= &rx_ring
->rx_buffer_info
[i
];
1158 skb
= netdev_alloc_skb_ip_align(rx_ring
->netdev
,
1159 rx_ring
->rx_buf_len
);
1161 rx_ring
->rx_stats
.alloc_rx_buff_failed
++;
1164 /* initialize queue mapping */
1165 skb_record_rx_queue(skb
, rx_ring
->queue_index
);
1170 bi
->dma
= dma_map_single(rx_ring
->dev
,
1172 rx_ring
->rx_buf_len
,
1174 if (dma_mapping_error(rx_ring
->dev
, bi
->dma
)) {
1175 rx_ring
->rx_stats
.alloc_rx_buff_failed
++;
1181 if (ring_is_ps_enabled(rx_ring
)) {
1183 bi
->page
= netdev_alloc_page(rx_ring
->netdev
);
1185 rx_ring
->rx_stats
.alloc_rx_page_failed
++;
1190 if (!bi
->page_dma
) {
1191 /* use a half page if we're re-using */
1192 bi
->page_offset
^= PAGE_SIZE
/ 2;
1193 bi
->page_dma
= dma_map_page(rx_ring
->dev
,
1198 if (dma_mapping_error(rx_ring
->dev
,
1200 rx_ring
->rx_stats
.alloc_rx_page_failed
++;
1206 /* Refresh the desc even if buffer_addrs didn't change
1207 * because each write-back erases this info. */
1208 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
1209 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
1211 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
1212 rx_desc
->read
.hdr_addr
= 0;
1216 if (i
== rx_ring
->count
)
1221 if (rx_ring
->next_to_use
!= i
) {
1222 rx_ring
->next_to_use
= i
;
1223 ixgbe_release_rx_desc(rx_ring
, i
);
1227 static inline u16
ixgbe_get_hlen(union ixgbe_adv_rx_desc
*rx_desc
)
1229 /* HW will not DMA in data larger than the given buffer, even if it
1230 * parses the (NFS, of course) header to be larger. In that case, it
1231 * fills the header buffer and spills the rest into the page.
1233 u16 hdr_info
= le16_to_cpu(rx_desc
->wb
.lower
.lo_dword
.hs_rss
.hdr_info
);
1234 u16 hlen
= (hdr_info
& IXGBE_RXDADV_HDRBUFLEN_MASK
) >>
1235 IXGBE_RXDADV_HDRBUFLEN_SHIFT
;
1236 if (hlen
> IXGBE_RX_HDR_SIZE
)
1237 hlen
= IXGBE_RX_HDR_SIZE
;
1242 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1243 * @skb: pointer to the last skb in the rsc queue
1245 * This function changes a queue full of hw rsc buffers into a completed
1246 * packet. It uses the ->prev pointers to find the first packet and then
1247 * turns it into the frag list owner.
1249 static inline struct sk_buff
*ixgbe_transform_rsc_queue(struct sk_buff
*skb
)
1251 unsigned int frag_list_size
= 0;
1252 unsigned int skb_cnt
= 1;
1255 struct sk_buff
*prev
= skb
->prev
;
1256 frag_list_size
+= skb
->len
;
1262 skb_shinfo(skb
)->frag_list
= skb
->next
;
1264 skb
->len
+= frag_list_size
;
1265 skb
->data_len
+= frag_list_size
;
1266 skb
->truesize
+= frag_list_size
;
1267 IXGBE_RSC_CB(skb
)->skb_cnt
= skb_cnt
;
1272 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc
*rx_desc
)
1274 return !!(le32_to_cpu(rx_desc
->wb
.lower
.lo_dword
.data
) &
1275 IXGBE_RXDADV_RSCCNT_MASK
);
1278 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector
*q_vector
,
1279 struct ixgbe_ring
*rx_ring
,
1280 int *work_done
, int work_to_do
)
1282 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1283 union ixgbe_adv_rx_desc
*rx_desc
, *next_rxd
;
1284 struct ixgbe_rx_buffer
*rx_buffer_info
, *next_buffer
;
1285 struct sk_buff
*skb
;
1286 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
1287 const int current_node
= numa_node_id();
1290 #endif /* IXGBE_FCOE */
1293 u16 cleaned_count
= 0;
1294 bool pkt_is_rsc
= false;
1296 i
= rx_ring
->next_to_clean
;
1297 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1298 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1300 while (staterr
& IXGBE_RXD_STAT_DD
) {
1303 rmb(); /* read descriptor and rx_buffer_info after status DD */
1305 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
1307 skb
= rx_buffer_info
->skb
;
1308 rx_buffer_info
->skb
= NULL
;
1309 prefetch(skb
->data
);
1311 if (ring_is_rsc_enabled(rx_ring
))
1312 pkt_is_rsc
= ixgbe_get_rsc_state(rx_desc
);
1314 /* if this is a skb from previous receive DMA will be 0 */
1315 if (rx_buffer_info
->dma
) {
1318 !(staterr
& IXGBE_RXD_STAT_EOP
) &&
1321 * When HWRSC is enabled, delay unmapping
1322 * of the first packet. It carries the
1323 * header information, HW may still
1324 * access the header after the writeback.
1325 * Only unmap it when EOP is reached
1327 IXGBE_RSC_CB(skb
)->delay_unmap
= true;
1328 IXGBE_RSC_CB(skb
)->dma
= rx_buffer_info
->dma
;
1330 dma_unmap_single(rx_ring
->dev
,
1331 rx_buffer_info
->dma
,
1332 rx_ring
->rx_buf_len
,
1335 rx_buffer_info
->dma
= 0;
1337 if (ring_is_ps_enabled(rx_ring
)) {
1338 hlen
= ixgbe_get_hlen(rx_desc
);
1339 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1341 hlen
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1346 /* assume packet split since header is unmapped */
1347 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1351 dma_unmap_page(rx_ring
->dev
,
1352 rx_buffer_info
->page_dma
,
1355 rx_buffer_info
->page_dma
= 0;
1356 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
1357 rx_buffer_info
->page
,
1358 rx_buffer_info
->page_offset
,
1361 if ((page_count(rx_buffer_info
->page
) == 1) &&
1362 (page_to_nid(rx_buffer_info
->page
) == current_node
))
1363 get_page(rx_buffer_info
->page
);
1365 rx_buffer_info
->page
= NULL
;
1367 skb
->len
+= upper_len
;
1368 skb
->data_len
+= upper_len
;
1369 skb
->truesize
+= upper_len
;
1373 if (i
== rx_ring
->count
)
1376 next_rxd
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1381 u32 nextp
= (staterr
& IXGBE_RXDADV_NEXTP_MASK
) >>
1382 IXGBE_RXDADV_NEXTP_SHIFT
;
1383 next_buffer
= &rx_ring
->rx_buffer_info
[nextp
];
1385 next_buffer
= &rx_ring
->rx_buffer_info
[i
];
1388 if (!(staterr
& IXGBE_RXD_STAT_EOP
)) {
1389 if (ring_is_ps_enabled(rx_ring
)) {
1390 rx_buffer_info
->skb
= next_buffer
->skb
;
1391 rx_buffer_info
->dma
= next_buffer
->dma
;
1392 next_buffer
->skb
= skb
;
1393 next_buffer
->dma
= 0;
1395 skb
->next
= next_buffer
->skb
;
1396 skb
->next
->prev
= skb
;
1398 rx_ring
->rx_stats
.non_eop_descs
++;
1403 skb
= ixgbe_transform_rsc_queue(skb
);
1404 /* if we got here without RSC the packet is invalid */
1406 __pskb_trim(skb
, 0);
1407 rx_buffer_info
->skb
= skb
;
1412 if (ring_is_rsc_enabled(rx_ring
)) {
1413 if (IXGBE_RSC_CB(skb
)->delay_unmap
) {
1414 dma_unmap_single(rx_ring
->dev
,
1415 IXGBE_RSC_CB(skb
)->dma
,
1416 rx_ring
->rx_buf_len
,
1418 IXGBE_RSC_CB(skb
)->dma
= 0;
1419 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
1423 if (ring_is_ps_enabled(rx_ring
))
1424 rx_ring
->rx_stats
.rsc_count
+=
1425 skb_shinfo(skb
)->nr_frags
;
1427 rx_ring
->rx_stats
.rsc_count
+=
1428 IXGBE_RSC_CB(skb
)->skb_cnt
;
1429 rx_ring
->rx_stats
.rsc_flush
++;
1432 /* ERR_MASK will only have valid bits if EOP set */
1433 if (staterr
& IXGBE_RXDADV_ERR_FRAME_ERR_MASK
) {
1434 /* trim packet back to size 0 and recycle it */
1435 __pskb_trim(skb
, 0);
1436 rx_buffer_info
->skb
= skb
;
1440 ixgbe_rx_checksum(adapter
, rx_desc
, skb
);
1441 if (adapter
->netdev
->features
& NETIF_F_RXHASH
)
1442 ixgbe_rx_hash(rx_desc
, skb
);
1444 /* probably a little skewed due to removing CRC */
1445 total_rx_bytes
+= skb
->len
;
1448 skb
->protocol
= eth_type_trans(skb
, rx_ring
->netdev
);
1450 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1451 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
1452 ddp_bytes
= ixgbe_fcoe_ddp(adapter
, rx_desc
, skb
);
1456 #endif /* IXGBE_FCOE */
1457 ixgbe_receive_skb(q_vector
, skb
, staterr
, rx_ring
, rx_desc
);
1460 rx_desc
->wb
.upper
.status_error
= 0;
1463 if (*work_done
>= work_to_do
)
1466 /* return some buffers to hardware, one at a time is too slow */
1467 if (cleaned_count
>= IXGBE_RX_BUFFER_WRITE
) {
1468 ixgbe_alloc_rx_buffers(rx_ring
, cleaned_count
);
1472 /* use prefetched values */
1474 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1477 rx_ring
->next_to_clean
= i
;
1478 cleaned_count
= IXGBE_DESC_UNUSED(rx_ring
);
1481 ixgbe_alloc_rx_buffers(rx_ring
, cleaned_count
);
1484 /* include DDPed FCoE data */
1485 if (ddp_bytes
> 0) {
1488 mss
= rx_ring
->netdev
->mtu
- sizeof(struct fcoe_hdr
) -
1489 sizeof(struct fc_frame_header
) -
1490 sizeof(struct fcoe_crc_eof
);
1493 total_rx_bytes
+= ddp_bytes
;
1494 total_rx_packets
+= DIV_ROUND_UP(ddp_bytes
, mss
);
1496 #endif /* IXGBE_FCOE */
1498 rx_ring
->total_packets
+= total_rx_packets
;
1499 rx_ring
->total_bytes
+= total_rx_bytes
;
1500 u64_stats_update_begin(&rx_ring
->syncp
);
1501 rx_ring
->stats
.packets
+= total_rx_packets
;
1502 rx_ring
->stats
.bytes
+= total_rx_bytes
;
1503 u64_stats_update_end(&rx_ring
->syncp
);
1506 static int ixgbe_clean_rxonly(struct napi_struct
*, int);
1508 * ixgbe_configure_msix - Configure MSI-X hardware
1509 * @adapter: board private structure
1511 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1514 static void ixgbe_configure_msix(struct ixgbe_adapter
*adapter
)
1516 struct ixgbe_q_vector
*q_vector
;
1517 int i
, q_vectors
, v_idx
, r_idx
;
1520 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1523 * Populate the IVAR table and set the ITR values to the
1524 * corresponding register.
1526 for (v_idx
= 0; v_idx
< q_vectors
; v_idx
++) {
1527 q_vector
= adapter
->q_vector
[v_idx
];
1528 /* XXX for_each_set_bit(...) */
1529 r_idx
= find_first_bit(q_vector
->rxr_idx
,
1530 adapter
->num_rx_queues
);
1532 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1533 u8 reg_idx
= adapter
->rx_ring
[r_idx
]->reg_idx
;
1534 ixgbe_set_ivar(adapter
, 0, reg_idx
, v_idx
);
1535 r_idx
= find_next_bit(q_vector
->rxr_idx
,
1536 adapter
->num_rx_queues
,
1539 r_idx
= find_first_bit(q_vector
->txr_idx
,
1540 adapter
->num_tx_queues
);
1542 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1543 u8 reg_idx
= adapter
->tx_ring
[r_idx
]->reg_idx
;
1544 ixgbe_set_ivar(adapter
, 1, reg_idx
, v_idx
);
1545 r_idx
= find_next_bit(q_vector
->txr_idx
,
1546 adapter
->num_tx_queues
,
1550 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
1552 q_vector
->eitr
= adapter
->tx_eitr_param
;
1553 else if (q_vector
->rxr_count
)
1555 q_vector
->eitr
= adapter
->rx_eitr_param
;
1557 ixgbe_write_eitr(q_vector
);
1558 /* If Flow Director is enabled, set interrupt affinity */
1559 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
1560 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)) {
1562 * Allocate the affinity_hint cpumask, assign the mask
1563 * for this vector, and set our affinity_hint for
1566 if (!alloc_cpumask_var(&q_vector
->affinity_mask
,
1569 cpumask_set_cpu(v_idx
, q_vector
->affinity_mask
);
1570 irq_set_affinity_hint(adapter
->msix_entries
[v_idx
].vector
,
1571 q_vector
->affinity_mask
);
1575 switch (adapter
->hw
.mac
.type
) {
1576 case ixgbe_mac_82598EB
:
1577 ixgbe_set_ivar(adapter
, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX
,
1580 case ixgbe_mac_82599EB
:
1581 case ixgbe_mac_X540
:
1582 ixgbe_set_ivar(adapter
, -1, 1, v_idx
);
1588 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
), 1950);
1590 /* set up to autoclear timer, and the vectors */
1591 mask
= IXGBE_EIMS_ENABLE_MASK
;
1592 if (adapter
->num_vfs
)
1593 mask
&= ~(IXGBE_EIMS_OTHER
|
1594 IXGBE_EIMS_MAILBOX
|
1597 mask
&= ~(IXGBE_EIMS_OTHER
| IXGBE_EIMS_LSC
);
1598 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIAC
, mask
);
1601 enum latency_range
{
1605 latency_invalid
= 255
1609 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1610 * @adapter: pointer to adapter
1611 * @eitr: eitr setting (ints per sec) to give last timeslice
1612 * @itr_setting: current throttle rate in ints/second
1613 * @packets: the number of packets during this measurement interval
1614 * @bytes: the number of bytes during this measurement interval
1616 * Stores a new ITR value based on packets and byte
1617 * counts during the last interrupt. The advantage of per interrupt
1618 * computation is faster updates and more accurate ITR for the current
1619 * traffic pattern. Constants in this function were computed
1620 * based on theoretical maximum wire speed and thresholds were set based
1621 * on testing data as well as attempting to minimize response time
1622 * while increasing bulk throughput.
1623 * this functionality is controlled by the InterruptThrottleRate module
1624 * parameter (see ixgbe_param.c)
1626 static u8
ixgbe_update_itr(struct ixgbe_adapter
*adapter
,
1627 u32 eitr
, u8 itr_setting
,
1628 int packets
, int bytes
)
1630 unsigned int retval
= itr_setting
;
1635 goto update_itr_done
;
1638 /* simple throttlerate management
1639 * 0-20MB/s lowest (100000 ints/s)
1640 * 20-100MB/s low (20000 ints/s)
1641 * 100-1249MB/s bulk (8000 ints/s)
1643 /* what was last interrupt timeslice? */
1644 timepassed_us
= 1000000/eitr
;
1645 bytes_perint
= bytes
/ timepassed_us
; /* bytes/usec */
1647 switch (itr_setting
) {
1648 case lowest_latency
:
1649 if (bytes_perint
> adapter
->eitr_low
)
1650 retval
= low_latency
;
1653 if (bytes_perint
> adapter
->eitr_high
)
1654 retval
= bulk_latency
;
1655 else if (bytes_perint
<= adapter
->eitr_low
)
1656 retval
= lowest_latency
;
1659 if (bytes_perint
<= adapter
->eitr_high
)
1660 retval
= low_latency
;
1669 * ixgbe_write_eitr - write EITR register in hardware specific way
1670 * @q_vector: structure containing interrupt and ring information
1672 * This function is made to be called by ethtool and by the driver
1673 * when it needs to update EITR registers at runtime. Hardware
1674 * specific quirks/differences are taken care of here.
1676 void ixgbe_write_eitr(struct ixgbe_q_vector
*q_vector
)
1678 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1679 struct ixgbe_hw
*hw
= &adapter
->hw
;
1680 int v_idx
= q_vector
->v_idx
;
1681 u32 itr_reg
= EITR_INTS_PER_SEC_TO_REG(q_vector
->eitr
);
1683 switch (adapter
->hw
.mac
.type
) {
1684 case ixgbe_mac_82598EB
:
1685 /* must write high and low 16 bits to reset counter */
1686 itr_reg
|= (itr_reg
<< 16);
1688 case ixgbe_mac_82599EB
:
1689 case ixgbe_mac_X540
:
1691 * 82599 and X540 can support a value of zero, so allow it for
1692 * max interrupt rate, but there is an errata where it can
1693 * not be zero with RSC
1696 !(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
))
1700 * set the WDIS bit to not clear the timer bits and cause an
1701 * immediate assertion of the interrupt
1703 itr_reg
|= IXGBE_EITR_CNT_WDIS
;
1708 IXGBE_WRITE_REG(hw
, IXGBE_EITR(v_idx
), itr_reg
);
1711 static void ixgbe_set_itr_msix(struct ixgbe_q_vector
*q_vector
)
1713 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1716 u8 current_itr
, ret_itr
;
1718 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1719 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1720 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[r_idx
];
1721 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1723 tx_ring
->total_packets
,
1724 tx_ring
->total_bytes
);
1725 /* if the result for this queue would decrease interrupt
1726 * rate for this vector then use that result */
1727 q_vector
->tx_itr
= ((q_vector
->tx_itr
> ret_itr
) ?
1728 q_vector
->tx_itr
- 1 : ret_itr
);
1729 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1733 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1734 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1735 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[r_idx
];
1736 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1738 rx_ring
->total_packets
,
1739 rx_ring
->total_bytes
);
1740 /* if the result for this queue would decrease interrupt
1741 * rate for this vector then use that result */
1742 q_vector
->rx_itr
= ((q_vector
->rx_itr
> ret_itr
) ?
1743 q_vector
->rx_itr
- 1 : ret_itr
);
1744 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1748 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1750 switch (current_itr
) {
1751 /* counts and packets in update_itr are dependent on these numbers */
1752 case lowest_latency
:
1756 new_itr
= 20000; /* aka hwitr = ~200 */
1764 if (new_itr
!= q_vector
->eitr
) {
1765 /* do an exponential smoothing */
1766 new_itr
= ((q_vector
->eitr
* 9) + new_itr
)/10;
1768 /* save the algorithm value here, not the smoothed one */
1769 q_vector
->eitr
= new_itr
;
1771 ixgbe_write_eitr(q_vector
);
1776 * ixgbe_check_overtemp_subtask - check for over tempurature
1777 * @adapter: pointer to adapter
1779 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter
*adapter
)
1781 struct ixgbe_hw
*hw
= &adapter
->hw
;
1782 u32 eicr
= adapter
->interrupt_event
;
1784 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
1787 if (!(adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
1788 !(adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_EVENT
))
1791 adapter
->flags2
&= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT
;
1793 switch (hw
->device_id
) {
1794 case IXGBE_DEV_ID_82599_T3_LOM
:
1796 * Since the warning interrupt is for both ports
1797 * we don't have to check if:
1798 * - This interrupt wasn't for our port.
1799 * - We may have missed the interrupt so always have to
1800 * check if we got a LSC
1802 if (!(eicr
& IXGBE_EICR_GPI_SDP0
) &&
1803 !(eicr
& IXGBE_EICR_LSC
))
1806 if (!(eicr
& IXGBE_EICR_LSC
) && hw
->mac
.ops
.check_link
) {
1808 bool link_up
= false;
1810 hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
1816 /* Check if this is not due to overtemp */
1817 if (hw
->phy
.ops
.check_overtemp(hw
) != IXGBE_ERR_OVERTEMP
)
1822 if (!(eicr
& IXGBE_EICR_GPI_SDP0
))
1827 "Network adapter has been stopped because it has over heated. "
1828 "Restart the computer. If the problem persists, "
1829 "power off the system and replace the adapter\n");
1831 adapter
->interrupt_event
= 0;
1834 static void ixgbe_check_fan_failure(struct ixgbe_adapter
*adapter
, u32 eicr
)
1836 struct ixgbe_hw
*hw
= &adapter
->hw
;
1838 if ((adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
1839 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
1840 e_crit(probe
, "Fan has stopped, replace the adapter\n");
1841 /* write to clear the interrupt */
1842 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1846 static void ixgbe_check_sfp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1848 struct ixgbe_hw
*hw
= &adapter
->hw
;
1850 if (eicr
& IXGBE_EICR_GPI_SDP2
) {
1851 /* Clear the interrupt */
1852 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2
);
1853 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1854 adapter
->flags2
|= IXGBE_FLAG2_SFP_NEEDS_RESET
;
1855 ixgbe_service_event_schedule(adapter
);
1859 if (eicr
& IXGBE_EICR_GPI_SDP1
) {
1860 /* Clear the interrupt */
1861 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1862 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1863 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_CONFIG
;
1864 ixgbe_service_event_schedule(adapter
);
1869 static void ixgbe_check_lsc(struct ixgbe_adapter
*adapter
)
1871 struct ixgbe_hw
*hw
= &adapter
->hw
;
1874 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
1875 adapter
->link_check_timeout
= jiffies
;
1876 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1877 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_LSC
);
1878 IXGBE_WRITE_FLUSH(hw
);
1879 ixgbe_service_event_schedule(adapter
);
1883 static irqreturn_t
ixgbe_msix_lsc(int irq
, void *data
)
1885 struct net_device
*netdev
= data
;
1886 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1887 struct ixgbe_hw
*hw
= &adapter
->hw
;
1891 * Workaround for Silicon errata. Use clear-by-write instead
1892 * of clear-by-read. Reading with EICS will return the
1893 * interrupt causes without clearing, which later be done
1894 * with the write to EICR.
1896 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICS
);
1897 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
1899 if (eicr
& IXGBE_EICR_LSC
)
1900 ixgbe_check_lsc(adapter
);
1902 if (eicr
& IXGBE_EICR_MAILBOX
)
1903 ixgbe_msg_task(adapter
);
1905 switch (hw
->mac
.type
) {
1906 case ixgbe_mac_82599EB
:
1907 case ixgbe_mac_X540
:
1908 /* Handle Flow Director Full threshold interrupt */
1909 if (eicr
& IXGBE_EICR_FLOW_DIR
) {
1910 int reinit_count
= 0;
1912 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1913 struct ixgbe_ring
*ring
= adapter
->tx_ring
[i
];
1914 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE
,
1919 /* no more flow director interrupts until after init */
1920 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_FLOW_DIR
);
1921 eicr
&= ~IXGBE_EICR_FLOW_DIR
;
1922 adapter
->flags2
|= IXGBE_FLAG2_FDIR_REQUIRES_REINIT
;
1923 ixgbe_service_event_schedule(adapter
);
1926 ixgbe_check_sfp_event(adapter
, eicr
);
1927 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
1928 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
))) {
1929 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1930 adapter
->interrupt_event
= eicr
;
1931 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_EVENT
;
1932 ixgbe_service_event_schedule(adapter
);
1940 ixgbe_check_fan_failure(adapter
, eicr
);
1942 /* re-enable the original interrupt state, no lsc, no queues */
1943 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1944 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, eicr
&
1945 ~(IXGBE_EIMS_LSC
| IXGBE_EIMS_RTX_QUEUE
));
1950 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter
*adapter
,
1954 struct ixgbe_hw
*hw
= &adapter
->hw
;
1956 switch (hw
->mac
.type
) {
1957 case ixgbe_mac_82598EB
:
1958 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1959 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, mask
);
1961 case ixgbe_mac_82599EB
:
1962 case ixgbe_mac_X540
:
1963 mask
= (qmask
& 0xFFFFFFFF);
1965 IXGBE_WRITE_REG(hw
, IXGBE_EIMS_EX(0), mask
);
1966 mask
= (qmask
>> 32);
1968 IXGBE_WRITE_REG(hw
, IXGBE_EIMS_EX(1), mask
);
1973 /* skip the flush */
1976 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter
*adapter
,
1980 struct ixgbe_hw
*hw
= &adapter
->hw
;
1982 switch (hw
->mac
.type
) {
1983 case ixgbe_mac_82598EB
:
1984 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1985 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, mask
);
1987 case ixgbe_mac_82599EB
:
1988 case ixgbe_mac_X540
:
1989 mask
= (qmask
& 0xFFFFFFFF);
1991 IXGBE_WRITE_REG(hw
, IXGBE_EIMC_EX(0), mask
);
1992 mask
= (qmask
>> 32);
1994 IXGBE_WRITE_REG(hw
, IXGBE_EIMC_EX(1), mask
);
1999 /* skip the flush */
2002 static irqreturn_t
ixgbe_msix_clean_tx(int irq
, void *data
)
2004 struct ixgbe_q_vector
*q_vector
= data
;
2005 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2006 struct ixgbe_ring
*tx_ring
;
2009 if (!q_vector
->txr_count
)
2012 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
2013 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
2014 tx_ring
= adapter
->tx_ring
[r_idx
];
2015 tx_ring
->total_bytes
= 0;
2016 tx_ring
->total_packets
= 0;
2017 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
2021 /* EIAM disabled interrupts (on this vector) for us */
2022 napi_schedule(&q_vector
->napi
);
2028 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2030 * @data: pointer to our q_vector struct for this interrupt vector
2032 static irqreturn_t
ixgbe_msix_clean_rx(int irq
, void *data
)
2034 struct ixgbe_q_vector
*q_vector
= data
;
2035 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2036 struct ixgbe_ring
*rx_ring
;
2040 #ifdef CONFIG_IXGBE_DCA
2041 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2042 ixgbe_update_dca(q_vector
);
2045 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2046 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
2047 rx_ring
= adapter
->rx_ring
[r_idx
];
2048 rx_ring
->total_bytes
= 0;
2049 rx_ring
->total_packets
= 0;
2050 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
2054 if (!q_vector
->rxr_count
)
2057 /* EIAM disabled interrupts (on this vector) for us */
2058 napi_schedule(&q_vector
->napi
);
2063 static irqreturn_t
ixgbe_msix_clean_many(int irq
, void *data
)
2065 struct ixgbe_q_vector
*q_vector
= data
;
2066 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2067 struct ixgbe_ring
*ring
;
2071 if (!q_vector
->txr_count
&& !q_vector
->rxr_count
)
2074 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
2075 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
2076 ring
= adapter
->tx_ring
[r_idx
];
2077 ring
->total_bytes
= 0;
2078 ring
->total_packets
= 0;
2079 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
2083 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2084 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
2085 ring
= adapter
->rx_ring
[r_idx
];
2086 ring
->total_bytes
= 0;
2087 ring
->total_packets
= 0;
2088 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
2092 /* EIAM disabled interrupts (on this vector) for us */
2093 napi_schedule(&q_vector
->napi
);
2099 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2100 * @napi: napi struct with our devices info in it
2101 * @budget: amount of work driver is allowed to do this pass, in packets
2103 * This function is optimized for cleaning one queue only on a single
2106 static int ixgbe_clean_rxonly(struct napi_struct
*napi
, int budget
)
2108 struct ixgbe_q_vector
*q_vector
=
2109 container_of(napi
, struct ixgbe_q_vector
, napi
);
2110 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2111 struct ixgbe_ring
*rx_ring
= NULL
;
2115 #ifdef CONFIG_IXGBE_DCA
2116 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2117 ixgbe_update_dca(q_vector
);
2120 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2121 rx_ring
= adapter
->rx_ring
[r_idx
];
2123 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
2125 /* If all Rx work done, exit the polling mode */
2126 if (work_done
< budget
) {
2127 napi_complete(napi
);
2128 if (adapter
->rx_itr_setting
& 1)
2129 ixgbe_set_itr_msix(q_vector
);
2130 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2131 ixgbe_irq_enable_queues(adapter
,
2132 ((u64
)1 << q_vector
->v_idx
));
2139 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2140 * @napi: napi struct with our devices info in it
2141 * @budget: amount of work driver is allowed to do this pass, in packets
2143 * This function will clean more than one rx queue associated with a
2146 static int ixgbe_clean_rxtx_many(struct napi_struct
*napi
, int budget
)
2148 struct ixgbe_q_vector
*q_vector
=
2149 container_of(napi
, struct ixgbe_q_vector
, napi
);
2150 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2151 struct ixgbe_ring
*ring
= NULL
;
2152 int work_done
= 0, i
;
2154 bool tx_clean_complete
= true;
2156 #ifdef CONFIG_IXGBE_DCA
2157 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2158 ixgbe_update_dca(q_vector
);
2161 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
2162 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
2163 ring
= adapter
->tx_ring
[r_idx
];
2164 tx_clean_complete
&= ixgbe_clean_tx_irq(q_vector
, ring
);
2165 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
2169 /* attempt to distribute budget to each queue fairly, but don't allow
2170 * the budget to go below 1 because we'll exit polling */
2171 budget
/= (q_vector
->rxr_count
?: 1);
2172 budget
= max(budget
, 1);
2173 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2174 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
2175 ring
= adapter
->rx_ring
[r_idx
];
2176 ixgbe_clean_rx_irq(q_vector
, ring
, &work_done
, budget
);
2177 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
2181 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2182 ring
= adapter
->rx_ring
[r_idx
];
2183 /* If all Rx work done, exit the polling mode */
2184 if (work_done
< budget
) {
2185 napi_complete(napi
);
2186 if (adapter
->rx_itr_setting
& 1)
2187 ixgbe_set_itr_msix(q_vector
);
2188 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2189 ixgbe_irq_enable_queues(adapter
,
2190 ((u64
)1 << q_vector
->v_idx
));
2198 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2199 * @napi: napi struct with our devices info in it
2200 * @budget: amount of work driver is allowed to do this pass, in packets
2202 * This function is optimized for cleaning one queue only on a single
2205 static int ixgbe_clean_txonly(struct napi_struct
*napi
, int budget
)
2207 struct ixgbe_q_vector
*q_vector
=
2208 container_of(napi
, struct ixgbe_q_vector
, napi
);
2209 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2210 struct ixgbe_ring
*tx_ring
= NULL
;
2214 #ifdef CONFIG_IXGBE_DCA
2215 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2216 ixgbe_update_dca(q_vector
);
2219 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
2220 tx_ring
= adapter
->tx_ring
[r_idx
];
2222 if (!ixgbe_clean_tx_irq(q_vector
, tx_ring
))
2225 /* If all Tx work done, exit the polling mode */
2226 if (work_done
< budget
) {
2227 napi_complete(napi
);
2228 if (adapter
->tx_itr_setting
& 1)
2229 ixgbe_set_itr_msix(q_vector
);
2230 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2231 ixgbe_irq_enable_queues(adapter
,
2232 ((u64
)1 << q_vector
->v_idx
));
2238 static inline void map_vector_to_rxq(struct ixgbe_adapter
*a
, int v_idx
,
2241 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2242 struct ixgbe_ring
*rx_ring
= a
->rx_ring
[r_idx
];
2244 set_bit(r_idx
, q_vector
->rxr_idx
);
2245 q_vector
->rxr_count
++;
2246 rx_ring
->q_vector
= q_vector
;
2249 static inline void map_vector_to_txq(struct ixgbe_adapter
*a
, int v_idx
,
2252 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2253 struct ixgbe_ring
*tx_ring
= a
->tx_ring
[t_idx
];
2255 set_bit(t_idx
, q_vector
->txr_idx
);
2256 q_vector
->txr_count
++;
2257 tx_ring
->q_vector
= q_vector
;
2261 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2262 * @adapter: board private structure to initialize
2264 * This function maps descriptor rings to the queue-specific vectors
2265 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2266 * one vector per ring/queue, but on a constrained vector budget, we
2267 * group the rings as "efficiently" as possible. You would add new
2268 * mapping configurations in here.
2270 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter
*adapter
)
2274 int rxr_idx
= 0, txr_idx
= 0;
2275 int rxr_remaining
= adapter
->num_rx_queues
;
2276 int txr_remaining
= adapter
->num_tx_queues
;
2281 /* No mapping required if MSI-X is disabled. */
2282 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2285 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2288 * The ideal configuration...
2289 * We have enough vectors to map one per queue.
2291 if (q_vectors
== adapter
->num_rx_queues
+ adapter
->num_tx_queues
) {
2292 for (; rxr_idx
< rxr_remaining
; v_start
++, rxr_idx
++)
2293 map_vector_to_rxq(adapter
, v_start
, rxr_idx
);
2295 for (; txr_idx
< txr_remaining
; v_start
++, txr_idx
++)
2296 map_vector_to_txq(adapter
, v_start
, txr_idx
);
2302 * If we don't have enough vectors for a 1-to-1
2303 * mapping, we'll have to group them so there are
2304 * multiple queues per vector.
2306 /* Re-adjusting *qpv takes care of the remainder. */
2307 for (i
= v_start
; i
< q_vectors
; i
++) {
2308 rqpv
= DIV_ROUND_UP(rxr_remaining
, q_vectors
- i
);
2309 for (j
= 0; j
< rqpv
; j
++) {
2310 map_vector_to_rxq(adapter
, i
, rxr_idx
);
2314 tqpv
= DIV_ROUND_UP(txr_remaining
, q_vectors
- i
);
2315 for (j
= 0; j
< tqpv
; j
++) {
2316 map_vector_to_txq(adapter
, i
, txr_idx
);
2326 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2327 * @adapter: board private structure
2329 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2330 * interrupts from the kernel.
2332 static int ixgbe_request_msix_irqs(struct ixgbe_adapter
*adapter
)
2334 struct net_device
*netdev
= adapter
->netdev
;
2335 irqreturn_t (*handler
)(int, void *);
2336 int i
, vector
, q_vectors
, err
;
2339 /* Decrement for Other and TCP Timer vectors */
2340 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2342 err
= ixgbe_map_rings_to_vectors(adapter
);
2346 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2347 ? &ixgbe_msix_clean_many : \
2348 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2349 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2351 for (vector
= 0; vector
< q_vectors
; vector
++) {
2352 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[vector
];
2353 handler
= SET_HANDLER(q_vector
);
2355 if (handler
== &ixgbe_msix_clean_rx
) {
2356 snprintf(q_vector
->name
, sizeof(q_vector
->name
) - 1,
2357 "%s-%s-%d", netdev
->name
, "rx", ri
++);
2358 } else if (handler
== &ixgbe_msix_clean_tx
) {
2359 snprintf(q_vector
->name
, sizeof(q_vector
->name
) - 1,
2360 "%s-%s-%d", netdev
->name
, "tx", ti
++);
2361 } else if (handler
== &ixgbe_msix_clean_many
) {
2362 snprintf(q_vector
->name
, sizeof(q_vector
->name
) - 1,
2363 "%s-%s-%d", netdev
->name
, "TxRx", ri
++);
2366 /* skip this unused q_vector */
2369 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2370 handler
, 0, q_vector
->name
,
2373 e_err(probe
, "request_irq failed for MSIX interrupt "
2374 "Error: %d\n", err
);
2375 goto free_queue_irqs
;
2379 sprintf(adapter
->lsc_int_name
, "%s:lsc", netdev
->name
);
2380 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2381 ixgbe_msix_lsc
, 0, adapter
->lsc_int_name
, netdev
);
2383 e_err(probe
, "request_irq for msix_lsc failed: %d\n", err
);
2384 goto free_queue_irqs
;
2390 for (i
= vector
- 1; i
>= 0; i
--)
2391 free_irq(adapter
->msix_entries
[--vector
].vector
,
2392 adapter
->q_vector
[i
]);
2393 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
2394 pci_disable_msix(adapter
->pdev
);
2395 kfree(adapter
->msix_entries
);
2396 adapter
->msix_entries
= NULL
;
2400 static void ixgbe_set_itr(struct ixgbe_adapter
*adapter
)
2402 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2403 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[0];
2404 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[0];
2405 u32 new_itr
= q_vector
->eitr
;
2408 q_vector
->tx_itr
= ixgbe_update_itr(adapter
, new_itr
,
2410 tx_ring
->total_packets
,
2411 tx_ring
->total_bytes
);
2412 q_vector
->rx_itr
= ixgbe_update_itr(adapter
, new_itr
,
2414 rx_ring
->total_packets
,
2415 rx_ring
->total_bytes
);
2417 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
2419 switch (current_itr
) {
2420 /* counts and packets in update_itr are dependent on these numbers */
2421 case lowest_latency
:
2425 new_itr
= 20000; /* aka hwitr = ~200 */
2434 if (new_itr
!= q_vector
->eitr
) {
2435 /* do an exponential smoothing */
2436 new_itr
= ((q_vector
->eitr
* 9) + new_itr
)/10;
2438 /* save the algorithm value here */
2439 q_vector
->eitr
= new_itr
;
2441 ixgbe_write_eitr(q_vector
);
2446 * ixgbe_irq_enable - Enable default interrupt generation settings
2447 * @adapter: board private structure
2449 static inline void ixgbe_irq_enable(struct ixgbe_adapter
*adapter
, bool queues
,
2454 mask
= (IXGBE_EIMS_ENABLE_MASK
& ~IXGBE_EIMS_RTX_QUEUE
);
2455 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
2456 mask
|= IXGBE_EIMS_GPI_SDP0
;
2457 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
2458 mask
|= IXGBE_EIMS_GPI_SDP1
;
2459 switch (adapter
->hw
.mac
.type
) {
2460 case ixgbe_mac_82599EB
:
2461 case ixgbe_mac_X540
:
2462 mask
|= IXGBE_EIMS_ECC
;
2463 mask
|= IXGBE_EIMS_GPI_SDP1
;
2464 mask
|= IXGBE_EIMS_GPI_SDP2
;
2465 if (adapter
->num_vfs
)
2466 mask
|= IXGBE_EIMS_MAILBOX
;
2471 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
2472 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
2473 mask
|= IXGBE_EIMS_FLOW_DIR
;
2475 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
2477 ixgbe_irq_enable_queues(adapter
, ~0);
2479 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2481 if (adapter
->num_vfs
> 32) {
2482 u32 eitrsel
= (1 << (adapter
->num_vfs
- 32)) - 1;
2483 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, eitrsel
);
2488 * ixgbe_intr - legacy mode Interrupt Handler
2489 * @irq: interrupt number
2490 * @data: pointer to a network interface device structure
2492 static irqreturn_t
ixgbe_intr(int irq
, void *data
)
2494 struct net_device
*netdev
= data
;
2495 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2496 struct ixgbe_hw
*hw
= &adapter
->hw
;
2497 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2501 * Workaround for silicon errata on 82598. Mask the interrupts
2502 * before the read of EICR.
2504 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
2506 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2507 * therefore no explict interrupt disable is necessary */
2508 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
2511 * shared interrupt alert!
2512 * make sure interrupts are enabled because the read will
2513 * have disabled interrupts due to EIAM
2514 * finish the workaround of silicon errata on 82598. Unmask
2515 * the interrupt that we masked before the EICR read.
2517 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2518 ixgbe_irq_enable(adapter
, true, true);
2519 return IRQ_NONE
; /* Not our interrupt */
2522 if (eicr
& IXGBE_EICR_LSC
)
2523 ixgbe_check_lsc(adapter
);
2525 switch (hw
->mac
.type
) {
2526 case ixgbe_mac_82599EB
:
2527 ixgbe_check_sfp_event(adapter
, eicr
);
2528 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
2529 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
))) {
2530 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
2531 adapter
->interrupt_event
= eicr
;
2532 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_EVENT
;
2533 ixgbe_service_event_schedule(adapter
);
2541 ixgbe_check_fan_failure(adapter
, eicr
);
2543 if (napi_schedule_prep(&(q_vector
->napi
))) {
2544 adapter
->tx_ring
[0]->total_packets
= 0;
2545 adapter
->tx_ring
[0]->total_bytes
= 0;
2546 adapter
->rx_ring
[0]->total_packets
= 0;
2547 adapter
->rx_ring
[0]->total_bytes
= 0;
2548 /* would disable interrupts here but EIAM disabled it */
2549 __napi_schedule(&(q_vector
->napi
));
2553 * re-enable link(maybe) and non-queue interrupts, no flush.
2554 * ixgbe_poll will re-enable the queue interrupts
2557 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2558 ixgbe_irq_enable(adapter
, false, false);
2563 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter
*adapter
)
2565 int i
, q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2567 for (i
= 0; i
< q_vectors
; i
++) {
2568 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
2569 bitmap_zero(q_vector
->rxr_idx
, MAX_RX_QUEUES
);
2570 bitmap_zero(q_vector
->txr_idx
, MAX_TX_QUEUES
);
2571 q_vector
->rxr_count
= 0;
2572 q_vector
->txr_count
= 0;
2577 * ixgbe_request_irq - initialize interrupts
2578 * @adapter: board private structure
2580 * Attempts to configure interrupts using the best available
2581 * capabilities of the hardware and kernel.
2583 static int ixgbe_request_irq(struct ixgbe_adapter
*adapter
)
2585 struct net_device
*netdev
= adapter
->netdev
;
2588 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2589 err
= ixgbe_request_msix_irqs(adapter
);
2590 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
2591 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, 0,
2592 netdev
->name
, netdev
);
2594 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, IRQF_SHARED
,
2595 netdev
->name
, netdev
);
2599 e_err(probe
, "request_irq failed, Error %d\n", err
);
2604 static void ixgbe_free_irq(struct ixgbe_adapter
*adapter
)
2606 struct net_device
*netdev
= adapter
->netdev
;
2608 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2611 q_vectors
= adapter
->num_msix_vectors
;
2614 free_irq(adapter
->msix_entries
[i
].vector
, netdev
);
2617 for (; i
>= 0; i
--) {
2618 /* free only the irqs that were actually requested */
2619 if (!adapter
->q_vector
[i
]->rxr_count
&&
2620 !adapter
->q_vector
[i
]->txr_count
)
2623 free_irq(adapter
->msix_entries
[i
].vector
,
2624 adapter
->q_vector
[i
]);
2627 ixgbe_reset_q_vectors(adapter
);
2629 free_irq(adapter
->pdev
->irq
, netdev
);
2634 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2635 * @adapter: board private structure
2637 static inline void ixgbe_irq_disable(struct ixgbe_adapter
*adapter
)
2639 switch (adapter
->hw
.mac
.type
) {
2640 case ixgbe_mac_82598EB
:
2641 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, ~0);
2643 case ixgbe_mac_82599EB
:
2644 case ixgbe_mac_X540
:
2645 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, 0xFFFF0000);
2646 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), ~0);
2647 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), ~0);
2648 if (adapter
->num_vfs
> 32)
2649 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, 0);
2654 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2655 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2657 for (i
= 0; i
< adapter
->num_msix_vectors
; i
++)
2658 synchronize_irq(adapter
->msix_entries
[i
].vector
);
2660 synchronize_irq(adapter
->pdev
->irq
);
2665 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2668 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter
*adapter
)
2670 struct ixgbe_hw
*hw
= &adapter
->hw
;
2672 IXGBE_WRITE_REG(hw
, IXGBE_EITR(0),
2673 EITR_INTS_PER_SEC_TO_REG(adapter
->rx_eitr_param
));
2675 ixgbe_set_ivar(adapter
, 0, 0, 0);
2676 ixgbe_set_ivar(adapter
, 1, 0, 0);
2678 map_vector_to_rxq(adapter
, 0, 0);
2679 map_vector_to_txq(adapter
, 0, 0);
2681 e_info(hw
, "Legacy interrupt IVAR setup done\n");
2685 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2686 * @adapter: board private structure
2687 * @ring: structure containing ring specific data
2689 * Configure the Tx descriptor ring after a reset.
2691 void ixgbe_configure_tx_ring(struct ixgbe_adapter
*adapter
,
2692 struct ixgbe_ring
*ring
)
2694 struct ixgbe_hw
*hw
= &adapter
->hw
;
2695 u64 tdba
= ring
->dma
;
2698 u8 reg_idx
= ring
->reg_idx
;
2700 /* disable queue to avoid issues while updating state */
2701 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
2702 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
),
2703 txdctl
& ~IXGBE_TXDCTL_ENABLE
);
2704 IXGBE_WRITE_FLUSH(hw
);
2706 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(reg_idx
),
2707 (tdba
& DMA_BIT_MASK(32)));
2708 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(reg_idx
), (tdba
>> 32));
2709 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(reg_idx
),
2710 ring
->count
* sizeof(union ixgbe_adv_tx_desc
));
2711 IXGBE_WRITE_REG(hw
, IXGBE_TDH(reg_idx
), 0);
2712 IXGBE_WRITE_REG(hw
, IXGBE_TDT(reg_idx
), 0);
2713 ring
->tail
= hw
->hw_addr
+ IXGBE_TDT(reg_idx
);
2715 /* configure fetching thresholds */
2716 if (adapter
->rx_itr_setting
== 0) {
2717 /* cannot set wthresh when itr==0 */
2718 txdctl
&= ~0x007F0000;
2720 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2721 txdctl
|= (8 << 16);
2723 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
2724 /* PThresh workaround for Tx hang with DFP enabled. */
2728 /* reinitialize flowdirector state */
2729 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) &&
2730 adapter
->atr_sample_rate
) {
2731 ring
->atr_sample_rate
= adapter
->atr_sample_rate
;
2732 ring
->atr_count
= 0;
2733 set_bit(__IXGBE_TX_FDIR_INIT_DONE
, &ring
->state
);
2735 ring
->atr_sample_rate
= 0;
2738 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &ring
->state
);
2741 txdctl
|= IXGBE_TXDCTL_ENABLE
;
2742 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
), txdctl
);
2744 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2745 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
2746 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
2749 /* poll to verify queue is enabled */
2751 usleep_range(1000, 2000);
2752 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
2753 } while (--wait_loop
&& !(txdctl
& IXGBE_TXDCTL_ENABLE
));
2755 e_err(drv
, "Could not enable Tx Queue %d\n", reg_idx
);
2758 static void ixgbe_setup_mtqc(struct ixgbe_adapter
*adapter
)
2760 struct ixgbe_hw
*hw
= &adapter
->hw
;
2763 u8 tcs
= netdev_get_num_tc(adapter
->netdev
);
2765 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2768 /* disable the arbiter while setting MTQC */
2769 rttdcs
= IXGBE_READ_REG(hw
, IXGBE_RTTDCS
);
2770 rttdcs
|= IXGBE_RTTDCS_ARBDIS
;
2771 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2773 /* set transmit pool layout */
2774 switch (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
2775 case (IXGBE_FLAG_SRIOV_ENABLED
):
2776 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2777 (IXGBE_MTQC_VT_ENA
| IXGBE_MTQC_64VF
));
2781 reg
= IXGBE_MTQC_64Q_1PB
;
2783 reg
= IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_4TC_4TQ
;
2785 reg
= IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_8TC_8TQ
;
2787 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, reg
);
2789 /* Enable Security TX Buffer IFG for multiple pb */
2791 reg
= IXGBE_READ_REG(hw
, IXGBE_SECTXMINIFG
);
2792 reg
|= IXGBE_SECTX_DCB
;
2793 IXGBE_WRITE_REG(hw
, IXGBE_SECTXMINIFG
, reg
);
2798 /* re-enable the arbiter */
2799 rttdcs
&= ~IXGBE_RTTDCS_ARBDIS
;
2800 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2804 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2805 * @adapter: board private structure
2807 * Configure the Tx unit of the MAC after a reset.
2809 static void ixgbe_configure_tx(struct ixgbe_adapter
*adapter
)
2811 struct ixgbe_hw
*hw
= &adapter
->hw
;
2815 ixgbe_setup_mtqc(adapter
);
2817 if (hw
->mac
.type
!= ixgbe_mac_82598EB
) {
2818 /* DMATXCTL.EN must be before Tx queues are enabled */
2819 dmatxctl
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
2820 dmatxctl
|= IXGBE_DMATXCTL_TE
;
2821 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, dmatxctl
);
2824 /* Setup the HW Tx Head and Tail descriptor pointers */
2825 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2826 ixgbe_configure_tx_ring(adapter
, adapter
->tx_ring
[i
]);
2829 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2831 static void ixgbe_configure_srrctl(struct ixgbe_adapter
*adapter
,
2832 struct ixgbe_ring
*rx_ring
)
2835 u8 reg_idx
= rx_ring
->reg_idx
;
2837 switch (adapter
->hw
.mac
.type
) {
2838 case ixgbe_mac_82598EB
: {
2839 struct ixgbe_ring_feature
*feature
= adapter
->ring_feature
;
2840 const int mask
= feature
[RING_F_RSS
].mask
;
2841 reg_idx
= reg_idx
& mask
;
2844 case ixgbe_mac_82599EB
:
2845 case ixgbe_mac_X540
:
2850 srrctl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SRRCTL(reg_idx
));
2852 srrctl
&= ~IXGBE_SRRCTL_BSIZEHDR_MASK
;
2853 srrctl
&= ~IXGBE_SRRCTL_BSIZEPKT_MASK
;
2854 if (adapter
->num_vfs
)
2855 srrctl
|= IXGBE_SRRCTL_DROP_EN
;
2857 srrctl
|= (IXGBE_RX_HDR_SIZE
<< IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
) &
2858 IXGBE_SRRCTL_BSIZEHDR_MASK
;
2860 if (ring_is_ps_enabled(rx_ring
)) {
2861 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2862 srrctl
|= IXGBE_MAX_RXBUFFER
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2864 srrctl
|= (PAGE_SIZE
/ 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2866 srrctl
|= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
2868 srrctl
|= ALIGN(rx_ring
->rx_buf_len
, 1024) >>
2869 IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2870 srrctl
|= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2873 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_SRRCTL(reg_idx
), srrctl
);
2876 static void ixgbe_setup_mrqc(struct ixgbe_adapter
*adapter
)
2878 struct ixgbe_hw
*hw
= &adapter
->hw
;
2879 static const u32 seed
[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2880 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2881 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2882 u32 mrqc
= 0, reta
= 0;
2885 u8 tcs
= netdev_get_num_tc(adapter
->netdev
);
2886 int maxq
= adapter
->ring_feature
[RING_F_RSS
].indices
;
2889 maxq
= min(maxq
, adapter
->num_tx_queues
/ tcs
);
2891 /* Fill out hash function seeds */
2892 for (i
= 0; i
< 10; i
++)
2893 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), seed
[i
]);
2895 /* Fill out redirection table */
2896 for (i
= 0, j
= 0; i
< 128; i
++, j
++) {
2899 /* reta = 4-byte sliding window of
2900 * 0x00..(indices-1)(indices-1)00..etc. */
2901 reta
= (reta
<< 8) | (j
* 0x11);
2903 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
2906 /* Disable indicating checksum in descriptor, enables RSS hash */
2907 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
2908 rxcsum
|= IXGBE_RXCSUM_PCSD
;
2909 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
2911 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
&&
2912 (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
)) {
2913 mrqc
= IXGBE_MRQC_RSSEN
;
2915 int mask
= adapter
->flags
& (IXGBE_FLAG_RSS_ENABLED
2916 | IXGBE_FLAG_SRIOV_ENABLED
);
2919 case (IXGBE_FLAG_RSS_ENABLED
):
2921 mrqc
= IXGBE_MRQC_RSSEN
;
2923 mrqc
= IXGBE_MRQC_RTRSS4TCEN
;
2925 mrqc
= IXGBE_MRQC_RTRSS8TCEN
;
2927 case (IXGBE_FLAG_SRIOV_ENABLED
):
2928 mrqc
= IXGBE_MRQC_VMDQEN
;
2935 /* Perform hash on these packet types */
2936 mrqc
|= IXGBE_MRQC_RSS_FIELD_IPV4
2937 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2938 | IXGBE_MRQC_RSS_FIELD_IPV6
2939 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
;
2941 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2945 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2946 * @adapter: address of board private structure
2947 * @ring: structure containing ring specific data
2949 void ixgbe_clear_rscctl(struct ixgbe_adapter
*adapter
,
2950 struct ixgbe_ring
*ring
)
2952 struct ixgbe_hw
*hw
= &adapter
->hw
;
2954 u8 reg_idx
= ring
->reg_idx
;
2956 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(reg_idx
));
2957 rscctrl
&= ~IXGBE_RSCCTL_RSCEN
;
2958 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(reg_idx
), rscctrl
);
2962 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2963 * @adapter: address of board private structure
2964 * @index: index of ring to set
2966 void ixgbe_configure_rscctl(struct ixgbe_adapter
*adapter
,
2967 struct ixgbe_ring
*ring
)
2969 struct ixgbe_hw
*hw
= &adapter
->hw
;
2972 u8 reg_idx
= ring
->reg_idx
;
2974 if (!ring_is_rsc_enabled(ring
))
2977 rx_buf_len
= ring
->rx_buf_len
;
2978 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(reg_idx
));
2979 rscctrl
|= IXGBE_RSCCTL_RSCEN
;
2981 * we must limit the number of descriptors so that the
2982 * total size of max desc * buf_len is not greater
2985 if (ring_is_ps_enabled(ring
)) {
2986 #if (MAX_SKB_FRAGS > 16)
2987 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2988 #elif (MAX_SKB_FRAGS > 8)
2989 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2990 #elif (MAX_SKB_FRAGS > 4)
2991 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2993 rscctrl
|= IXGBE_RSCCTL_MAXDESC_1
;
2996 if (rx_buf_len
< IXGBE_RXBUFFER_4096
)
2997 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2998 else if (rx_buf_len
< IXGBE_RXBUFFER_8192
)
2999 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
3001 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
3003 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(reg_idx
), rscctrl
);
3007 * ixgbe_set_uta - Set unicast filter table address
3008 * @adapter: board private structure
3010 * The unicast table address is a register array of 32-bit registers.
3011 * The table is meant to be used in a way similar to how the MTA is used
3012 * however due to certain limitations in the hardware it is necessary to
3013 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
3014 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
3016 static void ixgbe_set_uta(struct ixgbe_adapter
*adapter
)
3018 struct ixgbe_hw
*hw
= &adapter
->hw
;
3021 /* The UTA table only exists on 82599 hardware and newer */
3022 if (hw
->mac
.type
< ixgbe_mac_82599EB
)
3025 /* we only need to do this if VMDq is enabled */
3026 if (!(adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
))
3029 for (i
= 0; i
< 128; i
++)
3030 IXGBE_WRITE_REG(hw
, IXGBE_UTA(i
), ~0);
3033 #define IXGBE_MAX_RX_DESC_POLL 10
3034 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter
*adapter
,
3035 struct ixgbe_ring
*ring
)
3037 struct ixgbe_hw
*hw
= &adapter
->hw
;
3038 int wait_loop
= IXGBE_MAX_RX_DESC_POLL
;
3040 u8 reg_idx
= ring
->reg_idx
;
3042 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3043 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
3044 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
3048 usleep_range(1000, 2000);
3049 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
3050 } while (--wait_loop
&& !(rxdctl
& IXGBE_RXDCTL_ENABLE
));
3053 e_err(drv
, "RXDCTL.ENABLE on Rx queue %d not set within "
3054 "the polling period\n", reg_idx
);
3058 void ixgbe_disable_rx_queue(struct ixgbe_adapter
*adapter
,
3059 struct ixgbe_ring
*ring
)
3061 struct ixgbe_hw
*hw
= &adapter
->hw
;
3062 int wait_loop
= IXGBE_MAX_RX_DESC_POLL
;
3064 u8 reg_idx
= ring
->reg_idx
;
3066 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
3067 rxdctl
&= ~IXGBE_RXDCTL_ENABLE
;
3069 /* write value back with RXDCTL.ENABLE bit cleared */
3070 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(reg_idx
), rxdctl
);
3072 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
3073 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
3076 /* the hardware may take up to 100us to really disable the rx queue */
3079 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
3080 } while (--wait_loop
&& (rxdctl
& IXGBE_RXDCTL_ENABLE
));
3083 e_err(drv
, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3084 "the polling period\n", reg_idx
);
3088 void ixgbe_configure_rx_ring(struct ixgbe_adapter
*adapter
,
3089 struct ixgbe_ring
*ring
)
3091 struct ixgbe_hw
*hw
= &adapter
->hw
;
3092 u64 rdba
= ring
->dma
;
3094 u8 reg_idx
= ring
->reg_idx
;
3096 /* disable queue to avoid issues while updating state */
3097 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
3098 ixgbe_disable_rx_queue(adapter
, ring
);
3100 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(reg_idx
), (rdba
& DMA_BIT_MASK(32)));
3101 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(reg_idx
), (rdba
>> 32));
3102 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(reg_idx
),
3103 ring
->count
* sizeof(union ixgbe_adv_rx_desc
));
3104 IXGBE_WRITE_REG(hw
, IXGBE_RDH(reg_idx
), 0);
3105 IXGBE_WRITE_REG(hw
, IXGBE_RDT(reg_idx
), 0);
3106 ring
->tail
= hw
->hw_addr
+ IXGBE_RDT(reg_idx
);
3108 ixgbe_configure_srrctl(adapter
, ring
);
3109 ixgbe_configure_rscctl(adapter
, ring
);
3111 /* If operating in IOV mode set RLPML for X540 */
3112 if ((adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) &&
3113 hw
->mac
.type
== ixgbe_mac_X540
) {
3114 rxdctl
&= ~IXGBE_RXDCTL_RLPMLMASK
;
3115 rxdctl
|= ((ring
->netdev
->mtu
+ ETH_HLEN
+
3116 ETH_FCS_LEN
+ VLAN_HLEN
) | IXGBE_RXDCTL_RLPML_EN
);
3119 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
3121 * enable cache line friendly hardware writes:
3122 * PTHRESH=32 descriptors (half the internal cache),
3123 * this also removes ugly rx_no_buffer_count increment
3124 * HTHRESH=4 descriptors (to minimize latency on fetch)
3125 * WTHRESH=8 burst writeback up to two cache lines
3127 rxdctl
&= ~0x3FFFFF;
3131 /* enable receive descriptor ring */
3132 rxdctl
|= IXGBE_RXDCTL_ENABLE
;
3133 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(reg_idx
), rxdctl
);
3135 ixgbe_rx_desc_queue_enable(adapter
, ring
);
3136 ixgbe_alloc_rx_buffers(ring
, IXGBE_DESC_UNUSED(ring
));
3139 static void ixgbe_setup_psrtype(struct ixgbe_adapter
*adapter
)
3141 struct ixgbe_hw
*hw
= &adapter
->hw
;
3144 /* PSRTYPE must be initialized in non 82598 adapters */
3145 u32 psrtype
= IXGBE_PSRTYPE_TCPHDR
|
3146 IXGBE_PSRTYPE_UDPHDR
|
3147 IXGBE_PSRTYPE_IPV4HDR
|
3148 IXGBE_PSRTYPE_L2HDR
|
3149 IXGBE_PSRTYPE_IPV6HDR
;
3151 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3154 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
)
3155 psrtype
|= (adapter
->num_rx_queues_per_pool
<< 29);
3157 for (p
= 0; p
< adapter
->num_rx_pools
; p
++)
3158 IXGBE_WRITE_REG(hw
, IXGBE_PSRTYPE(adapter
->num_vfs
+ p
),
3162 static void ixgbe_configure_virtualization(struct ixgbe_adapter
*adapter
)
3164 struct ixgbe_hw
*hw
= &adapter
->hw
;
3167 u32 reg_offset
, vf_shift
;
3170 if (!(adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
))
3173 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
3174 vt_reg_bits
= IXGBE_VMD_CTL_VMDQ_EN
| IXGBE_VT_CTL_REPLEN
;
3175 vt_reg_bits
|= (adapter
->num_vfs
<< IXGBE_VT_CTL_POOL_SHIFT
);
3176 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
| vt_reg_bits
);
3178 vf_shift
= adapter
->num_vfs
% 32;
3179 reg_offset
= (adapter
->num_vfs
> 32) ? 1 : 0;
3181 /* Enable only the PF's pool for Tx/Rx */
3182 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
), (1 << vf_shift
));
3183 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
^ 1), 0);
3184 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
), (1 << vf_shift
));
3185 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
^ 1), 0);
3186 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
3188 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3189 hw
->mac
.ops
.set_vmdq(hw
, 0, adapter
->num_vfs
);
3192 * Set up VF register offsets for selected VT Mode,
3193 * i.e. 32 or 64 VFs for SR-IOV
3195 gcr_ext
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
3196 gcr_ext
|= IXGBE_GCR_EXT_MSIX_EN
;
3197 gcr_ext
|= IXGBE_GCR_EXT_VT_MODE_64
;
3198 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr_ext
);
3200 /* enable Tx loopback for VF/PF communication */
3201 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
3202 /* Enable MAC Anti-Spoofing */
3203 hw
->mac
.ops
.set_mac_anti_spoofing(hw
,
3204 (adapter
->antispoofing_enabled
=
3205 (adapter
->num_vfs
!= 0)),
3209 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter
*adapter
)
3211 struct ixgbe_hw
*hw
= &adapter
->hw
;
3212 struct net_device
*netdev
= adapter
->netdev
;
3213 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3215 struct ixgbe_ring
*rx_ring
;
3219 /* Decide whether to use packet split mode or not */
3221 adapter
->flags
|= IXGBE_FLAG_RX_PS_ENABLED
;
3223 /* Do not use packet split if we're in SR-IOV Mode */
3224 if (adapter
->num_vfs
)
3225 adapter
->flags
&= ~IXGBE_FLAG_RX_PS_ENABLED
;
3227 /* Disable packet split due to 82599 erratum #45 */
3228 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3229 adapter
->flags
&= ~IXGBE_FLAG_RX_PS_ENABLED
;
3231 /* Set the RX buffer length according to the mode */
3232 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
3233 rx_buf_len
= IXGBE_RX_HDR_SIZE
;
3235 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
3236 (netdev
->mtu
<= ETH_DATA_LEN
))
3237 rx_buf_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
3239 rx_buf_len
= ALIGN(max_frame
+ VLAN_HLEN
, 1024);
3243 /* adjust max frame to be able to do baby jumbo for FCoE */
3244 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
3245 (max_frame
< IXGBE_FCOE_JUMBO_FRAME_SIZE
))
3246 max_frame
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3248 #endif /* IXGBE_FCOE */
3249 mhadd
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
3250 if (max_frame
!= (mhadd
>> IXGBE_MHADD_MFS_SHIFT
)) {
3251 mhadd
&= ~IXGBE_MHADD_MFS_MASK
;
3252 mhadd
|= max_frame
<< IXGBE_MHADD_MFS_SHIFT
;
3254 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, mhadd
);
3257 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
3258 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3259 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
3260 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
3263 * Setup the HW Rx Head and Tail Descriptor Pointers and
3264 * the Base and Length of the Rx Descriptor Ring
3266 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3267 rx_ring
= adapter
->rx_ring
[i
];
3268 rx_ring
->rx_buf_len
= rx_buf_len
;
3270 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)
3271 set_ring_ps_enabled(rx_ring
);
3273 clear_ring_ps_enabled(rx_ring
);
3275 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
3276 set_ring_rsc_enabled(rx_ring
);
3278 clear_ring_rsc_enabled(rx_ring
);
3281 if (netdev
->features
& NETIF_F_FCOE_MTU
) {
3282 struct ixgbe_ring_feature
*f
;
3283 f
= &adapter
->ring_feature
[RING_F_FCOE
];
3284 if ((i
>= f
->mask
) && (i
< f
->mask
+ f
->indices
)) {
3285 clear_ring_ps_enabled(rx_ring
);
3286 if (rx_buf_len
< IXGBE_FCOE_JUMBO_FRAME_SIZE
)
3287 rx_ring
->rx_buf_len
=
3288 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3289 } else if (!ring_is_rsc_enabled(rx_ring
) &&
3290 !ring_is_ps_enabled(rx_ring
)) {
3291 rx_ring
->rx_buf_len
=
3292 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3295 #endif /* IXGBE_FCOE */
3299 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter
*adapter
)
3301 struct ixgbe_hw
*hw
= &adapter
->hw
;
3302 u32 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
3304 switch (hw
->mac
.type
) {
3305 case ixgbe_mac_82598EB
:
3307 * For VMDq support of different descriptor types or
3308 * buffer sizes through the use of multiple SRRCTL
3309 * registers, RDRXCTL.MVMEN must be set to 1
3311 * also, the manual doesn't mention it clearly but DCA hints
3312 * will only use queue 0's tags unless this bit is set. Side
3313 * effects of setting this bit are only that SRRCTL must be
3314 * fully programmed [0..15]
3316 rdrxctl
|= IXGBE_RDRXCTL_MVMEN
;
3318 case ixgbe_mac_82599EB
:
3319 case ixgbe_mac_X540
:
3320 /* Disable RSC for ACK packets */
3321 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
,
3322 (IXGBE_RSCDBU_RSCACKDIS
| IXGBE_READ_REG(hw
, IXGBE_RSCDBU
)));
3323 rdrxctl
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
3324 /* hardware requires some bits to be set by default */
3325 rdrxctl
|= (IXGBE_RDRXCTL_RSCACKC
| IXGBE_RDRXCTL_FCOE_WRFIX
);
3326 rdrxctl
|= IXGBE_RDRXCTL_CRCSTRIP
;
3329 /* We should do nothing since we don't know this hardware */
3333 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
3337 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3338 * @adapter: board private structure
3340 * Configure the Rx unit of the MAC after a reset.
3342 static void ixgbe_configure_rx(struct ixgbe_adapter
*adapter
)
3344 struct ixgbe_hw
*hw
= &adapter
->hw
;
3348 /* disable receives while setting up the descriptors */
3349 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3350 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3352 ixgbe_setup_psrtype(adapter
);
3353 ixgbe_setup_rdrxctl(adapter
);
3355 /* Program registers for the distribution of queues */
3356 ixgbe_setup_mrqc(adapter
);
3358 ixgbe_set_uta(adapter
);
3360 /* set_rx_buffer_len must be called before ring initialization */
3361 ixgbe_set_rx_buffer_len(adapter
);
3364 * Setup the HW Rx Head and Tail Descriptor Pointers and
3365 * the Base and Length of the Rx Descriptor Ring
3367 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3368 ixgbe_configure_rx_ring(adapter
, adapter
->rx_ring
[i
]);
3370 /* disable drop enable for 82598 parts */
3371 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3372 rxctrl
|= IXGBE_RXCTRL_DMBYPS
;
3374 /* enable all receives */
3375 rxctrl
|= IXGBE_RXCTRL_RXEN
;
3376 hw
->mac
.ops
.enable_rx_dma(hw
, rxctrl
);
3379 static void ixgbe_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
3381 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3382 struct ixgbe_hw
*hw
= &adapter
->hw
;
3383 int pool_ndx
= adapter
->num_vfs
;
3385 /* add VID to filter table */
3386 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, true);
3387 set_bit(vid
, adapter
->active_vlans
);
3390 static void ixgbe_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
3392 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3393 struct ixgbe_hw
*hw
= &adapter
->hw
;
3394 int pool_ndx
= adapter
->num_vfs
;
3396 /* remove VID from filter table */
3397 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, false);
3398 clear_bit(vid
, adapter
->active_vlans
);
3402 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3403 * @adapter: driver data
3405 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter
*adapter
)
3407 struct ixgbe_hw
*hw
= &adapter
->hw
;
3410 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3411 vlnctrl
&= ~(IXGBE_VLNCTRL_VFE
| IXGBE_VLNCTRL_CFIEN
);
3412 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3416 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3417 * @adapter: driver data
3419 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter
*adapter
)
3421 struct ixgbe_hw
*hw
= &adapter
->hw
;
3424 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3425 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
3426 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
3427 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3431 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3432 * @adapter: driver data
3434 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter
*adapter
)
3436 struct ixgbe_hw
*hw
= &adapter
->hw
;
3440 switch (hw
->mac
.type
) {
3441 case ixgbe_mac_82598EB
:
3442 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3443 vlnctrl
&= ~IXGBE_VLNCTRL_VME
;
3444 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3446 case ixgbe_mac_82599EB
:
3447 case ixgbe_mac_X540
:
3448 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3449 j
= adapter
->rx_ring
[i
]->reg_idx
;
3450 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3451 vlnctrl
&= ~IXGBE_RXDCTL_VME
;
3452 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
3461 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3462 * @adapter: driver data
3464 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter
*adapter
)
3466 struct ixgbe_hw
*hw
= &adapter
->hw
;
3470 switch (hw
->mac
.type
) {
3471 case ixgbe_mac_82598EB
:
3472 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3473 vlnctrl
|= IXGBE_VLNCTRL_VME
;
3474 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3476 case ixgbe_mac_82599EB
:
3477 case ixgbe_mac_X540
:
3478 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3479 j
= adapter
->rx_ring
[i
]->reg_idx
;
3480 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3481 vlnctrl
|= IXGBE_RXDCTL_VME
;
3482 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
3490 static void ixgbe_restore_vlan(struct ixgbe_adapter
*adapter
)
3494 ixgbe_vlan_rx_add_vid(adapter
->netdev
, 0);
3496 for_each_set_bit(vid
, adapter
->active_vlans
, VLAN_N_VID
)
3497 ixgbe_vlan_rx_add_vid(adapter
->netdev
, vid
);
3501 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3502 * @netdev: network interface device structure
3504 * Writes unicast address list to the RAR table.
3505 * Returns: -ENOMEM on failure/insufficient address space
3506 * 0 on no addresses written
3507 * X on writing X addresses to the RAR table
3509 static int ixgbe_write_uc_addr_list(struct net_device
*netdev
)
3511 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3512 struct ixgbe_hw
*hw
= &adapter
->hw
;
3513 unsigned int vfn
= adapter
->num_vfs
;
3514 unsigned int rar_entries
= IXGBE_MAX_PF_MACVLANS
;
3517 /* return ENOMEM indicating insufficient memory for addresses */
3518 if (netdev_uc_count(netdev
) > rar_entries
)
3521 if (!netdev_uc_empty(netdev
) && rar_entries
) {
3522 struct netdev_hw_addr
*ha
;
3523 /* return error if we do not support writing to RAR table */
3524 if (!hw
->mac
.ops
.set_rar
)
3527 netdev_for_each_uc_addr(ha
, netdev
) {
3530 hw
->mac
.ops
.set_rar(hw
, rar_entries
--, ha
->addr
,
3535 /* write the addresses in reverse order to avoid write combining */
3536 for (; rar_entries
> 0 ; rar_entries
--)
3537 hw
->mac
.ops
.clear_rar(hw
, rar_entries
);
3543 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3544 * @netdev: network interface device structure
3546 * The set_rx_method entry point is called whenever the unicast/multicast
3547 * address list or the network interface flags are updated. This routine is
3548 * responsible for configuring the hardware for proper unicast, multicast and
3551 void ixgbe_set_rx_mode(struct net_device
*netdev
)
3553 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3554 struct ixgbe_hw
*hw
= &adapter
->hw
;
3555 u32 fctrl
, vmolr
= IXGBE_VMOLR_BAM
| IXGBE_VMOLR_AUPE
;
3558 /* Check for Promiscuous and All Multicast modes */
3560 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
3562 /* set all bits that we expect to always be set */
3563 fctrl
|= IXGBE_FCTRL_BAM
;
3564 fctrl
|= IXGBE_FCTRL_DPF
; /* discard pause frames when FC enabled */
3565 fctrl
|= IXGBE_FCTRL_PMCF
;
3567 /* clear the bits we are changing the status of */
3568 fctrl
&= ~(IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3570 if (netdev
->flags
& IFF_PROMISC
) {
3571 hw
->addr_ctrl
.user_set_promisc
= true;
3572 fctrl
|= (IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3573 vmolr
|= (IXGBE_VMOLR_ROPE
| IXGBE_VMOLR_MPE
);
3574 /* don't hardware filter vlans in promisc mode */
3575 ixgbe_vlan_filter_disable(adapter
);
3577 if (netdev
->flags
& IFF_ALLMULTI
) {
3578 fctrl
|= IXGBE_FCTRL_MPE
;
3579 vmolr
|= IXGBE_VMOLR_MPE
;
3582 * Write addresses to the MTA, if the attempt fails
3583 * then we should just turn on promiscuous mode so
3584 * that we can at least receive multicast traffic
3586 hw
->mac
.ops
.update_mc_addr_list(hw
, netdev
);
3587 vmolr
|= IXGBE_VMOLR_ROMPE
;
3589 ixgbe_vlan_filter_enable(adapter
);
3590 hw
->addr_ctrl
.user_set_promisc
= false;
3592 * Write addresses to available RAR registers, if there is not
3593 * sufficient space to store all the addresses then enable
3594 * unicast promiscuous mode
3596 count
= ixgbe_write_uc_addr_list(netdev
);
3598 fctrl
|= IXGBE_FCTRL_UPE
;
3599 vmolr
|= IXGBE_VMOLR_ROPE
;
3603 if (adapter
->num_vfs
) {
3604 ixgbe_restore_vf_multicasts(adapter
);
3605 vmolr
|= IXGBE_READ_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
)) &
3606 ~(IXGBE_VMOLR_MPE
| IXGBE_VMOLR_ROMPE
|
3608 IXGBE_WRITE_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
), vmolr
);
3611 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
3613 if (netdev
->features
& NETIF_F_HW_VLAN_RX
)
3614 ixgbe_vlan_strip_enable(adapter
);
3616 ixgbe_vlan_strip_disable(adapter
);
3619 static void ixgbe_napi_enable_all(struct ixgbe_adapter
*adapter
)
3622 struct ixgbe_q_vector
*q_vector
;
3623 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3625 /* legacy and MSI only use one vector */
3626 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3629 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3630 struct napi_struct
*napi
;
3631 q_vector
= adapter
->q_vector
[q_idx
];
3632 napi
= &q_vector
->napi
;
3633 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3634 if (!q_vector
->rxr_count
|| !q_vector
->txr_count
) {
3635 if (q_vector
->txr_count
== 1)
3636 napi
->poll
= &ixgbe_clean_txonly
;
3637 else if (q_vector
->rxr_count
== 1)
3638 napi
->poll
= &ixgbe_clean_rxonly
;
3646 static void ixgbe_napi_disable_all(struct ixgbe_adapter
*adapter
)
3649 struct ixgbe_q_vector
*q_vector
;
3650 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3652 /* legacy and MSI only use one vector */
3653 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3656 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3657 q_vector
= adapter
->q_vector
[q_idx
];
3658 napi_disable(&q_vector
->napi
);
3662 #ifdef CONFIG_IXGBE_DCB
3664 * ixgbe_configure_dcb - Configure DCB hardware
3665 * @adapter: ixgbe adapter struct
3667 * This is called by the driver on open to configure the DCB hardware.
3668 * This is also called by the gennetlink interface when reconfiguring
3671 static void ixgbe_configure_dcb(struct ixgbe_adapter
*adapter
)
3673 struct ixgbe_hw
*hw
= &adapter
->hw
;
3674 int max_frame
= adapter
->netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3676 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)) {
3677 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3678 netif_set_gso_max_size(adapter
->netdev
, 65536);
3682 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3683 netif_set_gso_max_size(adapter
->netdev
, 32768);
3686 /* Enable VLAN tag insert/strip */
3687 adapter
->netdev
->features
|= NETIF_F_HW_VLAN_RX
;
3689 hw
->mac
.ops
.set_vfta(&adapter
->hw
, 0, 0, true);
3691 /* reconfigure the hardware */
3692 if (adapter
->dcbx_cap
& DCB_CAP_DCBX_VER_CEE
) {
3694 if (adapter
->netdev
->features
& NETIF_F_FCOE_MTU
)
3695 max_frame
= max(max_frame
, IXGBE_FCOE_JUMBO_FRAME_SIZE
);
3697 ixgbe_dcb_calculate_tc_credits(hw
, &adapter
->dcb_cfg
, max_frame
,
3699 ixgbe_dcb_calculate_tc_credits(hw
, &adapter
->dcb_cfg
, max_frame
,
3701 ixgbe_dcb_hw_config(hw
, &adapter
->dcb_cfg
);
3703 struct net_device
*dev
= adapter
->netdev
;
3705 if (adapter
->ixgbe_ieee_ets
)
3706 dev
->dcbnl_ops
->ieee_setets(dev
,
3707 adapter
->ixgbe_ieee_ets
);
3708 if (adapter
->ixgbe_ieee_pfc
)
3709 dev
->dcbnl_ops
->ieee_setpfc(dev
,
3710 adapter
->ixgbe_ieee_pfc
);
3713 /* Enable RSS Hash per TC */
3714 if (hw
->mac
.type
!= ixgbe_mac_82598EB
) {
3718 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++) {
3720 u8 cnt
= adapter
->netdev
->tc_to_txq
[i
].count
;
3725 reg
|= msb
<< IXGBE_RQTC_SHIFT_TC(i
);
3727 IXGBE_WRITE_REG(hw
, IXGBE_RQTC
, reg
);
3733 static void ixgbe_configure_pb(struct ixgbe_adapter
*adapter
)
3736 int num_tc
= netdev_get_num_tc(adapter
->netdev
);
3737 struct ixgbe_hw
*hw
= &adapter
->hw
;
3739 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3740 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
3741 hdrm
= 64 << adapter
->fdir_pballoc
;
3743 hw
->mac
.ops
.set_rxpba(&adapter
->hw
, num_tc
, hdrm
, PBA_STRATEGY_EQUAL
);
3746 static void ixgbe_configure(struct ixgbe_adapter
*adapter
)
3748 struct net_device
*netdev
= adapter
->netdev
;
3749 struct ixgbe_hw
*hw
= &adapter
->hw
;
3752 ixgbe_configure_pb(adapter
);
3753 #ifdef CONFIG_IXGBE_DCB
3754 ixgbe_configure_dcb(adapter
);
3757 ixgbe_set_rx_mode(netdev
);
3758 ixgbe_restore_vlan(adapter
);
3761 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
3762 ixgbe_configure_fcoe(adapter
);
3764 #endif /* IXGBE_FCOE */
3765 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
3766 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3767 adapter
->tx_ring
[i
]->atr_sample_rate
=
3768 adapter
->atr_sample_rate
;
3769 ixgbe_init_fdir_signature_82599(hw
, adapter
->fdir_pballoc
);
3770 } else if (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
) {
3771 ixgbe_init_fdir_perfect_82599(hw
, adapter
->fdir_pballoc
);
3773 ixgbe_configure_virtualization(adapter
);
3775 ixgbe_configure_tx(adapter
);
3776 ixgbe_configure_rx(adapter
);
3779 static inline bool ixgbe_is_sfp(struct ixgbe_hw
*hw
)
3781 switch (hw
->phy
.type
) {
3782 case ixgbe_phy_sfp_avago
:
3783 case ixgbe_phy_sfp_ftl
:
3784 case ixgbe_phy_sfp_intel
:
3785 case ixgbe_phy_sfp_unknown
:
3786 case ixgbe_phy_sfp_passive_tyco
:
3787 case ixgbe_phy_sfp_passive_unknown
:
3788 case ixgbe_phy_sfp_active_unknown
:
3789 case ixgbe_phy_sfp_ftl_active
:
3797 * ixgbe_sfp_link_config - set up SFP+ link
3798 * @adapter: pointer to private adapter struct
3800 static void ixgbe_sfp_link_config(struct ixgbe_adapter
*adapter
)
3803 * We are assuming the worst case scenerio here, and that
3804 * is that an SFP was inserted/removed after the reset
3805 * but before SFP detection was enabled. As such the best
3806 * solution is to just start searching as soon as we start
3808 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
3809 adapter
->flags2
|= IXGBE_FLAG2_SEARCH_FOR_SFP
;
3811 adapter
->flags2
|= IXGBE_FLAG2_SFP_NEEDS_RESET
;
3815 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3816 * @hw: pointer to private hardware struct
3818 * Returns 0 on success, negative on failure
3820 static int ixgbe_non_sfp_link_config(struct ixgbe_hw
*hw
)
3823 bool negotiation
, link_up
= false;
3824 u32 ret
= IXGBE_ERR_LINK_SETUP
;
3826 if (hw
->mac
.ops
.check_link
)
3827 ret
= hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
3832 autoneg
= hw
->phy
.autoneg_advertised
;
3833 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
3834 ret
= hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
,
3839 if (hw
->mac
.ops
.setup_link
)
3840 ret
= hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, link_up
);
3845 static void ixgbe_setup_gpie(struct ixgbe_adapter
*adapter
)
3847 struct ixgbe_hw
*hw
= &adapter
->hw
;
3850 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3851 gpie
= IXGBE_GPIE_MSIX_MODE
| IXGBE_GPIE_PBA_SUPPORT
|
3853 gpie
|= IXGBE_GPIE_EIAME
;
3855 * use EIAM to auto-mask when MSI-X interrupt is asserted
3856 * this saves a register write for every interrupt
3858 switch (hw
->mac
.type
) {
3859 case ixgbe_mac_82598EB
:
3860 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3862 case ixgbe_mac_82599EB
:
3863 case ixgbe_mac_X540
:
3865 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3866 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3870 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3871 * specifically only auto mask tx and rx interrupts */
3872 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3875 /* XXX: to interrupt immediately for EICS writes, enable this */
3876 /* gpie |= IXGBE_GPIE_EIMEN; */
3878 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
3879 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
3880 gpie
|= IXGBE_GPIE_VTMODE_64
;
3883 /* Enable fan failure interrupt */
3884 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
3885 gpie
|= IXGBE_SDP1_GPIEN
;
3887 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
3888 gpie
|= IXGBE_SDP1_GPIEN
;
3889 gpie
|= IXGBE_SDP2_GPIEN
;
3892 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3895 static int ixgbe_up_complete(struct ixgbe_adapter
*adapter
)
3897 struct ixgbe_hw
*hw
= &adapter
->hw
;
3901 ixgbe_get_hw_control(adapter
);
3902 ixgbe_setup_gpie(adapter
);
3904 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3905 ixgbe_configure_msix(adapter
);
3907 ixgbe_configure_msi_and_legacy(adapter
);
3909 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3910 if (hw
->mac
.ops
.enable_tx_laser
&&
3911 ((hw
->phy
.multispeed_fiber
) ||
3912 ((hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) &&
3913 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
3914 hw
->mac
.ops
.enable_tx_laser(hw
);
3916 clear_bit(__IXGBE_DOWN
, &adapter
->state
);
3917 ixgbe_napi_enable_all(adapter
);
3919 if (ixgbe_is_sfp(hw
)) {
3920 ixgbe_sfp_link_config(adapter
);
3922 err
= ixgbe_non_sfp_link_config(hw
);
3924 e_err(probe
, "link_config FAILED %d\n", err
);
3927 /* clear any pending interrupts, may auto mask */
3928 IXGBE_READ_REG(hw
, IXGBE_EICR
);
3929 ixgbe_irq_enable(adapter
, true, true);
3932 * If this adapter has a fan, check to see if we had a failure
3933 * before we enabled the interrupt.
3935 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
3936 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
3937 if (esdp
& IXGBE_ESDP_SDP1
)
3938 e_crit(drv
, "Fan has stopped, replace the adapter\n");
3941 /* enable transmits */
3942 netif_tx_start_all_queues(adapter
->netdev
);
3944 /* bring the link up in the watchdog, this could race with our first
3945 * link up interrupt but shouldn't be a problem */
3946 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
3947 adapter
->link_check_timeout
= jiffies
;
3948 mod_timer(&adapter
->service_timer
, jiffies
);
3950 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3951 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
3952 ctrl_ext
|= IXGBE_CTRL_EXT_PFRSTD
;
3953 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
3958 void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
)
3960 WARN_ON(in_interrupt());
3961 /* put off any impending NetWatchDogTimeout */
3962 adapter
->netdev
->trans_start
= jiffies
;
3964 while (test_and_set_bit(__IXGBE_RESETTING
, &adapter
->state
))
3965 usleep_range(1000, 2000);
3966 ixgbe_down(adapter
);
3968 * If SR-IOV enabled then wait a bit before bringing the adapter
3969 * back up to give the VFs time to respond to the reset. The
3970 * two second wait is based upon the watchdog timer cycle in
3973 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
3976 clear_bit(__IXGBE_RESETTING
, &adapter
->state
);
3979 int ixgbe_up(struct ixgbe_adapter
*adapter
)
3981 /* hardware has been reset, we need to reload some things */
3982 ixgbe_configure(adapter
);
3984 return ixgbe_up_complete(adapter
);
3987 void ixgbe_reset(struct ixgbe_adapter
*adapter
)
3989 struct ixgbe_hw
*hw
= &adapter
->hw
;
3992 /* lock SFP init bit to prevent race conditions with the watchdog */
3993 while (test_and_set_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
))
3994 usleep_range(1000, 2000);
3996 /* clear all SFP and link config related flags while holding SFP_INIT */
3997 adapter
->flags2
&= ~(IXGBE_FLAG2_SEARCH_FOR_SFP
|
3998 IXGBE_FLAG2_SFP_NEEDS_RESET
);
3999 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_CONFIG
;
4001 err
= hw
->mac
.ops
.init_hw(hw
);
4004 case IXGBE_ERR_SFP_NOT_PRESENT
:
4005 case IXGBE_ERR_SFP_NOT_SUPPORTED
:
4007 case IXGBE_ERR_MASTER_REQUESTS_PENDING
:
4008 e_dev_err("master disable timed out\n");
4010 case IXGBE_ERR_EEPROM_VERSION
:
4011 /* We are running on a pre-production device, log a warning */
4012 e_dev_warn("This device is a pre-production adapter/LOM. "
4013 "Please be aware there may be issuesassociated with "
4014 "your hardware. If you are experiencing problems "
4015 "please contact your Intel or hardware "
4016 "representative who provided you with this "
4020 e_dev_err("Hardware Error: %d\n", err
);
4023 clear_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
);
4025 /* reprogram the RAR[0] in case user changed it. */
4026 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
4031 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4032 * @rx_ring: ring to free buffers from
4034 static void ixgbe_clean_rx_ring(struct ixgbe_ring
*rx_ring
)
4036 struct device
*dev
= rx_ring
->dev
;
4040 /* ring already cleared, nothing to do */
4041 if (!rx_ring
->rx_buffer_info
)
4044 /* Free all the Rx ring sk_buffs */
4045 for (i
= 0; i
< rx_ring
->count
; i
++) {
4046 struct ixgbe_rx_buffer
*rx_buffer_info
;
4048 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
4049 if (rx_buffer_info
->dma
) {
4050 dma_unmap_single(rx_ring
->dev
, rx_buffer_info
->dma
,
4051 rx_ring
->rx_buf_len
,
4053 rx_buffer_info
->dma
= 0;
4055 if (rx_buffer_info
->skb
) {
4056 struct sk_buff
*skb
= rx_buffer_info
->skb
;
4057 rx_buffer_info
->skb
= NULL
;
4059 struct sk_buff
*this = skb
;
4060 if (IXGBE_RSC_CB(this)->delay_unmap
) {
4061 dma_unmap_single(dev
,
4062 IXGBE_RSC_CB(this)->dma
,
4063 rx_ring
->rx_buf_len
,
4065 IXGBE_RSC_CB(this)->dma
= 0;
4066 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
4069 dev_kfree_skb(this);
4072 if (!rx_buffer_info
->page
)
4074 if (rx_buffer_info
->page_dma
) {
4075 dma_unmap_page(dev
, rx_buffer_info
->page_dma
,
4076 PAGE_SIZE
/ 2, DMA_FROM_DEVICE
);
4077 rx_buffer_info
->page_dma
= 0;
4079 put_page(rx_buffer_info
->page
);
4080 rx_buffer_info
->page
= NULL
;
4081 rx_buffer_info
->page_offset
= 0;
4084 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
4085 memset(rx_ring
->rx_buffer_info
, 0, size
);
4087 /* Zero out the descriptor ring */
4088 memset(rx_ring
->desc
, 0, rx_ring
->size
);
4090 rx_ring
->next_to_clean
= 0;
4091 rx_ring
->next_to_use
= 0;
4095 * ixgbe_clean_tx_ring - Free Tx Buffers
4096 * @tx_ring: ring to be cleaned
4098 static void ixgbe_clean_tx_ring(struct ixgbe_ring
*tx_ring
)
4100 struct ixgbe_tx_buffer
*tx_buffer_info
;
4104 /* ring already cleared, nothing to do */
4105 if (!tx_ring
->tx_buffer_info
)
4108 /* Free all the Tx ring sk_buffs */
4109 for (i
= 0; i
< tx_ring
->count
; i
++) {
4110 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
4111 ixgbe_unmap_and_free_tx_resource(tx_ring
, tx_buffer_info
);
4114 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
4115 memset(tx_ring
->tx_buffer_info
, 0, size
);
4117 /* Zero out the descriptor ring */
4118 memset(tx_ring
->desc
, 0, tx_ring
->size
);
4120 tx_ring
->next_to_use
= 0;
4121 tx_ring
->next_to_clean
= 0;
4125 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4126 * @adapter: board private structure
4128 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter
*adapter
)
4132 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4133 ixgbe_clean_rx_ring(adapter
->rx_ring
[i
]);
4137 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4138 * @adapter: board private structure
4140 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter
*adapter
)
4144 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4145 ixgbe_clean_tx_ring(adapter
->tx_ring
[i
]);
4148 void ixgbe_down(struct ixgbe_adapter
*adapter
)
4150 struct net_device
*netdev
= adapter
->netdev
;
4151 struct ixgbe_hw
*hw
= &adapter
->hw
;
4154 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4156 /* signal that we are down to the interrupt handler */
4157 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4159 /* disable receives */
4160 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
4161 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
4163 /* disable all enabled rx queues */
4164 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4165 /* this call also flushes the previous write */
4166 ixgbe_disable_rx_queue(adapter
, adapter
->rx_ring
[i
]);
4168 usleep_range(10000, 20000);
4170 netif_tx_stop_all_queues(netdev
);
4172 /* call carrier off first to avoid false dev_watchdog timeouts */
4173 netif_carrier_off(netdev
);
4174 netif_tx_disable(netdev
);
4176 ixgbe_irq_disable(adapter
);
4178 ixgbe_napi_disable_all(adapter
);
4180 adapter
->flags2
&= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT
|
4181 IXGBE_FLAG2_RESET_REQUESTED
);
4182 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
4184 del_timer_sync(&adapter
->service_timer
);
4186 /* disable receive for all VFs and wait one second */
4187 if (adapter
->num_vfs
) {
4188 /* ping all the active vfs to let them know we are going down */
4189 ixgbe_ping_all_vfs(adapter
);
4191 /* Disable all VFTE/VFRE TX/RX */
4192 ixgbe_disable_tx_rx(adapter
);
4194 /* Mark all the VFs as inactive */
4195 for (i
= 0 ; i
< adapter
->num_vfs
; i
++)
4196 adapter
->vfinfo
[i
].clear_to_send
= 0;
4199 /* Cleanup the affinity_hint CPU mask memory and callback */
4200 for (i
= 0; i
< num_q_vectors
; i
++) {
4201 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
4202 /* clear the affinity_mask in the IRQ descriptor */
4203 irq_set_affinity_hint(adapter
->msix_entries
[i
]. vector
, NULL
);
4204 /* release the CPU mask memory */
4205 free_cpumask_var(q_vector
->affinity_mask
);
4208 /* disable transmits in the hardware now that interrupts are off */
4209 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4210 u8 reg_idx
= adapter
->tx_ring
[i
]->reg_idx
;
4211 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
), IXGBE_TXDCTL_SWFLSH
);
4214 /* Disable the Tx DMA engine on 82599 and X540 */
4215 switch (hw
->mac
.type
) {
4216 case ixgbe_mac_82599EB
:
4217 case ixgbe_mac_X540
:
4218 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
,
4219 (IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
) &
4220 ~IXGBE_DMATXCTL_TE
));
4226 if (!pci_channel_offline(adapter
->pdev
))
4227 ixgbe_reset(adapter
);
4229 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4230 if (hw
->mac
.ops
.disable_tx_laser
&&
4231 ((hw
->phy
.multispeed_fiber
) ||
4232 ((hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) &&
4233 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
4234 hw
->mac
.ops
.disable_tx_laser(hw
);
4236 ixgbe_clean_all_tx_rings(adapter
);
4237 ixgbe_clean_all_rx_rings(adapter
);
4239 #ifdef CONFIG_IXGBE_DCA
4240 /* since we reset the hardware DCA settings were cleared */
4241 ixgbe_setup_dca(adapter
);
4246 * ixgbe_poll - NAPI Rx polling callback
4247 * @napi: structure for representing this polling device
4248 * @budget: how many packets driver is allowed to clean
4250 * This function is used for legacy and MSI, NAPI mode
4252 static int ixgbe_poll(struct napi_struct
*napi
, int budget
)
4254 struct ixgbe_q_vector
*q_vector
=
4255 container_of(napi
, struct ixgbe_q_vector
, napi
);
4256 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
4257 int tx_clean_complete
, work_done
= 0;
4259 #ifdef CONFIG_IXGBE_DCA
4260 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
4261 ixgbe_update_dca(q_vector
);
4264 tx_clean_complete
= ixgbe_clean_tx_irq(q_vector
, adapter
->tx_ring
[0]);
4265 ixgbe_clean_rx_irq(q_vector
, adapter
->rx_ring
[0], &work_done
, budget
);
4267 if (!tx_clean_complete
)
4270 /* If budget not fully consumed, exit the polling mode */
4271 if (work_done
< budget
) {
4272 napi_complete(napi
);
4273 if (adapter
->rx_itr_setting
& 1)
4274 ixgbe_set_itr(adapter
);
4275 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
4276 ixgbe_irq_enable_queues(adapter
, IXGBE_EIMS_RTX_QUEUE
);
4282 * ixgbe_tx_timeout - Respond to a Tx Hang
4283 * @netdev: network interface device structure
4285 static void ixgbe_tx_timeout(struct net_device
*netdev
)
4287 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4289 /* Do the reset outside of interrupt context */
4290 ixgbe_tx_timeout_reset(adapter
);
4294 * ixgbe_set_rss_queues: Allocate queues for RSS
4295 * @adapter: board private structure to initialize
4297 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4298 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4301 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter
*adapter
)
4304 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_RSS
];
4306 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4308 adapter
->num_rx_queues
= f
->indices
;
4309 adapter
->num_tx_queues
= f
->indices
;
4319 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4320 * @adapter: board private structure to initialize
4322 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4323 * to the original CPU that initiated the Tx session. This runs in addition
4324 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4325 * Rx load across CPUs using RSS.
4328 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter
*adapter
)
4331 struct ixgbe_ring_feature
*f_fdir
= &adapter
->ring_feature
[RING_F_FDIR
];
4333 f_fdir
->indices
= min((int)num_online_cpus(), f_fdir
->indices
);
4336 /* Flow Director must have RSS enabled */
4337 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
4338 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
4339 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)))) {
4340 adapter
->num_tx_queues
= f_fdir
->indices
;
4341 adapter
->num_rx_queues
= f_fdir
->indices
;
4344 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4345 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4352 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4353 * @adapter: board private structure to initialize
4355 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4356 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4357 * rx queues out of the max number of rx queues, instead, it is used as the
4358 * index of the first rx queue used by FCoE.
4361 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter
*adapter
)
4363 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4365 if (!(adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
))
4368 f
->indices
= min((int)num_online_cpus(), f
->indices
);
4370 adapter
->num_rx_queues
= 1;
4371 adapter
->num_tx_queues
= 1;
4373 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4374 e_info(probe
, "FCoE enabled with RSS\n");
4375 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4376 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
4377 ixgbe_set_fdir_queues(adapter
);
4379 ixgbe_set_rss_queues(adapter
);
4381 /* adding FCoE rx rings to the end */
4382 f
->mask
= adapter
->num_rx_queues
;
4383 adapter
->num_rx_queues
+= f
->indices
;
4384 adapter
->num_tx_queues
+= f
->indices
;
4388 #endif /* IXGBE_FCOE */
4390 /* Artificial max queue cap per traffic class in DCB mode */
4391 #define DCB_QUEUE_CAP 8
4393 #ifdef CONFIG_IXGBE_DCB
4394 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter
*adapter
)
4396 int per_tc_q
, q
, i
, offset
= 0;
4397 struct net_device
*dev
= adapter
->netdev
;
4398 int tcs
= netdev_get_num_tc(dev
);
4403 /* Map queue offset and counts onto allocated tx queues */
4404 per_tc_q
= min(dev
->num_tx_queues
/ tcs
, (unsigned int)DCB_QUEUE_CAP
);
4405 q
= min((int)num_online_cpus(), per_tc_q
);
4407 for (i
= 0; i
< tcs
; i
++) {
4408 netdev_set_prio_tc_map(dev
, i
, i
);
4409 netdev_set_tc_queue(dev
, i
, q
, offset
);
4413 adapter
->num_tx_queues
= q
* tcs
;
4414 adapter
->num_rx_queues
= q
* tcs
;
4417 /* FCoE enabled queues require special configuration indexed
4418 * by feature specific indices and mask. Here we map FCoE
4419 * indices onto the DCB queue pairs allowing FCoE to own
4420 * configuration later.
4422 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
4424 struct ixgbe_ring_feature
*f
=
4425 &adapter
->ring_feature
[RING_F_FCOE
];
4427 tc
= netdev_get_prio_tc_map(dev
, adapter
->fcoe
.up
);
4428 f
->indices
= dev
->tc_to_txq
[tc
].count
;
4429 f
->mask
= dev
->tc_to_txq
[tc
].offset
;
4438 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4439 * @adapter: board private structure to initialize
4441 * IOV doesn't actually use anything, so just NAK the
4442 * request for now and let the other queue routines
4443 * figure out what to do.
4445 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter
*adapter
)
4451 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4452 * @adapter: board private structure to initialize
4454 * This is the top level queue allocation routine. The order here is very
4455 * important, starting with the "most" number of features turned on at once,
4456 * and ending with the smallest set of features. This way large combinations
4457 * can be allocated if they're turned on, and smaller combinations are the
4458 * fallthrough conditions.
4461 static int ixgbe_set_num_queues(struct ixgbe_adapter
*adapter
)
4463 /* Start with base case */
4464 adapter
->num_rx_queues
= 1;
4465 adapter
->num_tx_queues
= 1;
4466 adapter
->num_rx_pools
= adapter
->num_rx_queues
;
4467 adapter
->num_rx_queues_per_pool
= 1;
4469 if (ixgbe_set_sriov_queues(adapter
))
4472 #ifdef CONFIG_IXGBE_DCB
4473 if (ixgbe_set_dcb_queues(adapter
))
4478 if (ixgbe_set_fcoe_queues(adapter
))
4481 #endif /* IXGBE_FCOE */
4482 if (ixgbe_set_fdir_queues(adapter
))
4485 if (ixgbe_set_rss_queues(adapter
))
4488 /* fallback to base case */
4489 adapter
->num_rx_queues
= 1;
4490 adapter
->num_tx_queues
= 1;
4493 /* Notify the stack of the (possibly) reduced queue counts. */
4494 netif_set_real_num_tx_queues(adapter
->netdev
, adapter
->num_tx_queues
);
4495 return netif_set_real_num_rx_queues(adapter
->netdev
,
4496 adapter
->num_rx_queues
);
4499 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter
*adapter
,
4502 int err
, vector_threshold
;
4504 /* We'll want at least 3 (vector_threshold):
4507 * 3) Other (Link Status Change, etc.)
4508 * 4) TCP Timer (optional)
4510 vector_threshold
= MIN_MSIX_COUNT
;
4512 /* The more we get, the more we will assign to Tx/Rx Cleanup
4513 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4514 * Right now, we simply care about how many we'll get; we'll
4515 * set them up later while requesting irq's.
4517 while (vectors
>= vector_threshold
) {
4518 err
= pci_enable_msix(adapter
->pdev
, adapter
->msix_entries
,
4520 if (!err
) /* Success in acquiring all requested vectors. */
4523 vectors
= 0; /* Nasty failure, quit now */
4524 else /* err == number of vectors we should try again with */
4528 if (vectors
< vector_threshold
) {
4529 /* Can't allocate enough MSI-X interrupts? Oh well.
4530 * This just means we'll go with either a single MSI
4531 * vector or fall back to legacy interrupts.
4533 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4534 "Unable to allocate MSI-X interrupts\n");
4535 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4536 kfree(adapter
->msix_entries
);
4537 adapter
->msix_entries
= NULL
;
4539 adapter
->flags
|= IXGBE_FLAG_MSIX_ENABLED
; /* Woot! */
4541 * Adjust for only the vectors we'll use, which is minimum
4542 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4543 * vectors we were allocated.
4545 adapter
->num_msix_vectors
= min(vectors
,
4546 adapter
->max_msix_q_vectors
+ NON_Q_VECTORS
);
4551 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4552 * @adapter: board private structure to initialize
4554 * Cache the descriptor ring offsets for RSS to the assigned rings.
4557 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter
*adapter
)
4561 if (!(adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
))
4564 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4565 adapter
->rx_ring
[i
]->reg_idx
= i
;
4566 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4567 adapter
->tx_ring
[i
]->reg_idx
= i
;
4572 #ifdef CONFIG_IXGBE_DCB
4574 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4575 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter
*adapter
, u8 tc
,
4576 unsigned int *tx
, unsigned int *rx
)
4578 struct net_device
*dev
= adapter
->netdev
;
4579 struct ixgbe_hw
*hw
= &adapter
->hw
;
4580 u8 num_tcs
= netdev_get_num_tc(dev
);
4585 switch (hw
->mac
.type
) {
4586 case ixgbe_mac_82598EB
:
4590 case ixgbe_mac_82599EB
:
4591 case ixgbe_mac_X540
:
4596 } else if (tc
< 5) {
4597 *tx
= ((tc
+ 2) << 4);
4599 } else if (tc
< num_tcs
) {
4600 *tx
= ((tc
+ 8) << 3);
4603 } else if (num_tcs
== 4) {
4629 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4630 * @adapter: board private structure to initialize
4632 * Cache the descriptor ring offsets for DCB to the assigned rings.
4635 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter
*adapter
)
4637 struct net_device
*dev
= adapter
->netdev
;
4639 u8 num_tcs
= netdev_get_num_tc(dev
);
4644 for (i
= 0, k
= 0; i
< num_tcs
; i
++) {
4645 unsigned int tx_s
, rx_s
;
4646 u16 count
= dev
->tc_to_txq
[i
].count
;
4648 ixgbe_get_first_reg_idx(adapter
, i
, &tx_s
, &rx_s
);
4649 for (j
= 0; j
< count
; j
++, k
++) {
4650 adapter
->tx_ring
[k
]->reg_idx
= tx_s
+ j
;
4651 adapter
->rx_ring
[k
]->reg_idx
= rx_s
+ j
;
4652 adapter
->tx_ring
[k
]->dcb_tc
= i
;
4653 adapter
->rx_ring
[k
]->dcb_tc
= i
;
4662 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4663 * @adapter: board private structure to initialize
4665 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4668 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter
*adapter
)
4673 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
4674 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4675 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))) {
4676 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4677 adapter
->rx_ring
[i
]->reg_idx
= i
;
4678 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4679 adapter
->tx_ring
[i
]->reg_idx
= i
;
4688 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4689 * @adapter: board private structure to initialize
4691 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4694 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter
*adapter
)
4696 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4698 u8 fcoe_rx_i
= 0, fcoe_tx_i
= 0;
4700 if (!(adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
))
4703 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4704 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4705 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
4706 ixgbe_cache_ring_fdir(adapter
);
4708 ixgbe_cache_ring_rss(adapter
);
4710 fcoe_rx_i
= f
->mask
;
4711 fcoe_tx_i
= f
->mask
;
4713 for (i
= 0; i
< f
->indices
; i
++, fcoe_rx_i
++, fcoe_tx_i
++) {
4714 adapter
->rx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_rx_i
;
4715 adapter
->tx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_tx_i
;
4720 #endif /* IXGBE_FCOE */
4722 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4723 * @adapter: board private structure to initialize
4725 * SR-IOV doesn't use any descriptor rings but changes the default if
4726 * no other mapping is used.
4729 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter
*adapter
)
4731 adapter
->rx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4732 adapter
->tx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4733 if (adapter
->num_vfs
)
4740 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4741 * @adapter: board private structure to initialize
4743 * Once we know the feature-set enabled for the device, we'll cache
4744 * the register offset the descriptor ring is assigned to.
4746 * Note, the order the various feature calls is important. It must start with
4747 * the "most" features enabled at the same time, then trickle down to the
4748 * least amount of features turned on at once.
4750 static void ixgbe_cache_ring_register(struct ixgbe_adapter
*adapter
)
4752 /* start with default case */
4753 adapter
->rx_ring
[0]->reg_idx
= 0;
4754 adapter
->tx_ring
[0]->reg_idx
= 0;
4756 if (ixgbe_cache_ring_sriov(adapter
))
4759 #ifdef CONFIG_IXGBE_DCB
4760 if (ixgbe_cache_ring_dcb(adapter
))
4765 if (ixgbe_cache_ring_fcoe(adapter
))
4767 #endif /* IXGBE_FCOE */
4769 if (ixgbe_cache_ring_fdir(adapter
))
4772 if (ixgbe_cache_ring_rss(adapter
))
4777 * ixgbe_alloc_queues - Allocate memory for all rings
4778 * @adapter: board private structure to initialize
4780 * We allocate one ring per queue at run-time since we don't know the
4781 * number of queues at compile-time. The polling_netdev array is
4782 * intended for Multiqueue, but should work fine with a single queue.
4784 static int ixgbe_alloc_queues(struct ixgbe_adapter
*adapter
)
4786 int rx
= 0, tx
= 0, nid
= adapter
->node
;
4788 if (nid
< 0 || !node_online(nid
))
4789 nid
= first_online_node
;
4791 for (; tx
< adapter
->num_tx_queues
; tx
++) {
4792 struct ixgbe_ring
*ring
;
4794 ring
= kzalloc_node(sizeof(*ring
), GFP_KERNEL
, nid
);
4796 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
4798 goto err_allocation
;
4799 ring
->count
= adapter
->tx_ring_count
;
4800 ring
->queue_index
= tx
;
4801 ring
->numa_node
= nid
;
4802 ring
->dev
= &adapter
->pdev
->dev
;
4803 ring
->netdev
= adapter
->netdev
;
4805 adapter
->tx_ring
[tx
] = ring
;
4808 for (; rx
< adapter
->num_rx_queues
; rx
++) {
4809 struct ixgbe_ring
*ring
;
4811 ring
= kzalloc_node(sizeof(*ring
), GFP_KERNEL
, nid
);
4813 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
4815 goto err_allocation
;
4816 ring
->count
= adapter
->rx_ring_count
;
4817 ring
->queue_index
= rx
;
4818 ring
->numa_node
= nid
;
4819 ring
->dev
= &adapter
->pdev
->dev
;
4820 ring
->netdev
= adapter
->netdev
;
4822 adapter
->rx_ring
[rx
] = ring
;
4825 ixgbe_cache_ring_register(adapter
);
4831 kfree(adapter
->tx_ring
[--tx
]);
4834 kfree(adapter
->rx_ring
[--rx
]);
4839 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4840 * @adapter: board private structure to initialize
4842 * Attempt to configure the interrupts using the best available
4843 * capabilities of the hardware and the kernel.
4845 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter
*adapter
)
4847 struct ixgbe_hw
*hw
= &adapter
->hw
;
4849 int vector
, v_budget
;
4852 * It's easy to be greedy for MSI-X vectors, but it really
4853 * doesn't do us much good if we have a lot more vectors
4854 * than CPU's. So let's be conservative and only ask for
4855 * (roughly) the same number of vectors as there are CPU's.
4857 v_budget
= min(adapter
->num_rx_queues
+ adapter
->num_tx_queues
,
4858 (int)num_online_cpus()) + NON_Q_VECTORS
;
4861 * At the same time, hardware can only support a maximum of
4862 * hw.mac->max_msix_vectors vectors. With features
4863 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4864 * descriptor queues supported by our device. Thus, we cap it off in
4865 * those rare cases where the cpu count also exceeds our vector limit.
4867 v_budget
= min(v_budget
, (int)hw
->mac
.max_msix_vectors
);
4869 /* A failure in MSI-X entry allocation isn't fatal, but it does
4870 * mean we disable MSI-X capabilities of the adapter. */
4871 adapter
->msix_entries
= kcalloc(v_budget
,
4872 sizeof(struct msix_entry
), GFP_KERNEL
);
4873 if (adapter
->msix_entries
) {
4874 for (vector
= 0; vector
< v_budget
; vector
++)
4875 adapter
->msix_entries
[vector
].entry
= vector
;
4877 ixgbe_acquire_msix_vectors(adapter
, v_budget
);
4879 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4883 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
4884 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
4885 if (adapter
->flags
& (IXGBE_FLAG_FDIR_HASH_CAPABLE
|
4886 IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)) {
4888 "Flow Director is not supported while multiple "
4889 "queues are disabled. Disabling Flow Director\n");
4891 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4892 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4893 adapter
->atr_sample_rate
= 0;
4894 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
4895 ixgbe_disable_sriov(adapter
);
4897 err
= ixgbe_set_num_queues(adapter
);
4901 err
= pci_enable_msi(adapter
->pdev
);
4903 adapter
->flags
|= IXGBE_FLAG_MSI_ENABLED
;
4905 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4906 "Unable to allocate MSI interrupt, "
4907 "falling back to legacy. Error: %d\n", err
);
4917 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4918 * @adapter: board private structure to initialize
4920 * We allocate one q_vector per queue interrupt. If allocation fails we
4923 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter
*adapter
)
4925 int q_idx
, num_q_vectors
;
4926 struct ixgbe_q_vector
*q_vector
;
4927 int (*poll
)(struct napi_struct
*, int);
4929 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4930 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4931 poll
= &ixgbe_clean_rxtx_many
;
4937 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4938 q_vector
= kzalloc_node(sizeof(struct ixgbe_q_vector
),
4939 GFP_KERNEL
, adapter
->node
);
4941 q_vector
= kzalloc(sizeof(struct ixgbe_q_vector
),
4945 q_vector
->adapter
= adapter
;
4946 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
4947 q_vector
->eitr
= adapter
->tx_eitr_param
;
4949 q_vector
->eitr
= adapter
->rx_eitr_param
;
4950 q_vector
->v_idx
= q_idx
;
4951 netif_napi_add(adapter
->netdev
, &q_vector
->napi
, (*poll
), 64);
4952 adapter
->q_vector
[q_idx
] = q_vector
;
4960 q_vector
= adapter
->q_vector
[q_idx
];
4961 netif_napi_del(&q_vector
->napi
);
4963 adapter
->q_vector
[q_idx
] = NULL
;
4969 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4970 * @adapter: board private structure to initialize
4972 * This function frees the memory allocated to the q_vectors. In addition if
4973 * NAPI is enabled it will delete any references to the NAPI struct prior
4974 * to freeing the q_vector.
4976 static void ixgbe_free_q_vectors(struct ixgbe_adapter
*adapter
)
4978 int q_idx
, num_q_vectors
;
4980 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4981 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4985 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4986 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[q_idx
];
4987 adapter
->q_vector
[q_idx
] = NULL
;
4988 netif_napi_del(&q_vector
->napi
);
4993 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
)
4995 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4996 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4997 pci_disable_msix(adapter
->pdev
);
4998 kfree(adapter
->msix_entries
);
4999 adapter
->msix_entries
= NULL
;
5000 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
5001 adapter
->flags
&= ~IXGBE_FLAG_MSI_ENABLED
;
5002 pci_disable_msi(adapter
->pdev
);
5007 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5008 * @adapter: board private structure to initialize
5010 * We determine which interrupt scheme to use based on...
5011 * - Kernel support (MSI, MSI-X)
5012 * - which can be user-defined (via MODULE_PARAM)
5013 * - Hardware queue count (num_*_queues)
5014 * - defined by miscellaneous hardware support/features (RSS, etc.)
5016 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
)
5020 /* Number of supported queues */
5021 err
= ixgbe_set_num_queues(adapter
);
5025 err
= ixgbe_set_interrupt_capability(adapter
);
5027 e_dev_err("Unable to setup interrupt capabilities\n");
5028 goto err_set_interrupt
;
5031 err
= ixgbe_alloc_q_vectors(adapter
);
5033 e_dev_err("Unable to allocate memory for queue vectors\n");
5034 goto err_alloc_q_vectors
;
5037 err
= ixgbe_alloc_queues(adapter
);
5039 e_dev_err("Unable to allocate memory for queues\n");
5040 goto err_alloc_queues
;
5043 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
5044 (adapter
->num_rx_queues
> 1) ? "Enabled" : "Disabled",
5045 adapter
->num_rx_queues
, adapter
->num_tx_queues
);
5047 set_bit(__IXGBE_DOWN
, &adapter
->state
);
5052 ixgbe_free_q_vectors(adapter
);
5053 err_alloc_q_vectors
:
5054 ixgbe_reset_interrupt_capability(adapter
);
5060 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5061 * @adapter: board private structure to clear interrupt scheme on
5063 * We go through and clear interrupt specific resources and reset the structure
5064 * to pre-load conditions
5066 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
)
5070 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5071 kfree(adapter
->tx_ring
[i
]);
5072 adapter
->tx_ring
[i
] = NULL
;
5074 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5075 struct ixgbe_ring
*ring
= adapter
->rx_ring
[i
];
5077 /* ixgbe_get_stats64() might access this ring, we must wait
5078 * a grace period before freeing it.
5080 kfree_rcu(ring
, rcu
);
5081 adapter
->rx_ring
[i
] = NULL
;
5084 adapter
->num_tx_queues
= 0;
5085 adapter
->num_rx_queues
= 0;
5087 ixgbe_free_q_vectors(adapter
);
5088 ixgbe_reset_interrupt_capability(adapter
);
5092 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5093 * @adapter: board private structure to initialize
5095 * ixgbe_sw_init initializes the Adapter private data structure.
5096 * Fields are initialized based on PCI device information and
5097 * OS network device settings (MTU size).
5099 static int __devinit
ixgbe_sw_init(struct ixgbe_adapter
*adapter
)
5101 struct ixgbe_hw
*hw
= &adapter
->hw
;
5102 struct pci_dev
*pdev
= adapter
->pdev
;
5103 struct net_device
*dev
= adapter
->netdev
;
5105 #ifdef CONFIG_IXGBE_DCB
5107 struct tc_configuration
*tc
;
5109 int max_frame
= dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
5111 /* PCI config space info */
5113 hw
->vendor_id
= pdev
->vendor
;
5114 hw
->device_id
= pdev
->device
;
5115 hw
->revision_id
= pdev
->revision
;
5116 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
5117 hw
->subsystem_device_id
= pdev
->subsystem_device
;
5119 /* Set capability flags */
5120 rss
= min(IXGBE_MAX_RSS_INDICES
, (int)num_online_cpus());
5121 adapter
->ring_feature
[RING_F_RSS
].indices
= rss
;
5122 adapter
->flags
|= IXGBE_FLAG_RSS_ENABLED
;
5123 switch (hw
->mac
.type
) {
5124 case ixgbe_mac_82598EB
:
5125 if (hw
->device_id
== IXGBE_DEV_ID_82598AT
)
5126 adapter
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
5127 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82598
;
5129 case ixgbe_mac_82599EB
:
5130 case ixgbe_mac_X540
:
5131 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82599
;
5132 adapter
->flags2
|= IXGBE_FLAG2_RSC_CAPABLE
;
5133 adapter
->flags2
|= IXGBE_FLAG2_RSC_ENABLED
;
5134 if (hw
->device_id
== IXGBE_DEV_ID_82599_T3_LOM
)
5135 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
;
5136 /* n-tuple support exists, always init our spinlock */
5137 spin_lock_init(&adapter
->fdir_perfect_lock
);
5138 /* Flow Director hash filters enabled */
5139 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
5140 adapter
->atr_sample_rate
= 20;
5141 adapter
->ring_feature
[RING_F_FDIR
].indices
=
5142 IXGBE_MAX_FDIR_INDICES
;
5143 adapter
->fdir_pballoc
= 0;
5145 adapter
->flags
|= IXGBE_FLAG_FCOE_CAPABLE
;
5146 adapter
->flags
&= ~IXGBE_FLAG_FCOE_ENABLED
;
5147 adapter
->ring_feature
[RING_F_FCOE
].indices
= 0;
5148 #ifdef CONFIG_IXGBE_DCB
5149 /* Default traffic class to use for FCoE */
5150 adapter
->fcoe
.tc
= IXGBE_FCOE_DEFTC
;
5151 adapter
->fcoe
.up
= IXGBE_FCOE_DEFTC
;
5153 #endif /* IXGBE_FCOE */
5159 #ifdef CONFIG_IXGBE_DCB
5160 /* Configure DCB traffic classes */
5161 for (j
= 0; j
< MAX_TRAFFIC_CLASS
; j
++) {
5162 tc
= &adapter
->dcb_cfg
.tc_config
[j
];
5163 tc
->path
[DCB_TX_CONFIG
].bwg_id
= 0;
5164 tc
->path
[DCB_TX_CONFIG
].bwg_percent
= 12 + (j
& 1);
5165 tc
->path
[DCB_RX_CONFIG
].bwg_id
= 0;
5166 tc
->path
[DCB_RX_CONFIG
].bwg_percent
= 12 + (j
& 1);
5167 tc
->dcb_pfc
= pfc_disabled
;
5169 adapter
->dcb_cfg
.bw_percentage
[DCB_TX_CONFIG
][0] = 100;
5170 adapter
->dcb_cfg
.bw_percentage
[DCB_RX_CONFIG
][0] = 100;
5171 adapter
->dcb_cfg
.pfc_mode_enable
= false;
5172 adapter
->dcb_set_bitmap
= 0x00;
5173 adapter
->dcbx_cap
= DCB_CAP_DCBX_HOST
| DCB_CAP_DCBX_VER_CEE
;
5174 ixgbe_copy_dcb_cfg(&adapter
->dcb_cfg
, &adapter
->temp_dcb_cfg
,
5179 /* default flow control settings */
5180 hw
->fc
.requested_mode
= ixgbe_fc_full
;
5181 hw
->fc
.current_mode
= ixgbe_fc_full
; /* init for ethtool output */
5183 adapter
->last_lfc_mode
= hw
->fc
.current_mode
;
5185 hw
->fc
.high_water
= FC_HIGH_WATER(max_frame
);
5186 hw
->fc
.low_water
= FC_LOW_WATER(max_frame
);
5187 hw
->fc
.pause_time
= IXGBE_DEFAULT_FCPAUSE
;
5188 hw
->fc
.send_xon
= true;
5189 hw
->fc
.disable_fc_autoneg
= false;
5191 /* enable itr by default in dynamic mode */
5192 adapter
->rx_itr_setting
= 1;
5193 adapter
->rx_eitr_param
= 20000;
5194 adapter
->tx_itr_setting
= 1;
5195 adapter
->tx_eitr_param
= 10000;
5197 /* set defaults for eitr in MegaBytes */
5198 adapter
->eitr_low
= 10;
5199 adapter
->eitr_high
= 20;
5201 /* set default ring sizes */
5202 adapter
->tx_ring_count
= IXGBE_DEFAULT_TXD
;
5203 adapter
->rx_ring_count
= IXGBE_DEFAULT_RXD
;
5205 /* initialize eeprom parameters */
5206 if (ixgbe_init_eeprom_params_generic(hw
)) {
5207 e_dev_err("EEPROM initialization failed\n");
5211 /* enable rx csum by default */
5212 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
5214 /* get assigned NUMA node */
5215 adapter
->node
= dev_to_node(&pdev
->dev
);
5217 set_bit(__IXGBE_DOWN
, &adapter
->state
);
5223 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5224 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5226 * Return 0 on success, negative on failure
5228 int ixgbe_setup_tx_resources(struct ixgbe_ring
*tx_ring
)
5230 struct device
*dev
= tx_ring
->dev
;
5233 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
5234 tx_ring
->tx_buffer_info
= vzalloc_node(size
, tx_ring
->numa_node
);
5235 if (!tx_ring
->tx_buffer_info
)
5236 tx_ring
->tx_buffer_info
= vzalloc(size
);
5237 if (!tx_ring
->tx_buffer_info
)
5240 /* round up to nearest 4K */
5241 tx_ring
->size
= tx_ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
5242 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
5244 tx_ring
->desc
= dma_alloc_coherent(dev
, tx_ring
->size
,
5245 &tx_ring
->dma
, GFP_KERNEL
);
5249 tx_ring
->next_to_use
= 0;
5250 tx_ring
->next_to_clean
= 0;
5251 tx_ring
->work_limit
= tx_ring
->count
;
5255 vfree(tx_ring
->tx_buffer_info
);
5256 tx_ring
->tx_buffer_info
= NULL
;
5257 dev_err(dev
, "Unable to allocate memory for the Tx descriptor ring\n");
5262 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5263 * @adapter: board private structure
5265 * If this function returns with an error, then it's possible one or
5266 * more of the rings is populated (while the rest are not). It is the
5267 * callers duty to clean those orphaned rings.
5269 * Return 0 on success, negative on failure
5271 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter
*adapter
)
5275 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5276 err
= ixgbe_setup_tx_resources(adapter
->tx_ring
[i
]);
5279 e_err(probe
, "Allocation for Tx Queue %u failed\n", i
);
5287 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5288 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5290 * Returns 0 on success, negative on failure
5292 int ixgbe_setup_rx_resources(struct ixgbe_ring
*rx_ring
)
5294 struct device
*dev
= rx_ring
->dev
;
5297 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
5298 rx_ring
->rx_buffer_info
= vzalloc_node(size
, rx_ring
->numa_node
);
5299 if (!rx_ring
->rx_buffer_info
)
5300 rx_ring
->rx_buffer_info
= vzalloc(size
);
5301 if (!rx_ring
->rx_buffer_info
)
5304 /* Round up to nearest 4K */
5305 rx_ring
->size
= rx_ring
->count
* sizeof(union ixgbe_adv_rx_desc
);
5306 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
5308 rx_ring
->desc
= dma_alloc_coherent(dev
, rx_ring
->size
,
5309 &rx_ring
->dma
, GFP_KERNEL
);
5314 rx_ring
->next_to_clean
= 0;
5315 rx_ring
->next_to_use
= 0;
5319 vfree(rx_ring
->rx_buffer_info
);
5320 rx_ring
->rx_buffer_info
= NULL
;
5321 dev_err(dev
, "Unable to allocate memory for the Rx descriptor ring\n");
5326 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5327 * @adapter: board private structure
5329 * If this function returns with an error, then it's possible one or
5330 * more of the rings is populated (while the rest are not). It is the
5331 * callers duty to clean those orphaned rings.
5333 * Return 0 on success, negative on failure
5335 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter
*adapter
)
5339 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5340 err
= ixgbe_setup_rx_resources(adapter
->rx_ring
[i
]);
5343 e_err(probe
, "Allocation for Rx Queue %u failed\n", i
);
5351 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5352 * @tx_ring: Tx descriptor ring for a specific queue
5354 * Free all transmit software resources
5356 void ixgbe_free_tx_resources(struct ixgbe_ring
*tx_ring
)
5358 ixgbe_clean_tx_ring(tx_ring
);
5360 vfree(tx_ring
->tx_buffer_info
);
5361 tx_ring
->tx_buffer_info
= NULL
;
5363 /* if not set, then don't free */
5367 dma_free_coherent(tx_ring
->dev
, tx_ring
->size
,
5368 tx_ring
->desc
, tx_ring
->dma
);
5370 tx_ring
->desc
= NULL
;
5374 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5375 * @adapter: board private structure
5377 * Free all transmit software resources
5379 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter
*adapter
)
5383 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5384 if (adapter
->tx_ring
[i
]->desc
)
5385 ixgbe_free_tx_resources(adapter
->tx_ring
[i
]);
5389 * ixgbe_free_rx_resources - Free Rx Resources
5390 * @rx_ring: ring to clean the resources from
5392 * Free all receive software resources
5394 void ixgbe_free_rx_resources(struct ixgbe_ring
*rx_ring
)
5396 ixgbe_clean_rx_ring(rx_ring
);
5398 vfree(rx_ring
->rx_buffer_info
);
5399 rx_ring
->rx_buffer_info
= NULL
;
5401 /* if not set, then don't free */
5405 dma_free_coherent(rx_ring
->dev
, rx_ring
->size
,
5406 rx_ring
->desc
, rx_ring
->dma
);
5408 rx_ring
->desc
= NULL
;
5412 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5413 * @adapter: board private structure
5415 * Free all receive software resources
5417 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter
*adapter
)
5421 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
5422 if (adapter
->rx_ring
[i
]->desc
)
5423 ixgbe_free_rx_resources(adapter
->rx_ring
[i
]);
5427 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5428 * @netdev: network interface device structure
5429 * @new_mtu: new value for maximum frame size
5431 * Returns 0 on success, negative on failure
5433 static int ixgbe_change_mtu(struct net_device
*netdev
, int new_mtu
)
5435 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5436 struct ixgbe_hw
*hw
= &adapter
->hw
;
5437 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
5439 /* MTU < 68 is an error and causes problems on some kernels */
5440 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
&&
5441 hw
->mac
.type
!= ixgbe_mac_X540
) {
5442 if ((new_mtu
< 68) || (max_frame
> MAXIMUM_ETHERNET_VLAN_SIZE
))
5445 if ((new_mtu
< 68) || (max_frame
> IXGBE_MAX_JUMBO_FRAME_SIZE
))
5449 e_info(probe
, "changing MTU from %d to %d\n", netdev
->mtu
, new_mtu
);
5450 /* must set new MTU before calling down or up */
5451 netdev
->mtu
= new_mtu
;
5453 hw
->fc
.high_water
= FC_HIGH_WATER(max_frame
);
5454 hw
->fc
.low_water
= FC_LOW_WATER(max_frame
);
5456 if (netif_running(netdev
))
5457 ixgbe_reinit_locked(adapter
);
5463 * ixgbe_open - Called when a network interface is made active
5464 * @netdev: network interface device structure
5466 * Returns 0 on success, negative value on failure
5468 * The open entry point is called when a network interface is made
5469 * active by the system (IFF_UP). At this point all resources needed
5470 * for transmit and receive operations are allocated, the interrupt
5471 * handler is registered with the OS, the watchdog timer is started,
5472 * and the stack is notified that the interface is ready.
5474 static int ixgbe_open(struct net_device
*netdev
)
5476 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5479 /* disallow open during test */
5480 if (test_bit(__IXGBE_TESTING
, &adapter
->state
))
5483 netif_carrier_off(netdev
);
5485 /* allocate transmit descriptors */
5486 err
= ixgbe_setup_all_tx_resources(adapter
);
5490 /* allocate receive descriptors */
5491 err
= ixgbe_setup_all_rx_resources(adapter
);
5495 ixgbe_configure(adapter
);
5497 err
= ixgbe_request_irq(adapter
);
5501 err
= ixgbe_up_complete(adapter
);
5505 netif_tx_start_all_queues(netdev
);
5510 ixgbe_release_hw_control(adapter
);
5511 ixgbe_free_irq(adapter
);
5514 ixgbe_free_all_rx_resources(adapter
);
5516 ixgbe_free_all_tx_resources(adapter
);
5517 ixgbe_reset(adapter
);
5523 * ixgbe_close - Disables a network interface
5524 * @netdev: network interface device structure
5526 * Returns 0, this is not allowed to fail
5528 * The close entry point is called when an interface is de-activated
5529 * by the OS. The hardware is still under the drivers control, but
5530 * needs to be disabled. A global MAC reset is issued to stop the
5531 * hardware, and all transmit and receive resources are freed.
5533 static int ixgbe_close(struct net_device
*netdev
)
5535 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5537 ixgbe_down(adapter
);
5538 ixgbe_free_irq(adapter
);
5540 ixgbe_free_all_tx_resources(adapter
);
5541 ixgbe_free_all_rx_resources(adapter
);
5543 ixgbe_release_hw_control(adapter
);
5549 static int ixgbe_resume(struct pci_dev
*pdev
)
5551 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
5552 struct net_device
*netdev
= adapter
->netdev
;
5555 pci_set_power_state(pdev
, PCI_D0
);
5556 pci_restore_state(pdev
);
5558 * pci_restore_state clears dev->state_saved so call
5559 * pci_save_state to restore it.
5561 pci_save_state(pdev
);
5563 err
= pci_enable_device_mem(pdev
);
5565 e_dev_err("Cannot enable PCI device from suspend\n");
5568 pci_set_master(pdev
);
5570 pci_wake_from_d3(pdev
, false);
5572 err
= ixgbe_init_interrupt_scheme(adapter
);
5574 e_dev_err("Cannot initialize interrupts for device\n");
5578 ixgbe_reset(adapter
);
5580 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
5582 if (netif_running(netdev
)) {
5583 err
= ixgbe_open(netdev
);
5588 netif_device_attach(netdev
);
5592 #endif /* CONFIG_PM */
5594 static int __ixgbe_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
5596 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
5597 struct net_device
*netdev
= adapter
->netdev
;
5598 struct ixgbe_hw
*hw
= &adapter
->hw
;
5600 u32 wufc
= adapter
->wol
;
5605 netif_device_detach(netdev
);
5607 if (netif_running(netdev
)) {
5608 ixgbe_down(adapter
);
5609 ixgbe_free_irq(adapter
);
5610 ixgbe_free_all_tx_resources(adapter
);
5611 ixgbe_free_all_rx_resources(adapter
);
5614 ixgbe_clear_interrupt_scheme(adapter
);
5616 kfree(adapter
->ixgbe_ieee_pfc
);
5617 kfree(adapter
->ixgbe_ieee_ets
);
5621 retval
= pci_save_state(pdev
);
5627 ixgbe_set_rx_mode(netdev
);
5629 /* turn on all-multi mode if wake on multicast is enabled */
5630 if (wufc
& IXGBE_WUFC_MC
) {
5631 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5632 fctrl
|= IXGBE_FCTRL_MPE
;
5633 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
5636 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
5637 ctrl
|= IXGBE_CTRL_GIO_DIS
;
5638 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
5640 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, wufc
);
5642 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
5643 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, 0);
5646 switch (hw
->mac
.type
) {
5647 case ixgbe_mac_82598EB
:
5648 pci_wake_from_d3(pdev
, false);
5650 case ixgbe_mac_82599EB
:
5651 case ixgbe_mac_X540
:
5652 pci_wake_from_d3(pdev
, !!wufc
);
5658 *enable_wake
= !!wufc
;
5660 ixgbe_release_hw_control(adapter
);
5662 pci_disable_device(pdev
);
5668 static int ixgbe_suspend(struct pci_dev
*pdev
, pm_message_t state
)
5673 retval
= __ixgbe_shutdown(pdev
, &wake
);
5678 pci_prepare_to_sleep(pdev
);
5680 pci_wake_from_d3(pdev
, false);
5681 pci_set_power_state(pdev
, PCI_D3hot
);
5686 #endif /* CONFIG_PM */
5688 static void ixgbe_shutdown(struct pci_dev
*pdev
)
5692 __ixgbe_shutdown(pdev
, &wake
);
5694 if (system_state
== SYSTEM_POWER_OFF
) {
5695 pci_wake_from_d3(pdev
, wake
);
5696 pci_set_power_state(pdev
, PCI_D3hot
);
5701 * ixgbe_update_stats - Update the board statistics counters.
5702 * @adapter: board private structure
5704 void ixgbe_update_stats(struct ixgbe_adapter
*adapter
)
5706 struct net_device
*netdev
= adapter
->netdev
;
5707 struct ixgbe_hw
*hw
= &adapter
->hw
;
5708 struct ixgbe_hw_stats
*hwstats
= &adapter
->stats
;
5710 u32 i
, missed_rx
= 0, mpc
, bprc
, lxon
, lxoff
, xon_off_tot
;
5711 u64 non_eop_descs
= 0, restart_queue
= 0, tx_busy
= 0;
5712 u64 alloc_rx_page_failed
= 0, alloc_rx_buff_failed
= 0;
5713 u64 bytes
= 0, packets
= 0;
5715 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
5716 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
5719 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
5722 for (i
= 0; i
< 16; i
++)
5723 adapter
->hw_rx_no_dma_resources
+=
5724 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
5725 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5726 rsc_count
+= adapter
->rx_ring
[i
]->rx_stats
.rsc_count
;
5727 rsc_flush
+= adapter
->rx_ring
[i
]->rx_stats
.rsc_flush
;
5729 adapter
->rsc_total_count
= rsc_count
;
5730 adapter
->rsc_total_flush
= rsc_flush
;
5733 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5734 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[i
];
5735 non_eop_descs
+= rx_ring
->rx_stats
.non_eop_descs
;
5736 alloc_rx_page_failed
+= rx_ring
->rx_stats
.alloc_rx_page_failed
;
5737 alloc_rx_buff_failed
+= rx_ring
->rx_stats
.alloc_rx_buff_failed
;
5738 bytes
+= rx_ring
->stats
.bytes
;
5739 packets
+= rx_ring
->stats
.packets
;
5741 adapter
->non_eop_descs
= non_eop_descs
;
5742 adapter
->alloc_rx_page_failed
= alloc_rx_page_failed
;
5743 adapter
->alloc_rx_buff_failed
= alloc_rx_buff_failed
;
5744 netdev
->stats
.rx_bytes
= bytes
;
5745 netdev
->stats
.rx_packets
= packets
;
5749 /* gather some stats to the adapter struct that are per queue */
5750 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5751 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[i
];
5752 restart_queue
+= tx_ring
->tx_stats
.restart_queue
;
5753 tx_busy
+= tx_ring
->tx_stats
.tx_busy
;
5754 bytes
+= tx_ring
->stats
.bytes
;
5755 packets
+= tx_ring
->stats
.packets
;
5757 adapter
->restart_queue
= restart_queue
;
5758 adapter
->tx_busy
= tx_busy
;
5759 netdev
->stats
.tx_bytes
= bytes
;
5760 netdev
->stats
.tx_packets
= packets
;
5762 hwstats
->crcerrs
+= IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
5763 for (i
= 0; i
< 8; i
++) {
5764 /* for packet buffers not used, the register should read 0 */
5765 mpc
= IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
5767 hwstats
->mpc
[i
] += mpc
;
5768 total_mpc
+= hwstats
->mpc
[i
];
5769 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5770 hwstats
->rnbc
[i
] += IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
5771 hwstats
->qptc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
5772 hwstats
->qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
5773 hwstats
->qprc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
5774 hwstats
->qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
5775 switch (hw
->mac
.type
) {
5776 case ixgbe_mac_82598EB
:
5777 hwstats
->pxonrxc
[i
] +=
5778 IXGBE_READ_REG(hw
, IXGBE_PXONRXC(i
));
5780 case ixgbe_mac_82599EB
:
5781 case ixgbe_mac_X540
:
5782 hwstats
->pxonrxc
[i
] +=
5783 IXGBE_READ_REG(hw
, IXGBE_PXONRXCNT(i
));
5788 hwstats
->pxontxc
[i
] += IXGBE_READ_REG(hw
, IXGBE_PXONTXC(i
));
5789 hwstats
->pxofftxc
[i
] += IXGBE_READ_REG(hw
, IXGBE_PXOFFTXC(i
));
5791 hwstats
->gprc
+= IXGBE_READ_REG(hw
, IXGBE_GPRC
);
5792 /* work around hardware counting issue */
5793 hwstats
->gprc
-= missed_rx
;
5795 ixgbe_update_xoff_received(adapter
);
5797 /* 82598 hardware only has a 32 bit counter in the high register */
5798 switch (hw
->mac
.type
) {
5799 case ixgbe_mac_82598EB
:
5800 hwstats
->lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
5801 hwstats
->gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCH
);
5802 hwstats
->gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
5803 hwstats
->tor
+= IXGBE_READ_REG(hw
, IXGBE_TORH
);
5805 case ixgbe_mac_X540
:
5806 /* OS2BMC stats are X540 only*/
5807 hwstats
->o2bgptc
+= IXGBE_READ_REG(hw
, IXGBE_O2BGPTC
);
5808 hwstats
->o2bspc
+= IXGBE_READ_REG(hw
, IXGBE_O2BSPC
);
5809 hwstats
->b2ospc
+= IXGBE_READ_REG(hw
, IXGBE_B2OSPC
);
5810 hwstats
->b2ogprc
+= IXGBE_READ_REG(hw
, IXGBE_B2OGPRC
);
5811 case ixgbe_mac_82599EB
:
5812 hwstats
->gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCL
);
5813 IXGBE_READ_REG(hw
, IXGBE_GORCH
); /* to clear */
5814 hwstats
->gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
5815 IXGBE_READ_REG(hw
, IXGBE_GOTCH
); /* to clear */
5816 hwstats
->tor
+= IXGBE_READ_REG(hw
, IXGBE_TORL
);
5817 IXGBE_READ_REG(hw
, IXGBE_TORH
); /* to clear */
5818 hwstats
->lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
5819 hwstats
->fdirmatch
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
5820 hwstats
->fdirmiss
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
5822 hwstats
->fccrc
+= IXGBE_READ_REG(hw
, IXGBE_FCCRC
);
5823 hwstats
->fcoerpdc
+= IXGBE_READ_REG(hw
, IXGBE_FCOERPDC
);
5824 hwstats
->fcoeprc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPRC
);
5825 hwstats
->fcoeptc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPTC
);
5826 hwstats
->fcoedwrc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWRC
);
5827 hwstats
->fcoedwtc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWTC
);
5828 #endif /* IXGBE_FCOE */
5833 bprc
= IXGBE_READ_REG(hw
, IXGBE_BPRC
);
5834 hwstats
->bprc
+= bprc
;
5835 hwstats
->mprc
+= IXGBE_READ_REG(hw
, IXGBE_MPRC
);
5836 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5837 hwstats
->mprc
-= bprc
;
5838 hwstats
->roc
+= IXGBE_READ_REG(hw
, IXGBE_ROC
);
5839 hwstats
->prc64
+= IXGBE_READ_REG(hw
, IXGBE_PRC64
);
5840 hwstats
->prc127
+= IXGBE_READ_REG(hw
, IXGBE_PRC127
);
5841 hwstats
->prc255
+= IXGBE_READ_REG(hw
, IXGBE_PRC255
);
5842 hwstats
->prc511
+= IXGBE_READ_REG(hw
, IXGBE_PRC511
);
5843 hwstats
->prc1023
+= IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
5844 hwstats
->prc1522
+= IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
5845 hwstats
->rlec
+= IXGBE_READ_REG(hw
, IXGBE_RLEC
);
5846 lxon
= IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
5847 hwstats
->lxontxc
+= lxon
;
5848 lxoff
= IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
5849 hwstats
->lxofftxc
+= lxoff
;
5850 hwstats
->ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5851 hwstats
->gptc
+= IXGBE_READ_REG(hw
, IXGBE_GPTC
);
5852 hwstats
->mptc
+= IXGBE_READ_REG(hw
, IXGBE_MPTC
);
5854 * 82598 errata - tx of flow control packets is included in tx counters
5856 xon_off_tot
= lxon
+ lxoff
;
5857 hwstats
->gptc
-= xon_off_tot
;
5858 hwstats
->mptc
-= xon_off_tot
;
5859 hwstats
->gotc
-= (xon_off_tot
* (ETH_ZLEN
+ ETH_FCS_LEN
));
5860 hwstats
->ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5861 hwstats
->rfc
+= IXGBE_READ_REG(hw
, IXGBE_RFC
);
5862 hwstats
->rjc
+= IXGBE_READ_REG(hw
, IXGBE_RJC
);
5863 hwstats
->tpr
+= IXGBE_READ_REG(hw
, IXGBE_TPR
);
5864 hwstats
->ptc64
+= IXGBE_READ_REG(hw
, IXGBE_PTC64
);
5865 hwstats
->ptc64
-= xon_off_tot
;
5866 hwstats
->ptc127
+= IXGBE_READ_REG(hw
, IXGBE_PTC127
);
5867 hwstats
->ptc255
+= IXGBE_READ_REG(hw
, IXGBE_PTC255
);
5868 hwstats
->ptc511
+= IXGBE_READ_REG(hw
, IXGBE_PTC511
);
5869 hwstats
->ptc1023
+= IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
5870 hwstats
->ptc1522
+= IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
5871 hwstats
->bptc
+= IXGBE_READ_REG(hw
, IXGBE_BPTC
);
5873 /* Fill out the OS statistics structure */
5874 netdev
->stats
.multicast
= hwstats
->mprc
;
5877 netdev
->stats
.rx_errors
= hwstats
->crcerrs
+ hwstats
->rlec
;
5878 netdev
->stats
.rx_dropped
= 0;
5879 netdev
->stats
.rx_length_errors
= hwstats
->rlec
;
5880 netdev
->stats
.rx_crc_errors
= hwstats
->crcerrs
;
5881 netdev
->stats
.rx_missed_errors
= total_mpc
;
5885 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5886 * @adapter - pointer to the device adapter structure
5888 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter
*adapter
)
5890 struct ixgbe_hw
*hw
= &adapter
->hw
;
5893 if (!(adapter
->flags2
& IXGBE_FLAG2_FDIR_REQUIRES_REINIT
))
5896 adapter
->flags2
&= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT
;
5898 /* if interface is down do nothing */
5899 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
5902 /* do nothing if we are not using signature filters */
5903 if (!(adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
))
5906 adapter
->fdir_overflow
++;
5908 if (ixgbe_reinit_fdir_tables_82599(hw
) == 0) {
5909 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5910 set_bit(__IXGBE_TX_FDIR_INIT_DONE
,
5911 &(adapter
->tx_ring
[i
]->state
));
5912 /* re-enable flow director interrupts */
5913 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMS_FLOW_DIR
);
5915 e_err(probe
, "failed to finish FDIR re-initialization, "
5916 "ignored adding FDIR ATR filters\n");
5921 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5922 * @adapter - pointer to the device adapter structure
5924 * This function serves two purposes. First it strobes the interrupt lines
5925 * in order to make certain interrupts are occuring. Secondly it sets the
5926 * bits needed to check for TX hangs. As a result we should immediately
5927 * determine if a hang has occured.
5929 static void ixgbe_check_hang_subtask(struct ixgbe_adapter
*adapter
)
5931 struct ixgbe_hw
*hw
= &adapter
->hw
;
5935 /* If we're down or resetting, just bail */
5936 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
5937 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
5940 /* Force detection of hung controller */
5941 if (netif_carrier_ok(adapter
->netdev
)) {
5942 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5943 set_check_for_tx_hang(adapter
->tx_ring
[i
]);
5946 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
5948 * for legacy and MSI interrupts don't set any bits
5949 * that are enabled for EIAM, because this operation
5950 * would set *both* EIMS and EICS for any bit in EIAM
5952 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
5953 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
5955 /* get one bit for every active tx/rx interrupt vector */
5956 for (i
= 0; i
< adapter
->num_msix_vectors
- NON_Q_VECTORS
; i
++) {
5957 struct ixgbe_q_vector
*qv
= adapter
->q_vector
[i
];
5958 if (qv
->rxr_count
|| qv
->txr_count
)
5959 eics
|= ((u64
)1 << i
);
5963 /* Cause software interrupt to ensure rings are cleaned */
5964 ixgbe_irq_rearm_queues(adapter
, eics
);
5969 * ixgbe_watchdog_update_link - update the link status
5970 * @adapter - pointer to the device adapter structure
5971 * @link_speed - pointer to a u32 to store the link_speed
5973 static void ixgbe_watchdog_update_link(struct ixgbe_adapter
*adapter
)
5975 struct ixgbe_hw
*hw
= &adapter
->hw
;
5976 u32 link_speed
= adapter
->link_speed
;
5977 bool link_up
= adapter
->link_up
;
5980 if (!(adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
))
5983 if (hw
->mac
.ops
.check_link
) {
5984 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
5986 /* always assume link is up, if no check link function */
5987 link_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
5991 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5992 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++)
5993 hw
->mac
.ops
.fc_enable(hw
, i
);
5995 hw
->mac
.ops
.fc_enable(hw
, 0);
6000 time_after(jiffies
, (adapter
->link_check_timeout
+
6001 IXGBE_TRY_LINK_TIMEOUT
))) {
6002 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
6003 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMC_LSC
);
6004 IXGBE_WRITE_FLUSH(hw
);
6007 adapter
->link_up
= link_up
;
6008 adapter
->link_speed
= link_speed
;
6012 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6013 * print link up message
6014 * @adapter - pointer to the device adapter structure
6016 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter
*adapter
)
6018 struct net_device
*netdev
= adapter
->netdev
;
6019 struct ixgbe_hw
*hw
= &adapter
->hw
;
6020 u32 link_speed
= adapter
->link_speed
;
6021 bool flow_rx
, flow_tx
;
6023 /* only continue if link was previously down */
6024 if (netif_carrier_ok(netdev
))
6027 adapter
->flags2
&= ~IXGBE_FLAG2_SEARCH_FOR_SFP
;
6029 switch (hw
->mac
.type
) {
6030 case ixgbe_mac_82598EB
: {
6031 u32 frctl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
6032 u32 rmcs
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
6033 flow_rx
= !!(frctl
& IXGBE_FCTRL_RFCE
);
6034 flow_tx
= !!(rmcs
& IXGBE_RMCS_TFCE_802_3X
);
6037 case ixgbe_mac_X540
:
6038 case ixgbe_mac_82599EB
: {
6039 u32 mflcn
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
6040 u32 fccfg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
6041 flow_rx
= !!(mflcn
& IXGBE_MFLCN_RFCE
);
6042 flow_tx
= !!(fccfg
& IXGBE_FCCFG_TFCE_802_3X
);
6050 e_info(drv
, "NIC Link is Up %s, Flow Control: %s\n",
6051 (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
?
6053 (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
?
6055 (link_speed
== IXGBE_LINK_SPEED_100_FULL
?
6058 ((flow_rx
&& flow_tx
) ? "RX/TX" :
6060 (flow_tx
? "TX" : "None"))));
6062 netif_carrier_on(netdev
);
6063 #ifdef HAVE_IPLINK_VF_CONFIG
6064 ixgbe_check_vf_rate_limit(adapter
);
6065 #endif /* HAVE_IPLINK_VF_CONFIG */
6069 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6070 * print link down message
6071 * @adapter - pointer to the adapter structure
6073 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter
* adapter
)
6075 struct net_device
*netdev
= adapter
->netdev
;
6076 struct ixgbe_hw
*hw
= &adapter
->hw
;
6078 adapter
->link_up
= false;
6079 adapter
->link_speed
= 0;
6081 /* only continue if link was up previously */
6082 if (!netif_carrier_ok(netdev
))
6085 /* poll for SFP+ cable when link is down */
6086 if (ixgbe_is_sfp(hw
) && hw
->mac
.type
== ixgbe_mac_82598EB
)
6087 adapter
->flags2
|= IXGBE_FLAG2_SEARCH_FOR_SFP
;
6089 e_info(drv
, "NIC Link is Down\n");
6090 netif_carrier_off(netdev
);
6094 * ixgbe_watchdog_flush_tx - flush queues on link down
6095 * @adapter - pointer to the device adapter structure
6097 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter
*adapter
)
6100 int some_tx_pending
= 0;
6102 if (!netif_carrier_ok(adapter
->netdev
)) {
6103 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
6104 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[i
];
6105 if (tx_ring
->next_to_use
!= tx_ring
->next_to_clean
) {
6106 some_tx_pending
= 1;
6111 if (some_tx_pending
) {
6112 /* We've lost link, so the controller stops DMA,
6113 * but we've got queued Tx work that's never going
6114 * to get done, so reset controller to flush Tx.
6115 * (Do the reset outside of interrupt context).
6117 adapter
->flags2
|= IXGBE_FLAG2_RESET_REQUESTED
;
6122 static void ixgbe_spoof_check(struct ixgbe_adapter
*adapter
)
6126 /* Do not perform spoof check for 82598 */
6127 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
6130 ssvpc
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SSVPC
);
6133 * ssvpc register is cleared on read, if zero then no
6134 * spoofed packets in the last interval.
6139 e_warn(drv
, "%d Spoofed packets detected\n", ssvpc
);
6143 * ixgbe_watchdog_subtask - check and bring link up
6144 * @adapter - pointer to the device adapter structure
6146 static void ixgbe_watchdog_subtask(struct ixgbe_adapter
*adapter
)
6148 /* if interface is down do nothing */
6149 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
6152 ixgbe_watchdog_update_link(adapter
);
6154 if (adapter
->link_up
)
6155 ixgbe_watchdog_link_is_up(adapter
);
6157 ixgbe_watchdog_link_is_down(adapter
);
6159 ixgbe_spoof_check(adapter
);
6160 ixgbe_update_stats(adapter
);
6162 ixgbe_watchdog_flush_tx(adapter
);
6166 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6167 * @adapter - the ixgbe adapter structure
6169 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter
*adapter
)
6171 struct ixgbe_hw
*hw
= &adapter
->hw
;
6174 /* not searching for SFP so there is nothing to do here */
6175 if (!(adapter
->flags2
& IXGBE_FLAG2_SEARCH_FOR_SFP
) &&
6176 !(adapter
->flags2
& IXGBE_FLAG2_SFP_NEEDS_RESET
))
6179 /* someone else is in init, wait until next service event */
6180 if (test_and_set_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
))
6183 err
= hw
->phy
.ops
.identify_sfp(hw
);
6184 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
6187 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
) {
6188 /* If no cable is present, then we need to reset
6189 * the next time we find a good cable. */
6190 adapter
->flags2
|= IXGBE_FLAG2_SFP_NEEDS_RESET
;
6197 /* exit if reset not needed */
6198 if (!(adapter
->flags2
& IXGBE_FLAG2_SFP_NEEDS_RESET
))
6201 adapter
->flags2
&= ~IXGBE_FLAG2_SFP_NEEDS_RESET
;
6204 * A module may be identified correctly, but the EEPROM may not have
6205 * support for that module. setup_sfp() will fail in that case, so
6206 * we should not allow that module to load.
6208 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
6209 err
= hw
->phy
.ops
.reset(hw
);
6211 err
= hw
->mac
.ops
.setup_sfp(hw
);
6213 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
6216 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_CONFIG
;
6217 e_info(probe
, "detected SFP+: %d\n", hw
->phy
.sfp_type
);
6220 clear_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
);
6222 if ((err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) &&
6223 (adapter
->netdev
->reg_state
== NETREG_REGISTERED
)) {
6224 e_dev_err("failed to initialize because an unsupported "
6225 "SFP+ module type was detected.\n");
6226 e_dev_err("Reload the driver after installing a "
6227 "supported module.\n");
6228 unregister_netdev(adapter
->netdev
);
6233 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6234 * @adapter - the ixgbe adapter structure
6236 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter
*adapter
)
6238 struct ixgbe_hw
*hw
= &adapter
->hw
;
6242 if (!(adapter
->flags
& IXGBE_FLAG_NEED_LINK_CONFIG
))
6245 /* someone else is in init, wait until next service event */
6246 if (test_and_set_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
))
6249 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_CONFIG
;
6251 autoneg
= hw
->phy
.autoneg_advertised
;
6252 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
6253 hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
6254 hw
->mac
.autotry_restart
= false;
6255 if (hw
->mac
.ops
.setup_link
)
6256 hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, true);
6258 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
6259 adapter
->link_check_timeout
= jiffies
;
6260 clear_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
);
6264 * ixgbe_service_timer - Timer Call-back
6265 * @data: pointer to adapter cast into an unsigned long
6267 static void ixgbe_service_timer(unsigned long data
)
6269 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
6270 unsigned long next_event_offset
;
6272 /* poll faster when waiting for link */
6273 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
)
6274 next_event_offset
= HZ
/ 10;
6276 next_event_offset
= HZ
* 2;
6278 /* Reset the timer */
6279 mod_timer(&adapter
->service_timer
, next_event_offset
+ jiffies
);
6281 ixgbe_service_event_schedule(adapter
);
6284 static void ixgbe_reset_subtask(struct ixgbe_adapter
*adapter
)
6286 if (!(adapter
->flags2
& IXGBE_FLAG2_RESET_REQUESTED
))
6289 adapter
->flags2
&= ~IXGBE_FLAG2_RESET_REQUESTED
;
6291 /* If we're already down or resetting, just bail */
6292 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
6293 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
6296 ixgbe_dump(adapter
);
6297 netdev_err(adapter
->netdev
, "Reset adapter\n");
6298 adapter
->tx_timeout_count
++;
6300 ixgbe_reinit_locked(adapter
);
6304 * ixgbe_service_task - manages and runs subtasks
6305 * @work: pointer to work_struct containing our data
6307 static void ixgbe_service_task(struct work_struct
*work
)
6309 struct ixgbe_adapter
*adapter
= container_of(work
,
6310 struct ixgbe_adapter
,
6313 ixgbe_reset_subtask(adapter
);
6314 ixgbe_sfp_detection_subtask(adapter
);
6315 ixgbe_sfp_link_config_subtask(adapter
);
6316 ixgbe_check_overtemp_subtask(adapter
);
6317 ixgbe_watchdog_subtask(adapter
);
6318 ixgbe_fdir_reinit_subtask(adapter
);
6319 ixgbe_check_hang_subtask(adapter
);
6321 ixgbe_service_event_complete(adapter
);
6324 static int ixgbe_tso(struct ixgbe_adapter
*adapter
,
6325 struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
6326 u32 tx_flags
, u8
*hdr_len
, __be16 protocol
)
6328 struct ixgbe_adv_tx_context_desc
*context_desc
;
6331 struct ixgbe_tx_buffer
*tx_buffer_info
;
6332 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
;
6333 u32 mss_l4len_idx
, l4len
;
6335 if (skb_is_gso(skb
)) {
6336 if (skb_header_cloned(skb
)) {
6337 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
6341 l4len
= tcp_hdrlen(skb
);
6344 if (protocol
== htons(ETH_P_IP
)) {
6345 struct iphdr
*iph
= ip_hdr(skb
);
6348 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
6352 } else if (skb_is_gso_v6(skb
)) {
6353 ipv6_hdr(skb
)->payload_len
= 0;
6354 tcp_hdr(skb
)->check
=
6355 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
6356 &ipv6_hdr(skb
)->daddr
,
6360 i
= tx_ring
->next_to_use
;
6362 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6363 context_desc
= IXGBE_TX_CTXTDESC_ADV(tx_ring
, i
);
6365 /* VLAN MACLEN IPLEN */
6366 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
6368 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
6369 vlan_macip_lens
|= ((skb_network_offset(skb
)) <<
6370 IXGBE_ADVTXD_MACLEN_SHIFT
);
6371 *hdr_len
+= skb_network_offset(skb
);
6373 (skb_transport_header(skb
) - skb_network_header(skb
));
6375 (skb_transport_header(skb
) - skb_network_header(skb
));
6376 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
6377 context_desc
->seqnum_seed
= 0;
6379 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6380 type_tucmd_mlhl
= (IXGBE_TXD_CMD_DEXT
|
6381 IXGBE_ADVTXD_DTYP_CTXT
);
6383 if (protocol
== htons(ETH_P_IP
))
6384 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
6385 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6386 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
6390 (skb_shinfo(skb
)->gso_size
<< IXGBE_ADVTXD_MSS_SHIFT
);
6391 mss_l4len_idx
|= (l4len
<< IXGBE_ADVTXD_L4LEN_SHIFT
);
6392 /* use index 1 for TSO */
6393 mss_l4len_idx
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6394 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
6396 tx_buffer_info
->time_stamp
= jiffies
;
6397 tx_buffer_info
->next_to_watch
= i
;
6400 if (i
== tx_ring
->count
)
6402 tx_ring
->next_to_use
= i
;
6409 static u32
ixgbe_psum(struct ixgbe_adapter
*adapter
, struct sk_buff
*skb
,
6415 case cpu_to_be16(ETH_P_IP
):
6416 rtn
|= IXGBE_ADVTXD_TUCMD_IPV4
;
6417 switch (ip_hdr(skb
)->protocol
) {
6419 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6422 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
6426 case cpu_to_be16(ETH_P_IPV6
):
6427 /* XXX what about other V6 headers?? */
6428 switch (ipv6_hdr(skb
)->nexthdr
) {
6430 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6433 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
6438 if (unlikely(net_ratelimit()))
6439 e_warn(probe
, "partial checksum but proto=%x!\n",
6447 static bool ixgbe_tx_csum(struct ixgbe_adapter
*adapter
,
6448 struct ixgbe_ring
*tx_ring
,
6449 struct sk_buff
*skb
, u32 tx_flags
,
6452 struct ixgbe_adv_tx_context_desc
*context_desc
;
6454 struct ixgbe_tx_buffer
*tx_buffer_info
;
6455 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
= 0;
6457 if (skb
->ip_summed
== CHECKSUM_PARTIAL
||
6458 (tx_flags
& IXGBE_TX_FLAGS_VLAN
)) {
6459 i
= tx_ring
->next_to_use
;
6460 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6461 context_desc
= IXGBE_TX_CTXTDESC_ADV(tx_ring
, i
);
6463 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
6465 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
6466 vlan_macip_lens
|= (skb_network_offset(skb
) <<
6467 IXGBE_ADVTXD_MACLEN_SHIFT
);
6468 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
6469 vlan_macip_lens
|= (skb_transport_header(skb
) -
6470 skb_network_header(skb
));
6472 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
6473 context_desc
->seqnum_seed
= 0;
6475 type_tucmd_mlhl
|= (IXGBE_TXD_CMD_DEXT
|
6476 IXGBE_ADVTXD_DTYP_CTXT
);
6478 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
6479 type_tucmd_mlhl
|= ixgbe_psum(adapter
, skb
, protocol
);
6481 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
6482 /* use index zero for tx checksum offload */
6483 context_desc
->mss_l4len_idx
= 0;
6485 tx_buffer_info
->time_stamp
= jiffies
;
6486 tx_buffer_info
->next_to_watch
= i
;
6489 if (i
== tx_ring
->count
)
6491 tx_ring
->next_to_use
= i
;
6499 static int ixgbe_tx_map(struct ixgbe_adapter
*adapter
,
6500 struct ixgbe_ring
*tx_ring
,
6501 struct sk_buff
*skb
, u32 tx_flags
,
6502 unsigned int first
, const u8 hdr_len
)
6504 struct device
*dev
= tx_ring
->dev
;
6505 struct ixgbe_tx_buffer
*tx_buffer_info
;
6507 unsigned int total
= skb
->len
;
6508 unsigned int offset
= 0, size
, count
= 0, i
;
6509 unsigned int nr_frags
= skb_shinfo(skb
)->nr_frags
;
6511 unsigned int bytecount
= skb
->len
;
6514 i
= tx_ring
->next_to_use
;
6516 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
)
6517 /* excluding fcoe_crc_eof for FCoE */
6518 total
-= sizeof(struct fcoe_crc_eof
);
6520 len
= min(skb_headlen(skb
), total
);
6522 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6523 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
6525 tx_buffer_info
->length
= size
;
6526 tx_buffer_info
->mapped_as_page
= false;
6527 tx_buffer_info
->dma
= dma_map_single(dev
,
6529 size
, DMA_TO_DEVICE
);
6530 if (dma_mapping_error(dev
, tx_buffer_info
->dma
))
6532 tx_buffer_info
->time_stamp
= jiffies
;
6533 tx_buffer_info
->next_to_watch
= i
;
6542 if (i
== tx_ring
->count
)
6547 for (f
= 0; f
< nr_frags
; f
++) {
6548 struct skb_frag_struct
*frag
;
6550 frag
= &skb_shinfo(skb
)->frags
[f
];
6551 len
= min((unsigned int)frag
->size
, total
);
6552 offset
= frag
->page_offset
;
6556 if (i
== tx_ring
->count
)
6559 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6560 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
6562 tx_buffer_info
->length
= size
;
6563 tx_buffer_info
->dma
= dma_map_page(dev
,
6567 tx_buffer_info
->mapped_as_page
= true;
6568 if (dma_mapping_error(dev
, tx_buffer_info
->dma
))
6570 tx_buffer_info
->time_stamp
= jiffies
;
6571 tx_buffer_info
->next_to_watch
= i
;
6582 if (tx_flags
& IXGBE_TX_FLAGS_TSO
)
6583 gso_segs
= skb_shinfo(skb
)->gso_segs
;
6585 /* adjust for FCoE Sequence Offload */
6586 else if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
6587 gso_segs
= DIV_ROUND_UP(skb
->len
- hdr_len
,
6588 skb_shinfo(skb
)->gso_size
);
6589 #endif /* IXGBE_FCOE */
6590 bytecount
+= (gso_segs
- 1) * hdr_len
;
6592 /* multiply data chunks by size of headers */
6593 tx_ring
->tx_buffer_info
[i
].bytecount
= bytecount
;
6594 tx_ring
->tx_buffer_info
[i
].gso_segs
= gso_segs
;
6595 tx_ring
->tx_buffer_info
[i
].skb
= skb
;
6596 tx_ring
->tx_buffer_info
[first
].next_to_watch
= i
;
6601 e_dev_err("TX DMA map failed\n");
6603 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6604 tx_buffer_info
->dma
= 0;
6605 tx_buffer_info
->time_stamp
= 0;
6606 tx_buffer_info
->next_to_watch
= 0;
6610 /* clear timestamp and dma mappings for remaining portion of packet */
6613 i
+= tx_ring
->count
;
6615 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6616 ixgbe_unmap_and_free_tx_resource(tx_ring
, tx_buffer_info
);
6622 static void ixgbe_tx_queue(struct ixgbe_ring
*tx_ring
,
6623 int tx_flags
, int count
, u32 paylen
, u8 hdr_len
)
6625 union ixgbe_adv_tx_desc
*tx_desc
= NULL
;
6626 struct ixgbe_tx_buffer
*tx_buffer_info
;
6627 u32 olinfo_status
= 0, cmd_type_len
= 0;
6629 u32 txd_cmd
= IXGBE_TXD_CMD_EOP
| IXGBE_TXD_CMD_RS
| IXGBE_TXD_CMD_IFCS
;
6631 cmd_type_len
|= IXGBE_ADVTXD_DTYP_DATA
;
6633 cmd_type_len
|= IXGBE_ADVTXD_DCMD_IFCS
| IXGBE_ADVTXD_DCMD_DEXT
;
6635 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
6636 cmd_type_len
|= IXGBE_ADVTXD_DCMD_VLE
;
6638 if (tx_flags
& IXGBE_TX_FLAGS_TSO
) {
6639 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6641 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6642 IXGBE_ADVTXD_POPTS_SHIFT
;
6644 /* use index 1 context for tso */
6645 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6646 if (tx_flags
& IXGBE_TX_FLAGS_IPV4
)
6647 olinfo_status
|= IXGBE_TXD_POPTS_IXSM
<<
6648 IXGBE_ADVTXD_POPTS_SHIFT
;
6650 } else if (tx_flags
& IXGBE_TX_FLAGS_CSUM
)
6651 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6652 IXGBE_ADVTXD_POPTS_SHIFT
;
6654 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6655 olinfo_status
|= IXGBE_ADVTXD_CC
;
6656 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6657 if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
6658 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6661 olinfo_status
|= ((paylen
- hdr_len
) << IXGBE_ADVTXD_PAYLEN_SHIFT
);
6663 i
= tx_ring
->next_to_use
;
6665 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6666 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
6667 tx_desc
->read
.buffer_addr
= cpu_to_le64(tx_buffer_info
->dma
);
6668 tx_desc
->read
.cmd_type_len
=
6669 cpu_to_le32(cmd_type_len
| tx_buffer_info
->length
);
6670 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
6672 if (i
== tx_ring
->count
)
6676 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(txd_cmd
);
6679 * Force memory writes to complete before letting h/w
6680 * know there are new descriptors to fetch. (Only
6681 * applicable for weak-ordered memory model archs,
6686 tx_ring
->next_to_use
= i
;
6687 writel(i
, tx_ring
->tail
);
6690 static void ixgbe_atr(struct ixgbe_ring
*ring
, struct sk_buff
*skb
,
6691 u32 tx_flags
, __be16 protocol
)
6693 struct ixgbe_q_vector
*q_vector
= ring
->q_vector
;
6694 union ixgbe_atr_hash_dword input
= { .dword
= 0 };
6695 union ixgbe_atr_hash_dword common
= { .dword
= 0 };
6697 unsigned char *network
;
6699 struct ipv6hdr
*ipv6
;
6704 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6708 /* do nothing if sampling is disabled */
6709 if (!ring
->atr_sample_rate
)
6714 /* snag network header to get L4 type and address */
6715 hdr
.network
= skb_network_header(skb
);
6717 /* Currently only IPv4/IPv6 with TCP is supported */
6718 if ((protocol
!= __constant_htons(ETH_P_IPV6
) ||
6719 hdr
.ipv6
->nexthdr
!= IPPROTO_TCP
) &&
6720 (protocol
!= __constant_htons(ETH_P_IP
) ||
6721 hdr
.ipv4
->protocol
!= IPPROTO_TCP
))
6726 /* skip this packet since the socket is closing */
6730 /* sample on all syn packets or once every atr sample count */
6731 if (!th
->syn
&& (ring
->atr_count
< ring
->atr_sample_rate
))
6734 /* reset sample count */
6735 ring
->atr_count
= 0;
6737 vlan_id
= htons(tx_flags
>> IXGBE_TX_FLAGS_VLAN_SHIFT
);
6740 * src and dst are inverted, think how the receiver sees them
6742 * The input is broken into two sections, a non-compressed section
6743 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6744 * is XORed together and stored in the compressed dword.
6746 input
.formatted
.vlan_id
= vlan_id
;
6749 * since src port and flex bytes occupy the same word XOR them together
6750 * and write the value to source port portion of compressed dword
6753 common
.port
.src
^= th
->dest
^ __constant_htons(ETH_P_8021Q
);
6755 common
.port
.src
^= th
->dest
^ protocol
;
6756 common
.port
.dst
^= th
->source
;
6758 if (protocol
== __constant_htons(ETH_P_IP
)) {
6759 input
.formatted
.flow_type
= IXGBE_ATR_FLOW_TYPE_TCPV4
;
6760 common
.ip
^= hdr
.ipv4
->saddr
^ hdr
.ipv4
->daddr
;
6762 input
.formatted
.flow_type
= IXGBE_ATR_FLOW_TYPE_TCPV6
;
6763 common
.ip
^= hdr
.ipv6
->saddr
.s6_addr32
[0] ^
6764 hdr
.ipv6
->saddr
.s6_addr32
[1] ^
6765 hdr
.ipv6
->saddr
.s6_addr32
[2] ^
6766 hdr
.ipv6
->saddr
.s6_addr32
[3] ^
6767 hdr
.ipv6
->daddr
.s6_addr32
[0] ^
6768 hdr
.ipv6
->daddr
.s6_addr32
[1] ^
6769 hdr
.ipv6
->daddr
.s6_addr32
[2] ^
6770 hdr
.ipv6
->daddr
.s6_addr32
[3];
6773 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6774 ixgbe_fdir_add_signature_filter_82599(&q_vector
->adapter
->hw
,
6775 input
, common
, ring
->queue_index
);
6778 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring
*tx_ring
, int size
)
6780 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
6781 /* Herbert's original patch had:
6782 * smp_mb__after_netif_stop_queue();
6783 * but since that doesn't exist yet, just open code it. */
6786 /* We need to check again in a case another CPU has just
6787 * made room available. */
6788 if (likely(IXGBE_DESC_UNUSED(tx_ring
) < size
))
6791 /* A reprieve! - use start_queue because it doesn't call schedule */
6792 netif_start_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
6793 ++tx_ring
->tx_stats
.restart_queue
;
6797 static int ixgbe_maybe_stop_tx(struct ixgbe_ring
*tx_ring
, int size
)
6799 if (likely(IXGBE_DESC_UNUSED(tx_ring
) >= size
))
6801 return __ixgbe_maybe_stop_tx(tx_ring
, size
);
6804 static u16
ixgbe_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
6806 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6807 int txq
= smp_processor_id();
6811 protocol
= vlan_get_protocol(skb
);
6813 if (((protocol
== htons(ETH_P_FCOE
)) ||
6814 (protocol
== htons(ETH_P_FIP
))) &&
6815 (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)) {
6816 txq
&= (adapter
->ring_feature
[RING_F_FCOE
].indices
- 1);
6817 txq
+= adapter
->ring_feature
[RING_F_FCOE
].mask
;
6822 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
6823 while (unlikely(txq
>= dev
->real_num_tx_queues
))
6824 txq
-= dev
->real_num_tx_queues
;
6828 return skb_tx_hash(dev
, skb
);
6831 netdev_tx_t
ixgbe_xmit_frame_ring(struct sk_buff
*skb
,
6832 struct ixgbe_adapter
*adapter
,
6833 struct ixgbe_ring
*tx_ring
)
6836 unsigned int tx_flags
= 0;
6843 protocol
= vlan_get_protocol(skb
);
6845 if (vlan_tx_tag_present(skb
)) {
6846 tx_flags
|= vlan_tx_tag_get(skb
);
6847 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6848 tx_flags
&= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK
;
6849 tx_flags
|= tx_ring
->dcb_tc
<< 13;
6851 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6852 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6853 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
&&
6854 skb
->priority
!= TC_PRIO_CONTROL
) {
6855 tx_flags
|= tx_ring
->dcb_tc
<< 13;
6856 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6857 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6861 /* for FCoE with DCB, we force the priority to what
6862 * was specified by the switch */
6863 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
&&
6864 (protocol
== htons(ETH_P_FCOE
)))
6865 tx_flags
|= IXGBE_TX_FLAGS_FCOE
;
6868 /* four things can cause us to need a context descriptor */
6869 if (skb_is_gso(skb
) ||
6870 (skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
6871 (tx_flags
& IXGBE_TX_FLAGS_VLAN
) ||
6872 (tx_flags
& IXGBE_TX_FLAGS_FCOE
))
6875 count
+= TXD_USE_COUNT(skb_headlen(skb
));
6876 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
6877 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
6879 if (ixgbe_maybe_stop_tx(tx_ring
, count
)) {
6880 tx_ring
->tx_stats
.tx_busy
++;
6881 return NETDEV_TX_BUSY
;
6884 first
= tx_ring
->next_to_use
;
6885 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6887 /* setup tx offload for FCoE */
6888 tso
= ixgbe_fso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
6890 dev_kfree_skb_any(skb
);
6891 return NETDEV_TX_OK
;
6894 tx_flags
|= IXGBE_TX_FLAGS_FSO
;
6895 #endif /* IXGBE_FCOE */
6897 if (protocol
== htons(ETH_P_IP
))
6898 tx_flags
|= IXGBE_TX_FLAGS_IPV4
;
6899 tso
= ixgbe_tso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
,
6902 dev_kfree_skb_any(skb
);
6903 return NETDEV_TX_OK
;
6907 tx_flags
|= IXGBE_TX_FLAGS_TSO
;
6908 else if (ixgbe_tx_csum(adapter
, tx_ring
, skb
, tx_flags
,
6910 (skb
->ip_summed
== CHECKSUM_PARTIAL
))
6911 tx_flags
|= IXGBE_TX_FLAGS_CSUM
;
6914 count
= ixgbe_tx_map(adapter
, tx_ring
, skb
, tx_flags
, first
, hdr_len
);
6916 /* add the ATR filter if ATR is on */
6917 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE
, &tx_ring
->state
))
6918 ixgbe_atr(tx_ring
, skb
, tx_flags
, protocol
);
6919 ixgbe_tx_queue(tx_ring
, tx_flags
, count
, skb
->len
, hdr_len
);
6920 ixgbe_maybe_stop_tx(tx_ring
, DESC_NEEDED
);
6923 dev_kfree_skb_any(skb
);
6924 tx_ring
->tx_buffer_info
[first
].time_stamp
= 0;
6925 tx_ring
->next_to_use
= first
;
6928 return NETDEV_TX_OK
;
6931 static netdev_tx_t
ixgbe_xmit_frame(struct sk_buff
*skb
, struct net_device
*netdev
)
6933 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6934 struct ixgbe_ring
*tx_ring
;
6936 tx_ring
= adapter
->tx_ring
[skb
->queue_mapping
];
6937 return ixgbe_xmit_frame_ring(skb
, adapter
, tx_ring
);
6941 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6942 * @netdev: network interface device structure
6943 * @p: pointer to an address structure
6945 * Returns 0 on success, negative on failure
6947 static int ixgbe_set_mac(struct net_device
*netdev
, void *p
)
6949 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6950 struct ixgbe_hw
*hw
= &adapter
->hw
;
6951 struct sockaddr
*addr
= p
;
6953 if (!is_valid_ether_addr(addr
->sa_data
))
6954 return -EADDRNOTAVAIL
;
6956 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
6957 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
6959 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
6966 ixgbe_mdio_read(struct net_device
*netdev
, int prtad
, int devad
, u16 addr
)
6968 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6969 struct ixgbe_hw
*hw
= &adapter
->hw
;
6973 if (prtad
!= hw
->phy
.mdio
.prtad
)
6975 rc
= hw
->phy
.ops
.read_reg(hw
, addr
, devad
, &value
);
6981 static int ixgbe_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
6982 u16 addr
, u16 value
)
6984 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6985 struct ixgbe_hw
*hw
= &adapter
->hw
;
6987 if (prtad
!= hw
->phy
.mdio
.prtad
)
6989 return hw
->phy
.ops
.write_reg(hw
, addr
, devad
, value
);
6992 static int ixgbe_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
6994 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6996 return mdio_mii_ioctl(&adapter
->hw
.phy
.mdio
, if_mii(req
), cmd
);
7000 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
7002 * @netdev: network interface device structure
7004 * Returns non-zero on failure
7006 static int ixgbe_add_sanmac_netdev(struct net_device
*dev
)
7009 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
7010 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
7012 if (is_valid_ether_addr(mac
->san_addr
)) {
7014 err
= dev_addr_add(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
7021 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7023 * @netdev: network interface device structure
7025 * Returns non-zero on failure
7027 static int ixgbe_del_sanmac_netdev(struct net_device
*dev
)
7030 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
7031 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
7033 if (is_valid_ether_addr(mac
->san_addr
)) {
7035 err
= dev_addr_del(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
7041 #ifdef CONFIG_NET_POLL_CONTROLLER
7043 * Polling 'interrupt' - used by things like netconsole to send skbs
7044 * without having to re-enable interrupts. It's not called while
7045 * the interrupt routine is executing.
7047 static void ixgbe_netpoll(struct net_device
*netdev
)
7049 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7052 /* if interface is down do nothing */
7053 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
7056 adapter
->flags
|= IXGBE_FLAG_IN_NETPOLL
;
7057 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
7058 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
7059 for (i
= 0; i
< num_q_vectors
; i
++) {
7060 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
7061 ixgbe_msix_clean_many(0, q_vector
);
7064 ixgbe_intr(adapter
->pdev
->irq
, netdev
);
7066 adapter
->flags
&= ~IXGBE_FLAG_IN_NETPOLL
;
7070 static struct rtnl_link_stats64
*ixgbe_get_stats64(struct net_device
*netdev
,
7071 struct rtnl_link_stats64
*stats
)
7073 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7077 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
7078 struct ixgbe_ring
*ring
= ACCESS_ONCE(adapter
->rx_ring
[i
]);
7084 start
= u64_stats_fetch_begin_bh(&ring
->syncp
);
7085 packets
= ring
->stats
.packets
;
7086 bytes
= ring
->stats
.bytes
;
7087 } while (u64_stats_fetch_retry_bh(&ring
->syncp
, start
));
7088 stats
->rx_packets
+= packets
;
7089 stats
->rx_bytes
+= bytes
;
7093 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
7094 struct ixgbe_ring
*ring
= ACCESS_ONCE(adapter
->tx_ring
[i
]);
7100 start
= u64_stats_fetch_begin_bh(&ring
->syncp
);
7101 packets
= ring
->stats
.packets
;
7102 bytes
= ring
->stats
.bytes
;
7103 } while (u64_stats_fetch_retry_bh(&ring
->syncp
, start
));
7104 stats
->tx_packets
+= packets
;
7105 stats
->tx_bytes
+= bytes
;
7109 /* following stats updated by ixgbe_watchdog_task() */
7110 stats
->multicast
= netdev
->stats
.multicast
;
7111 stats
->rx_errors
= netdev
->stats
.rx_errors
;
7112 stats
->rx_length_errors
= netdev
->stats
.rx_length_errors
;
7113 stats
->rx_crc_errors
= netdev
->stats
.rx_crc_errors
;
7114 stats
->rx_missed_errors
= netdev
->stats
.rx_missed_errors
;
7118 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7119 * #adapter: pointer to ixgbe_adapter
7120 * @tc: number of traffic classes currently enabled
7122 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7123 * 802.1Q priority maps to a packet buffer that exists.
7125 static void ixgbe_validate_rtr(struct ixgbe_adapter
*adapter
, u8 tc
)
7127 struct ixgbe_hw
*hw
= &adapter
->hw
;
7131 /* 82598 have a static priority to TC mapping that can not
7132 * be changed so no validation is needed.
7134 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
7137 reg
= IXGBE_READ_REG(hw
, IXGBE_RTRUP2TC
);
7140 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++) {
7141 u8 up2tc
= reg
>> (i
* IXGBE_RTRUP2TC_UP_SHIFT
);
7143 /* If up2tc is out of bounds default to zero */
7145 reg
&= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT
);
7149 IXGBE_WRITE_REG(hw
, IXGBE_RTRUP2TC
, reg
);
7155 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7158 * @netdev: net device to configure
7159 * @tc: number of traffic classes to enable
7161 int ixgbe_setup_tc(struct net_device
*dev
, u8 tc
)
7163 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
7164 struct ixgbe_hw
*hw
= &adapter
->hw
;
7166 /* If DCB is anabled do not remove traffic classes, multiple
7167 * traffic classes are required to implement DCB
7169 if (!tc
&& (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
7172 /* Hardware supports up to 8 traffic classes */
7173 if (tc
> MAX_TRAFFIC_CLASS
||
7174 (hw
->mac
.type
== ixgbe_mac_82598EB
&& tc
< MAX_TRAFFIC_CLASS
))
7177 /* Hardware has to reinitialize queues and interrupts to
7178 * match packet buffer alignment. Unfortunantly, the
7179 * hardware is not flexible enough to do this dynamically.
7181 if (netif_running(dev
))
7183 ixgbe_clear_interrupt_scheme(adapter
);
7186 netdev_set_num_tc(dev
, tc
);
7188 netdev_reset_tc(dev
);
7190 ixgbe_init_interrupt_scheme(adapter
);
7191 ixgbe_validate_rtr(adapter
, tc
);
7192 if (netif_running(dev
))
7198 static const struct net_device_ops ixgbe_netdev_ops
= {
7199 .ndo_open
= ixgbe_open
,
7200 .ndo_stop
= ixgbe_close
,
7201 .ndo_start_xmit
= ixgbe_xmit_frame
,
7202 .ndo_select_queue
= ixgbe_select_queue
,
7203 .ndo_set_rx_mode
= ixgbe_set_rx_mode
,
7204 .ndo_set_multicast_list
= ixgbe_set_rx_mode
,
7205 .ndo_validate_addr
= eth_validate_addr
,
7206 .ndo_set_mac_address
= ixgbe_set_mac
,
7207 .ndo_change_mtu
= ixgbe_change_mtu
,
7208 .ndo_tx_timeout
= ixgbe_tx_timeout
,
7209 .ndo_vlan_rx_add_vid
= ixgbe_vlan_rx_add_vid
,
7210 .ndo_vlan_rx_kill_vid
= ixgbe_vlan_rx_kill_vid
,
7211 .ndo_do_ioctl
= ixgbe_ioctl
,
7212 .ndo_set_vf_mac
= ixgbe_ndo_set_vf_mac
,
7213 .ndo_set_vf_vlan
= ixgbe_ndo_set_vf_vlan
,
7214 .ndo_set_vf_tx_rate
= ixgbe_ndo_set_vf_bw
,
7215 .ndo_get_vf_config
= ixgbe_ndo_get_vf_config
,
7216 .ndo_get_stats64
= ixgbe_get_stats64
,
7217 .ndo_setup_tc
= ixgbe_setup_tc
,
7218 #ifdef CONFIG_NET_POLL_CONTROLLER
7219 .ndo_poll_controller
= ixgbe_netpoll
,
7222 .ndo_fcoe_ddp_setup
= ixgbe_fcoe_ddp_get
,
7223 .ndo_fcoe_ddp_target
= ixgbe_fcoe_ddp_target
,
7224 .ndo_fcoe_ddp_done
= ixgbe_fcoe_ddp_put
,
7225 .ndo_fcoe_enable
= ixgbe_fcoe_enable
,
7226 .ndo_fcoe_disable
= ixgbe_fcoe_disable
,
7227 .ndo_fcoe_get_wwn
= ixgbe_fcoe_get_wwn
,
7228 #endif /* IXGBE_FCOE */
7231 static void __devinit
ixgbe_probe_vf(struct ixgbe_adapter
*adapter
,
7232 const struct ixgbe_info
*ii
)
7234 #ifdef CONFIG_PCI_IOV
7235 struct ixgbe_hw
*hw
= &adapter
->hw
;
7237 int num_vf_macvlans
, i
;
7238 struct vf_macvlans
*mv_list
;
7240 if (hw
->mac
.type
== ixgbe_mac_82598EB
|| !max_vfs
)
7243 /* The 82599 supports up to 64 VFs per physical function
7244 * but this implementation limits allocation to 63 so that
7245 * basic networking resources are still available to the
7248 adapter
->num_vfs
= (max_vfs
> 63) ? 63 : max_vfs
;
7249 adapter
->flags
|= IXGBE_FLAG_SRIOV_ENABLED
;
7250 err
= pci_enable_sriov(adapter
->pdev
, adapter
->num_vfs
);
7252 e_err(probe
, "Failed to enable PCI sriov: %d\n", err
);
7256 num_vf_macvlans
= hw
->mac
.num_rar_entries
-
7257 (IXGBE_MAX_PF_MACVLANS
+ 1 + adapter
->num_vfs
);
7259 adapter
->mv_list
= mv_list
= kcalloc(num_vf_macvlans
,
7260 sizeof(struct vf_macvlans
),
7263 /* Initialize list of VF macvlans */
7264 INIT_LIST_HEAD(&adapter
->vf_mvs
.l
);
7265 for (i
= 0; i
< num_vf_macvlans
; i
++) {
7267 mv_list
->free
= true;
7268 mv_list
->rar_entry
= hw
->mac
.num_rar_entries
-
7269 (i
+ adapter
->num_vfs
+ 1);
7270 list_add(&mv_list
->l
, &adapter
->vf_mvs
.l
);
7275 /* If call to enable VFs succeeded then allocate memory
7276 * for per VF control structures.
7279 kcalloc(adapter
->num_vfs
,
7280 sizeof(struct vf_data_storage
), GFP_KERNEL
);
7281 if (adapter
->vfinfo
) {
7282 /* Now that we're sure SR-IOV is enabled
7283 * and memory allocated set up the mailbox parameters
7285 ixgbe_init_mbx_params_pf(hw
);
7286 memcpy(&hw
->mbx
.ops
, ii
->mbx_ops
,
7287 sizeof(hw
->mbx
.ops
));
7289 /* Disable RSC when in SR-IOV mode */
7290 adapter
->flags2
&= ~(IXGBE_FLAG2_RSC_CAPABLE
|
7291 IXGBE_FLAG2_RSC_ENABLED
);
7296 e_err(probe
, "Unable to allocate memory for VF Data Storage - "
7297 "SRIOV disabled\n");
7298 pci_disable_sriov(adapter
->pdev
);
7301 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
7302 adapter
->num_vfs
= 0;
7303 #endif /* CONFIG_PCI_IOV */
7307 * ixgbe_probe - Device Initialization Routine
7308 * @pdev: PCI device information struct
7309 * @ent: entry in ixgbe_pci_tbl
7311 * Returns 0 on success, negative on failure
7313 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7314 * The OS initialization, configuring of the adapter private structure,
7315 * and a hardware reset occur.
7317 static int __devinit
ixgbe_probe(struct pci_dev
*pdev
,
7318 const struct pci_device_id
*ent
)
7320 struct net_device
*netdev
;
7321 struct ixgbe_adapter
*adapter
= NULL
;
7322 struct ixgbe_hw
*hw
;
7323 const struct ixgbe_info
*ii
= ixgbe_info_tbl
[ent
->driver_data
];
7324 static int cards_found
;
7325 int i
, err
, pci_using_dac
;
7326 u8 part_str
[IXGBE_PBANUM_LENGTH
];
7327 unsigned int indices
= num_possible_cpus();
7333 /* Catch broken hardware that put the wrong VF device ID in
7334 * the PCIe SR-IOV capability.
7336 if (pdev
->is_virtfn
) {
7337 WARN(1, KERN_ERR
"%s (%hx:%hx) should not be a VF!\n",
7338 pci_name(pdev
), pdev
->vendor
, pdev
->device
);
7342 err
= pci_enable_device_mem(pdev
);
7346 if (!dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64)) &&
7347 !dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64))) {
7350 err
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(32));
7352 err
= dma_set_coherent_mask(&pdev
->dev
,
7356 "No usable DMA configuration, aborting\n");
7363 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
7364 IORESOURCE_MEM
), ixgbe_driver_name
);
7367 "pci_request_selected_regions failed 0x%x\n", err
);
7371 pci_enable_pcie_error_reporting(pdev
);
7373 pci_set_master(pdev
);
7374 pci_save_state(pdev
);
7376 #ifdef CONFIG_IXGBE_DCB
7377 indices
*= MAX_TRAFFIC_CLASS
;
7380 if (ii
->mac
== ixgbe_mac_82598EB
)
7381 indices
= min_t(unsigned int, indices
, IXGBE_MAX_RSS_INDICES
);
7383 indices
= min_t(unsigned int, indices
, IXGBE_MAX_FDIR_INDICES
);
7386 indices
+= min_t(unsigned int, num_possible_cpus(),
7387 IXGBE_MAX_FCOE_INDICES
);
7389 netdev
= alloc_etherdev_mq(sizeof(struct ixgbe_adapter
), indices
);
7392 goto err_alloc_etherdev
;
7395 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
7397 adapter
= netdev_priv(netdev
);
7398 pci_set_drvdata(pdev
, adapter
);
7400 adapter
->netdev
= netdev
;
7401 adapter
->pdev
= pdev
;
7404 adapter
->msg_enable
= (1 << DEFAULT_DEBUG_LEVEL_SHIFT
) - 1;
7406 hw
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
7407 pci_resource_len(pdev
, 0));
7413 for (i
= 1; i
<= 5; i
++) {
7414 if (pci_resource_len(pdev
, i
) == 0)
7418 netdev
->netdev_ops
= &ixgbe_netdev_ops
;
7419 ixgbe_set_ethtool_ops(netdev
);
7420 netdev
->watchdog_timeo
= 5 * HZ
;
7421 strncpy(netdev
->name
, pci_name(pdev
), sizeof(netdev
->name
) - 1);
7423 adapter
->bd_number
= cards_found
;
7426 memcpy(&hw
->mac
.ops
, ii
->mac_ops
, sizeof(hw
->mac
.ops
));
7427 hw
->mac
.type
= ii
->mac
;
7430 memcpy(&hw
->eeprom
.ops
, ii
->eeprom_ops
, sizeof(hw
->eeprom
.ops
));
7431 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
7432 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7433 if (!(eec
& (1 << 8)))
7434 hw
->eeprom
.ops
.read
= &ixgbe_read_eeprom_bit_bang_generic
;
7437 memcpy(&hw
->phy
.ops
, ii
->phy_ops
, sizeof(hw
->phy
.ops
));
7438 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
7439 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7440 hw
->phy
.mdio
.prtad
= MDIO_PRTAD_NONE
;
7441 hw
->phy
.mdio
.mmds
= 0;
7442 hw
->phy
.mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
7443 hw
->phy
.mdio
.dev
= netdev
;
7444 hw
->phy
.mdio
.mdio_read
= ixgbe_mdio_read
;
7445 hw
->phy
.mdio
.mdio_write
= ixgbe_mdio_write
;
7447 ii
->get_invariants(hw
);
7449 /* setup the private structure */
7450 err
= ixgbe_sw_init(adapter
);
7454 /* Make it possible the adapter to be woken up via WOL */
7455 switch (adapter
->hw
.mac
.type
) {
7456 case ixgbe_mac_82599EB
:
7457 case ixgbe_mac_X540
:
7458 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
7465 * If there is a fan on this device and it has failed log the
7468 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
7469 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
7470 if (esdp
& IXGBE_ESDP_SDP1
)
7471 e_crit(probe
, "Fan has stopped, replace the adapter\n");
7474 /* reset_hw fills in the perm_addr as well */
7475 hw
->phy
.reset_if_overtemp
= true;
7476 err
= hw
->mac
.ops
.reset_hw(hw
);
7477 hw
->phy
.reset_if_overtemp
= false;
7478 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
&&
7479 hw
->mac
.type
== ixgbe_mac_82598EB
) {
7481 } else if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
7482 e_dev_err("failed to load because an unsupported SFP+ "
7483 "module type was detected.\n");
7484 e_dev_err("Reload the driver after installing a supported "
7488 e_dev_err("HW Init failed: %d\n", err
);
7492 ixgbe_probe_vf(adapter
, ii
);
7494 netdev
->features
= NETIF_F_SG
|
7496 NETIF_F_HW_VLAN_TX
|
7497 NETIF_F_HW_VLAN_RX
|
7498 NETIF_F_HW_VLAN_FILTER
;
7500 netdev
->features
|= NETIF_F_IPV6_CSUM
;
7501 netdev
->features
|= NETIF_F_TSO
;
7502 netdev
->features
|= NETIF_F_TSO6
;
7503 netdev
->features
|= NETIF_F_GRO
;
7504 netdev
->features
|= NETIF_F_RXHASH
;
7506 switch (adapter
->hw
.mac
.type
) {
7507 case ixgbe_mac_82599EB
:
7508 case ixgbe_mac_X540
:
7509 netdev
->features
|= NETIF_F_SCTP_CSUM
;
7515 netdev
->vlan_features
|= NETIF_F_TSO
;
7516 netdev
->vlan_features
|= NETIF_F_TSO6
;
7517 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
7518 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
7519 netdev
->vlan_features
|= NETIF_F_SG
;
7521 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7522 adapter
->flags
&= ~(IXGBE_FLAG_RSS_ENABLED
|
7523 IXGBE_FLAG_DCB_ENABLED
);
7525 #ifdef CONFIG_IXGBE_DCB
7526 netdev
->dcbnl_ops
= &dcbnl_ops
;
7530 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
7531 if (hw
->mac
.ops
.get_device_caps
) {
7532 hw
->mac
.ops
.get_device_caps(hw
, &device_caps
);
7533 if (device_caps
& IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
)
7534 adapter
->flags
&= ~IXGBE_FLAG_FCOE_CAPABLE
;
7537 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
7538 netdev
->vlan_features
|= NETIF_F_FCOE_CRC
;
7539 netdev
->vlan_features
|= NETIF_F_FSO
;
7540 netdev
->vlan_features
|= NETIF_F_FCOE_MTU
;
7542 #endif /* IXGBE_FCOE */
7543 if (pci_using_dac
) {
7544 netdev
->features
|= NETIF_F_HIGHDMA
;
7545 netdev
->vlan_features
|= NETIF_F_HIGHDMA
;
7548 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
7549 netdev
->features
|= NETIF_F_LRO
;
7551 /* make sure the EEPROM is good */
7552 if (hw
->eeprom
.ops
.validate_checksum(hw
, NULL
) < 0) {
7553 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7558 memcpy(netdev
->dev_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
7559 memcpy(netdev
->perm_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
7561 if (ixgbe_validate_mac_addr(netdev
->perm_addr
)) {
7562 e_dev_err("invalid MAC address\n");
7567 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7568 if (hw
->mac
.ops
.disable_tx_laser
&&
7569 ((hw
->phy
.multispeed_fiber
) ||
7570 ((hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) &&
7571 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
7572 hw
->mac
.ops
.disable_tx_laser(hw
);
7574 setup_timer(&adapter
->service_timer
, &ixgbe_service_timer
,
7575 (unsigned long) adapter
);
7577 INIT_WORK(&adapter
->service_task
, ixgbe_service_task
);
7578 clear_bit(__IXGBE_SERVICE_SCHED
, &adapter
->state
);
7580 err
= ixgbe_init_interrupt_scheme(adapter
);
7584 if (!(adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
))
7585 netdev
->features
&= ~NETIF_F_RXHASH
;
7587 switch (pdev
->device
) {
7588 case IXGBE_DEV_ID_82599_SFP
:
7589 /* Only this subdevice supports WOL */
7590 if (pdev
->subsystem_device
== IXGBE_SUBDEV_ID_82599_SFP
)
7591 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
7592 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
7594 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE
:
7595 /* All except this subdevice support WOL */
7596 if (pdev
->subsystem_device
!= IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ
)
7597 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
7598 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
7600 case IXGBE_DEV_ID_82599_KX4
:
7601 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
7602 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
7608 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
7610 /* pick up the PCI bus settings for reporting later */
7611 hw
->mac
.ops
.get_bus_info(hw
);
7613 /* print bus type/speed/width info */
7614 e_dev_info("(PCI Express:%s:%s) %pM\n",
7615 (hw
->bus
.speed
== ixgbe_bus_speed_5000
? "5.0GT/s" :
7616 hw
->bus
.speed
== ixgbe_bus_speed_2500
? "2.5GT/s" :
7618 (hw
->bus
.width
== ixgbe_bus_width_pcie_x8
? "Width x8" :
7619 hw
->bus
.width
== ixgbe_bus_width_pcie_x4
? "Width x4" :
7620 hw
->bus
.width
== ixgbe_bus_width_pcie_x1
? "Width x1" :
7624 err
= ixgbe_read_pba_string_generic(hw
, part_str
, IXGBE_PBANUM_LENGTH
);
7626 strncpy(part_str
, "Unknown", IXGBE_PBANUM_LENGTH
);
7627 if (ixgbe_is_sfp(hw
) && hw
->phy
.sfp_type
!= ixgbe_sfp_type_not_present
)
7628 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7629 hw
->mac
.type
, hw
->phy
.type
, hw
->phy
.sfp_type
,
7632 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7633 hw
->mac
.type
, hw
->phy
.type
, part_str
);
7635 if (hw
->bus
.width
<= ixgbe_bus_width_pcie_x4
) {
7636 e_dev_warn("PCI-Express bandwidth available for this card is "
7637 "not sufficient for optimal performance.\n");
7638 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7642 /* save off EEPROM version number */
7643 hw
->eeprom
.ops
.read(hw
, 0x29, &adapter
->eeprom_version
);
7645 /* reset the hardware with the new settings */
7646 err
= hw
->mac
.ops
.start_hw(hw
);
7648 if (err
== IXGBE_ERR_EEPROM_VERSION
) {
7649 /* We are running on a pre-production device, log a warning */
7650 e_dev_warn("This device is a pre-production adapter/LOM. "
7651 "Please be aware there may be issues associated "
7652 "with your hardware. If you are experiencing "
7653 "problems please contact your Intel or hardware "
7654 "representative who provided you with this "
7657 strcpy(netdev
->name
, "eth%d");
7658 err
= register_netdev(netdev
);
7662 /* carrier off reporting is important to ethtool even BEFORE open */
7663 netif_carrier_off(netdev
);
7665 #ifdef CONFIG_IXGBE_DCA
7666 if (dca_add_requester(&pdev
->dev
) == 0) {
7667 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
7668 ixgbe_setup_dca(adapter
);
7671 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
7672 e_info(probe
, "IOV is enabled with %d VFs\n", adapter
->num_vfs
);
7673 for (i
= 0; i
< adapter
->num_vfs
; i
++)
7674 ixgbe_vf_configuration(pdev
, (i
| 0x10000000));
7677 /* Inform firmware of driver version */
7678 if (hw
->mac
.ops
.set_fw_drv_ver
)
7679 hw
->mac
.ops
.set_fw_drv_ver(hw
, MAJ
, MIN
, BUILD
, KFIX
);
7681 /* add san mac addr to netdev */
7682 ixgbe_add_sanmac_netdev(netdev
);
7684 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7689 ixgbe_release_hw_control(adapter
);
7690 ixgbe_clear_interrupt_scheme(adapter
);
7693 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7694 ixgbe_disable_sriov(adapter
);
7695 adapter
->flags2
&= ~IXGBE_FLAG2_SEARCH_FOR_SFP
;
7696 iounmap(hw
->hw_addr
);
7698 free_netdev(netdev
);
7700 pci_release_selected_regions(pdev
,
7701 pci_select_bars(pdev
, IORESOURCE_MEM
));
7704 pci_disable_device(pdev
);
7709 * ixgbe_remove - Device Removal Routine
7710 * @pdev: PCI device information struct
7712 * ixgbe_remove is called by the PCI subsystem to alert the driver
7713 * that it should release a PCI device. The could be caused by a
7714 * Hot-Plug event, or because the driver is going to be removed from
7717 static void __devexit
ixgbe_remove(struct pci_dev
*pdev
)
7719 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7720 struct net_device
*netdev
= adapter
->netdev
;
7722 set_bit(__IXGBE_DOWN
, &adapter
->state
);
7723 cancel_work_sync(&adapter
->service_task
);
7725 #ifdef CONFIG_IXGBE_DCA
7726 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
7727 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
7728 dca_remove_requester(&pdev
->dev
);
7729 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
7734 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
7735 ixgbe_cleanup_fcoe(adapter
);
7737 #endif /* IXGBE_FCOE */
7739 /* remove the added san mac */
7740 ixgbe_del_sanmac_netdev(netdev
);
7742 if (netdev
->reg_state
== NETREG_REGISTERED
)
7743 unregister_netdev(netdev
);
7745 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7746 ixgbe_disable_sriov(adapter
);
7748 ixgbe_clear_interrupt_scheme(adapter
);
7750 ixgbe_release_hw_control(adapter
);
7752 iounmap(adapter
->hw
.hw_addr
);
7753 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
7756 e_dev_info("complete\n");
7758 free_netdev(netdev
);
7760 pci_disable_pcie_error_reporting(pdev
);
7762 pci_disable_device(pdev
);
7766 * ixgbe_io_error_detected - called when PCI error is detected
7767 * @pdev: Pointer to PCI device
7768 * @state: The current pci connection state
7770 * This function is called after a PCI bus error affecting
7771 * this device has been detected.
7773 static pci_ers_result_t
ixgbe_io_error_detected(struct pci_dev
*pdev
,
7774 pci_channel_state_t state
)
7776 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7777 struct net_device
*netdev
= adapter
->netdev
;
7779 netif_device_detach(netdev
);
7781 if (state
== pci_channel_io_perm_failure
)
7782 return PCI_ERS_RESULT_DISCONNECT
;
7784 if (netif_running(netdev
))
7785 ixgbe_down(adapter
);
7786 pci_disable_device(pdev
);
7788 /* Request a slot reset. */
7789 return PCI_ERS_RESULT_NEED_RESET
;
7793 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7794 * @pdev: Pointer to PCI device
7796 * Restart the card from scratch, as if from a cold-boot.
7798 static pci_ers_result_t
ixgbe_io_slot_reset(struct pci_dev
*pdev
)
7800 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7801 pci_ers_result_t result
;
7804 if (pci_enable_device_mem(pdev
)) {
7805 e_err(probe
, "Cannot re-enable PCI device after reset.\n");
7806 result
= PCI_ERS_RESULT_DISCONNECT
;
7808 pci_set_master(pdev
);
7809 pci_restore_state(pdev
);
7810 pci_save_state(pdev
);
7812 pci_wake_from_d3(pdev
, false);
7814 ixgbe_reset(adapter
);
7815 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
7816 result
= PCI_ERS_RESULT_RECOVERED
;
7819 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
7821 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7822 "failed 0x%0x\n", err
);
7823 /* non-fatal, continue */
7830 * ixgbe_io_resume - called when traffic can start flowing again.
7831 * @pdev: Pointer to PCI device
7833 * This callback is called when the error recovery driver tells us that
7834 * its OK to resume normal operation.
7836 static void ixgbe_io_resume(struct pci_dev
*pdev
)
7838 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7839 struct net_device
*netdev
= adapter
->netdev
;
7841 if (netif_running(netdev
)) {
7842 if (ixgbe_up(adapter
)) {
7843 e_info(probe
, "ixgbe_up failed after reset\n");
7848 netif_device_attach(netdev
);
7851 static struct pci_error_handlers ixgbe_err_handler
= {
7852 .error_detected
= ixgbe_io_error_detected
,
7853 .slot_reset
= ixgbe_io_slot_reset
,
7854 .resume
= ixgbe_io_resume
,
7857 static struct pci_driver ixgbe_driver
= {
7858 .name
= ixgbe_driver_name
,
7859 .id_table
= ixgbe_pci_tbl
,
7860 .probe
= ixgbe_probe
,
7861 .remove
= __devexit_p(ixgbe_remove
),
7863 .suspend
= ixgbe_suspend
,
7864 .resume
= ixgbe_resume
,
7866 .shutdown
= ixgbe_shutdown
,
7867 .err_handler
= &ixgbe_err_handler
7871 * ixgbe_init_module - Driver Registration Routine
7873 * ixgbe_init_module is the first routine called when the driver is
7874 * loaded. All it does is register with the PCI subsystem.
7876 static int __init
ixgbe_init_module(void)
7879 pr_info("%s - version %s\n", ixgbe_driver_string
, ixgbe_driver_version
);
7880 pr_info("%s\n", ixgbe_copyright
);
7882 #ifdef CONFIG_IXGBE_DCA
7883 dca_register_notify(&dca_notifier
);
7886 ret
= pci_register_driver(&ixgbe_driver
);
7890 module_init(ixgbe_init_module
);
7893 * ixgbe_exit_module - Driver Exit Cleanup Routine
7895 * ixgbe_exit_module is called just before the driver is removed
7898 static void __exit
ixgbe_exit_module(void)
7900 #ifdef CONFIG_IXGBE_DCA
7901 dca_unregister_notify(&dca_notifier
);
7903 pci_unregister_driver(&ixgbe_driver
);
7904 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7907 #ifdef CONFIG_IXGBE_DCA
7908 static int ixgbe_notify_dca(struct notifier_block
*nb
, unsigned long event
,
7913 ret_val
= driver_for_each_device(&ixgbe_driver
.driver
, NULL
, &event
,
7914 __ixgbe_notify_dca
);
7916 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
7919 #endif /* CONFIG_IXGBE_DCA */
7921 module_exit(ixgbe_exit_module
);