2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through platform_device. Structures which
29 * define the configuration needed by the board are defined in a
30 * board structure in arch/ppc/platforms (though I do not
31 * discount the possibility that other architectures could one
34 * The Gianfar Ethernet Controller uses a ring of buffer
35 * descriptors. The beginning is indicated by a register
36 * pointing to the physical address of the start of the ring.
37 * The end is determined by a "wrap" bit being set in the
38 * last descriptor of the ring.
40 * When a packet is received, the RXF bit in the
41 * IEVENT register is set, triggering an interrupt when the
42 * corresponding bit in the IMASK register is also set (if
43 * interrupt coalescing is active, then the interrupt may not
44 * happen immediately, but will wait until either a set number
45 * of frames or amount of time have passed). In NAPI, the
46 * interrupt handler will signal there is work to be done, and
47 * exit. Without NAPI, the packet(s) will be handled
48 * immediately. Both methods will start at the last known empty
49 * descriptor, and process every subsequent descriptor until there
50 * are none left with data (NAPI will stop after a set number of
51 * packets to give time to other tasks, but will eventually
52 * process all the packets). The data arrives inside a
53 * pre-allocated skb, and so after the skb is passed up to the
54 * stack, a new skb must be allocated, and the address field in
55 * the buffer descriptor must be updated to indicate this new
58 * When the kernel requests that a packet be transmitted, the
59 * driver starts where it left off last time, and points the
60 * descriptor at the buffer which was passed in. The driver
61 * then informs the DMA engine that there are packets ready to
62 * be transmitted. Once the controller is finished transmitting
63 * the packet, an interrupt may be triggered (under the same
64 * conditions as for reception, but depending on the TXF bit).
65 * The driver then cleans up the buffer.
68 #include <linux/kernel.h>
69 #include <linux/string.h>
70 #include <linux/errno.h>
71 #include <linux/unistd.h>
72 #include <linux/slab.h>
73 #include <linux/interrupt.h>
74 #include <linux/init.h>
75 #include <linux/delay.h>
76 #include <linux/netdevice.h>
77 #include <linux/etherdevice.h>
78 #include <linux/skbuff.h>
79 #include <linux/if_vlan.h>
80 #include <linux/spinlock.h>
82 #include <linux/platform_device.h>
84 #include <linux/tcp.h>
85 #include <linux/udp.h>
90 #include <asm/uaccess.h>
91 #include <linux/module.h>
92 #include <linux/dma-mapping.h>
93 #include <linux/crc32.h>
94 #include <linux/mii.h>
95 #include <linux/phy.h>
98 #include "gianfar_mii.h"
100 #define TX_TIMEOUT (1*HZ)
101 #define SKB_ALLOC_TIMEOUT 1000000
102 #undef BRIEF_GFAR_ERRORS
103 #undef VERBOSE_GFAR_ERRORS
105 #ifdef CONFIG_GFAR_NAPI
106 #define RECEIVE(x) netif_receive_skb(x)
108 #define RECEIVE(x) netif_rx(x)
111 const char gfar_driver_name
[] = "Gianfar Ethernet";
112 const char gfar_driver_version
[] = "1.3";
114 static int gfar_enet_open(struct net_device
*dev
);
115 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
116 static void gfar_timeout(struct net_device
*dev
);
117 static int gfar_close(struct net_device
*dev
);
118 struct sk_buff
*gfar_new_skb(struct net_device
*dev
, struct rxbd8
*bdp
);
119 static int gfar_set_mac_address(struct net_device
*dev
);
120 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
);
121 static irqreturn_t
gfar_error(int irq
, void *dev_id
);
122 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
);
123 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
);
124 static void adjust_link(struct net_device
*dev
);
125 static void init_registers(struct net_device
*dev
);
126 static int init_phy(struct net_device
*dev
);
127 static int gfar_probe(struct platform_device
*pdev
);
128 static int gfar_remove(struct platform_device
*pdev
);
129 static void free_skb_resources(struct gfar_private
*priv
);
130 static void gfar_set_multi(struct net_device
*dev
);
131 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
);
132 static void gfar_configure_serdes(struct net_device
*dev
);
133 extern int gfar_local_mdio_write(struct gfar_mii
*regs
, int mii_id
, int regnum
, u16 value
);
134 extern int gfar_local_mdio_read(struct gfar_mii
*regs
, int mii_id
, int regnum
);
135 #ifdef CONFIG_GFAR_NAPI
136 static int gfar_poll(struct napi_struct
*napi
, int budget
);
138 #ifdef CONFIG_NET_POLL_CONTROLLER
139 static void gfar_netpoll(struct net_device
*dev
);
141 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
);
142 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
, int length
);
143 static void gfar_vlan_rx_register(struct net_device
*netdev
,
144 struct vlan_group
*grp
);
145 void gfar_halt(struct net_device
*dev
);
146 void gfar_start(struct net_device
*dev
);
147 static void gfar_clear_exact_match(struct net_device
*dev
);
148 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
);
150 extern const struct ethtool_ops gfar_ethtool_ops
;
152 MODULE_AUTHOR("Freescale Semiconductor, Inc");
153 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
154 MODULE_LICENSE("GPL");
156 /* Returns 1 if incoming frames use an FCB */
157 static inline int gfar_uses_fcb(struct gfar_private
*priv
)
159 return (priv
->vlan_enable
|| priv
->rx_csum_enable
);
162 /* Set up the ethernet device structure, private data,
163 * and anything else we need before we start */
164 static int gfar_probe(struct platform_device
*pdev
)
167 struct net_device
*dev
= NULL
;
168 struct gfar_private
*priv
= NULL
;
169 struct gianfar_platform_data
*einfo
;
173 DECLARE_MAC_BUF(mac
);
175 einfo
= (struct gianfar_platform_data
*) pdev
->dev
.platform_data
;
178 printk(KERN_ERR
"gfar %d: Missing additional data!\n",
184 /* Create an ethernet device instance */
185 dev
= alloc_etherdev(sizeof (*priv
));
190 priv
= netdev_priv(dev
);
193 /* Set the info in the priv to the current info */
196 /* fill out IRQ fields */
197 if (einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
198 priv
->interruptTransmit
= platform_get_irq_byname(pdev
, "tx");
199 priv
->interruptReceive
= platform_get_irq_byname(pdev
, "rx");
200 priv
->interruptError
= platform_get_irq_byname(pdev
, "error");
201 if (priv
->interruptTransmit
< 0 || priv
->interruptReceive
< 0 || priv
->interruptError
< 0)
204 priv
->interruptTransmit
= platform_get_irq(pdev
, 0);
205 if (priv
->interruptTransmit
< 0)
209 /* get a pointer to the register memory */
210 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
211 priv
->regs
= ioremap(r
->start
, sizeof (struct gfar
));
213 if (NULL
== priv
->regs
) {
218 spin_lock_init(&priv
->txlock
);
219 spin_lock_init(&priv
->rxlock
);
221 platform_set_drvdata(pdev
, dev
);
223 /* Stop the DMA engine now, in case it was running before */
224 /* (The firmware could have used it, and left it running). */
225 /* To do this, we write Graceful Receive Stop and Graceful */
226 /* Transmit Stop, and then wait until the corresponding bits */
227 /* in IEVENT indicate the stops have completed. */
228 tempval
= gfar_read(&priv
->regs
->dmactrl
);
229 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
230 gfar_write(&priv
->regs
->dmactrl
, tempval
);
232 tempval
= gfar_read(&priv
->regs
->dmactrl
);
233 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
234 gfar_write(&priv
->regs
->dmactrl
, tempval
);
236 while (!(gfar_read(&priv
->regs
->ievent
) & (IEVENT_GRSC
| IEVENT_GTSC
)))
239 /* Reset MAC layer */
240 gfar_write(&priv
->regs
->maccfg1
, MACCFG1_SOFT_RESET
);
242 tempval
= (MACCFG1_TX_FLOW
| MACCFG1_RX_FLOW
);
243 gfar_write(&priv
->regs
->maccfg1
, tempval
);
245 /* Initialize MACCFG2. */
246 gfar_write(&priv
->regs
->maccfg2
, MACCFG2_INIT_SETTINGS
);
248 /* Initialize ECNTRL */
249 gfar_write(&priv
->regs
->ecntrl
, ECNTRL_INIT_SETTINGS
);
251 /* Copy the station address into the dev structure, */
252 memcpy(dev
->dev_addr
, einfo
->mac_addr
, MAC_ADDR_LEN
);
254 /* Set the dev->base_addr to the gfar reg region */
255 dev
->base_addr
= (unsigned long) (priv
->regs
);
257 SET_NETDEV_DEV(dev
, &pdev
->dev
);
259 /* Fill in the dev structure */
260 dev
->open
= gfar_enet_open
;
261 dev
->hard_start_xmit
= gfar_start_xmit
;
262 dev
->tx_timeout
= gfar_timeout
;
263 dev
->watchdog_timeo
= TX_TIMEOUT
;
264 #ifdef CONFIG_GFAR_NAPI
265 netif_napi_add(dev
, &priv
->napi
, gfar_poll
, GFAR_DEV_WEIGHT
);
267 #ifdef CONFIG_NET_POLL_CONTROLLER
268 dev
->poll_controller
= gfar_netpoll
;
270 dev
->stop
= gfar_close
;
271 dev
->change_mtu
= gfar_change_mtu
;
273 dev
->set_multicast_list
= gfar_set_multi
;
275 dev
->ethtool_ops
= &gfar_ethtool_ops
;
277 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_CSUM
) {
278 priv
->rx_csum_enable
= 1;
279 dev
->features
|= NETIF_F_IP_CSUM
;
281 priv
->rx_csum_enable
= 0;
285 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_VLAN
) {
286 dev
->vlan_rx_register
= gfar_vlan_rx_register
;
288 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
290 priv
->vlan_enable
= 1;
293 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
) {
294 priv
->extended_hash
= 1;
295 priv
->hash_width
= 9;
297 priv
->hash_regs
[0] = &priv
->regs
->igaddr0
;
298 priv
->hash_regs
[1] = &priv
->regs
->igaddr1
;
299 priv
->hash_regs
[2] = &priv
->regs
->igaddr2
;
300 priv
->hash_regs
[3] = &priv
->regs
->igaddr3
;
301 priv
->hash_regs
[4] = &priv
->regs
->igaddr4
;
302 priv
->hash_regs
[5] = &priv
->regs
->igaddr5
;
303 priv
->hash_regs
[6] = &priv
->regs
->igaddr6
;
304 priv
->hash_regs
[7] = &priv
->regs
->igaddr7
;
305 priv
->hash_regs
[8] = &priv
->regs
->gaddr0
;
306 priv
->hash_regs
[9] = &priv
->regs
->gaddr1
;
307 priv
->hash_regs
[10] = &priv
->regs
->gaddr2
;
308 priv
->hash_regs
[11] = &priv
->regs
->gaddr3
;
309 priv
->hash_regs
[12] = &priv
->regs
->gaddr4
;
310 priv
->hash_regs
[13] = &priv
->regs
->gaddr5
;
311 priv
->hash_regs
[14] = &priv
->regs
->gaddr6
;
312 priv
->hash_regs
[15] = &priv
->regs
->gaddr7
;
315 priv
->extended_hash
= 0;
316 priv
->hash_width
= 8;
318 priv
->hash_regs
[0] = &priv
->regs
->gaddr0
;
319 priv
->hash_regs
[1] = &priv
->regs
->gaddr1
;
320 priv
->hash_regs
[2] = &priv
->regs
->gaddr2
;
321 priv
->hash_regs
[3] = &priv
->regs
->gaddr3
;
322 priv
->hash_regs
[4] = &priv
->regs
->gaddr4
;
323 priv
->hash_regs
[5] = &priv
->regs
->gaddr5
;
324 priv
->hash_regs
[6] = &priv
->regs
->gaddr6
;
325 priv
->hash_regs
[7] = &priv
->regs
->gaddr7
;
328 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_PADDING
)
329 priv
->padding
= DEFAULT_PADDING
;
333 if (dev
->features
& NETIF_F_IP_CSUM
)
334 dev
->hard_header_len
+= GMAC_FCB_LEN
;
336 priv
->rx_buffer_size
= DEFAULT_RX_BUFFER_SIZE
;
337 priv
->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
338 priv
->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
340 priv
->txcoalescing
= DEFAULT_TX_COALESCE
;
341 priv
->txcount
= DEFAULT_TXCOUNT
;
342 priv
->txtime
= DEFAULT_TXTIME
;
343 priv
->rxcoalescing
= DEFAULT_RX_COALESCE
;
344 priv
->rxcount
= DEFAULT_RXCOUNT
;
345 priv
->rxtime
= DEFAULT_RXTIME
;
347 /* Enable most messages by default */
348 priv
->msg_enable
= (NETIF_MSG_IFUP
<< 1 ) - 1;
350 err
= register_netdev(dev
);
353 printk(KERN_ERR
"%s: Cannot register net device, aborting.\n",
358 /* Create all the sysfs files */
359 gfar_init_sysfs(dev
);
361 /* Print out the device info */
362 printk(KERN_INFO DEVICE_NAME
"%s\n",
363 dev
->name
, print_mac(mac
, dev
->dev_addr
));
365 /* Even more device info helps when determining which kernel */
366 /* provided which set of benchmarks. */
367 #ifdef CONFIG_GFAR_NAPI
368 printk(KERN_INFO
"%s: Running with NAPI enabled\n", dev
->name
);
370 printk(KERN_INFO
"%s: Running with NAPI disabled\n", dev
->name
);
372 printk(KERN_INFO
"%s: %d/%d RX/TX BD ring size\n",
373 dev
->name
, priv
->rx_ring_size
, priv
->tx_ring_size
);
384 static int gfar_remove(struct platform_device
*pdev
)
386 struct net_device
*dev
= platform_get_drvdata(pdev
);
387 struct gfar_private
*priv
= netdev_priv(dev
);
389 platform_set_drvdata(pdev
, NULL
);
398 /* Reads the controller's registers to determine what interface
399 * connects it to the PHY.
401 static phy_interface_t
gfar_get_interface(struct net_device
*dev
)
403 struct gfar_private
*priv
= netdev_priv(dev
);
404 u32 ecntrl
= gfar_read(&priv
->regs
->ecntrl
);
406 if (ecntrl
& ECNTRL_SGMII_MODE
)
407 return PHY_INTERFACE_MODE_SGMII
;
409 if (ecntrl
& ECNTRL_TBI_MODE
) {
410 if (ecntrl
& ECNTRL_REDUCED_MODE
)
411 return PHY_INTERFACE_MODE_RTBI
;
413 return PHY_INTERFACE_MODE_TBI
;
416 if (ecntrl
& ECNTRL_REDUCED_MODE
) {
417 if (ecntrl
& ECNTRL_REDUCED_MII_MODE
)
418 return PHY_INTERFACE_MODE_RMII
;
420 phy_interface_t interface
= priv
->einfo
->interface
;
423 * This isn't autodetected right now, so it must
424 * be set by the device tree or platform code.
426 if (interface
== PHY_INTERFACE_MODE_RGMII_ID
)
427 return PHY_INTERFACE_MODE_RGMII_ID
;
429 return PHY_INTERFACE_MODE_RGMII
;
433 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
)
434 return PHY_INTERFACE_MODE_GMII
;
436 return PHY_INTERFACE_MODE_MII
;
440 /* Initializes driver's PHY state, and attaches to the PHY.
441 * Returns 0 on success.
443 static int init_phy(struct net_device
*dev
)
445 struct gfar_private
*priv
= netdev_priv(dev
);
446 uint gigabit_support
=
447 priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
?
448 SUPPORTED_1000baseT_Full
: 0;
449 struct phy_device
*phydev
;
450 char phy_id
[BUS_ID_SIZE
];
451 phy_interface_t interface
;
455 priv
->oldduplex
= -1;
457 snprintf(phy_id
, BUS_ID_SIZE
, PHY_ID_FMT
, priv
->einfo
->bus_id
, priv
->einfo
->phy_id
);
459 interface
= gfar_get_interface(dev
);
461 phydev
= phy_connect(dev
, phy_id
, &adjust_link
, 0, interface
);
463 if (interface
== PHY_INTERFACE_MODE_SGMII
)
464 gfar_configure_serdes(dev
);
466 if (IS_ERR(phydev
)) {
467 printk(KERN_ERR
"%s: Could not attach to PHY\n", dev
->name
);
468 return PTR_ERR(phydev
);
471 /* Remove any features not supported by the controller */
472 phydev
->supported
&= (GFAR_SUPPORTED
| gigabit_support
);
473 phydev
->advertising
= phydev
->supported
;
475 priv
->phydev
= phydev
;
480 static void gfar_configure_serdes(struct net_device
*dev
)
482 struct gfar_private
*priv
= netdev_priv(dev
);
483 struct gfar_mii __iomem
*regs
=
484 (void __iomem
*)&priv
->regs
->gfar_mii_regs
;
486 /* Initialise TBI i/f to communicate with serdes (lynx phy) */
488 /* Single clk mode, mii mode off(for aerdes communication) */
489 gfar_local_mdio_write(regs
, TBIPA_VALUE
, MII_TBICON
, TBICON_CLK_SELECT
);
491 /* Supported pause and full-duplex, no half-duplex */
492 gfar_local_mdio_write(regs
, TBIPA_VALUE
, MII_ADVERTISE
,
493 ADVERTISE_1000XFULL
| ADVERTISE_1000XPAUSE
|
494 ADVERTISE_1000XPSE_ASYM
);
496 /* ANEG enable, restart ANEG, full duplex mode, speed[1] set */
497 gfar_local_mdio_write(regs
, TBIPA_VALUE
, MII_BMCR
, BMCR_ANENABLE
|
498 BMCR_ANRESTART
| BMCR_FULLDPLX
| BMCR_SPEED1000
);
501 static void init_registers(struct net_device
*dev
)
503 struct gfar_private
*priv
= netdev_priv(dev
);
506 gfar_write(&priv
->regs
->ievent
, IEVENT_INIT_CLEAR
);
508 /* Initialize IMASK */
509 gfar_write(&priv
->regs
->imask
, IMASK_INIT_CLEAR
);
511 /* Init hash registers to zero */
512 gfar_write(&priv
->regs
->igaddr0
, 0);
513 gfar_write(&priv
->regs
->igaddr1
, 0);
514 gfar_write(&priv
->regs
->igaddr2
, 0);
515 gfar_write(&priv
->regs
->igaddr3
, 0);
516 gfar_write(&priv
->regs
->igaddr4
, 0);
517 gfar_write(&priv
->regs
->igaddr5
, 0);
518 gfar_write(&priv
->regs
->igaddr6
, 0);
519 gfar_write(&priv
->regs
->igaddr7
, 0);
521 gfar_write(&priv
->regs
->gaddr0
, 0);
522 gfar_write(&priv
->regs
->gaddr1
, 0);
523 gfar_write(&priv
->regs
->gaddr2
, 0);
524 gfar_write(&priv
->regs
->gaddr3
, 0);
525 gfar_write(&priv
->regs
->gaddr4
, 0);
526 gfar_write(&priv
->regs
->gaddr5
, 0);
527 gfar_write(&priv
->regs
->gaddr6
, 0);
528 gfar_write(&priv
->regs
->gaddr7
, 0);
530 /* Zero out the rmon mib registers if it has them */
531 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_RMON
) {
532 memset_io(&(priv
->regs
->rmon
), 0, sizeof (struct rmon_mib
));
534 /* Mask off the CAM interrupts */
535 gfar_write(&priv
->regs
->rmon
.cam1
, 0xffffffff);
536 gfar_write(&priv
->regs
->rmon
.cam2
, 0xffffffff);
539 /* Initialize the max receive buffer length */
540 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
542 /* Initialize the Minimum Frame Length Register */
543 gfar_write(&priv
->regs
->minflr
, MINFLR_INIT_SETTINGS
);
545 /* Assign the TBI an address which won't conflict with the PHYs */
546 gfar_write(&priv
->regs
->tbipa
, TBIPA_VALUE
);
550 /* Halt the receive and transmit queues */
551 void gfar_halt(struct net_device
*dev
)
553 struct gfar_private
*priv
= netdev_priv(dev
);
554 struct gfar __iomem
*regs
= priv
->regs
;
557 /* Mask all interrupts */
558 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
560 /* Clear all interrupts */
561 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
563 /* Stop the DMA, and wait for it to stop */
564 tempval
= gfar_read(&priv
->regs
->dmactrl
);
565 if ((tempval
& (DMACTRL_GRS
| DMACTRL_GTS
))
566 != (DMACTRL_GRS
| DMACTRL_GTS
)) {
567 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
568 gfar_write(&priv
->regs
->dmactrl
, tempval
);
570 while (!(gfar_read(&priv
->regs
->ievent
) &
571 (IEVENT_GRSC
| IEVENT_GTSC
)))
575 /* Disable Rx and Tx */
576 tempval
= gfar_read(®s
->maccfg1
);
577 tempval
&= ~(MACCFG1_RX_EN
| MACCFG1_TX_EN
);
578 gfar_write(®s
->maccfg1
, tempval
);
581 void stop_gfar(struct net_device
*dev
)
583 struct gfar_private
*priv
= netdev_priv(dev
);
584 struct gfar __iomem
*regs
= priv
->regs
;
587 phy_stop(priv
->phydev
);
590 spin_lock_irqsave(&priv
->txlock
, flags
);
591 spin_lock(&priv
->rxlock
);
595 spin_unlock(&priv
->rxlock
);
596 spin_unlock_irqrestore(&priv
->txlock
, flags
);
599 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
600 free_irq(priv
->interruptError
, dev
);
601 free_irq(priv
->interruptTransmit
, dev
);
602 free_irq(priv
->interruptReceive
, dev
);
604 free_irq(priv
->interruptTransmit
, dev
);
607 free_skb_resources(priv
);
609 dma_free_coherent(NULL
,
610 sizeof(struct txbd8
)*priv
->tx_ring_size
611 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
613 gfar_read(®s
->tbase0
));
616 /* If there are any tx skbs or rx skbs still around, free them.
617 * Then free tx_skbuff and rx_skbuff */
618 static void free_skb_resources(struct gfar_private
*priv
)
624 /* Go through all the buffer descriptors and free their data buffers */
625 txbdp
= priv
->tx_bd_base
;
627 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
629 if (priv
->tx_skbuff
[i
]) {
630 dma_unmap_single(NULL
, txbdp
->bufPtr
,
633 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
634 priv
->tx_skbuff
[i
] = NULL
;
638 kfree(priv
->tx_skbuff
);
640 rxbdp
= priv
->rx_bd_base
;
642 /* rx_skbuff is not guaranteed to be allocated, so only
643 * free it and its contents if it is allocated */
644 if(priv
->rx_skbuff
!= NULL
) {
645 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
646 if (priv
->rx_skbuff
[i
]) {
647 dma_unmap_single(NULL
, rxbdp
->bufPtr
,
648 priv
->rx_buffer_size
,
651 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
652 priv
->rx_skbuff
[i
] = NULL
;
662 kfree(priv
->rx_skbuff
);
666 void gfar_start(struct net_device
*dev
)
668 struct gfar_private
*priv
= netdev_priv(dev
);
669 struct gfar __iomem
*regs
= priv
->regs
;
672 /* Enable Rx and Tx in MACCFG1 */
673 tempval
= gfar_read(®s
->maccfg1
);
674 tempval
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
675 gfar_write(®s
->maccfg1
, tempval
);
677 /* Initialize DMACTRL to have WWR and WOP */
678 tempval
= gfar_read(&priv
->regs
->dmactrl
);
679 tempval
|= DMACTRL_INIT_SETTINGS
;
680 gfar_write(&priv
->regs
->dmactrl
, tempval
);
682 /* Make sure we aren't stopped */
683 tempval
= gfar_read(&priv
->regs
->dmactrl
);
684 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
685 gfar_write(&priv
->regs
->dmactrl
, tempval
);
687 /* Clear THLT/RHLT, so that the DMA starts polling now */
688 gfar_write(®s
->tstat
, TSTAT_CLEAR_THALT
);
689 gfar_write(®s
->rstat
, RSTAT_CLEAR_RHALT
);
691 /* Unmask the interrupts we look for */
692 gfar_write(®s
->imask
, IMASK_DEFAULT
);
695 /* Bring the controller up and running */
696 int startup_gfar(struct net_device
*dev
)
703 struct gfar_private
*priv
= netdev_priv(dev
);
704 struct gfar __iomem
*regs
= priv
->regs
;
709 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
711 /* Allocate memory for the buffer descriptors */
712 vaddr
= (unsigned long) dma_alloc_coherent(NULL
,
713 sizeof (struct txbd8
) * priv
->tx_ring_size
+
714 sizeof (struct rxbd8
) * priv
->rx_ring_size
,
718 if (netif_msg_ifup(priv
))
719 printk(KERN_ERR
"%s: Could not allocate buffer descriptors!\n",
724 priv
->tx_bd_base
= (struct txbd8
*) vaddr
;
726 /* enet DMA only understands physical addresses */
727 gfar_write(®s
->tbase0
, addr
);
729 /* Start the rx descriptor ring where the tx ring leaves off */
730 addr
= addr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
731 vaddr
= vaddr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
732 priv
->rx_bd_base
= (struct rxbd8
*) vaddr
;
733 gfar_write(®s
->rbase0
, addr
);
735 /* Setup the skbuff rings */
737 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
738 priv
->tx_ring_size
, GFP_KERNEL
);
740 if (NULL
== priv
->tx_skbuff
) {
741 if (netif_msg_ifup(priv
))
742 printk(KERN_ERR
"%s: Could not allocate tx_skbuff\n",
748 for (i
= 0; i
< priv
->tx_ring_size
; i
++)
749 priv
->tx_skbuff
[i
] = NULL
;
752 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
753 priv
->rx_ring_size
, GFP_KERNEL
);
755 if (NULL
== priv
->rx_skbuff
) {
756 if (netif_msg_ifup(priv
))
757 printk(KERN_ERR
"%s: Could not allocate rx_skbuff\n",
763 for (i
= 0; i
< priv
->rx_ring_size
; i
++)
764 priv
->rx_skbuff
[i
] = NULL
;
766 /* Initialize some variables in our dev structure */
767 priv
->dirty_tx
= priv
->cur_tx
= priv
->tx_bd_base
;
768 priv
->cur_rx
= priv
->rx_bd_base
;
769 priv
->skb_curtx
= priv
->skb_dirtytx
= 0;
772 /* Initialize Transmit Descriptor Ring */
773 txbdp
= priv
->tx_bd_base
;
774 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
781 /* Set the last descriptor in the ring to indicate wrap */
783 txbdp
->status
|= TXBD_WRAP
;
785 rxbdp
= priv
->rx_bd_base
;
786 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
787 struct sk_buff
*skb
= NULL
;
791 skb
= gfar_new_skb(dev
, rxbdp
);
793 priv
->rx_skbuff
[i
] = skb
;
798 /* Set the last descriptor in the ring to wrap */
800 rxbdp
->status
|= RXBD_WRAP
;
802 /* If the device has multiple interrupts, register for
803 * them. Otherwise, only register for the one */
804 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
805 /* Install our interrupt handlers for Error,
806 * Transmit, and Receive */
807 if (request_irq(priv
->interruptError
, gfar_error
,
808 0, "enet_error", dev
) < 0) {
809 if (netif_msg_intr(priv
))
810 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
811 dev
->name
, priv
->interruptError
);
817 if (request_irq(priv
->interruptTransmit
, gfar_transmit
,
818 0, "enet_tx", dev
) < 0) {
819 if (netif_msg_intr(priv
))
820 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
821 dev
->name
, priv
->interruptTransmit
);
828 if (request_irq(priv
->interruptReceive
, gfar_receive
,
829 0, "enet_rx", dev
) < 0) {
830 if (netif_msg_intr(priv
))
831 printk(KERN_ERR
"%s: Can't get IRQ %d (receive0)\n",
832 dev
->name
, priv
->interruptReceive
);
838 if (request_irq(priv
->interruptTransmit
, gfar_interrupt
,
839 0, "gfar_interrupt", dev
) < 0) {
840 if (netif_msg_intr(priv
))
841 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
842 dev
->name
, priv
->interruptError
);
849 phy_start(priv
->phydev
);
851 /* Configure the coalescing support */
852 if (priv
->txcoalescing
)
853 gfar_write(®s
->txic
,
854 mk_ic_value(priv
->txcount
, priv
->txtime
));
856 gfar_write(®s
->txic
, 0);
858 if (priv
->rxcoalescing
)
859 gfar_write(®s
->rxic
,
860 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
862 gfar_write(®s
->rxic
, 0);
864 if (priv
->rx_csum_enable
)
865 rctrl
|= RCTRL_CHECKSUMMING
;
867 if (priv
->extended_hash
) {
868 rctrl
|= RCTRL_EXTHASH
;
870 gfar_clear_exact_match(dev
);
874 if (priv
->vlan_enable
)
878 rctrl
&= ~RCTRL_PAL_MASK
;
879 rctrl
|= RCTRL_PADDING(priv
->padding
);
882 /* Init rctrl based on our settings */
883 gfar_write(&priv
->regs
->rctrl
, rctrl
);
885 if (dev
->features
& NETIF_F_IP_CSUM
)
886 gfar_write(&priv
->regs
->tctrl
, TCTRL_INIT_CSUM
);
888 /* Set the extraction length and index */
889 attrs
= ATTRELI_EL(priv
->rx_stash_size
) |
890 ATTRELI_EI(priv
->rx_stash_index
);
892 gfar_write(&priv
->regs
->attreli
, attrs
);
894 /* Start with defaults, and add stashing or locking
895 * depending on the approprate variables */
896 attrs
= ATTR_INIT_SETTINGS
;
898 if (priv
->bd_stash_en
)
899 attrs
|= ATTR_BDSTASH
;
901 if (priv
->rx_stash_size
!= 0)
902 attrs
|= ATTR_BUFSTASH
;
904 gfar_write(&priv
->regs
->attr
, attrs
);
906 gfar_write(&priv
->regs
->fifo_tx_thr
, priv
->fifo_threshold
);
907 gfar_write(&priv
->regs
->fifo_tx_starve
, priv
->fifo_starve
);
908 gfar_write(&priv
->regs
->fifo_tx_starve_shutoff
, priv
->fifo_starve_off
);
910 /* Start the controller */
916 free_irq(priv
->interruptTransmit
, dev
);
918 free_irq(priv
->interruptError
, dev
);
921 free_skb_resources(priv
);
923 dma_free_coherent(NULL
,
924 sizeof(struct txbd8
)*priv
->tx_ring_size
925 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
927 gfar_read(®s
->tbase0
));
932 /* Called when something needs to use the ethernet device */
933 /* Returns 0 for success. */
934 static int gfar_enet_open(struct net_device
*dev
)
936 struct gfar_private
*priv
= netdev_priv(dev
);
939 napi_enable(&priv
->napi
);
941 /* Initialize a bunch of registers */
944 gfar_set_mac_address(dev
);
949 napi_disable(&priv
->napi
);
953 err
= startup_gfar(dev
);
955 napi_disable(&priv
->napi
);
957 netif_start_queue(dev
);
962 static inline struct txfcb
*gfar_add_fcb(struct sk_buff
*skb
, struct txbd8
*bdp
)
964 struct txfcb
*fcb
= (struct txfcb
*)skb_push (skb
, GMAC_FCB_LEN
);
966 memset(fcb
, 0, GMAC_FCB_LEN
);
971 static inline void gfar_tx_checksum(struct sk_buff
*skb
, struct txfcb
*fcb
)
975 /* If we're here, it's a IP packet with a TCP or UDP
976 * payload. We set it to checksum, using a pseudo-header
979 flags
= TXFCB_DEFAULT
;
981 /* Tell the controller what the protocol is */
982 /* And provide the already calculated phcs */
983 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
) {
985 fcb
->phcs
= udp_hdr(skb
)->check
;
987 fcb
->phcs
= tcp_hdr(skb
)->check
;
989 /* l3os is the distance between the start of the
990 * frame (skb->data) and the start of the IP hdr.
991 * l4os is the distance between the start of the
992 * l3 hdr and the l4 hdr */
993 fcb
->l3os
= (u16
)(skb_network_offset(skb
) - GMAC_FCB_LEN
);
994 fcb
->l4os
= skb_network_header_len(skb
);
999 void inline gfar_tx_vlan(struct sk_buff
*skb
, struct txfcb
*fcb
)
1001 fcb
->flags
|= TXFCB_VLN
;
1002 fcb
->vlctl
= vlan_tx_tag_get(skb
);
1005 /* This is called by the kernel when a frame is ready for transmission. */
1006 /* It is pointed to by the dev->hard_start_xmit function pointer */
1007 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1009 struct gfar_private
*priv
= netdev_priv(dev
);
1010 struct txfcb
*fcb
= NULL
;
1011 struct txbd8
*txbdp
;
1013 unsigned long flags
;
1015 /* Update transmit stats */
1016 dev
->stats
.tx_bytes
+= skb
->len
;
1019 spin_lock_irqsave(&priv
->txlock
, flags
);
1021 /* Point at the first free tx descriptor */
1022 txbdp
= priv
->cur_tx
;
1024 /* Clear all but the WRAP status flags */
1025 status
= txbdp
->status
& TXBD_WRAP
;
1027 /* Set up checksumming */
1028 if (likely((dev
->features
& NETIF_F_IP_CSUM
)
1029 && (CHECKSUM_PARTIAL
== skb
->ip_summed
))) {
1030 fcb
= gfar_add_fcb(skb
, txbdp
);
1032 gfar_tx_checksum(skb
, fcb
);
1035 if (priv
->vlan_enable
&&
1036 unlikely(priv
->vlgrp
&& vlan_tx_tag_present(skb
))) {
1037 if (unlikely(NULL
== fcb
)) {
1038 fcb
= gfar_add_fcb(skb
, txbdp
);
1042 gfar_tx_vlan(skb
, fcb
);
1045 /* Set buffer length and pointer */
1046 txbdp
->length
= skb
->len
;
1047 txbdp
->bufPtr
= dma_map_single(NULL
, skb
->data
,
1048 skb
->len
, DMA_TO_DEVICE
);
1050 /* Save the skb pointer so we can free it later */
1051 priv
->tx_skbuff
[priv
->skb_curtx
] = skb
;
1053 /* Update the current skb pointer (wrapping if this was the last) */
1055 (priv
->skb_curtx
+ 1) & TX_RING_MOD_MASK(priv
->tx_ring_size
);
1057 /* Flag the BD as interrupt-causing */
1058 status
|= TXBD_INTERRUPT
;
1060 /* Flag the BD as ready to go, last in frame, and */
1061 /* in need of CRC */
1062 status
|= (TXBD_READY
| TXBD_LAST
| TXBD_CRC
);
1064 dev
->trans_start
= jiffies
;
1066 /* The powerpc-specific eieio() is used, as wmb() has too strong
1067 * semantics (it requires synchronization between cacheable and
1068 * uncacheable mappings, which eieio doesn't provide and which we
1069 * don't need), thus requiring a more expensive sync instruction. At
1070 * some point, the set of architecture-independent barrier functions
1071 * should be expanded to include weaker barriers.
1075 txbdp
->status
= status
;
1077 /* If this was the last BD in the ring, the next one */
1078 /* is at the beginning of the ring */
1079 if (txbdp
->status
& TXBD_WRAP
)
1080 txbdp
= priv
->tx_bd_base
;
1084 /* If the next BD still needs to be cleaned up, then the bds
1085 are full. We need to tell the kernel to stop sending us stuff. */
1086 if (txbdp
== priv
->dirty_tx
) {
1087 netif_stop_queue(dev
);
1089 dev
->stats
.tx_fifo_errors
++;
1092 /* Update the current txbd to the next one */
1093 priv
->cur_tx
= txbdp
;
1095 /* Tell the DMA to go go go */
1096 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1099 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1104 /* Stops the kernel queue, and halts the controller */
1105 static int gfar_close(struct net_device
*dev
)
1107 struct gfar_private
*priv
= netdev_priv(dev
);
1109 napi_disable(&priv
->napi
);
1113 /* Disconnect from the PHY */
1114 phy_disconnect(priv
->phydev
);
1115 priv
->phydev
= NULL
;
1117 netif_stop_queue(dev
);
1122 /* Changes the mac address if the controller is not running. */
1123 int gfar_set_mac_address(struct net_device
*dev
)
1125 gfar_set_mac_for_addr(dev
, 0, dev
->dev_addr
);
1131 /* Enables and disables VLAN insertion/extraction */
1132 static void gfar_vlan_rx_register(struct net_device
*dev
,
1133 struct vlan_group
*grp
)
1135 struct gfar_private
*priv
= netdev_priv(dev
);
1136 unsigned long flags
;
1139 spin_lock_irqsave(&priv
->rxlock
, flags
);
1144 /* Enable VLAN tag insertion */
1145 tempval
= gfar_read(&priv
->regs
->tctrl
);
1146 tempval
|= TCTRL_VLINS
;
1148 gfar_write(&priv
->regs
->tctrl
, tempval
);
1150 /* Enable VLAN tag extraction */
1151 tempval
= gfar_read(&priv
->regs
->rctrl
);
1152 tempval
|= RCTRL_VLEX
;
1153 gfar_write(&priv
->regs
->rctrl
, tempval
);
1155 /* Disable VLAN tag insertion */
1156 tempval
= gfar_read(&priv
->regs
->tctrl
);
1157 tempval
&= ~TCTRL_VLINS
;
1158 gfar_write(&priv
->regs
->tctrl
, tempval
);
1160 /* Disable VLAN tag extraction */
1161 tempval
= gfar_read(&priv
->regs
->rctrl
);
1162 tempval
&= ~RCTRL_VLEX
;
1163 gfar_write(&priv
->regs
->rctrl
, tempval
);
1166 spin_unlock_irqrestore(&priv
->rxlock
, flags
);
1169 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
)
1171 int tempsize
, tempval
;
1172 struct gfar_private
*priv
= netdev_priv(dev
);
1173 int oldsize
= priv
->rx_buffer_size
;
1174 int frame_size
= new_mtu
+ ETH_HLEN
;
1176 if (priv
->vlan_enable
)
1177 frame_size
+= VLAN_ETH_HLEN
;
1179 if (gfar_uses_fcb(priv
))
1180 frame_size
+= GMAC_FCB_LEN
;
1182 frame_size
+= priv
->padding
;
1184 if ((frame_size
< 64) || (frame_size
> JUMBO_FRAME_SIZE
)) {
1185 if (netif_msg_drv(priv
))
1186 printk(KERN_ERR
"%s: Invalid MTU setting\n",
1192 (frame_size
& ~(INCREMENTAL_BUFFER_SIZE
- 1)) +
1193 INCREMENTAL_BUFFER_SIZE
;
1195 /* Only stop and start the controller if it isn't already
1196 * stopped, and we changed something */
1197 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1200 priv
->rx_buffer_size
= tempsize
;
1204 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
1205 gfar_write(&priv
->regs
->maxfrm
, priv
->rx_buffer_size
);
1207 /* If the mtu is larger than the max size for standard
1208 * ethernet frames (ie, a jumbo frame), then set maccfg2
1209 * to allow huge frames, and to check the length */
1210 tempval
= gfar_read(&priv
->regs
->maccfg2
);
1212 if (priv
->rx_buffer_size
> DEFAULT_RX_BUFFER_SIZE
)
1213 tempval
|= (MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1215 tempval
&= ~(MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1217 gfar_write(&priv
->regs
->maccfg2
, tempval
);
1219 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1225 /* gfar_timeout gets called when a packet has not been
1226 * transmitted after a set amount of time.
1227 * For now, assume that clearing out all the structures, and
1228 * starting over will fix the problem. */
1229 static void gfar_timeout(struct net_device
*dev
)
1231 struct gfar_private
*priv
= netdev_priv(dev
);
1233 dev
->stats
.tx_errors
++;
1235 if (dev
->flags
& IFF_UP
) {
1240 netif_schedule(dev
);
1243 /* Interrupt Handler for Transmit complete */
1244 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
)
1246 struct net_device
*dev
= (struct net_device
*) dev_id
;
1247 struct gfar_private
*priv
= netdev_priv(dev
);
1251 gfar_write(&priv
->regs
->ievent
, IEVENT_TX_MASK
);
1254 spin_lock(&priv
->txlock
);
1255 bdp
= priv
->dirty_tx
;
1256 while ((bdp
->status
& TXBD_READY
) == 0) {
1257 /* If dirty_tx and cur_tx are the same, then either the */
1258 /* ring is empty or full now (it could only be full in the beginning, */
1259 /* obviously). If it is empty, we are done. */
1260 if ((bdp
== priv
->cur_tx
) && (netif_queue_stopped(dev
) == 0))
1263 dev
->stats
.tx_packets
++;
1265 /* Deferred means some collisions occurred during transmit, */
1266 /* but we eventually sent the packet. */
1267 if (bdp
->status
& TXBD_DEF
)
1268 dev
->stats
.collisions
++;
1270 /* Free the sk buffer associated with this TxBD */
1271 dev_kfree_skb_irq(priv
->tx_skbuff
[priv
->skb_dirtytx
]);
1272 priv
->tx_skbuff
[priv
->skb_dirtytx
] = NULL
;
1274 (priv
->skb_dirtytx
+
1275 1) & TX_RING_MOD_MASK(priv
->tx_ring_size
);
1277 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1278 if (bdp
->status
& TXBD_WRAP
)
1279 bdp
= priv
->tx_bd_base
;
1283 /* Move dirty_tx to be the next bd */
1284 priv
->dirty_tx
= bdp
;
1286 /* We freed a buffer, so now we can restart transmission */
1287 if (netif_queue_stopped(dev
))
1288 netif_wake_queue(dev
);
1289 } /* while ((bdp->status & TXBD_READY) == 0) */
1291 /* If we are coalescing the interrupts, reset the timer */
1292 /* Otherwise, clear it */
1293 if (priv
->txcoalescing
)
1294 gfar_write(&priv
->regs
->txic
,
1295 mk_ic_value(priv
->txcount
, priv
->txtime
));
1297 gfar_write(&priv
->regs
->txic
, 0);
1299 spin_unlock(&priv
->txlock
);
1304 struct sk_buff
* gfar_new_skb(struct net_device
*dev
, struct rxbd8
*bdp
)
1306 unsigned int alignamount
;
1307 struct gfar_private
*priv
= netdev_priv(dev
);
1308 struct sk_buff
*skb
= NULL
;
1309 unsigned int timeout
= SKB_ALLOC_TIMEOUT
;
1311 /* We have to allocate the skb, so keep trying till we succeed */
1312 while ((!skb
) && timeout
--)
1313 skb
= dev_alloc_skb(priv
->rx_buffer_size
+ RXBUF_ALIGNMENT
);
1318 alignamount
= RXBUF_ALIGNMENT
-
1319 (((unsigned long) skb
->data
) & (RXBUF_ALIGNMENT
- 1));
1321 /* We need the data buffer to be aligned properly. We will reserve
1322 * as many bytes as needed to align the data properly
1324 skb_reserve(skb
, alignamount
);
1326 bdp
->bufPtr
= dma_map_single(NULL
, skb
->data
,
1327 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
1331 /* Mark the buffer empty */
1333 bdp
->status
|= (RXBD_EMPTY
| RXBD_INTERRUPT
);
1338 static inline void count_errors(unsigned short status
, struct gfar_private
*priv
)
1340 struct net_device_stats
*stats
= &dev
->stats
;
1341 struct gfar_extra_stats
*estats
= &priv
->extra_stats
;
1343 /* If the packet was truncated, none of the other errors
1345 if (status
& RXBD_TRUNCATED
) {
1346 stats
->rx_length_errors
++;
1352 /* Count the errors, if there were any */
1353 if (status
& (RXBD_LARGE
| RXBD_SHORT
)) {
1354 stats
->rx_length_errors
++;
1356 if (status
& RXBD_LARGE
)
1361 if (status
& RXBD_NONOCTET
) {
1362 stats
->rx_frame_errors
++;
1363 estats
->rx_nonoctet
++;
1365 if (status
& RXBD_CRCERR
) {
1366 estats
->rx_crcerr
++;
1367 stats
->rx_crc_errors
++;
1369 if (status
& RXBD_OVERRUN
) {
1370 estats
->rx_overrun
++;
1371 stats
->rx_crc_errors
++;
1375 irqreturn_t
gfar_receive(int irq
, void *dev_id
)
1377 struct net_device
*dev
= (struct net_device
*) dev_id
;
1378 struct gfar_private
*priv
= netdev_priv(dev
);
1379 #ifdef CONFIG_GFAR_NAPI
1382 unsigned long flags
;
1385 /* Clear IEVENT, so rx interrupt isn't called again
1386 * because of this interrupt */
1387 gfar_write(&priv
->regs
->ievent
, IEVENT_RX_MASK
);
1390 #ifdef CONFIG_GFAR_NAPI
1391 if (netif_rx_schedule_prep(dev
, &priv
->napi
)) {
1392 tempval
= gfar_read(&priv
->regs
->imask
);
1393 tempval
&= IMASK_RX_DISABLED
;
1394 gfar_write(&priv
->regs
->imask
, tempval
);
1396 __netif_rx_schedule(dev
, &priv
->napi
);
1398 if (netif_msg_rx_err(priv
))
1399 printk(KERN_DEBUG
"%s: receive called twice (%x)[%x]\n",
1400 dev
->name
, gfar_read(&priv
->regs
->ievent
),
1401 gfar_read(&priv
->regs
->imask
));
1405 spin_lock_irqsave(&priv
->rxlock
, flags
);
1406 gfar_clean_rx_ring(dev
, priv
->rx_ring_size
);
1408 /* If we are coalescing interrupts, update the timer */
1409 /* Otherwise, clear it */
1410 if (priv
->rxcoalescing
)
1411 gfar_write(&priv
->regs
->rxic
,
1412 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
1414 gfar_write(&priv
->regs
->rxic
, 0);
1416 spin_unlock_irqrestore(&priv
->rxlock
, flags
);
1422 static inline int gfar_rx_vlan(struct sk_buff
*skb
,
1423 struct vlan_group
*vlgrp
, unsigned short vlctl
)
1425 #ifdef CONFIG_GFAR_NAPI
1426 return vlan_hwaccel_receive_skb(skb
, vlgrp
, vlctl
);
1428 return vlan_hwaccel_rx(skb
, vlgrp
, vlctl
);
1432 static inline void gfar_rx_checksum(struct sk_buff
*skb
, struct rxfcb
*fcb
)
1434 /* If valid headers were found, and valid sums
1435 * were verified, then we tell the kernel that no
1436 * checksumming is necessary. Otherwise, it is */
1437 if ((fcb
->flags
& RXFCB_CSUM_MASK
) == (RXFCB_CIP
| RXFCB_CTU
))
1438 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1440 skb
->ip_summed
= CHECKSUM_NONE
;
1444 static inline struct rxfcb
*gfar_get_fcb(struct sk_buff
*skb
)
1446 struct rxfcb
*fcb
= (struct rxfcb
*)skb
->data
;
1448 /* Remove the FCB from the skb */
1449 skb_pull(skb
, GMAC_FCB_LEN
);
1454 /* gfar_process_frame() -- handle one incoming packet if skb
1456 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
1459 struct gfar_private
*priv
= netdev_priv(dev
);
1460 struct rxfcb
*fcb
= NULL
;
1463 if (netif_msg_rx_err(priv
))
1464 printk(KERN_WARNING
"%s: Missing skb!!.\n", dev
->name
);
1465 dev
->stats
.rx_dropped
++;
1466 priv
->extra_stats
.rx_skbmissing
++;
1470 /* Prep the skb for the packet */
1471 skb_put(skb
, length
);
1473 /* Grab the FCB if there is one */
1474 if (gfar_uses_fcb(priv
))
1475 fcb
= gfar_get_fcb(skb
);
1477 /* Remove the padded bytes, if there are any */
1479 skb_pull(skb
, priv
->padding
);
1481 if (priv
->rx_csum_enable
)
1482 gfar_rx_checksum(skb
, fcb
);
1484 /* Tell the skb what kind of packet this is */
1485 skb
->protocol
= eth_type_trans(skb
, dev
);
1487 /* Send the packet up the stack */
1488 if (unlikely(priv
->vlgrp
&& (fcb
->flags
& RXFCB_VLN
)))
1489 ret
= gfar_rx_vlan(skb
, priv
->vlgrp
, fcb
->vlctl
);
1493 if (NET_RX_DROP
== ret
)
1494 priv
->extra_stats
.kernel_dropped
++;
1500 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1501 * until the budget/quota has been reached. Returns the number
1504 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
)
1507 struct sk_buff
*skb
;
1510 struct gfar_private
*priv
= netdev_priv(dev
);
1512 /* Get the first full descriptor */
1515 while (!((bdp
->status
& RXBD_EMPTY
) || (--rx_work_limit
< 0))) {
1517 skb
= priv
->rx_skbuff
[priv
->skb_currx
];
1520 (RXBD_LARGE
| RXBD_SHORT
| RXBD_NONOCTET
1521 | RXBD_CRCERR
| RXBD_OVERRUN
| RXBD_TRUNCATED
))) {
1522 /* Increment the number of packets */
1523 dev
->stats
.rx_packets
++;
1526 /* Remove the FCS from the packet length */
1527 pkt_len
= bdp
->length
- 4;
1529 gfar_process_frame(dev
, skb
, pkt_len
);
1531 dev
->stats
.rx_bytes
+= pkt_len
;
1533 count_errors(bdp
->status
, priv
);
1536 dev_kfree_skb_any(skb
);
1538 priv
->rx_skbuff
[priv
->skb_currx
] = NULL
;
1541 dev
->last_rx
= jiffies
;
1543 /* Clear the status flags for this buffer */
1544 bdp
->status
&= ~RXBD_STATS
;
1546 /* Add another skb for the future */
1547 skb
= gfar_new_skb(dev
, bdp
);
1548 priv
->rx_skbuff
[priv
->skb_currx
] = skb
;
1550 /* Update to the next pointer */
1551 if (bdp
->status
& RXBD_WRAP
)
1552 bdp
= priv
->rx_bd_base
;
1556 /* update to point at the next skb */
1559 1) & RX_RING_MOD_MASK(priv
->rx_ring_size
);
1563 /* Update the current rxbd pointer to be the next one */
1569 #ifdef CONFIG_GFAR_NAPI
1570 static int gfar_poll(struct napi_struct
*napi
, int budget
)
1572 struct gfar_private
*priv
= container_of(napi
, struct gfar_private
, napi
);
1573 struct net_device
*dev
= priv
->dev
;
1576 howmany
= gfar_clean_rx_ring(dev
, budget
);
1578 if (howmany
< budget
) {
1579 netif_rx_complete(dev
, napi
);
1581 /* Clear the halt bit in RSTAT */
1582 gfar_write(&priv
->regs
->rstat
, RSTAT_CLEAR_RHALT
);
1584 gfar_write(&priv
->regs
->imask
, IMASK_DEFAULT
);
1586 /* If we are coalescing interrupts, update the timer */
1587 /* Otherwise, clear it */
1588 if (priv
->rxcoalescing
)
1589 gfar_write(&priv
->regs
->rxic
,
1590 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
1592 gfar_write(&priv
->regs
->rxic
, 0);
1599 #ifdef CONFIG_NET_POLL_CONTROLLER
1601 * Polling 'interrupt' - used by things like netconsole to send skbs
1602 * without having to re-enable interrupts. It's not called while
1603 * the interrupt routine is executing.
1605 static void gfar_netpoll(struct net_device
*dev
)
1607 struct gfar_private
*priv
= netdev_priv(dev
);
1609 /* If the device has multiple interrupts, run tx/rx */
1610 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1611 disable_irq(priv
->interruptTransmit
);
1612 disable_irq(priv
->interruptReceive
);
1613 disable_irq(priv
->interruptError
);
1614 gfar_interrupt(priv
->interruptTransmit
, dev
);
1615 enable_irq(priv
->interruptError
);
1616 enable_irq(priv
->interruptReceive
);
1617 enable_irq(priv
->interruptTransmit
);
1619 disable_irq(priv
->interruptTransmit
);
1620 gfar_interrupt(priv
->interruptTransmit
, dev
);
1621 enable_irq(priv
->interruptTransmit
);
1626 /* The interrupt handler for devices with one interrupt */
1627 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
)
1629 struct net_device
*dev
= dev_id
;
1630 struct gfar_private
*priv
= netdev_priv(dev
);
1632 /* Save ievent for future reference */
1633 u32 events
= gfar_read(&priv
->regs
->ievent
);
1635 /* Check for reception */
1636 if (events
& IEVENT_RX_MASK
)
1637 gfar_receive(irq
, dev_id
);
1639 /* Check for transmit completion */
1640 if (events
& IEVENT_TX_MASK
)
1641 gfar_transmit(irq
, dev_id
);
1643 /* Check for errors */
1644 if (events
& IEVENT_ERR_MASK
)
1645 gfar_error(irq
, dev_id
);
1650 /* Called every time the controller might need to be made
1651 * aware of new link state. The PHY code conveys this
1652 * information through variables in the phydev structure, and this
1653 * function converts those variables into the appropriate
1654 * register values, and can bring down the device if needed.
1656 static void adjust_link(struct net_device
*dev
)
1658 struct gfar_private
*priv
= netdev_priv(dev
);
1659 struct gfar __iomem
*regs
= priv
->regs
;
1660 unsigned long flags
;
1661 struct phy_device
*phydev
= priv
->phydev
;
1664 spin_lock_irqsave(&priv
->txlock
, flags
);
1666 u32 tempval
= gfar_read(®s
->maccfg2
);
1667 u32 ecntrl
= gfar_read(®s
->ecntrl
);
1669 /* Now we make sure that we can be in full duplex mode.
1670 * If not, we operate in half-duplex mode. */
1671 if (phydev
->duplex
!= priv
->oldduplex
) {
1673 if (!(phydev
->duplex
))
1674 tempval
&= ~(MACCFG2_FULL_DUPLEX
);
1676 tempval
|= MACCFG2_FULL_DUPLEX
;
1678 priv
->oldduplex
= phydev
->duplex
;
1681 if (phydev
->speed
!= priv
->oldspeed
) {
1683 switch (phydev
->speed
) {
1686 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_GMII
);
1691 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_MII
);
1693 /* Reduced mode distinguishes
1694 * between 10 and 100 */
1695 if (phydev
->speed
== SPEED_100
)
1696 ecntrl
|= ECNTRL_R100
;
1698 ecntrl
&= ~(ECNTRL_R100
);
1701 if (netif_msg_link(priv
))
1703 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
1704 dev
->name
, phydev
->speed
);
1708 priv
->oldspeed
= phydev
->speed
;
1711 gfar_write(®s
->maccfg2
, tempval
);
1712 gfar_write(®s
->ecntrl
, ecntrl
);
1714 if (!priv
->oldlink
) {
1717 netif_schedule(dev
);
1719 } else if (priv
->oldlink
) {
1723 priv
->oldduplex
= -1;
1726 if (new_state
&& netif_msg_link(priv
))
1727 phy_print_status(phydev
);
1729 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1732 /* Update the hash table based on the current list of multicast
1733 * addresses we subscribe to. Also, change the promiscuity of
1734 * the device based on the flags (this function is called
1735 * whenever dev->flags is changed */
1736 static void gfar_set_multi(struct net_device
*dev
)
1738 struct dev_mc_list
*mc_ptr
;
1739 struct gfar_private
*priv
= netdev_priv(dev
);
1740 struct gfar __iomem
*regs
= priv
->regs
;
1743 if(dev
->flags
& IFF_PROMISC
) {
1744 /* Set RCTRL to PROM */
1745 tempval
= gfar_read(®s
->rctrl
);
1746 tempval
|= RCTRL_PROM
;
1747 gfar_write(®s
->rctrl
, tempval
);
1749 /* Set RCTRL to not PROM */
1750 tempval
= gfar_read(®s
->rctrl
);
1751 tempval
&= ~(RCTRL_PROM
);
1752 gfar_write(®s
->rctrl
, tempval
);
1755 if(dev
->flags
& IFF_ALLMULTI
) {
1756 /* Set the hash to rx all multicast frames */
1757 gfar_write(®s
->igaddr0
, 0xffffffff);
1758 gfar_write(®s
->igaddr1
, 0xffffffff);
1759 gfar_write(®s
->igaddr2
, 0xffffffff);
1760 gfar_write(®s
->igaddr3
, 0xffffffff);
1761 gfar_write(®s
->igaddr4
, 0xffffffff);
1762 gfar_write(®s
->igaddr5
, 0xffffffff);
1763 gfar_write(®s
->igaddr6
, 0xffffffff);
1764 gfar_write(®s
->igaddr7
, 0xffffffff);
1765 gfar_write(®s
->gaddr0
, 0xffffffff);
1766 gfar_write(®s
->gaddr1
, 0xffffffff);
1767 gfar_write(®s
->gaddr2
, 0xffffffff);
1768 gfar_write(®s
->gaddr3
, 0xffffffff);
1769 gfar_write(®s
->gaddr4
, 0xffffffff);
1770 gfar_write(®s
->gaddr5
, 0xffffffff);
1771 gfar_write(®s
->gaddr6
, 0xffffffff);
1772 gfar_write(®s
->gaddr7
, 0xffffffff);
1777 /* zero out the hash */
1778 gfar_write(®s
->igaddr0
, 0x0);
1779 gfar_write(®s
->igaddr1
, 0x0);
1780 gfar_write(®s
->igaddr2
, 0x0);
1781 gfar_write(®s
->igaddr3
, 0x0);
1782 gfar_write(®s
->igaddr4
, 0x0);
1783 gfar_write(®s
->igaddr5
, 0x0);
1784 gfar_write(®s
->igaddr6
, 0x0);
1785 gfar_write(®s
->igaddr7
, 0x0);
1786 gfar_write(®s
->gaddr0
, 0x0);
1787 gfar_write(®s
->gaddr1
, 0x0);
1788 gfar_write(®s
->gaddr2
, 0x0);
1789 gfar_write(®s
->gaddr3
, 0x0);
1790 gfar_write(®s
->gaddr4
, 0x0);
1791 gfar_write(®s
->gaddr5
, 0x0);
1792 gfar_write(®s
->gaddr6
, 0x0);
1793 gfar_write(®s
->gaddr7
, 0x0);
1795 /* If we have extended hash tables, we need to
1796 * clear the exact match registers to prepare for
1798 if (priv
->extended_hash
) {
1799 em_num
= GFAR_EM_NUM
+ 1;
1800 gfar_clear_exact_match(dev
);
1807 if(dev
->mc_count
== 0)
1810 /* Parse the list, and set the appropriate bits */
1811 for(mc_ptr
= dev
->mc_list
; mc_ptr
; mc_ptr
= mc_ptr
->next
) {
1813 gfar_set_mac_for_addr(dev
, idx
,
1817 gfar_set_hash_for_addr(dev
, mc_ptr
->dmi_addr
);
1825 /* Clears each of the exact match registers to zero, so they
1826 * don't interfere with normal reception */
1827 static void gfar_clear_exact_match(struct net_device
*dev
)
1830 u8 zero_arr
[MAC_ADDR_LEN
] = {0,0,0,0,0,0};
1832 for(idx
= 1;idx
< GFAR_EM_NUM
+ 1;idx
++)
1833 gfar_set_mac_for_addr(dev
, idx
, (u8
*)zero_arr
);
1836 /* Set the appropriate hash bit for the given addr */
1837 /* The algorithm works like so:
1838 * 1) Take the Destination Address (ie the multicast address), and
1839 * do a CRC on it (little endian), and reverse the bits of the
1841 * 2) Use the 8 most significant bits as a hash into a 256-entry
1842 * table. The table is controlled through 8 32-bit registers:
1843 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1844 * gaddr7. This means that the 3 most significant bits in the
1845 * hash index which gaddr register to use, and the 5 other bits
1846 * indicate which bit (assuming an IBM numbering scheme, which
1847 * for PowerPC (tm) is usually the case) in the register holds
1849 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
)
1852 struct gfar_private
*priv
= netdev_priv(dev
);
1853 u32 result
= ether_crc(MAC_ADDR_LEN
, addr
);
1854 int width
= priv
->hash_width
;
1855 u8 whichbit
= (result
>> (32 - width
)) & 0x1f;
1856 u8 whichreg
= result
>> (32 - width
+ 5);
1857 u32 value
= (1 << (31-whichbit
));
1859 tempval
= gfar_read(priv
->hash_regs
[whichreg
]);
1861 gfar_write(priv
->hash_regs
[whichreg
], tempval
);
1867 /* There are multiple MAC Address register pairs on some controllers
1868 * This function sets the numth pair to a given address
1870 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
)
1872 struct gfar_private
*priv
= netdev_priv(dev
);
1874 char tmpbuf
[MAC_ADDR_LEN
];
1876 u32 __iomem
*macptr
= &priv
->regs
->macstnaddr1
;
1880 /* Now copy it into the mac registers backwards, cuz */
1881 /* little endian is silly */
1882 for (idx
= 0; idx
< MAC_ADDR_LEN
; idx
++)
1883 tmpbuf
[MAC_ADDR_LEN
- 1 - idx
] = addr
[idx
];
1885 gfar_write(macptr
, *((u32
*) (tmpbuf
)));
1887 tempval
= *((u32
*) (tmpbuf
+ 4));
1889 gfar_write(macptr
+1, tempval
);
1892 /* GFAR error interrupt handler */
1893 static irqreturn_t
gfar_error(int irq
, void *dev_id
)
1895 struct net_device
*dev
= dev_id
;
1896 struct gfar_private
*priv
= netdev_priv(dev
);
1898 /* Save ievent for future reference */
1899 u32 events
= gfar_read(&priv
->regs
->ievent
);
1902 gfar_write(&priv
->regs
->ievent
, IEVENT_ERR_MASK
);
1905 if (netif_msg_rx_err(priv
) || netif_msg_tx_err(priv
))
1906 printk(KERN_DEBUG
"%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1907 dev
->name
, events
, gfar_read(&priv
->regs
->imask
));
1909 /* Update the error counters */
1910 if (events
& IEVENT_TXE
) {
1911 dev
->stats
.tx_errors
++;
1913 if (events
& IEVENT_LC
)
1914 dev
->stats
.tx_window_errors
++;
1915 if (events
& IEVENT_CRL
)
1916 dev
->stats
.tx_aborted_errors
++;
1917 if (events
& IEVENT_XFUN
) {
1918 if (netif_msg_tx_err(priv
))
1919 printk(KERN_DEBUG
"%s: TX FIFO underrun, "
1920 "packet dropped.\n", dev
->name
);
1921 dev
->stats
.tx_dropped
++;
1922 priv
->extra_stats
.tx_underrun
++;
1924 /* Reactivate the Tx Queues */
1925 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1927 if (netif_msg_tx_err(priv
))
1928 printk(KERN_DEBUG
"%s: Transmit Error\n", dev
->name
);
1930 if (events
& IEVENT_BSY
) {
1931 dev
->stats
.rx_errors
++;
1932 priv
->extra_stats
.rx_bsy
++;
1934 gfar_receive(irq
, dev_id
);
1936 #ifndef CONFIG_GFAR_NAPI
1937 /* Clear the halt bit in RSTAT */
1938 gfar_write(&priv
->regs
->rstat
, RSTAT_CLEAR_RHALT
);
1941 if (netif_msg_rx_err(priv
))
1942 printk(KERN_DEBUG
"%s: busy error (rstat: %x)\n",
1943 dev
->name
, gfar_read(&priv
->regs
->rstat
));
1945 if (events
& IEVENT_BABR
) {
1946 dev
->stats
.rx_errors
++;
1947 priv
->extra_stats
.rx_babr
++;
1949 if (netif_msg_rx_err(priv
))
1950 printk(KERN_DEBUG
"%s: babbling RX error\n", dev
->name
);
1952 if (events
& IEVENT_EBERR
) {
1953 priv
->extra_stats
.eberr
++;
1954 if (netif_msg_rx_err(priv
))
1955 printk(KERN_DEBUG
"%s: bus error\n", dev
->name
);
1957 if ((events
& IEVENT_RXC
) && netif_msg_rx_status(priv
))
1958 printk(KERN_DEBUG
"%s: control frame\n", dev
->name
);
1960 if (events
& IEVENT_BABT
) {
1961 priv
->extra_stats
.tx_babt
++;
1962 if (netif_msg_tx_err(priv
))
1963 printk(KERN_DEBUG
"%s: babbling TX error\n", dev
->name
);
1968 /* Structure for a device driver */
1969 static struct platform_driver gfar_driver
= {
1970 .probe
= gfar_probe
,
1971 .remove
= gfar_remove
,
1973 .name
= "fsl-gianfar",
1977 static int __init
gfar_init(void)
1979 int err
= gfar_mdio_init();
1984 err
= platform_driver_register(&gfar_driver
);
1992 static void __exit
gfar_exit(void)
1994 platform_driver_unregister(&gfar_driver
);
1998 module_init(gfar_init
);
1999 module_exit(gfar_exit
);