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mlx4_core: Support multiple pre-reserved QP regions
[linux-2.6.git] / drivers / net / mlx4 / fw.c
blob40d8142c23b262d78e1d30fcec899f26bf9ecfae
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/mlx4/cmd.h>
36
37 #include "fw.h"
38 #include "icm.h"
39
40 enum {
41 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
42 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
43 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
44 };
45
46 extern void __buggy_use_of_MLX4_GET(void);
47 extern void __buggy_use_of_MLX4_PUT(void);
48
49 static int enable_qos;
50 module_param(enable_qos, bool, 0444);
51 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
52
53 #define MLX4_GET(dest, source, offset) \
54 do { \
55 void *__p = (char *) (source) + (offset); \
56 switch (sizeof (dest)) { \
57 case 1: (dest) = *(u8 *) __p; break; \
58 case 2: (dest) = be16_to_cpup(__p); break; \
59 case 4: (dest) = be32_to_cpup(__p); break; \
60 case 8: (dest) = be64_to_cpup(__p); break; \
61 default: __buggy_use_of_MLX4_GET(); \
62 } \
63 } while (0)
64
65 #define MLX4_PUT(dest, source, offset) \
66 do { \
67 void *__d = ((char *) (dest) + (offset)); \
68 switch (sizeof(source)) { \
69 case 1: *(u8 *) __d = (source); break; \
70 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
71 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
72 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
73 default: __buggy_use_of_MLX4_PUT(); \
74 } \
75 } while (0)
76
77 static void dump_dev_cap_flags(struct mlx4_dev *dev, u32 flags)
78 {
79 static const char *fname[] = {
80 [ 0] = "RC transport",
81 [ 1] = "UC transport",
82 [ 2] = "UD transport",
83 [ 3] = "XRC transport",
84 [ 4] = "reliable multicast",
85 [ 5] = "FCoIB support",
86 [ 6] = "SRQ support",
87 [ 7] = "IPoIB checksum offload",
88 [ 8] = "P_Key violation counter",
89 [ 9] = "Q_Key violation counter",
90 [10] = "VMM",
91 [16] = "MW support",
92 [17] = "APM support",
93 [18] = "Atomic ops support",
94 [19] = "Raw multicast support",
95 [20] = "Address vector port checking support",
96 [21] = "UD multicast support",
97 [24] = "Demand paging support",
98 [25] = "Router support"
99 };
100 int i;
101
102 mlx4_dbg(dev, "DEV_CAP flags:\n");
103 for (i = 0; i < ARRAY_SIZE(fname); ++i)
104 if (fname[i] && (flags & (1 << i)))
105 mlx4_dbg(dev, " %s\n", fname[i]);
106 }
107
108 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
109 {
110 struct mlx4_cmd_mailbox *mailbox;
111 u32 *inbox;
112 int err = 0;
113
114 #define MOD_STAT_CFG_IN_SIZE 0x100
115
116 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
117 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
118
119 mailbox = mlx4_alloc_cmd_mailbox(dev);
120 if (IS_ERR(mailbox))
121 return PTR_ERR(mailbox);
122 inbox = mailbox->buf;
123
124 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
125
126 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
127 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
128
129 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
130 MLX4_CMD_TIME_CLASS_A);
131
132 mlx4_free_cmd_mailbox(dev, mailbox);
133 return err;
134 }
135
136 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
137 {
138 struct mlx4_cmd_mailbox *mailbox;
139 u32 *outbox;
140 u8 field;
141 u16 size;
142 u16 stat_rate;
143 int err;
144 int i;
145
146 #define QUERY_DEV_CAP_OUT_SIZE 0x100
147 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
148 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
149 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
150 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
151 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
152 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
153 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
154 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
155 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
156 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
157 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
158 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
159 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
160 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
161 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
162 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
163 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
164 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
165 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
166 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
167 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
168 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
169 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
170 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
171 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
172 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
173 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
174 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
175 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
176 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
177 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
178 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
179 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
180 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
181 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
182 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
183 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
184 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
185 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
186 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
187 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
188 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
189 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
190 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
191 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
192 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
193 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
194 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
195 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
196 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
197 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
198 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
199 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
200 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
201 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
202 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
203 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
204 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
205 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
206 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
207 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
208
209 mailbox = mlx4_alloc_cmd_mailbox(dev);
210 if (IS_ERR(mailbox))
211 return PTR_ERR(mailbox);
212 outbox = mailbox->buf;
213
214 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
215 MLX4_CMD_TIME_CLASS_A);
216 if (err)
217 goto out;
218
219 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
220 dev_cap->reserved_qps = 1 << (field & 0xf);
221 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
222 dev_cap->max_qps = 1 << (field & 0x1f);
223 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
224 dev_cap->reserved_srqs = 1 << (field >> 4);
225 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
226 dev_cap->max_srqs = 1 << (field & 0x1f);
227 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
228 dev_cap->max_cq_sz = 1 << field;
229 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
230 dev_cap->reserved_cqs = 1 << (field & 0xf);
231 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
232 dev_cap->max_cqs = 1 << (field & 0x1f);
233 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
234 dev_cap->max_mpts = 1 << (field & 0x3f);
235 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
236 dev_cap->reserved_eqs = 1 << (field & 0xf);
237 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
238 dev_cap->max_eqs = 1 << (field & 0xf);
239 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
240 dev_cap->reserved_mtts = 1 << (field >> 4);
241 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
242 dev_cap->max_mrw_sz = 1 << field;
243 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
244 dev_cap->reserved_mrws = 1 << (field & 0xf);
245 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
246 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
247 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
248 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
249 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
250 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
251 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
252 field &= 0x1f;
253 if (!field)
254 dev_cap->max_gso_sz = 0;
255 else
256 dev_cap->max_gso_sz = 1 << field;
257
258 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
259 dev_cap->max_rdma_global = 1 << (field & 0x3f);
260 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
261 dev_cap->local_ca_ack_delay = field & 0x1f;
262 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
263 dev_cap->num_ports = field & 0xf;
264 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
265 dev_cap->max_msg_sz = 1 << (field & 0x1f);
266 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
267 dev_cap->stat_rate_support = stat_rate;
268 MLX4_GET(dev_cap->flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
269 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
270 dev_cap->reserved_uars = field >> 4;
271 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
272 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
273 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
274 dev_cap->min_page_sz = 1 << field;
275
276 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
277 if (field & 0x80) {
278 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
279 dev_cap->bf_reg_size = 1 << (field & 0x1f);
280 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
281 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
282 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
283 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
284 } else {
285 dev_cap->bf_reg_size = 0;
286 mlx4_dbg(dev, "BlueFlame not available\n");
287 }
288
289 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
290 dev_cap->max_sq_sg = field;
291 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
292 dev_cap->max_sq_desc_sz = size;
293
294 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
295 dev_cap->max_qp_per_mcg = 1 << field;
296 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
297 dev_cap->reserved_mgms = field & 0xf;
298 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
299 dev_cap->max_mcgs = 1 << field;
300 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
301 dev_cap->reserved_pds = field >> 4;
302 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
303 dev_cap->max_pds = 1 << (field & 0x3f);
304
305 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
306 dev_cap->rdmarc_entry_sz = size;
307 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
308 dev_cap->qpc_entry_sz = size;
309 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
310 dev_cap->aux_entry_sz = size;
311 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
312 dev_cap->altc_entry_sz = size;
313 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
314 dev_cap->eqc_entry_sz = size;
315 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
316 dev_cap->cqc_entry_sz = size;
317 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
318 dev_cap->srq_entry_sz = size;
319 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
320 dev_cap->cmpt_entry_sz = size;
321 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
322 dev_cap->mtt_entry_sz = size;
323 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
324 dev_cap->dmpt_entry_sz = size;
325
326 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
327 dev_cap->max_srq_sz = 1 << field;
328 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
329 dev_cap->max_qp_sz = 1 << field;
330 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
331 dev_cap->resize_srq = field & 1;
332 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
333 dev_cap->max_rq_sg = field;
334 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
335 dev_cap->max_rq_desc_sz = size;
336
337 MLX4_GET(dev_cap->bmme_flags, outbox,
338 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
339 MLX4_GET(dev_cap->reserved_lkey, outbox,
340 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
341 MLX4_GET(dev_cap->max_icm_sz, outbox,
342 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
343
344 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
345 for (i = 1; i <= dev_cap->num_ports; ++i) {
346 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
347 dev_cap->max_vl[i] = field >> 4;
348 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
349 dev_cap->max_mtu[i] = field >> 4;
350 dev_cap->max_port_width[i] = field & 0xf;
351 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
352 dev_cap->max_gids[i] = 1 << (field & 0xf);
353 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
354 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
355 }
356 } else {
357 #define QUERY_PORT_MTU_OFFSET 0x01
358 #define QUERY_PORT_WIDTH_OFFSET 0x06
359 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
360 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
361 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
362
363 for (i = 1; i <= dev_cap->num_ports; ++i) {
364 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
365 MLX4_CMD_TIME_CLASS_B);
366 if (err)
367 goto out;
368
369 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
370 dev_cap->max_mtu[i] = field & 0xf;
371 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
372 dev_cap->max_port_width[i] = field & 0xf;
373 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
374 dev_cap->max_gids[i] = 1 << (field >> 4);
375 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
376 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
377 dev_cap->max_vl[i] = field & 0xf;
378 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
379 dev_cap->log_max_macs[i] = field & 0xf;
380 dev_cap->log_max_vlans[i] = field >> 4;
381
382 }
383 }
384
385 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
386 dev_cap->bmme_flags, dev_cap->reserved_lkey);
387
388 /*
389 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
390 * we can't use any EQs whose doorbell falls on that page,
391 * even if the EQ itself isn't reserved.
392 */
393 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
394 dev_cap->reserved_eqs);
395
396 mlx4_dbg(dev, "Max ICM size %lld MB\n",
397 (unsigned long long) dev_cap->max_icm_sz >> 20);
398 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
399 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
400 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
401 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
402 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
403 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
404 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
405 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
406 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
407 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
408 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
409 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
410 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
411 dev_cap->max_pds, dev_cap->reserved_mgms);
412 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
413 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
414 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
415 dev_cap->local_ca_ack_delay, 128 << dev_cap->max_mtu[1],
416 dev_cap->max_port_width[1]);
417 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
418 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
419 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
420 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
421 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
422
423 dump_dev_cap_flags(dev, dev_cap->flags);
424
425 out:
426 mlx4_free_cmd_mailbox(dev, mailbox);
427 return err;
428 }
429
430 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
431 {
432 struct mlx4_cmd_mailbox *mailbox;
433 struct mlx4_icm_iter iter;
434 __be64 *pages;
435 int lg;
436 int nent = 0;
437 int i;
438 int err = 0;
439 int ts = 0, tc = 0;
440
441 mailbox = mlx4_alloc_cmd_mailbox(dev);
442 if (IS_ERR(mailbox))
443 return PTR_ERR(mailbox);
444 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
445 pages = mailbox->buf;
446
447 for (mlx4_icm_first(icm, &iter);
448 !mlx4_icm_last(&iter);
449 mlx4_icm_next(&iter)) {
450 /*
451 * We have to pass pages that are aligned to their
452 * size, so find the least significant 1 in the
453 * address or size and use that as our log2 size.
454 */
455 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
456 if (lg < MLX4_ICM_PAGE_SHIFT) {
457 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
458 MLX4_ICM_PAGE_SIZE,
459 (unsigned long long) mlx4_icm_addr(&iter),
460 mlx4_icm_size(&iter));
461 err = -EINVAL;
462 goto out;
463 }
464
465 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
466 if (virt != -1) {
467 pages[nent * 2] = cpu_to_be64(virt);
468 virt += 1 << lg;
469 }
470
471 pages[nent * 2 + 1] =
472 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
473 (lg - MLX4_ICM_PAGE_SHIFT));
474 ts += 1 << (lg - 10);
475 ++tc;
476
477 if (++nent == MLX4_MAILBOX_SIZE / 16) {
478 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
479 MLX4_CMD_TIME_CLASS_B);
480 if (err)
481 goto out;
482 nent = 0;
483 }
484 }
485 }
486
487 if (nent)
488 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B);
489 if (err)
490 goto out;
491
492 switch (op) {
493 case MLX4_CMD_MAP_FA:
494 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
495 break;
496 case MLX4_CMD_MAP_ICM_AUX:
497 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
498 break;
499 case MLX4_CMD_MAP_ICM:
500 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
501 tc, ts, (unsigned long long) virt - (ts << 10));
502 break;
503 }
504
505 out:
506 mlx4_free_cmd_mailbox(dev, mailbox);
507 return err;
508 }
509
510 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
511 {
512 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
513 }
514
515 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
516 {
517 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B);
518 }
519
520
521 int mlx4_RUN_FW(struct mlx4_dev *dev)
522 {
523 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A);
524 }
525
526 int mlx4_QUERY_FW(struct mlx4_dev *dev)
527 {
528 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
529 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
530 struct mlx4_cmd_mailbox *mailbox;
531 u32 *outbox;
532 int err = 0;
533 u64 fw_ver;
534 u16 cmd_if_rev;
535 u8 lg;
536
537 #define QUERY_FW_OUT_SIZE 0x100
538 #define QUERY_FW_VER_OFFSET 0x00
539 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
540 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
541 #define QUERY_FW_ERR_START_OFFSET 0x30
542 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
543 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
544
545 #define QUERY_FW_SIZE_OFFSET 0x00
546 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
547 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
548
549 mailbox = mlx4_alloc_cmd_mailbox(dev);
550 if (IS_ERR(mailbox))
551 return PTR_ERR(mailbox);
552 outbox = mailbox->buf;
553
554 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
555 MLX4_CMD_TIME_CLASS_A);
556 if (err)
557 goto out;
558
559 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
560 /*
561 * FW subminor version is at more significant bits than minor
562 * version, so swap here.
563 */
564 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
565 ((fw_ver & 0xffff0000ull) >> 16) |
566 ((fw_ver & 0x0000ffffull) << 16);
567
568 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
569 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
570 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
571 mlx4_err(dev, "Installed FW has unsupported "
572 "command interface revision %d.\n",
573 cmd_if_rev);
574 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
575 (int) (dev->caps.fw_ver >> 32),
576 (int) (dev->caps.fw_ver >> 16) & 0xffff,
577 (int) dev->caps.fw_ver & 0xffff);
578 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
579 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
580 err = -ENODEV;
581 goto out;
582 }
583
584 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
585 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
586
587 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
588 cmd->max_cmds = 1 << lg;
589
590 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
591 (int) (dev->caps.fw_ver >> 32),
592 (int) (dev->caps.fw_ver >> 16) & 0xffff,
593 (int) dev->caps.fw_ver & 0xffff,
594 cmd_if_rev, cmd->max_cmds);
595
596 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
597 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
598 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
599 fw->catas_bar = (fw->catas_bar >> 6) * 2;
600
601 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
602 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
603
604 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
605 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
606 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
607 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
608
609 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
610
611 /*
612 * Round up number of system pages needed in case
613 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
614 */
615 fw->fw_pages =
616 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
617 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
618
619 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
620 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
621
622 out:
623 mlx4_free_cmd_mailbox(dev, mailbox);
624 return err;
625 }
626
627 static void get_board_id(void *vsd, char *board_id)
628 {
629 int i;
630
631 #define VSD_OFFSET_SIG1 0x00
632 #define VSD_OFFSET_SIG2 0xde
633 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
634 #define VSD_OFFSET_TS_BOARD_ID 0x20
635
636 #define VSD_SIGNATURE_TOPSPIN 0x5ad
637
638 memset(board_id, 0, MLX4_BOARD_ID_LEN);
639
640 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
641 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
642 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
643 } else {
644 /*
645 * The board ID is a string but the firmware byte
646 * swaps each 4-byte word before passing it back to
647 * us. Therefore we need to swab it before printing.
648 */
649 for (i = 0; i < 4; ++i)
650 ((u32 *) board_id)[i] =
651 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
652 }
653 }
654
655 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
656 {
657 struct mlx4_cmd_mailbox *mailbox;
658 u32 *outbox;
659 int err;
660
661 #define QUERY_ADAPTER_OUT_SIZE 0x100
662 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
663 #define QUERY_ADAPTER_VSD_OFFSET 0x20
664
665 mailbox = mlx4_alloc_cmd_mailbox(dev);
666 if (IS_ERR(mailbox))
667 return PTR_ERR(mailbox);
668 outbox = mailbox->buf;
669
670 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
671 MLX4_CMD_TIME_CLASS_A);
672 if (err)
673 goto out;
674
675 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
676
677 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
678 adapter->board_id);
679
680 out:
681 mlx4_free_cmd_mailbox(dev, mailbox);
682 return err;
683 }
684
685 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
686 {
687 struct mlx4_cmd_mailbox *mailbox;
688 __be32 *inbox;
689 int err;
690
691 #define INIT_HCA_IN_SIZE 0x200
692 #define INIT_HCA_VERSION_OFFSET 0x000
693 #define INIT_HCA_VERSION 2
694 #define INIT_HCA_FLAGS_OFFSET 0x014
695 #define INIT_HCA_QPC_OFFSET 0x020
696 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
697 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
698 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
699 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
700 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
701 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
702 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
703 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
704 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
705 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
706 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
707 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
708 #define INIT_HCA_MCAST_OFFSET 0x0c0
709 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
710 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
711 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
712 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
713 #define INIT_HCA_TPT_OFFSET 0x0f0
714 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
715 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
716 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
717 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
718 #define INIT_HCA_UAR_OFFSET 0x120
719 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
720 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
721
722 mailbox = mlx4_alloc_cmd_mailbox(dev);
723 if (IS_ERR(mailbox))
724 return PTR_ERR(mailbox);
725 inbox = mailbox->buf;
726
727 memset(inbox, 0, INIT_HCA_IN_SIZE);
728
729 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
730
731 #if defined(__LITTLE_ENDIAN)
732 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
733 #elif defined(__BIG_ENDIAN)
734 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
735 #else
736 #error Host endianness not defined
737 #endif
738 /* Check port for UD address vector: */
739 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
740
741 /* Enable IPoIB checksumming if we can: */
742 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
743 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
744
745 /* Enable QoS support if module parameter set */
746 if (enable_qos)
747 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
748
749 /* QPC/EEC/CQC/EQC/RDMARC attributes */
750
751 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
752 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
753 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
754 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
755 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
756 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
757 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
758 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
759 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
760 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
761 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
762 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
763
764 /* multicast attributes */
765
766 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
767 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
768 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
769 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
770
771 /* TPT attributes */
772
773 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
774 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
775 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
776 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
777
778 /* UAR attributes */
779
780 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
781 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
782
783 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000);
784
785 if (err)
786 mlx4_err(dev, "INIT_HCA returns %d\n", err);
787
788 mlx4_free_cmd_mailbox(dev, mailbox);
789 return err;
790 }
791
792 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
793 {
794 struct mlx4_cmd_mailbox *mailbox;
795 u32 *inbox;
796 int err;
797 u32 flags;
798 u16 field;
799
800 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
801 #define INIT_PORT_IN_SIZE 256
802 #define INIT_PORT_FLAGS_OFFSET 0x00
803 #define INIT_PORT_FLAG_SIG (1 << 18)
804 #define INIT_PORT_FLAG_NG (1 << 17)
805 #define INIT_PORT_FLAG_G0 (1 << 16)
806 #define INIT_PORT_VL_SHIFT 4
807 #define INIT_PORT_PORT_WIDTH_SHIFT 8
808 #define INIT_PORT_MTU_OFFSET 0x04
809 #define INIT_PORT_MAX_GID_OFFSET 0x06
810 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
811 #define INIT_PORT_GUID0_OFFSET 0x10
812 #define INIT_PORT_NODE_GUID_OFFSET 0x18
813 #define INIT_PORT_SI_GUID_OFFSET 0x20
814
815 mailbox = mlx4_alloc_cmd_mailbox(dev);
816 if (IS_ERR(mailbox))
817 return PTR_ERR(mailbox);
818 inbox = mailbox->buf;
819
820 memset(inbox, 0, INIT_PORT_IN_SIZE);
821
822 flags = 0;
823 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
824 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
825 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
826
827 field = 128 << dev->caps.mtu_cap[port];
828 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
829 field = dev->caps.gid_table_len[port];
830 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
831 field = dev->caps.pkey_table_len[port];
832 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
833
834 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
835 MLX4_CMD_TIME_CLASS_A);
836
837 mlx4_free_cmd_mailbox(dev, mailbox);
838 } else
839 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
840 MLX4_CMD_TIME_CLASS_A);
841
842 return err;
843 }
844 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
845
846 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
847 {
848 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000);
849 }
850 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
851
852 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
853 {
854 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000);
855 }
856
857 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
858 {
859 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
860 MLX4_CMD_SET_ICM_SIZE,
861 MLX4_CMD_TIME_CLASS_A);
862 if (ret)
863 return ret;
864
865 /*
866 * Round up number of system pages needed in case
867 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
868 */
869 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
870 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
871
872 return 0;
873 }
874
875 int mlx4_NOP(struct mlx4_dev *dev)
876 {
877 /* Input modifier of 0x1f means "finish as soon as possible." */
878 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100);
879 }
Linus' kernel tree