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[DCCP]: Shift the retransmit timer for active-close into output.c
[linux-2.6.git] / drivers / char / agp / intel-agp.c
blob03eac1eb8e0fc863356905611bf344a5828a1554
1 /*
2 * Intel AGPGART routines.
3 */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
11 #include "agp.h"
12
13 #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
14 #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
15 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
16 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
17 #define PCI_DEVICE_ID_INTEL_82965G_1_HB 0x2980
18 #define PCI_DEVICE_ID_INTEL_82965G_1_IG 0x2982
19 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
20 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
21 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
22 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
23 #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
24 #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
25 #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
26 #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
27 #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
28 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
29 #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
30 #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
31 #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
32 #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
33 #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
34 #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
35
36 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
37 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
38 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
39 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
40 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
41 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
42
43 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
44 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
45 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
46
47 extern int agp_memory_reserved;
48
49
50 /* Intel 815 register */
51 #define INTEL_815_APCONT 0x51
52 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
53
54 /* Intel i820 registers */
55 #define INTEL_I820_RDCR 0x51
56 #define INTEL_I820_ERRSTS 0xc8
57
58 /* Intel i840 registers */
59 #define INTEL_I840_MCHCFG 0x50
60 #define INTEL_I840_ERRSTS 0xc8
61
62 /* Intel i850 registers */
63 #define INTEL_I850_MCHCFG 0x50
64 #define INTEL_I850_ERRSTS 0xc8
65
66 /* intel 915G registers */
67 #define I915_GMADDR 0x18
68 #define I915_MMADDR 0x10
69 #define I915_PTEADDR 0x1C
70 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
71 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
72 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
73 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
74
75 /* Intel 965G registers */
76 #define I965_MSAC 0x62
77
78 /* Intel 7505 registers */
79 #define INTEL_I7505_APSIZE 0x74
80 #define INTEL_I7505_NCAPID 0x60
81 #define INTEL_I7505_NISTAT 0x6c
82 #define INTEL_I7505_ATTBASE 0x78
83 #define INTEL_I7505_ERRSTS 0x42
84 #define INTEL_I7505_AGPCTRL 0x70
85 #define INTEL_I7505_MCHCFG 0x50
86
87 static const struct aper_size_info_fixed intel_i810_sizes[] =
88 {
89 {64, 16384, 4},
90 /* The 32M mode still requires a 64k gatt */
91 {32, 8192, 4}
92 };
93
94 #define AGP_DCACHE_MEMORY 1
95 #define AGP_PHYS_MEMORY 2
96 #define INTEL_AGP_CACHED_MEMORY 3
97
98 static struct gatt_mask intel_i810_masks[] =
99 {
100 {.mask = I810_PTE_VALID, .type = 0},
101 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
102 {.mask = I810_PTE_VALID, .type = 0},
103 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
104 .type = INTEL_AGP_CACHED_MEMORY}
105 };
106
107 static struct _intel_private {
108 struct pci_dev *pcidev; /* device one */
109 u8 __iomem *registers;
110 u32 __iomem *gtt; /* I915G */
111 int num_dcache_entries;
112 /* gtt_entries is the number of gtt entries that are already mapped
113 * to stolen memory. Stolen memory is larger than the memory mapped
114 * through gtt_entries, as it includes some reserved space for the BIOS
115 * popup and for the GTT.
116 */
117 int gtt_entries; /* i830+ */
118 } intel_private;
119
120 static int intel_i810_fetch_size(void)
121 {
122 u32 smram_miscc;
123 struct aper_size_info_fixed *values;
124
125 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
126 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
127
128 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
129 printk(KERN_WARNING PFX "i810 is disabled\n");
130 return 0;
131 }
132 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
133 agp_bridge->previous_size =
134 agp_bridge->current_size = (void *) (values + 1);
135 agp_bridge->aperture_size_idx = 1;
136 return values[1].size;
137 } else {
138 agp_bridge->previous_size =
139 agp_bridge->current_size = (void *) (values);
140 agp_bridge->aperture_size_idx = 0;
141 return values[0].size;
142 }
143
144 return 0;
145 }
146
147 static int intel_i810_configure(void)
148 {
149 struct aper_size_info_fixed *current_size;
150 u32 temp;
151 int i;
152
153 current_size = A_SIZE_FIX(agp_bridge->current_size);
154
155 if (!intel_private.registers) {
156 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
157 temp &= 0xfff80000;
158
159 intel_private.registers = ioremap(temp, 128 * 4096);
160 if (!intel_private.registers) {
161 printk(KERN_ERR PFX "Unable to remap memory.\n");
162 return -ENOMEM;
163 }
164 }
165
166 if ((readl(intel_private.registers+I810_DRAM_CTL)
167 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
168 /* This will need to be dynamically assigned */
169 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
170 intel_private.num_dcache_entries = 1024;
171 }
172 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
173 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
174 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
175 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
176
177 if (agp_bridge->driver->needs_scratch_page) {
178 for (i = 0; i < current_size->num_entries; i++) {
179 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
180 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */
181 }
182 }
183 global_cache_flush();
184 return 0;
185 }
186
187 static void intel_i810_cleanup(void)
188 {
189 writel(0, intel_private.registers+I810_PGETBL_CTL);
190 readl(intel_private.registers); /* PCI Posting. */
191 iounmap(intel_private.registers);
192 }
193
194 static void intel_i810_tlbflush(struct agp_memory *mem)
195 {
196 return;
197 }
198
199 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
200 {
201 return;
202 }
203
204 /* Exists to support ARGB cursors */
205 static void *i8xx_alloc_pages(void)
206 {
207 struct page * page;
208
209 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
210 if (page == NULL)
211 return NULL;
212
213 if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) {
214 change_page_attr(page, 4, PAGE_KERNEL);
215 global_flush_tlb();
216 __free_pages(page, 2);
217 return NULL;
218 }
219 global_flush_tlb();
220 get_page(page);
221 atomic_inc(&agp_bridge->current_memory_agp);
222 return page_address(page);
223 }
224
225 static void i8xx_destroy_pages(void *addr)
226 {
227 struct page *page;
228
229 if (addr == NULL)
230 return;
231
232 page = virt_to_page(addr);
233 change_page_attr(page, 4, PAGE_KERNEL);
234 global_flush_tlb();
235 put_page(page);
236 __free_pages(page, 2);
237 atomic_dec(&agp_bridge->current_memory_agp);
238 }
239
240 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
241 int type)
242 {
243 if (type < AGP_USER_TYPES)
244 return type;
245 else if (type == AGP_USER_CACHED_MEMORY)
246 return INTEL_AGP_CACHED_MEMORY;
247 else
248 return 0;
249 }
250
251 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
252 int type)
253 {
254 int i, j, num_entries;
255 void *temp;
256 int ret = -EINVAL;
257 int mask_type;
258
259 if (mem->page_count == 0)
260 goto out;
261
262 temp = agp_bridge->current_size;
263 num_entries = A_SIZE_FIX(temp)->num_entries;
264
265 if ((pg_start + mem->page_count) > num_entries)
266 goto out_err;
267
268
269 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
270 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
271 ret = -EBUSY;
272 goto out_err;
273 }
274 }
275
276 if (type != mem->type)
277 goto out_err;
278
279 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
280
281 switch (mask_type) {
282 case AGP_DCACHE_MEMORY:
283 if (!mem->is_flushed)
284 global_cache_flush();
285 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
286 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
287 intel_private.registers+I810_PTE_BASE+(i*4));
288 }
289 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
290 break;
291 case AGP_PHYS_MEMORY:
292 case AGP_NORMAL_MEMORY:
293 if (!mem->is_flushed)
294 global_cache_flush();
295 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
296 writel(agp_bridge->driver->mask_memory(agp_bridge,
297 mem->memory[i],
298 mask_type),
299 intel_private.registers+I810_PTE_BASE+(j*4));
300 }
301 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
302 break;
303 default:
304 goto out_err;
305 }
306
307 agp_bridge->driver->tlb_flush(mem);
308 out:
309 ret = 0;
310 out_err:
311 mem->is_flushed = 1;
312 return ret;
313 }
314
315 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
316 int type)
317 {
318 int i;
319
320 if (mem->page_count == 0)
321 return 0;
322
323 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
324 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
325 }
326 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
327
328 agp_bridge->driver->tlb_flush(mem);
329 return 0;
330 }
331
332 /*
333 * The i810/i830 requires a physical address to program its mouse
334 * pointer into hardware.
335 * However the Xserver still writes to it through the agp aperture.
336 */
337 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
338 {
339 struct agp_memory *new;
340 void *addr;
341
342 switch (pg_count) {
343 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
344 global_flush_tlb();
345 break;
346 case 4:
347 /* kludge to get 4 physical pages for ARGB cursor */
348 addr = i8xx_alloc_pages();
349 break;
350 default:
351 return NULL;
352 }
353
354 if (addr == NULL)
355 return NULL;
356
357 new = agp_create_memory(pg_count);
358 if (new == NULL)
359 return NULL;
360
361 new->memory[0] = virt_to_gart(addr);
362 if (pg_count == 4) {
363 /* kludge to get 4 physical pages for ARGB cursor */
364 new->memory[1] = new->memory[0] + PAGE_SIZE;
365 new->memory[2] = new->memory[1] + PAGE_SIZE;
366 new->memory[3] = new->memory[2] + PAGE_SIZE;
367 }
368 new->page_count = pg_count;
369 new->num_scratch_pages = pg_count;
370 new->type = AGP_PHYS_MEMORY;
371 new->physical = new->memory[0];
372 return new;
373 }
374
375 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
376 {
377 struct agp_memory *new;
378
379 if (type == AGP_DCACHE_MEMORY) {
380 if (pg_count != intel_private.num_dcache_entries)
381 return NULL;
382
383 new = agp_create_memory(1);
384 if (new == NULL)
385 return NULL;
386
387 new->type = AGP_DCACHE_MEMORY;
388 new->page_count = pg_count;
389 new->num_scratch_pages = 0;
390 agp_free_page_array(new);
391 return new;
392 }
393 if (type == AGP_PHYS_MEMORY)
394 return alloc_agpphysmem_i8xx(pg_count, type);
395 return NULL;
396 }
397
398 static void intel_i810_free_by_type(struct agp_memory *curr)
399 {
400 agp_free_key(curr->key);
401 if (curr->type == AGP_PHYS_MEMORY) {
402 if (curr->page_count == 4)
403 i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
404 else {
405 agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
406 AGP_PAGE_DESTROY_UNMAP);
407 global_flush_tlb();
408 agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
409 AGP_PAGE_DESTROY_FREE);
410 }
411 agp_free_page_array(curr);
412 }
413 kfree(curr);
414 }
415
416 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
417 unsigned long addr, int type)
418 {
419 /* Type checking must be done elsewhere */
420 return addr | bridge->driver->masks[type].mask;
421 }
422
423 static struct aper_size_info_fixed intel_i830_sizes[] =
424 {
425 {128, 32768, 5},
426 /* The 64M mode still requires a 128k gatt */
427 {64, 16384, 5},
428 {256, 65536, 6},
429 {512, 131072, 7},
430 };
431
432 static void intel_i830_init_gtt_entries(void)
433 {
434 u16 gmch_ctrl;
435 int gtt_entries;
436 u8 rdct;
437 int local = 0;
438 static const int ddt[4] = { 0, 16, 32, 64 };
439 int size; /* reserved space (in kb) at the top of stolen memory */
440
441 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
442
443 if (IS_I965) {
444 u32 pgetbl_ctl;
445 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
446
447 /* The 965 has a field telling us the size of the GTT,
448 * which may be larger than what is necessary to map the
449 * aperture.
450 */
451 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
452 case I965_PGETBL_SIZE_128KB:
453 size = 128;
454 break;
455 case I965_PGETBL_SIZE_256KB:
456 size = 256;
457 break;
458 case I965_PGETBL_SIZE_512KB:
459 size = 512;
460 break;
461 default:
462 printk(KERN_INFO PFX "Unknown page table size, "
463 "assuming 512KB\n");
464 size = 512;
465 }
466 size += 4; /* add in BIOS popup space */
467 } else if (IS_G33) {
468 /* G33's GTT size defined in gmch_ctrl */
469 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
470 case G33_PGETBL_SIZE_1M:
471 size = 1024;
472 break;
473 case G33_PGETBL_SIZE_2M:
474 size = 2048;
475 break;
476 default:
477 printk(KERN_INFO PFX "Unknown page table size 0x%x, "
478 "assuming 512KB\n",
479 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
480 size = 512;
481 }
482 size += 4;
483 } else {
484 /* On previous hardware, the GTT size was just what was
485 * required to map the aperture.
486 */
487 size = agp_bridge->driver->fetch_size() + 4;
488 }
489
490 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
491 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
492 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
493 case I830_GMCH_GMS_STOLEN_512:
494 gtt_entries = KB(512) - KB(size);
495 break;
496 case I830_GMCH_GMS_STOLEN_1024:
497 gtt_entries = MB(1) - KB(size);
498 break;
499 case I830_GMCH_GMS_STOLEN_8192:
500 gtt_entries = MB(8) - KB(size);
501 break;
502 case I830_GMCH_GMS_LOCAL:
503 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
504 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
505 MB(ddt[I830_RDRAM_DDT(rdct)]);
506 local = 1;
507 break;
508 default:
509 gtt_entries = 0;
510 break;
511 }
512 } else {
513 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
514 case I855_GMCH_GMS_STOLEN_1M:
515 gtt_entries = MB(1) - KB(size);
516 break;
517 case I855_GMCH_GMS_STOLEN_4M:
518 gtt_entries = MB(4) - KB(size);
519 break;
520 case I855_GMCH_GMS_STOLEN_8M:
521 gtt_entries = MB(8) - KB(size);
522 break;
523 case I855_GMCH_GMS_STOLEN_16M:
524 gtt_entries = MB(16) - KB(size);
525 break;
526 case I855_GMCH_GMS_STOLEN_32M:
527 gtt_entries = MB(32) - KB(size);
528 break;
529 case I915_GMCH_GMS_STOLEN_48M:
530 /* Check it's really I915G */
531 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB ||
532 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
533 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
534 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
535 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
536 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
537 IS_I965 || IS_G33)
538 gtt_entries = MB(48) - KB(size);
539 else
540 gtt_entries = 0;
541 break;
542 case I915_GMCH_GMS_STOLEN_64M:
543 /* Check it's really I915G */
544 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB ||
545 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
546 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
547 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
548 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
549 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
550 IS_I965 || IS_G33)
551 gtt_entries = MB(64) - KB(size);
552 else
553 gtt_entries = 0;
554 break;
555 case G33_GMCH_GMS_STOLEN_128M:
556 if (IS_G33)
557 gtt_entries = MB(128) - KB(size);
558 else
559 gtt_entries = 0;
560 break;
561 case G33_GMCH_GMS_STOLEN_256M:
562 if (IS_G33)
563 gtt_entries = MB(256) - KB(size);
564 else
565 gtt_entries = 0;
566 break;
567 default:
568 gtt_entries = 0;
569 break;
570 }
571 }
572 if (gtt_entries > 0)
573 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
574 gtt_entries / KB(1), local ? "local" : "stolen");
575 else
576 printk(KERN_INFO PFX
577 "No pre-allocated video memory detected.\n");
578 gtt_entries /= KB(4);
579
580 intel_private.gtt_entries = gtt_entries;
581 }
582
583 /* The intel i830 automatically initializes the agp aperture during POST.
584 * Use the memory already set aside for in the GTT.
585 */
586 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
587 {
588 int page_order;
589 struct aper_size_info_fixed *size;
590 int num_entries;
591 u32 temp;
592
593 size = agp_bridge->current_size;
594 page_order = size->page_order;
595 num_entries = size->num_entries;
596 agp_bridge->gatt_table_real = NULL;
597
598 pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp);
599 temp &= 0xfff80000;
600
601 intel_private.registers = ioremap(temp,128 * 4096);
602 if (!intel_private.registers)
603 return -ENOMEM;
604
605 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
606 global_cache_flush(); /* FIXME: ?? */
607
608 /* we have to call this as early as possible after the MMIO base address is known */
609 intel_i830_init_gtt_entries();
610
611 agp_bridge->gatt_table = NULL;
612
613 agp_bridge->gatt_bus_addr = temp;
614
615 return 0;
616 }
617
618 /* Return the gatt table to a sane state. Use the top of stolen
619 * memory for the GTT.
620 */
621 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
622 {
623 return 0;
624 }
625
626 static int intel_i830_fetch_size(void)
627 {
628 u16 gmch_ctrl;
629 struct aper_size_info_fixed *values;
630
631 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
632
633 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
634 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
635 /* 855GM/852GM/865G has 128MB aperture size */
636 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
637 agp_bridge->aperture_size_idx = 0;
638 return values[0].size;
639 }
640
641 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
642
643 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
644 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
645 agp_bridge->aperture_size_idx = 0;
646 return values[0].size;
647 } else {
648 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
649 agp_bridge->aperture_size_idx = 1;
650 return values[1].size;
651 }
652
653 return 0;
654 }
655
656 static int intel_i830_configure(void)
657 {
658 struct aper_size_info_fixed *current_size;
659 u32 temp;
660 u16 gmch_ctrl;
661 int i;
662
663 current_size = A_SIZE_FIX(agp_bridge->current_size);
664
665 pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp);
666 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
667
668 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
669 gmch_ctrl |= I830_GMCH_ENABLED;
670 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
671
672 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
673 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
674
675 if (agp_bridge->driver->needs_scratch_page) {
676 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
677 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
678 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
679 }
680 }
681
682 global_cache_flush();
683 return 0;
684 }
685
686 static void intel_i830_cleanup(void)
687 {
688 iounmap(intel_private.registers);
689 }
690
691 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
692 {
693 int i,j,num_entries;
694 void *temp;
695 int ret = -EINVAL;
696 int mask_type;
697
698 if (mem->page_count == 0)
699 goto out;
700
701 temp = agp_bridge->current_size;
702 num_entries = A_SIZE_FIX(temp)->num_entries;
703
704 if (pg_start < intel_private.gtt_entries) {
705 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
706 pg_start,intel_private.gtt_entries);
707
708 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
709 goto out_err;
710 }
711
712 if ((pg_start + mem->page_count) > num_entries)
713 goto out_err;
714
715 /* The i830 can't check the GTT for entries since its read only,
716 * depend on the caller to make the correct offset decisions.
717 */
718
719 if (type != mem->type)
720 goto out_err;
721
722 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
723
724 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
725 mask_type != INTEL_AGP_CACHED_MEMORY)
726 goto out_err;
727
728 if (!mem->is_flushed)
729 global_cache_flush();
730
731 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
732 writel(agp_bridge->driver->mask_memory(agp_bridge,
733 mem->memory[i], mask_type),
734 intel_private.registers+I810_PTE_BASE+(j*4));
735 }
736 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
737 agp_bridge->driver->tlb_flush(mem);
738
739 out:
740 ret = 0;
741 out_err:
742 mem->is_flushed = 1;
743 return ret;
744 }
745
746 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
747 int type)
748 {
749 int i;
750
751 if (mem->page_count == 0)
752 return 0;
753
754 if (pg_start < intel_private.gtt_entries) {
755 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
756 return -EINVAL;
757 }
758
759 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
760 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
761 }
762 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
763
764 agp_bridge->driver->tlb_flush(mem);
765 return 0;
766 }
767
768 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
769 {
770 if (type == AGP_PHYS_MEMORY)
771 return alloc_agpphysmem_i8xx(pg_count, type);
772 /* always return NULL for other allocation types for now */
773 return NULL;
774 }
775
776 static int intel_i915_configure(void)
777 {
778 struct aper_size_info_fixed *current_size;
779 u32 temp;
780 u16 gmch_ctrl;
781 int i;
782
783 current_size = A_SIZE_FIX(agp_bridge->current_size);
784
785 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
786
787 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
788
789 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
790 gmch_ctrl |= I830_GMCH_ENABLED;
791 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
792
793 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
794 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
795
796 if (agp_bridge->driver->needs_scratch_page) {
797 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
798 writel(agp_bridge->scratch_page, intel_private.gtt+i);
799 readl(intel_private.gtt+i); /* PCI Posting. */
800 }
801 }
802
803 global_cache_flush();
804 return 0;
805 }
806
807 static void intel_i915_cleanup(void)
808 {
809 iounmap(intel_private.gtt);
810 iounmap(intel_private.registers);
811 }
812
813 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
814 int type)
815 {
816 int i,j,num_entries;
817 void *temp;
818 int ret = -EINVAL;
819 int mask_type;
820
821 if (mem->page_count == 0)
822 goto out;
823
824 temp = agp_bridge->current_size;
825 num_entries = A_SIZE_FIX(temp)->num_entries;
826
827 if (pg_start < intel_private.gtt_entries) {
828 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
829 pg_start,intel_private.gtt_entries);
830
831 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
832 goto out_err;
833 }
834
835 if ((pg_start + mem->page_count) > num_entries)
836 goto out_err;
837
838 /* The i915 can't check the GTT for entries since its read only,
839 * depend on the caller to make the correct offset decisions.
840 */
841
842 if (type != mem->type)
843 goto out_err;
844
845 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
846
847 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
848 mask_type != INTEL_AGP_CACHED_MEMORY)
849 goto out_err;
850
851 if (!mem->is_flushed)
852 global_cache_flush();
853
854 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
855 writel(agp_bridge->driver->mask_memory(agp_bridge,
856 mem->memory[i], mask_type), intel_private.gtt+j);
857 }
858
859 readl(intel_private.gtt+j-1);
860 agp_bridge->driver->tlb_flush(mem);
861
862 out:
863 ret = 0;
864 out_err:
865 mem->is_flushed = 1;
866 return ret;
867 }
868
869 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
870 int type)
871 {
872 int i;
873
874 if (mem->page_count == 0)
875 return 0;
876
877 if (pg_start < intel_private.gtt_entries) {
878 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
879 return -EINVAL;
880 }
881
882 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
883 writel(agp_bridge->scratch_page, intel_private.gtt+i);
884 }
885 readl(intel_private.gtt+i-1);
886
887 agp_bridge->driver->tlb_flush(mem);
888 return 0;
889 }
890
891 /* Return the aperture size by just checking the resource length. The effect
892 * described in the spec of the MSAC registers is just changing of the
893 * resource size.
894 */
895 static int intel_i9xx_fetch_size(void)
896 {
897 int num_sizes = ARRAY_SIZE(intel_i830_sizes);
898 int aper_size; /* size in megabytes */
899 int i;
900
901 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
902
903 for (i = 0; i < num_sizes; i++) {
904 if (aper_size == intel_i830_sizes[i].size) {
905 agp_bridge->current_size = intel_i830_sizes + i;
906 agp_bridge->previous_size = agp_bridge->current_size;
907 return aper_size;
908 }
909 }
910
911 return 0;
912 }
913
914 /* The intel i915 automatically initializes the agp aperture during POST.
915 * Use the memory already set aside for in the GTT.
916 */
917 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
918 {
919 int page_order;
920 struct aper_size_info_fixed *size;
921 int num_entries;
922 u32 temp, temp2;
923 int gtt_map_size = 256 * 1024;
924
925 size = agp_bridge->current_size;
926 page_order = size->page_order;
927 num_entries = size->num_entries;
928 agp_bridge->gatt_table_real = NULL;
929
930 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
931 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2);
932
933 if (IS_G33)
934 gtt_map_size = 1024 * 1024; /* 1M on G33 */
935 intel_private.gtt = ioremap(temp2, gtt_map_size);
936 if (!intel_private.gtt)
937 return -ENOMEM;
938
939 temp &= 0xfff80000;
940
941 intel_private.registers = ioremap(temp,128 * 4096);
942 if (!intel_private.registers) {
943 iounmap(intel_private.gtt);
944 return -ENOMEM;
945 }
946
947 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
948 global_cache_flush(); /* FIXME: ? */
949
950 /* we have to call this as early as possible after the MMIO base address is known */
951 intel_i830_init_gtt_entries();
952
953 agp_bridge->gatt_table = NULL;
954
955 agp_bridge->gatt_bus_addr = temp;
956
957 return 0;
958 }
959
960 /*
961 * The i965 supports 36-bit physical addresses, but to keep
962 * the format of the GTT the same, the bits that don't fit
963 * in a 32-bit word are shifted down to bits 4..7.
964 *
965 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
966 * is always zero on 32-bit architectures, so no need to make
967 * this conditional.
968 */
969 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
970 unsigned long addr, int type)
971 {
972 /* Shift high bits down */
973 addr |= (addr >> 28) & 0xf0;
974
975 /* Type checking must be done elsewhere */
976 return addr | bridge->driver->masks[type].mask;
977 }
978
979 /* The intel i965 automatically initializes the agp aperture during POST.
980 * Use the memory already set aside for in the GTT.
981 */
982 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
983 {
984 int page_order;
985 struct aper_size_info_fixed *size;
986 int num_entries;
987 u32 temp;
988
989 size = agp_bridge->current_size;
990 page_order = size->page_order;
991 num_entries = size->num_entries;
992 agp_bridge->gatt_table_real = NULL;
993
994 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
995
996 temp &= 0xfff00000;
997 intel_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024);
998
999 if (!intel_private.gtt)
1000 return -ENOMEM;
1001
1002
1003 intel_private.registers = ioremap(temp,128 * 4096);
1004 if (!intel_private.registers) {
1005 iounmap(intel_private.gtt);
1006 return -ENOMEM;
1007 }
1008
1009 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1010 global_cache_flush(); /* FIXME: ? */
1011
1012 /* we have to call this as early as possible after the MMIO base address is known */
1013 intel_i830_init_gtt_entries();
1014
1015 agp_bridge->gatt_table = NULL;
1016
1017 agp_bridge->gatt_bus_addr = temp;
1018
1019 return 0;
1020 }
1021
1022
1023 static int intel_fetch_size(void)
1024 {
1025 int i;
1026 u16 temp;
1027 struct aper_size_info_16 *values;
1028
1029 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1030 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1031
1032 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1033 if (temp == values[i].size_value) {
1034 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1035 agp_bridge->aperture_size_idx = i;
1036 return values[i].size;
1037 }
1038 }
1039
1040 return 0;
1041 }
1042
1043 static int __intel_8xx_fetch_size(u8 temp)
1044 {
1045 int i;
1046 struct aper_size_info_8 *values;
1047
1048 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1049
1050 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1051 if (temp == values[i].size_value) {
1052 agp_bridge->previous_size =
1053 agp_bridge->current_size = (void *) (values + i);
1054 agp_bridge->aperture_size_idx = i;
1055 return values[i].size;
1056 }
1057 }
1058 return 0;
1059 }
1060
1061 static int intel_8xx_fetch_size(void)
1062 {
1063 u8 temp;
1064
1065 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1066 return __intel_8xx_fetch_size(temp);
1067 }
1068
1069 static int intel_815_fetch_size(void)
1070 {
1071 u8 temp;
1072
1073 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1074 * one non-reserved bit, so mask the others out ... */
1075 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1076 temp &= (1 << 3);
1077
1078 return __intel_8xx_fetch_size(temp);
1079 }
1080
1081 static void intel_tlbflush(struct agp_memory *mem)
1082 {
1083 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1084 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1085 }
1086
1087
1088 static void intel_8xx_tlbflush(struct agp_memory *mem)
1089 {
1090 u32 temp;
1091 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1092 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1093 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1094 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1095 }
1096
1097
1098 static void intel_cleanup(void)
1099 {
1100 u16 temp;
1101 struct aper_size_info_16 *previous_size;
1102
1103 previous_size = A_SIZE_16(agp_bridge->previous_size);
1104 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1105 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1106 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1107 }
1108
1109
1110 static void intel_8xx_cleanup(void)
1111 {
1112 u16 temp;
1113 struct aper_size_info_8 *previous_size;
1114
1115 previous_size = A_SIZE_8(agp_bridge->previous_size);
1116 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1117 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1118 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1119 }
1120
1121
1122 static int intel_configure(void)
1123 {
1124 u32 temp;
1125 u16 temp2;
1126 struct aper_size_info_16 *current_size;
1127
1128 current_size = A_SIZE_16(agp_bridge->current_size);
1129
1130 /* aperture size */
1131 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1132
1133 /* address to map to */
1134 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1135 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1136
1137 /* attbase - aperture base */
1138 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1139
1140 /* agpctrl */
1141 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1142
1143 /* paccfg/nbxcfg */
1144 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1145 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1146 (temp2 & ~(1 << 10)) | (1 << 9));
1147 /* clear any possible error conditions */
1148 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1149 return 0;
1150 }
1151
1152 static int intel_815_configure(void)
1153 {
1154 u32 temp, addr;
1155 u8 temp2;
1156 struct aper_size_info_8 *current_size;
1157
1158 /* attbase - aperture base */
1159 /* the Intel 815 chipset spec. says that bits 29-31 in the
1160 * ATTBASE register are reserved -> try not to write them */
1161 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1162 printk (KERN_EMERG PFX "gatt bus addr too high");
1163 return -EINVAL;
1164 }
1165
1166 current_size = A_SIZE_8(agp_bridge->current_size);
1167
1168 /* aperture size */
1169 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1170 current_size->size_value);
1171
1172 /* address to map to */
1173 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1174 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1175
1176 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1177 addr &= INTEL_815_ATTBASE_MASK;
1178 addr |= agp_bridge->gatt_bus_addr;
1179 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1180
1181 /* agpctrl */
1182 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1183
1184 /* apcont */
1185 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1186 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1187
1188 /* clear any possible error conditions */
1189 /* Oddness : this chipset seems to have no ERRSTS register ! */
1190 return 0;
1191 }
1192
1193 static void intel_820_tlbflush(struct agp_memory *mem)
1194 {
1195 return;
1196 }
1197
1198 static void intel_820_cleanup(void)
1199 {
1200 u8 temp;
1201 struct aper_size_info_8 *previous_size;
1202
1203 previous_size = A_SIZE_8(agp_bridge->previous_size);
1204 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1205 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1206 temp & ~(1 << 1));
1207 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1208 previous_size->size_value);
1209 }
1210
1211
1212 static int intel_820_configure(void)
1213 {
1214 u32 temp;
1215 u8 temp2;
1216 struct aper_size_info_8 *current_size;
1217
1218 current_size = A_SIZE_8(agp_bridge->current_size);
1219
1220 /* aperture size */
1221 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1222
1223 /* address to map to */
1224 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1225 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1226
1227 /* attbase - aperture base */
1228 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1229
1230 /* agpctrl */
1231 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1232
1233 /* global enable aperture access */
1234 /* This flag is not accessed through MCHCFG register as in */
1235 /* i850 chipset. */
1236 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1237 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1238 /* clear any possible AGP-related error conditions */
1239 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1240 return 0;
1241 }
1242
1243 static int intel_840_configure(void)
1244 {
1245 u32 temp;
1246 u16 temp2;
1247 struct aper_size_info_8 *current_size;
1248
1249 current_size = A_SIZE_8(agp_bridge->current_size);
1250
1251 /* aperture size */
1252 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1253
1254 /* address to map to */
1255 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1256 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1257
1258 /* attbase - aperture base */
1259 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1260
1261 /* agpctrl */
1262 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1263
1264 /* mcgcfg */
1265 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1266 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1267 /* clear any possible error conditions */
1268 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1269 return 0;
1270 }
1271
1272 static int intel_845_configure(void)
1273 {
1274 u32 temp;
1275 u8 temp2;
1276 struct aper_size_info_8 *current_size;
1277
1278 current_size = A_SIZE_8(agp_bridge->current_size);
1279
1280 /* aperture size */
1281 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1282
1283 if (agp_bridge->apbase_config != 0) {
1284 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1285 agp_bridge->apbase_config);
1286 } else {
1287 /* address to map to */
1288 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1289 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1290 agp_bridge->apbase_config = temp;
1291 }
1292
1293 /* attbase - aperture base */
1294 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1295
1296 /* agpctrl */
1297 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1298
1299 /* agpm */
1300 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1301 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1302 /* clear any possible error conditions */
1303 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1304 return 0;
1305 }
1306
1307 static int intel_850_configure(void)
1308 {
1309 u32 temp;
1310 u16 temp2;
1311 struct aper_size_info_8 *current_size;
1312
1313 current_size = A_SIZE_8(agp_bridge->current_size);
1314
1315 /* aperture size */
1316 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1317
1318 /* address to map to */
1319 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1320 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1321
1322 /* attbase - aperture base */
1323 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1324
1325 /* agpctrl */
1326 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1327
1328 /* mcgcfg */
1329 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1330 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1331 /* clear any possible AGP-related error conditions */
1332 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1333 return 0;
1334 }
1335
1336 static int intel_860_configure(void)
1337 {
1338 u32 temp;
1339 u16 temp2;
1340 struct aper_size_info_8 *current_size;
1341
1342 current_size = A_SIZE_8(agp_bridge->current_size);
1343
1344 /* aperture size */
1345 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1346
1347 /* address to map to */
1348 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1349 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1350
1351 /* attbase - aperture base */
1352 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1353
1354 /* agpctrl */
1355 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1356
1357 /* mcgcfg */
1358 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1359 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1360 /* clear any possible AGP-related error conditions */
1361 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1362 return 0;
1363 }
1364
1365 static int intel_830mp_configure(void)
1366 {
1367 u32 temp;
1368 u16 temp2;
1369 struct aper_size_info_8 *current_size;
1370
1371 current_size = A_SIZE_8(agp_bridge->current_size);
1372
1373 /* aperture size */
1374 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1375
1376 /* address to map to */
1377 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1378 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1379
1380 /* attbase - aperture base */
1381 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1382
1383 /* agpctrl */
1384 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1385
1386 /* gmch */
1387 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1388 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1389 /* clear any possible AGP-related error conditions */
1390 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1391 return 0;
1392 }
1393
1394 static int intel_7505_configure(void)
1395 {
1396 u32 temp;
1397 u16 temp2;
1398 struct aper_size_info_8 *current_size;
1399
1400 current_size = A_SIZE_8(agp_bridge->current_size);
1401
1402 /* aperture size */
1403 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1404
1405 /* address to map to */
1406 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1407 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1408
1409 /* attbase - aperture base */
1410 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1411
1412 /* agpctrl */
1413 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1414
1415 /* mchcfg */
1416 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1417 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1418
1419 return 0;
1420 }
1421
1422 /* Setup function */
1423 static const struct gatt_mask intel_generic_masks[] =
1424 {
1425 {.mask = 0x00000017, .type = 0}
1426 };
1427
1428 static const struct aper_size_info_8 intel_815_sizes[2] =
1429 {
1430 {64, 16384, 4, 0},
1431 {32, 8192, 3, 8},
1432 };
1433
1434 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1435 {
1436 {256, 65536, 6, 0},
1437 {128, 32768, 5, 32},
1438 {64, 16384, 4, 48},
1439 {32, 8192, 3, 56},
1440 {16, 4096, 2, 60},
1441 {8, 2048, 1, 62},
1442 {4, 1024, 0, 63}
1443 };
1444
1445 static const struct aper_size_info_16 intel_generic_sizes[7] =
1446 {
1447 {256, 65536, 6, 0},
1448 {128, 32768, 5, 32},
1449 {64, 16384, 4, 48},
1450 {32, 8192, 3, 56},
1451 {16, 4096, 2, 60},
1452 {8, 2048, 1, 62},
1453 {4, 1024, 0, 63}
1454 };
1455
1456 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1457 {
1458 {256, 65536, 6, 0},
1459 {128, 32768, 5, 32},
1460 {64, 16384, 4, 48},
1461 {32, 8192, 3, 56}
1462 };
1463
1464 static const struct agp_bridge_driver intel_generic_driver = {
1465 .owner = THIS_MODULE,
1466 .aperture_sizes = intel_generic_sizes,
1467 .size_type = U16_APER_SIZE,
1468 .num_aperture_sizes = 7,
1469 .configure = intel_configure,
1470 .fetch_size = intel_fetch_size,
1471 .cleanup = intel_cleanup,
1472 .tlb_flush = intel_tlbflush,
1473 .mask_memory = agp_generic_mask_memory,
1474 .masks = intel_generic_masks,
1475 .agp_enable = agp_generic_enable,
1476 .cache_flush = global_cache_flush,
1477 .create_gatt_table = agp_generic_create_gatt_table,
1478 .free_gatt_table = agp_generic_free_gatt_table,
1479 .insert_memory = agp_generic_insert_memory,
1480 .remove_memory = agp_generic_remove_memory,
1481 .alloc_by_type = agp_generic_alloc_by_type,
1482 .free_by_type = agp_generic_free_by_type,
1483 .agp_alloc_page = agp_generic_alloc_page,
1484 .agp_destroy_page = agp_generic_destroy_page,
1485 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1486 };
1487
1488 static const struct agp_bridge_driver intel_810_driver = {
1489 .owner = THIS_MODULE,
1490 .aperture_sizes = intel_i810_sizes,
1491 .size_type = FIXED_APER_SIZE,
1492 .num_aperture_sizes = 2,
1493 .needs_scratch_page = TRUE,
1494 .configure = intel_i810_configure,
1495 .fetch_size = intel_i810_fetch_size,
1496 .cleanup = intel_i810_cleanup,
1497 .tlb_flush = intel_i810_tlbflush,
1498 .mask_memory = intel_i810_mask_memory,
1499 .masks = intel_i810_masks,
1500 .agp_enable = intel_i810_agp_enable,
1501 .cache_flush = global_cache_flush,
1502 .create_gatt_table = agp_generic_create_gatt_table,
1503 .free_gatt_table = agp_generic_free_gatt_table,
1504 .insert_memory = intel_i810_insert_entries,
1505 .remove_memory = intel_i810_remove_entries,
1506 .alloc_by_type = intel_i810_alloc_by_type,
1507 .free_by_type = intel_i810_free_by_type,
1508 .agp_alloc_page = agp_generic_alloc_page,
1509 .agp_destroy_page = agp_generic_destroy_page,
1510 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1511 };
1512
1513 static const struct agp_bridge_driver intel_815_driver = {
1514 .owner = THIS_MODULE,
1515 .aperture_sizes = intel_815_sizes,
1516 .size_type = U8_APER_SIZE,
1517 .num_aperture_sizes = 2,
1518 .configure = intel_815_configure,
1519 .fetch_size = intel_815_fetch_size,
1520 .cleanup = intel_8xx_cleanup,
1521 .tlb_flush = intel_8xx_tlbflush,
1522 .mask_memory = agp_generic_mask_memory,
1523 .masks = intel_generic_masks,
1524 .agp_enable = agp_generic_enable,
1525 .cache_flush = global_cache_flush,
1526 .create_gatt_table = agp_generic_create_gatt_table,
1527 .free_gatt_table = agp_generic_free_gatt_table,
1528 .insert_memory = agp_generic_insert_memory,
1529 .remove_memory = agp_generic_remove_memory,
1530 .alloc_by_type = agp_generic_alloc_by_type,
1531 .free_by_type = agp_generic_free_by_type,
1532 .agp_alloc_page = agp_generic_alloc_page,
1533 .agp_destroy_page = agp_generic_destroy_page,
1534 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1535 };
1536
1537 static const struct agp_bridge_driver intel_830_driver = {
1538 .owner = THIS_MODULE,
1539 .aperture_sizes = intel_i830_sizes,
1540 .size_type = FIXED_APER_SIZE,
1541 .num_aperture_sizes = 4,
1542 .needs_scratch_page = TRUE,
1543 .configure = intel_i830_configure,
1544 .fetch_size = intel_i830_fetch_size,
1545 .cleanup = intel_i830_cleanup,
1546 .tlb_flush = intel_i810_tlbflush,
1547 .mask_memory = intel_i810_mask_memory,
1548 .masks = intel_i810_masks,
1549 .agp_enable = intel_i810_agp_enable,
1550 .cache_flush = global_cache_flush,
1551 .create_gatt_table = intel_i830_create_gatt_table,
1552 .free_gatt_table = intel_i830_free_gatt_table,
1553 .insert_memory = intel_i830_insert_entries,
1554 .remove_memory = intel_i830_remove_entries,
1555 .alloc_by_type = intel_i830_alloc_by_type,
1556 .free_by_type = intel_i810_free_by_type,
1557 .agp_alloc_page = agp_generic_alloc_page,
1558 .agp_destroy_page = agp_generic_destroy_page,
1559 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1560 };
1561
1562 static const struct agp_bridge_driver intel_820_driver = {
1563 .owner = THIS_MODULE,
1564 .aperture_sizes = intel_8xx_sizes,
1565 .size_type = U8_APER_SIZE,
1566 .num_aperture_sizes = 7,
1567 .configure = intel_820_configure,
1568 .fetch_size = intel_8xx_fetch_size,
1569 .cleanup = intel_820_cleanup,
1570 .tlb_flush = intel_820_tlbflush,
1571 .mask_memory = agp_generic_mask_memory,
1572 .masks = intel_generic_masks,
1573 .agp_enable = agp_generic_enable,
1574 .cache_flush = global_cache_flush,
1575 .create_gatt_table = agp_generic_create_gatt_table,
1576 .free_gatt_table = agp_generic_free_gatt_table,
1577 .insert_memory = agp_generic_insert_memory,
1578 .remove_memory = agp_generic_remove_memory,
1579 .alloc_by_type = agp_generic_alloc_by_type,
1580 .free_by_type = agp_generic_free_by_type,
1581 .agp_alloc_page = agp_generic_alloc_page,
1582 .agp_destroy_page = agp_generic_destroy_page,
1583 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1584 };
1585
1586 static const struct agp_bridge_driver intel_830mp_driver = {
1587 .owner = THIS_MODULE,
1588 .aperture_sizes = intel_830mp_sizes,
1589 .size_type = U8_APER_SIZE,
1590 .num_aperture_sizes = 4,
1591 .configure = intel_830mp_configure,
1592 .fetch_size = intel_8xx_fetch_size,
1593 .cleanup = intel_8xx_cleanup,
1594 .tlb_flush = intel_8xx_tlbflush,
1595 .mask_memory = agp_generic_mask_memory,
1596 .masks = intel_generic_masks,
1597 .agp_enable = agp_generic_enable,
1598 .cache_flush = global_cache_flush,
1599 .create_gatt_table = agp_generic_create_gatt_table,
1600 .free_gatt_table = agp_generic_free_gatt_table,
1601 .insert_memory = agp_generic_insert_memory,
1602 .remove_memory = agp_generic_remove_memory,
1603 .alloc_by_type = agp_generic_alloc_by_type,
1604 .free_by_type = agp_generic_free_by_type,
1605 .agp_alloc_page = agp_generic_alloc_page,
1606 .agp_destroy_page = agp_generic_destroy_page,
1607 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1608 };
1609
1610 static const struct agp_bridge_driver intel_840_driver = {
1611 .owner = THIS_MODULE,
1612 .aperture_sizes = intel_8xx_sizes,
1613 .size_type = U8_APER_SIZE,
1614 .num_aperture_sizes = 7,
1615 .configure = intel_840_configure,
1616 .fetch_size = intel_8xx_fetch_size,
1617 .cleanup = intel_8xx_cleanup,
1618 .tlb_flush = intel_8xx_tlbflush,
1619 .mask_memory = agp_generic_mask_memory,
1620 .masks = intel_generic_masks,
1621 .agp_enable = agp_generic_enable,
1622 .cache_flush = global_cache_flush,
1623 .create_gatt_table = agp_generic_create_gatt_table,
1624 .free_gatt_table = agp_generic_free_gatt_table,
1625 .insert_memory = agp_generic_insert_memory,
1626 .remove_memory = agp_generic_remove_memory,
1627 .alloc_by_type = agp_generic_alloc_by_type,
1628 .free_by_type = agp_generic_free_by_type,
1629 .agp_alloc_page = agp_generic_alloc_page,
1630 .agp_destroy_page = agp_generic_destroy_page,
1631 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1632 };
1633
1634 static const struct agp_bridge_driver intel_845_driver = {
1635 .owner = THIS_MODULE,
1636 .aperture_sizes = intel_8xx_sizes,
1637 .size_type = U8_APER_SIZE,
1638 .num_aperture_sizes = 7,
1639 .configure = intel_845_configure,
1640 .fetch_size = intel_8xx_fetch_size,
1641 .cleanup = intel_8xx_cleanup,
1642 .tlb_flush = intel_8xx_tlbflush,
1643 .mask_memory = agp_generic_mask_memory,
1644 .masks = intel_generic_masks,
1645 .agp_enable = agp_generic_enable,
1646 .cache_flush = global_cache_flush,
1647 .create_gatt_table = agp_generic_create_gatt_table,
1648 .free_gatt_table = agp_generic_free_gatt_table,
1649 .insert_memory = agp_generic_insert_memory,
1650 .remove_memory = agp_generic_remove_memory,
1651 .alloc_by_type = agp_generic_alloc_by_type,
1652 .free_by_type = agp_generic_free_by_type,
1653 .agp_alloc_page = agp_generic_alloc_page,
1654 .agp_destroy_page = agp_generic_destroy_page,
1655 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1656 };
1657
1658 static const struct agp_bridge_driver intel_850_driver = {
1659 .owner = THIS_MODULE,
1660 .aperture_sizes = intel_8xx_sizes,
1661 .size_type = U8_APER_SIZE,
1662 .num_aperture_sizes = 7,
1663 .configure = intel_850_configure,
1664 .fetch_size = intel_8xx_fetch_size,
1665 .cleanup = intel_8xx_cleanup,
1666 .tlb_flush = intel_8xx_tlbflush,
1667 .mask_memory = agp_generic_mask_memory,
1668 .masks = intel_generic_masks,
1669 .agp_enable = agp_generic_enable,
1670 .cache_flush = global_cache_flush,
1671 .create_gatt_table = agp_generic_create_gatt_table,
1672 .free_gatt_table = agp_generic_free_gatt_table,
1673 .insert_memory = agp_generic_insert_memory,
1674 .remove_memory = agp_generic_remove_memory,
1675 .alloc_by_type = agp_generic_alloc_by_type,
1676 .free_by_type = agp_generic_free_by_type,
1677 .agp_alloc_page = agp_generic_alloc_page,
1678 .agp_destroy_page = agp_generic_destroy_page,
1679 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1680 };
1681
1682 static const struct agp_bridge_driver intel_860_driver = {
1683 .owner = THIS_MODULE,
1684 .aperture_sizes = intel_8xx_sizes,
1685 .size_type = U8_APER_SIZE,
1686 .num_aperture_sizes = 7,
1687 .configure = intel_860_configure,
1688 .fetch_size = intel_8xx_fetch_size,
1689 .cleanup = intel_8xx_cleanup,
1690 .tlb_flush = intel_8xx_tlbflush,
1691 .mask_memory = agp_generic_mask_memory,
1692 .masks = intel_generic_masks,
1693 .agp_enable = agp_generic_enable,
1694 .cache_flush = global_cache_flush,
1695 .create_gatt_table = agp_generic_create_gatt_table,
1696 .free_gatt_table = agp_generic_free_gatt_table,
1697 .insert_memory = agp_generic_insert_memory,
1698 .remove_memory = agp_generic_remove_memory,
1699 .alloc_by_type = agp_generic_alloc_by_type,
1700 .free_by_type = agp_generic_free_by_type,
1701 .agp_alloc_page = agp_generic_alloc_page,
1702 .agp_destroy_page = agp_generic_destroy_page,
1703 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1704 };
1705
1706 static const struct agp_bridge_driver intel_915_driver = {
1707 .owner = THIS_MODULE,
1708 .aperture_sizes = intel_i830_sizes,
1709 .size_type = FIXED_APER_SIZE,
1710 .num_aperture_sizes = 4,
1711 .needs_scratch_page = TRUE,
1712 .configure = intel_i915_configure,
1713 .fetch_size = intel_i9xx_fetch_size,
1714 .cleanup = intel_i915_cleanup,
1715 .tlb_flush = intel_i810_tlbflush,
1716 .mask_memory = intel_i810_mask_memory,
1717 .masks = intel_i810_masks,
1718 .agp_enable = intel_i810_agp_enable,
1719 .cache_flush = global_cache_flush,
1720 .create_gatt_table = intel_i915_create_gatt_table,
1721 .free_gatt_table = intel_i830_free_gatt_table,
1722 .insert_memory = intel_i915_insert_entries,
1723 .remove_memory = intel_i915_remove_entries,
1724 .alloc_by_type = intel_i830_alloc_by_type,
1725 .free_by_type = intel_i810_free_by_type,
1726 .agp_alloc_page = agp_generic_alloc_page,
1727 .agp_destroy_page = agp_generic_destroy_page,
1728 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1729 };
1730
1731 static const struct agp_bridge_driver intel_i965_driver = {
1732 .owner = THIS_MODULE,
1733 .aperture_sizes = intel_i830_sizes,
1734 .size_type = FIXED_APER_SIZE,
1735 .num_aperture_sizes = 4,
1736 .needs_scratch_page = TRUE,
1737 .configure = intel_i915_configure,
1738 .fetch_size = intel_i9xx_fetch_size,
1739 .cleanup = intel_i915_cleanup,
1740 .tlb_flush = intel_i810_tlbflush,
1741 .mask_memory = intel_i965_mask_memory,
1742 .masks = intel_i810_masks,
1743 .agp_enable = intel_i810_agp_enable,
1744 .cache_flush = global_cache_flush,
1745 .create_gatt_table = intel_i965_create_gatt_table,
1746 .free_gatt_table = intel_i830_free_gatt_table,
1747 .insert_memory = intel_i915_insert_entries,
1748 .remove_memory = intel_i915_remove_entries,
1749 .alloc_by_type = intel_i830_alloc_by_type,
1750 .free_by_type = intel_i810_free_by_type,
1751 .agp_alloc_page = agp_generic_alloc_page,
1752 .agp_destroy_page = agp_generic_destroy_page,
1753 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1754 };
1755
1756 static const struct agp_bridge_driver intel_7505_driver = {
1757 .owner = THIS_MODULE,
1758 .aperture_sizes = intel_8xx_sizes,
1759 .size_type = U8_APER_SIZE,
1760 .num_aperture_sizes = 7,
1761 .configure = intel_7505_configure,
1762 .fetch_size = intel_8xx_fetch_size,
1763 .cleanup = intel_8xx_cleanup,
1764 .tlb_flush = intel_8xx_tlbflush,
1765 .mask_memory = agp_generic_mask_memory,
1766 .masks = intel_generic_masks,
1767 .agp_enable = agp_generic_enable,
1768 .cache_flush = global_cache_flush,
1769 .create_gatt_table = agp_generic_create_gatt_table,
1770 .free_gatt_table = agp_generic_free_gatt_table,
1771 .insert_memory = agp_generic_insert_memory,
1772 .remove_memory = agp_generic_remove_memory,
1773 .alloc_by_type = agp_generic_alloc_by_type,
1774 .free_by_type = agp_generic_free_by_type,
1775 .agp_alloc_page = agp_generic_alloc_page,
1776 .agp_destroy_page = agp_generic_destroy_page,
1777 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1778 };
1779
1780 static const struct agp_bridge_driver intel_g33_driver = {
1781 .owner = THIS_MODULE,
1782 .aperture_sizes = intel_i830_sizes,
1783 .size_type = FIXED_APER_SIZE,
1784 .num_aperture_sizes = 4,
1785 .needs_scratch_page = TRUE,
1786 .configure = intel_i915_configure,
1787 .fetch_size = intel_i9xx_fetch_size,
1788 .cleanup = intel_i915_cleanup,
1789 .tlb_flush = intel_i810_tlbflush,
1790 .mask_memory = intel_i965_mask_memory,
1791 .masks = intel_i810_masks,
1792 .agp_enable = intel_i810_agp_enable,
1793 .cache_flush = global_cache_flush,
1794 .create_gatt_table = intel_i915_create_gatt_table,
1795 .free_gatt_table = intel_i830_free_gatt_table,
1796 .insert_memory = intel_i915_insert_entries,
1797 .remove_memory = intel_i915_remove_entries,
1798 .alloc_by_type = intel_i830_alloc_by_type,
1799 .free_by_type = intel_i810_free_by_type,
1800 .agp_alloc_page = agp_generic_alloc_page,
1801 .agp_destroy_page = agp_generic_destroy_page,
1802 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1803 };
1804
1805 static int find_gmch(u16 device)
1806 {
1807 struct pci_dev *gmch_device;
1808
1809 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1810 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1811 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1812 device, gmch_device);
1813 }
1814
1815 if (!gmch_device)
1816 return 0;
1817
1818 intel_private.pcidev = gmch_device;
1819 return 1;
1820 }
1821
1822 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1823 * driver and gmch_driver must be non-null, and find_gmch will determine
1824 * which one should be used if a gmch_chip_id is present.
1825 */
1826 static const struct intel_driver_description {
1827 unsigned int chip_id;
1828 unsigned int gmch_chip_id;
1829 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
1830 char *name;
1831 const struct agp_bridge_driver *driver;
1832 const struct agp_bridge_driver *gmch_driver;
1833 } intel_agp_chipsets[] = {
1834 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
1835 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
1836 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
1837 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
1838 NULL, &intel_810_driver },
1839 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
1840 NULL, &intel_810_driver },
1841 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
1842 NULL, &intel_810_driver },
1843 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
1844 &intel_815_driver, &intel_810_driver },
1845 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
1846 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
1847 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
1848 &intel_830mp_driver, &intel_830_driver },
1849 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
1850 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
1851 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
1852 &intel_845_driver, &intel_830_driver },
1853 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
1854 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
1855 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
1856 &intel_845_driver, &intel_830_driver },
1857 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
1858 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
1859 &intel_845_driver, &intel_830_driver },
1860 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
1861 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
1862 NULL, &intel_915_driver },
1863 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
1864 NULL, &intel_915_driver },
1865 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
1866 NULL, &intel_915_driver },
1867 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
1868 NULL, &intel_915_driver },
1869 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
1870 NULL, &intel_915_driver },
1871 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
1872 NULL, &intel_915_driver },
1873 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
1874 NULL, &intel_i965_driver },
1875 { PCI_DEVICE_ID_INTEL_82965G_1_HB, PCI_DEVICE_ID_INTEL_82965G_1_IG, 0, "965G",
1876 NULL, &intel_i965_driver },
1877 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
1878 NULL, &intel_i965_driver },
1879 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
1880 NULL, &intel_i965_driver },
1881 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
1882 NULL, &intel_i965_driver },
1883 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
1884 NULL, &intel_i965_driver },
1885 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
1886 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
1887 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
1888 NULL, &intel_g33_driver },
1889 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
1890 NULL, &intel_g33_driver },
1891 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
1892 NULL, &intel_g33_driver },
1893 { 0, 0, 0, NULL, NULL, NULL }
1894 };
1895
1896 static int __devinit agp_intel_probe(struct pci_dev *pdev,
1897 const struct pci_device_id *ent)
1898 {
1899 struct agp_bridge_data *bridge;
1900 u8 cap_ptr = 0;
1901 struct resource *r;
1902 int i;
1903
1904 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
1905
1906 bridge = agp_alloc_bridge();
1907 if (!bridge)
1908 return -ENOMEM;
1909
1910 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
1911 /* In case that multiple models of gfx chip may
1912 stand on same host bridge type, this can be
1913 sure we detect the right IGD. */
1914 if (pdev->device == intel_agp_chipsets[i].chip_id) {
1915 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
1916 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
1917 bridge->driver =
1918 intel_agp_chipsets[i].gmch_driver;
1919 break;
1920 } else if (intel_agp_chipsets[i].multi_gmch_chip) {
1921 continue;
1922 } else {
1923 bridge->driver = intel_agp_chipsets[i].driver;
1924 break;
1925 }
1926 }
1927 }
1928
1929 if (intel_agp_chipsets[i].name == NULL) {
1930 if (cap_ptr)
1931 printk(KERN_WARNING PFX "Unsupported Intel chipset"
1932 "(device id: %04x)\n", pdev->device);
1933 agp_put_bridge(bridge);
1934 return -ENODEV;
1935 }
1936
1937 if (bridge->driver == NULL) {
1938 /* bridge has no AGP and no IGD detected */
1939 if (cap_ptr)
1940 printk(KERN_WARNING PFX "Failed to find bridge device "
1941 "(chip_id: %04x)\n",
1942 intel_agp_chipsets[i].gmch_chip_id);
1943 agp_put_bridge(bridge);
1944 return -ENODEV;
1945 }
1946
1947 bridge->dev = pdev;
1948 bridge->capndx = cap_ptr;
1949 bridge->dev_private_data = &intel_private;
1950
1951 printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n",
1952 intel_agp_chipsets[i].name);
1953
1954 /*
1955 * The following fixes the case where the BIOS has "forgotten" to
1956 * provide an address range for the GART.
1957 * 20030610 - hamish@zot.org
1958 */
1959 r = &pdev->resource[0];
1960 if (!r->start && r->end) {
1961 if (pci_assign_resource(pdev, 0)) {
1962 printk(KERN_ERR PFX "could not assign resource 0\n");
1963 agp_put_bridge(bridge);
1964 return -ENODEV;
1965 }
1966 }
1967
1968 /*
1969 * If the device has not been properly setup, the following will catch
1970 * the problem and should stop the system from crashing.
1971 * 20030610 - hamish@zot.org
1972 */
1973 if (pci_enable_device(pdev)) {
1974 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
1975 agp_put_bridge(bridge);
1976 return -ENODEV;
1977 }
1978
1979 /* Fill in the mode register */
1980 if (cap_ptr) {
1981 pci_read_config_dword(pdev,
1982 bridge->capndx+PCI_AGP_STATUS,
1983 &bridge->mode);
1984 }
1985
1986 pci_set_drvdata(pdev, bridge);
1987 return agp_add_bridge(bridge);
1988 }
1989
1990 static void __devexit agp_intel_remove(struct pci_dev *pdev)
1991 {
1992 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1993
1994 agp_remove_bridge(bridge);
1995
1996 if (intel_private.pcidev)
1997 pci_dev_put(intel_private.pcidev);
1998
1999 agp_put_bridge(bridge);
2000 }
2001
2002 #ifdef CONFIG_PM
2003 static int agp_intel_resume(struct pci_dev *pdev)
2004 {
2005 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2006
2007 pci_restore_state(pdev);
2008
2009 /* We should restore our graphics device's config space,
2010 * as host bridge (00:00) resumes before graphics device (02:00),
2011 * then our access to its pci space can work right.
2012 */
2013 if (intel_private.pcidev)
2014 pci_restore_state(intel_private.pcidev);
2015
2016 if (bridge->driver == &intel_generic_driver)
2017 intel_configure();
2018 else if (bridge->driver == &intel_850_driver)
2019 intel_850_configure();
2020 else if (bridge->driver == &intel_845_driver)
2021 intel_845_configure();
2022 else if (bridge->driver == &intel_830mp_driver)
2023 intel_830mp_configure();
2024 else if (bridge->driver == &intel_915_driver)
2025 intel_i915_configure();
2026 else if (bridge->driver == &intel_830_driver)
2027 intel_i830_configure();
2028 else if (bridge->driver == &intel_810_driver)
2029 intel_i810_configure();
2030 else if (bridge->driver == &intel_i965_driver)
2031 intel_i915_configure();
2032
2033 return 0;
2034 }
2035 #endif
2036
2037 static struct pci_device_id agp_intel_pci_table[] = {
2038 #define ID(x) \
2039 { \
2040 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
2041 .class_mask = ~0, \
2042 .vendor = PCI_VENDOR_ID_INTEL, \
2043 .device = x, \
2044 .subvendor = PCI_ANY_ID, \
2045 .subdevice = PCI_ANY_ID, \
2046 }
2047 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2048 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2049 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2050 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2051 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2052 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2053 ID(PCI_DEVICE_ID_INTEL_82815_MC),
2054 ID(PCI_DEVICE_ID_INTEL_82820_HB),
2055 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2056 ID(PCI_DEVICE_ID_INTEL_82830_HB),
2057 ID(PCI_DEVICE_ID_INTEL_82840_HB),
2058 ID(PCI_DEVICE_ID_INTEL_82845_HB),
2059 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2060 ID(PCI_DEVICE_ID_INTEL_82850_HB),
2061 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2062 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2063 ID(PCI_DEVICE_ID_INTEL_82860_HB),
2064 ID(PCI_DEVICE_ID_INTEL_82865_HB),
2065 ID(PCI_DEVICE_ID_INTEL_82875_HB),
2066 ID(PCI_DEVICE_ID_INTEL_7505_0),
2067 ID(PCI_DEVICE_ID_INTEL_7205_0),
2068 ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2069 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2070 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2071 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2072 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2073 ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2074 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2075 ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
2076 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2077 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2078 ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2079 ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2080 ID(PCI_DEVICE_ID_INTEL_G33_HB),
2081 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2082 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2083 { }
2084 };
2085
2086 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2087
2088 static struct pci_driver agp_intel_pci_driver = {
2089 .name = "agpgart-intel",
2090 .id_table = agp_intel_pci_table,
2091 .probe = agp_intel_probe,
2092 .remove = __devexit_p(agp_intel_remove),
2093 #ifdef CONFIG_PM
2094 .resume = agp_intel_resume,
2095 #endif
2096 };
2097
2098 static int __init agp_intel_init(void)
2099 {
2100 if (agp_off)
2101 return -EINVAL;
2102 return pci_register_driver(&agp_intel_pci_driver);
2103 }
2104
2105 static void __exit agp_intel_cleanup(void)
2106 {
2107 pci_unregister_driver(&agp_intel_pci_driver);
2108 }
2109
2110 module_init(agp_intel_init);
2111 module_exit(agp_intel_cleanup);
2112
2113 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2114 MODULE_LICENSE("GPL and additional rights");
Linus' kernel tree