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sky2: rename up/down functions
[linux-2.6.git] / drivers / net / ethernet / marvell / sky2.c
blob98d435a187b101fd529845b34e10731e5587a73c
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/slab.h>
38 #include <net/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/in.h>
41 #include <linux/delay.h>
42 #include <linux/workqueue.h>
43 #include <linux/if_vlan.h>
44 #include <linux/prefetch.h>
45 #include <linux/debugfs.h>
46 #include <linux/mii.h>
47
48 #include <asm/irq.h>
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.29"
54
55 /*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
58 * similar to Tigon3.
59 */
60
61 #define RX_LE_SIZE 1024
62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
64 #define RX_DEF_PENDING RX_MAX_PENDING
65
66 /* This is the worst case number of transmit list elements for a single skb:
67 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
68 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
69 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
70 #define TX_MAX_PENDING 1024
71 #define TX_DEF_PENDING 127
72
73 #define TX_WATCHDOG (5 * HZ)
74 #define NAPI_WEIGHT 64
75 #define PHY_RETRIES 1000
76
77 #define SKY2_EEPROM_MAGIC 0x9955aabb
78
79 #define RING_NEXT(x, s) (((x)+1) & ((s)-1))
80
81 static const u32 default_msg =
82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
85
86 static int debug = -1; /* defaults above */
87 module_param(debug, int, 0);
88 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
90 static int copybreak __read_mostly = 128;
91 module_param(copybreak, int, 0);
92 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
94 static int disable_msi = 0;
95 module_param(disable_msi, int, 0);
96 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
98 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
99 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
102 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
140 { 0 }
141 };
142
143 MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145 /* Avoid conditionals by using array */
146 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
148 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
149
150 static void sky2_set_multicast(struct net_device *dev);
151 static irqreturn_t sky2_intr(int irq, void *dev_id);
152
153 /* Access to PHY via serial interconnect */
154 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
155 {
156 int i;
157
158 gma_write16(hw, port, GM_SMI_DATA, val);
159 gma_write16(hw, port, GM_SMI_CTRL,
160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
161
162 for (i = 0; i < PHY_RETRIES; i++) {
163 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
164 if (ctrl == 0xffff)
165 goto io_error;
166
167 if (!(ctrl & GM_SMI_CT_BUSY))
168 return 0;
169
170 udelay(10);
171 }
172
173 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
174 return -ETIMEDOUT;
175
176 io_error:
177 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
178 return -EIO;
179 }
180
181 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
182 {
183 int i;
184
185 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
186 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
187
188 for (i = 0; i < PHY_RETRIES; i++) {
189 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
190 if (ctrl == 0xffff)
191 goto io_error;
192
193 if (ctrl & GM_SMI_CT_RD_VAL) {
194 *val = gma_read16(hw, port, GM_SMI_DATA);
195 return 0;
196 }
197
198 udelay(10);
199 }
200
201 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
202 return -ETIMEDOUT;
203 io_error:
204 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
205 return -EIO;
206 }
207
208 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
209 {
210 u16 v;
211 __gm_phy_read(hw, port, reg, &v);
212 return v;
213 }
214
215
216 static void sky2_power_on(struct sky2_hw *hw)
217 {
218 /* switch power to VCC (WA for VAUX problem) */
219 sky2_write8(hw, B0_POWER_CTRL,
220 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
221
222 /* disable Core Clock Division, */
223 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
224
225 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
226 /* enable bits are inverted */
227 sky2_write8(hw, B2_Y2_CLK_GATE,
228 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
229 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
230 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
231 else
232 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
233
234 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
235 u32 reg;
236
237 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
238
239 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
240 /* set all bits to 0 except bits 15..12 and 8 */
241 reg &= P_ASPM_CONTROL_MSK;
242 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
243
244 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
245 /* set all bits to 0 except bits 28 & 27 */
246 reg &= P_CTL_TIM_VMAIN_AV_MSK;
247 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
248
249 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
250
251 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
252
253 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
254 reg = sky2_read32(hw, B2_GP_IO);
255 reg |= GLB_GPIO_STAT_RACE_DIS;
256 sky2_write32(hw, B2_GP_IO, reg);
257
258 sky2_read32(hw, B2_GP_IO);
259 }
260
261 /* Turn on "driver loaded" LED */
262 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
263 }
264
265 static void sky2_power_aux(struct sky2_hw *hw)
266 {
267 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
268 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
269 else
270 /* enable bits are inverted */
271 sky2_write8(hw, B2_Y2_CLK_GATE,
272 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
273 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
274 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
275
276 /* switch power to VAUX if supported and PME from D3cold */
277 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
278 pci_pme_capable(hw->pdev, PCI_D3cold))
279 sky2_write8(hw, B0_POWER_CTRL,
280 (PC_VAUX_ENA | PC_VCC_ENA |
281 PC_VAUX_ON | PC_VCC_OFF));
282
283 /* turn off "driver loaded LED" */
284 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
285 }
286
287 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
288 {
289 u16 reg;
290
291 /* disable all GMAC IRQ's */
292 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
293
294 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
295 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
298
299 reg = gma_read16(hw, port, GM_RX_CTRL);
300 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
301 gma_write16(hw, port, GM_RX_CTRL, reg);
302 }
303
304 /* flow control to advertise bits */
305 static const u16 copper_fc_adv[] = {
306 [FC_NONE] = 0,
307 [FC_TX] = PHY_M_AN_ASP,
308 [FC_RX] = PHY_M_AN_PC,
309 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
310 };
311
312 /* flow control to advertise bits when using 1000BaseX */
313 static const u16 fiber_fc_adv[] = {
314 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
315 [FC_TX] = PHY_M_P_ASYM_MD_X,
316 [FC_RX] = PHY_M_P_SYM_MD_X,
317 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
318 };
319
320 /* flow control to GMA disable bits */
321 static const u16 gm_fc_disable[] = {
322 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
323 [FC_TX] = GM_GPCR_FC_RX_DIS,
324 [FC_RX] = GM_GPCR_FC_TX_DIS,
325 [FC_BOTH] = 0,
326 };
327
328
329 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
330 {
331 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
332 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
333
334 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
335 !(hw->flags & SKY2_HW_NEWER_PHY)) {
336 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
337
338 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
339 PHY_M_EC_MAC_S_MSK);
340 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
341
342 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
343 if (hw->chip_id == CHIP_ID_YUKON_EC)
344 /* set downshift counter to 3x and enable downshift */
345 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
346 else
347 /* set master & slave downshift counter to 1x */
348 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
349
350 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
351 }
352
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
354 if (sky2_is_copper(hw)) {
355 if (!(hw->flags & SKY2_HW_GIGABIT)) {
356 /* enable automatic crossover */
357 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
358
359 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
360 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
361 u16 spec;
362
363 /* Enable Class A driver for FE+ A0 */
364 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
365 spec |= PHY_M_FESC_SEL_CL_A;
366 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
367 }
368 } else {
369 /* disable energy detect */
370 ctrl &= ~PHY_M_PC_EN_DET_MSK;
371
372 /* enable automatic crossover */
373 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
374
375 /* downshift on PHY 88E1112 and 88E1149 is changed */
376 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
377 (hw->flags & SKY2_HW_NEWER_PHY)) {
378 /* set downshift counter to 3x and enable downshift */
379 ctrl &= ~PHY_M_PC_DSC_MSK;
380 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
381 }
382 }
383 } else {
384 /* workaround for deviation #4.88 (CRC errors) */
385 /* disable Automatic Crossover */
386
387 ctrl &= ~PHY_M_PC_MDIX_MSK;
388 }
389
390 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
391
392 /* special setup for PHY 88E1112 Fiber */
393 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
394 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
395
396 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
397 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl &= ~PHY_M_MAC_MD_MSK;
400 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
401 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
402
403 if (hw->pmd_type == 'P') {
404 /* select page 1 to access Fiber registers */
405 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
406
407 /* for SFP-module set SIGDET polarity to low */
408 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
409 ctrl |= PHY_M_FIB_SIGD_POL;
410 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
411 }
412
413 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
414 }
415
416 ctrl = PHY_CT_RESET;
417 ct1000 = 0;
418 adv = PHY_AN_CSMA;
419 reg = 0;
420
421 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
422 if (sky2_is_copper(hw)) {
423 if (sky2->advertising & ADVERTISED_1000baseT_Full)
424 ct1000 |= PHY_M_1000C_AFD;
425 if (sky2->advertising & ADVERTISED_1000baseT_Half)
426 ct1000 |= PHY_M_1000C_AHD;
427 if (sky2->advertising & ADVERTISED_100baseT_Full)
428 adv |= PHY_M_AN_100_FD;
429 if (sky2->advertising & ADVERTISED_100baseT_Half)
430 adv |= PHY_M_AN_100_HD;
431 if (sky2->advertising & ADVERTISED_10baseT_Full)
432 adv |= PHY_M_AN_10_FD;
433 if (sky2->advertising & ADVERTISED_10baseT_Half)
434 adv |= PHY_M_AN_10_HD;
435
436 } else { /* special defines for FIBER (88E1040S only) */
437 if (sky2->advertising & ADVERTISED_1000baseT_Full)
438 adv |= PHY_M_AN_1000X_AFD;
439 if (sky2->advertising & ADVERTISED_1000baseT_Half)
440 adv |= PHY_M_AN_1000X_AHD;
441 }
442
443 /* Restart Auto-negotiation */
444 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
445 } else {
446 /* forced speed/duplex settings */
447 ct1000 = PHY_M_1000C_MSE;
448
449 /* Disable auto update for duplex flow control and duplex */
450 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
451
452 switch (sky2->speed) {
453 case SPEED_1000:
454 ctrl |= PHY_CT_SP1000;
455 reg |= GM_GPCR_SPEED_1000;
456 break;
457 case SPEED_100:
458 ctrl |= PHY_CT_SP100;
459 reg |= GM_GPCR_SPEED_100;
460 break;
461 }
462
463 if (sky2->duplex == DUPLEX_FULL) {
464 reg |= GM_GPCR_DUP_FULL;
465 ctrl |= PHY_CT_DUP_MD;
466 } else if (sky2->speed < SPEED_1000)
467 sky2->flow_mode = FC_NONE;
468 }
469
470 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
471 if (sky2_is_copper(hw))
472 adv |= copper_fc_adv[sky2->flow_mode];
473 else
474 adv |= fiber_fc_adv[sky2->flow_mode];
475 } else {
476 reg |= GM_GPCR_AU_FCT_DIS;
477 reg |= gm_fc_disable[sky2->flow_mode];
478
479 /* Forward pause packets to GMAC? */
480 if (sky2->flow_mode & FC_RX)
481 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
482 else
483 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
484 }
485
486 gma_write16(hw, port, GM_GP_CTRL, reg);
487
488 if (hw->flags & SKY2_HW_GIGABIT)
489 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
490
491 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
492 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
493
494 /* Setup Phy LED's */
495 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
496 ledover = 0;
497
498 switch (hw->chip_id) {
499 case CHIP_ID_YUKON_FE:
500 /* on 88E3082 these bits are at 11..9 (shifted left) */
501 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
502
503 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
504
505 /* delete ACT LED control bits */
506 ctrl &= ~PHY_M_FELP_LED1_MSK;
507 /* change ACT LED control to blink mode */
508 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
509 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
510 break;
511
512 case CHIP_ID_YUKON_FE_P:
513 /* Enable Link Partner Next Page */
514 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
515 ctrl |= PHY_M_PC_ENA_LIP_NP;
516
517 /* disable Energy Detect and enable scrambler */
518 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
519 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
520
521 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
522 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
523 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
524 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
525
526 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
527 break;
528
529 case CHIP_ID_YUKON_XL:
530 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
531
532 /* select page 3 to access LED control register */
533 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
534
535 /* set LED Function Control register */
536 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
537 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
538 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
539 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
540 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
541
542 /* set Polarity Control register */
543 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
544 (PHY_M_POLC_LS1_P_MIX(4) |
545 PHY_M_POLC_IS0_P_MIX(4) |
546 PHY_M_POLC_LOS_CTRL(2) |
547 PHY_M_POLC_INIT_CTRL(2) |
548 PHY_M_POLC_STA1_CTRL(2) |
549 PHY_M_POLC_STA0_CTRL(2)));
550
551 /* restore page register */
552 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
553 break;
554
555 case CHIP_ID_YUKON_EC_U:
556 case CHIP_ID_YUKON_EX:
557 case CHIP_ID_YUKON_SUPR:
558 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
559
560 /* select page 3 to access LED control register */
561 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
562
563 /* set LED Function Control register */
564 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
565 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
566 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
567 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
568 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
569
570 /* set Blink Rate in LED Timer Control Register */
571 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
572 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
573 /* restore page register */
574 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
575 break;
576
577 default:
578 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
579 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
580
581 /* turn off the Rx LED (LED_RX) */
582 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
583 }
584
585 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
586 /* apply fixes in PHY AFE */
587 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
588
589 /* increase differential signal amplitude in 10BASE-T */
590 gm_phy_write(hw, port, 0x18, 0xaa99);
591 gm_phy_write(hw, port, 0x17, 0x2011);
592
593 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
594 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
595 gm_phy_write(hw, port, 0x18, 0xa204);
596 gm_phy_write(hw, port, 0x17, 0x2002);
597 }
598
599 /* set page register to 0 */
600 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
601 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
602 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
603 /* apply workaround for integrated resistors calibration */
604 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
605 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
606 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
607 /* apply fixes in PHY AFE */
608 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
609
610 /* apply RDAC termination workaround */
611 gm_phy_write(hw, port, 24, 0x2800);
612 gm_phy_write(hw, port, 23, 0x2001);
613
614 /* set page register back to 0 */
615 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
616 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
617 hw->chip_id < CHIP_ID_YUKON_SUPR) {
618 /* no effect on Yukon-XL */
619 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
620
621 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
622 sky2->speed == SPEED_100) {
623 /* turn on 100 Mbps LED (LED_LINK100) */
624 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
625 }
626
627 if (ledover)
628 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
629
630 } else if (hw->chip_id == CHIP_ID_YUKON_PRM &&
631 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) {
632 int i;
633 /* This a phy register setup workaround copied from vendor driver. */
634 static const struct {
635 u16 reg, val;
636 } eee_afe[] = {
637 { 0x156, 0x58ce },
638 { 0x153, 0x99eb },
639 { 0x141, 0x8064 },
640 /* { 0x155, 0x130b },*/
641 { 0x000, 0x0000 },
642 { 0x151, 0x8433 },
643 { 0x14b, 0x8c44 },
644 { 0x14c, 0x0f90 },
645 { 0x14f, 0x39aa },
646 /* { 0x154, 0x2f39 },*/
647 { 0x14d, 0xba33 },
648 { 0x144, 0x0048 },
649 { 0x152, 0x2010 },
650 /* { 0x158, 0x1223 },*/
651 { 0x140, 0x4444 },
652 { 0x154, 0x2f3b },
653 { 0x158, 0xb203 },
654 { 0x157, 0x2029 },
655 };
656
657 /* Start Workaround for OptimaEEE Rev.Z0 */
658 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb);
659
660 gm_phy_write(hw, port, 1, 0x4099);
661 gm_phy_write(hw, port, 3, 0x1120);
662 gm_phy_write(hw, port, 11, 0x113c);
663 gm_phy_write(hw, port, 14, 0x8100);
664 gm_phy_write(hw, port, 15, 0x112a);
665 gm_phy_write(hw, port, 17, 0x1008);
666
667 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc);
668 gm_phy_write(hw, port, 1, 0x20b0);
669
670 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
671
672 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) {
673 /* apply AFE settings */
674 gm_phy_write(hw, port, 17, eee_afe[i].val);
675 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13);
676 }
677
678 /* End Workaround for OptimaEEE */
679 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
680
681 /* Enable 10Base-Te (EEE) */
682 if (hw->chip_id >= CHIP_ID_YUKON_PRM) {
683 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
684 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL,
685 reg | PHY_M_10B_TE_ENABLE);
686 }
687 }
688
689 /* Enable phy interrupt on auto-negotiation complete (or link up) */
690 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
691 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
692 else
693 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
694 }
695
696 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
697 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
698
699 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
700 {
701 u32 reg1;
702
703 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
704 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
705 reg1 &= ~phy_power[port];
706
707 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
708 reg1 |= coma_mode[port];
709
710 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
711 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
712 sky2_pci_read32(hw, PCI_DEV_REG1);
713
714 if (hw->chip_id == CHIP_ID_YUKON_FE)
715 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
716 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
717 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
718 }
719
720 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
721 {
722 u32 reg1;
723 u16 ctrl;
724
725 /* release GPHY Control reset */
726 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
727
728 /* release GMAC reset */
729 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
730
731 if (hw->flags & SKY2_HW_NEWER_PHY) {
732 /* select page 2 to access MAC control register */
733 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
734
735 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
736 /* allow GMII Power Down */
737 ctrl &= ~PHY_M_MAC_GMIF_PUP;
738 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
739
740 /* set page register back to 0 */
741 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
742 }
743
744 /* setup General Purpose Control Register */
745 gma_write16(hw, port, GM_GP_CTRL,
746 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
747 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
748 GM_GPCR_AU_SPD_DIS);
749
750 if (hw->chip_id != CHIP_ID_YUKON_EC) {
751 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
752 /* select page 2 to access MAC control register */
753 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
754
755 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
756 /* enable Power Down */
757 ctrl |= PHY_M_PC_POW_D_ENA;
758 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
759
760 /* set page register back to 0 */
761 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
762 }
763
764 /* set IEEE compatible Power Down Mode (dev. #4.99) */
765 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
766 }
767
768 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
769 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
770 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
771 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
772 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
773 }
774
775 /* configure IPG according to used link speed */
776 static void sky2_set_ipg(struct sky2_port *sky2)
777 {
778 u16 reg;
779
780 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE);
781 reg &= ~GM_SMOD_IPG_MSK;
782 if (sky2->speed > SPEED_100)
783 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
784 else
785 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
786 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg);
787 }
788
789 /* Enable Rx/Tx */
790 static void sky2_enable_rx_tx(struct sky2_port *sky2)
791 {
792 struct sky2_hw *hw = sky2->hw;
793 unsigned port = sky2->port;
794 u16 reg;
795
796 reg = gma_read16(hw, port, GM_GP_CTRL);
797 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
798 gma_write16(hw, port, GM_GP_CTRL, reg);
799 }
800
801 /* Force a renegotiation */
802 static void sky2_phy_reinit(struct sky2_port *sky2)
803 {
804 spin_lock_bh(&sky2->phy_lock);
805 sky2_phy_init(sky2->hw, sky2->port);
806 sky2_enable_rx_tx(sky2);
807 spin_unlock_bh(&sky2->phy_lock);
808 }
809
810 /* Put device in state to listen for Wake On Lan */
811 static void sky2_wol_init(struct sky2_port *sky2)
812 {
813 struct sky2_hw *hw = sky2->hw;
814 unsigned port = sky2->port;
815 enum flow_control save_mode;
816 u16 ctrl;
817
818 /* Bring hardware out of reset */
819 sky2_write16(hw, B0_CTST, CS_RST_CLR);
820 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
821
822 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
823 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
824
825 /* Force to 10/100
826 * sky2_reset will re-enable on resume
827 */
828 save_mode = sky2->flow_mode;
829 ctrl = sky2->advertising;
830
831 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
832 sky2->flow_mode = FC_NONE;
833
834 spin_lock_bh(&sky2->phy_lock);
835 sky2_phy_power_up(hw, port);
836 sky2_phy_init(hw, port);
837 spin_unlock_bh(&sky2->phy_lock);
838
839 sky2->flow_mode = save_mode;
840 sky2->advertising = ctrl;
841
842 /* Set GMAC to no flow control and auto update for speed/duplex */
843 gma_write16(hw, port, GM_GP_CTRL,
844 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
845 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
846
847 /* Set WOL address */
848 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
849 sky2->netdev->dev_addr, ETH_ALEN);
850
851 /* Turn on appropriate WOL control bits */
852 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
853 ctrl = 0;
854 if (sky2->wol & WAKE_PHY)
855 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
856 else
857 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
858
859 if (sky2->wol & WAKE_MAGIC)
860 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
861 else
862 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
863
864 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
865 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
866
867 /* Disable PiG firmware */
868 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
869
870 /* block receiver */
871 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
872 sky2_read32(hw, B0_CTST);
873 }
874
875 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
876 {
877 struct net_device *dev = hw->dev[port];
878
879 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
880 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
881 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
882 /* Yukon-Extreme B0 and further Extreme devices */
883 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
884 } else if (dev->mtu > ETH_DATA_LEN) {
885 /* set Tx GMAC FIFO Almost Empty Threshold */
886 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
887 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
888
889 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
890 } else
891 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
892 }
893
894 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
895 {
896 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
897 u16 reg;
898 u32 rx_reg;
899 int i;
900 const u8 *addr = hw->dev[port]->dev_addr;
901
902 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
903 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
904
905 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
906
907 if (hw->chip_id == CHIP_ID_YUKON_XL &&
908 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
909 port == 1) {
910 /* WA DEV_472 -- looks like crossed wires on port 2 */
911 /* clear GMAC 1 Control reset */
912 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
913 do {
914 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
915 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
916 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
917 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
918 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
919 }
920
921 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
922
923 /* Enable Transmit FIFO Underrun */
924 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
925
926 spin_lock_bh(&sky2->phy_lock);
927 sky2_phy_power_up(hw, port);
928 sky2_phy_init(hw, port);
929 spin_unlock_bh(&sky2->phy_lock);
930
931 /* MIB clear */
932 reg = gma_read16(hw, port, GM_PHY_ADDR);
933 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
934
935 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
936 gma_read16(hw, port, i);
937 gma_write16(hw, port, GM_PHY_ADDR, reg);
938
939 /* transmit control */
940 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
941
942 /* receive control reg: unicast + multicast + no FCS */
943 gma_write16(hw, port, GM_RX_CTRL,
944 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
945
946 /* transmit flow control */
947 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
948
949 /* transmit parameter */
950 gma_write16(hw, port, GM_TX_PARAM,
951 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
952 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
953 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
954 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
955
956 /* serial mode register */
957 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
958 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000);
959
960 if (hw->dev[port]->mtu > ETH_DATA_LEN)
961 reg |= GM_SMOD_JUMBO_ENA;
962
963 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
964 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
965 reg |= GM_NEW_FLOW_CTRL;
966
967 gma_write16(hw, port, GM_SERIAL_MODE, reg);
968
969 /* virtual address for data */
970 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
971
972 /* physical address: used for pause frames */
973 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
974
975 /* ignore counter overflows */
976 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
977 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
978 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
979
980 /* Configure Rx MAC FIFO */
981 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
982 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
983 if (hw->chip_id == CHIP_ID_YUKON_EX ||
984 hw->chip_id == CHIP_ID_YUKON_FE_P)
985 rx_reg |= GMF_RX_OVER_ON;
986
987 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
988
989 if (hw->chip_id == CHIP_ID_YUKON_XL) {
990 /* Hardware errata - clear flush mask */
991 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
992 } else {
993 /* Flush Rx MAC FIFO on any flow control or error */
994 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
995 }
996
997 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
998 reg = RX_GMF_FL_THR_DEF + 1;
999 /* Another magic mystery workaround from sk98lin */
1000 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1001 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1002 reg = 0x178;
1003 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
1004
1005 /* Configure Tx MAC FIFO */
1006 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1007 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1008
1009 /* On chips without ram buffer, pause is controlled by MAC level */
1010 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
1011 /* Pause threshold is scaled by 8 in bytes */
1012 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1013 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1014 reg = 1568 / 8;
1015 else
1016 reg = 1024 / 8;
1017 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
1018 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
1019
1020 sky2_set_tx_stfwd(hw, port);
1021 }
1022
1023 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1024 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
1025 /* disable dynamic watermark */
1026 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
1027 reg &= ~TX_DYN_WM_ENA;
1028 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
1029 }
1030 }
1031
1032 /* Assign Ram Buffer allocation to queue */
1033 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
1034 {
1035 u32 end;
1036
1037 /* convert from K bytes to qwords used for hw register */
1038 start *= 1024/8;
1039 space *= 1024/8;
1040 end = start + space - 1;
1041
1042 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1043 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1044 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1045 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1046 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1047
1048 if (q == Q_R1 || q == Q_R2) {
1049 u32 tp = space - space/4;
1050
1051 /* On receive queue's set the thresholds
1052 * give receiver priority when > 3/4 full
1053 * send pause when down to 2K
1054 */
1055 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1056 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
1057
1058 tp = space - 2048/8;
1059 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1060 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
1061 } else {
1062 /* Enable store & forward on Tx queue's because
1063 * Tx FIFO is only 1K on Yukon
1064 */
1065 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1066 }
1067
1068 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1069 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1070 }
1071
1072 /* Setup Bus Memory Interface */
1073 static void sky2_qset(struct sky2_hw *hw, u16 q)
1074 {
1075 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1076 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1077 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1078 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1079 }
1080
1081 /* Setup prefetch unit registers. This is the interface between
1082 * hardware and driver list elements
1083 */
1084 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1085 dma_addr_t addr, u32 last)
1086 {
1087 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1088 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1089 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1090 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1091 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1092 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1093
1094 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1095 }
1096
1097 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1098 {
1099 struct sky2_tx_le *le = sky2->tx_le + *slot;
1100
1101 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1102 le->ctrl = 0;
1103 return le;
1104 }
1105
1106 static void tx_init(struct sky2_port *sky2)
1107 {
1108 struct sky2_tx_le *le;
1109
1110 sky2->tx_prod = sky2->tx_cons = 0;
1111 sky2->tx_tcpsum = 0;
1112 sky2->tx_last_mss = 0;
1113
1114 le = get_tx_le(sky2, &sky2->tx_prod);
1115 le->addr = 0;
1116 le->opcode = OP_ADDR64 | HW_OWNER;
1117 sky2->tx_last_upper = 0;
1118 }
1119
1120 /* Update chip's next pointer */
1121 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1122 {
1123 /* Make sure write' to descriptors are complete before we tell hardware */
1124 wmb();
1125 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1126
1127 /* Synchronize I/O on since next processor may write to tail */
1128 mmiowb();
1129 }
1130
1131
1132 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1133 {
1134 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1135 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1136 le->ctrl = 0;
1137 return le;
1138 }
1139
1140 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
1141 {
1142 unsigned size;
1143
1144 /* Space needed for frame data + headers rounded up */
1145 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1146
1147 /* Stopping point for hardware truncation */
1148 return (size - 8) / sizeof(u32);
1149 }
1150
1151 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
1152 {
1153 struct rx_ring_info *re;
1154 unsigned size;
1155
1156 /* Space needed for frame data + headers rounded up */
1157 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1158
1159 sky2->rx_nfrags = size >> PAGE_SHIFT;
1160 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1161
1162 /* Compute residue after pages */
1163 size -= sky2->rx_nfrags << PAGE_SHIFT;
1164
1165 /* Optimize to handle small packets and headers */
1166 if (size < copybreak)
1167 size = copybreak;
1168 if (size < ETH_HLEN)
1169 size = ETH_HLEN;
1170
1171 return size;
1172 }
1173
1174 /* Build description to hardware for one receive segment */
1175 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1176 dma_addr_t map, unsigned len)
1177 {
1178 struct sky2_rx_le *le;
1179
1180 if (sizeof(dma_addr_t) > sizeof(u32)) {
1181 le = sky2_next_rx(sky2);
1182 le->addr = cpu_to_le32(upper_32_bits(map));
1183 le->opcode = OP_ADDR64 | HW_OWNER;
1184 }
1185
1186 le = sky2_next_rx(sky2);
1187 le->addr = cpu_to_le32(lower_32_bits(map));
1188 le->length = cpu_to_le16(len);
1189 le->opcode = op | HW_OWNER;
1190 }
1191
1192 /* Build description to hardware for one possibly fragmented skb */
1193 static void sky2_rx_submit(struct sky2_port *sky2,
1194 const struct rx_ring_info *re)
1195 {
1196 int i;
1197
1198 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1199
1200 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1201 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1202 }
1203
1204
1205 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1206 unsigned size)
1207 {
1208 struct sk_buff *skb = re->skb;
1209 int i;
1210
1211 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1212 if (pci_dma_mapping_error(pdev, re->data_addr))
1213 goto mapping_error;
1214
1215 dma_unmap_len_set(re, data_size, size);
1216
1217 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1218 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1219
1220 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0,
1221 skb_frag_size(frag),
1222 DMA_FROM_DEVICE);
1223
1224 if (dma_mapping_error(&pdev->dev, re->frag_addr[i]))
1225 goto map_page_error;
1226 }
1227 return 0;
1228
1229 map_page_error:
1230 while (--i >= 0) {
1231 pci_unmap_page(pdev, re->frag_addr[i],
1232 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1233 PCI_DMA_FROMDEVICE);
1234 }
1235
1236 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1237 PCI_DMA_FROMDEVICE);
1238
1239 mapping_error:
1240 if (net_ratelimit())
1241 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1242 skb->dev->name);
1243 return -EIO;
1244 }
1245
1246 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1247 {
1248 struct sk_buff *skb = re->skb;
1249 int i;
1250
1251 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1252 PCI_DMA_FROMDEVICE);
1253
1254 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1255 pci_unmap_page(pdev, re->frag_addr[i],
1256 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1257 PCI_DMA_FROMDEVICE);
1258 }
1259
1260 /* Tell chip where to start receive checksum.
1261 * Actually has two checksums, but set both same to avoid possible byte
1262 * order problems.
1263 */
1264 static void rx_set_checksum(struct sky2_port *sky2)
1265 {
1266 struct sky2_rx_le *le = sky2_next_rx(sky2);
1267
1268 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1269 le->ctrl = 0;
1270 le->opcode = OP_TCPSTART | HW_OWNER;
1271
1272 sky2_write32(sky2->hw,
1273 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1274 (sky2->netdev->features & NETIF_F_RXCSUM)
1275 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1276 }
1277
1278 /* Enable/disable receive hash calculation (RSS) */
1279 static void rx_set_rss(struct net_device *dev, u32 features)
1280 {
1281 struct sky2_port *sky2 = netdev_priv(dev);
1282 struct sky2_hw *hw = sky2->hw;
1283 int i, nkeys = 4;
1284
1285 /* Supports IPv6 and other modes */
1286 if (hw->flags & SKY2_HW_NEW_LE) {
1287 nkeys = 10;
1288 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1289 }
1290
1291 /* Program RSS initial values */
1292 if (features & NETIF_F_RXHASH) {
1293 u32 key[nkeys];
1294
1295 get_random_bytes(key, nkeys * sizeof(u32));
1296 for (i = 0; i < nkeys; i++)
1297 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1298 key[i]);
1299
1300 /* Need to turn on (undocumented) flag to make hashing work */
1301 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1302 RX_STFW_ENA);
1303
1304 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1305 BMU_ENA_RX_RSS_HASH);
1306 } else
1307 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1308 BMU_DIS_RX_RSS_HASH);
1309 }
1310
1311 /*
1312 * The RX Stop command will not work for Yukon-2 if the BMU does not
1313 * reach the end of packet and since we can't make sure that we have
1314 * incoming data, we must reset the BMU while it is not doing a DMA
1315 * transfer. Since it is possible that the RX path is still active,
1316 * the RX RAM buffer will be stopped first, so any possible incoming
1317 * data will not trigger a DMA. After the RAM buffer is stopped, the
1318 * BMU is polled until any DMA in progress is ended and only then it
1319 * will be reset.
1320 */
1321 static void sky2_rx_stop(struct sky2_port *sky2)
1322 {
1323 struct sky2_hw *hw = sky2->hw;
1324 unsigned rxq = rxqaddr[sky2->port];
1325 int i;
1326
1327 /* disable the RAM Buffer receive queue */
1328 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1329
1330 for (i = 0; i < 0xffff; i++)
1331 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1332 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1333 goto stopped;
1334
1335 netdev_warn(sky2->netdev, "receiver stop failed\n");
1336 stopped:
1337 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1338
1339 /* reset the Rx prefetch unit */
1340 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1341 mmiowb();
1342 }
1343
1344 /* Clean out receive buffer area, assumes receiver hardware stopped */
1345 static void sky2_rx_clean(struct sky2_port *sky2)
1346 {
1347 unsigned i;
1348
1349 memset(sky2->rx_le, 0, RX_LE_BYTES);
1350 for (i = 0; i < sky2->rx_pending; i++) {
1351 struct rx_ring_info *re = sky2->rx_ring + i;
1352
1353 if (re->skb) {
1354 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1355 kfree_skb(re->skb);
1356 re->skb = NULL;
1357 }
1358 }
1359 }
1360
1361 /* Basic MII support */
1362 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1363 {
1364 struct mii_ioctl_data *data = if_mii(ifr);
1365 struct sky2_port *sky2 = netdev_priv(dev);
1366 struct sky2_hw *hw = sky2->hw;
1367 int err = -EOPNOTSUPP;
1368
1369 if (!netif_running(dev))
1370 return -ENODEV; /* Phy still in reset */
1371
1372 switch (cmd) {
1373 case SIOCGMIIPHY:
1374 data->phy_id = PHY_ADDR_MARV;
1375
1376 /* fallthru */
1377 case SIOCGMIIREG: {
1378 u16 val = 0;
1379
1380 spin_lock_bh(&sky2->phy_lock);
1381 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1382 spin_unlock_bh(&sky2->phy_lock);
1383
1384 data->val_out = val;
1385 break;
1386 }
1387
1388 case SIOCSMIIREG:
1389 spin_lock_bh(&sky2->phy_lock);
1390 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1391 data->val_in);
1392 spin_unlock_bh(&sky2->phy_lock);
1393 break;
1394 }
1395 return err;
1396 }
1397
1398 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
1399
1400 static void sky2_vlan_mode(struct net_device *dev, u32 features)
1401 {
1402 struct sky2_port *sky2 = netdev_priv(dev);
1403 struct sky2_hw *hw = sky2->hw;
1404 u16 port = sky2->port;
1405
1406 if (features & NETIF_F_HW_VLAN_RX)
1407 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1408 RX_VLAN_STRIP_ON);
1409 else
1410 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1411 RX_VLAN_STRIP_OFF);
1412
1413 if (features & NETIF_F_HW_VLAN_TX) {
1414 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1415 TX_VLAN_TAG_ON);
1416
1417 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
1418 } else {
1419 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1420 TX_VLAN_TAG_OFF);
1421
1422 /* Can't do transmit offload of vlan without hw vlan */
1423 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS;
1424 }
1425 }
1426
1427 /* Amount of required worst case padding in rx buffer */
1428 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1429 {
1430 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1431 }
1432
1433 /*
1434 * Allocate an skb for receiving. If the MTU is large enough
1435 * make the skb non-linear with a fragment list of pages.
1436 */
1437 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp)
1438 {
1439 struct sk_buff *skb;
1440 int i;
1441
1442 skb = __netdev_alloc_skb(sky2->netdev,
1443 sky2->rx_data_size + sky2_rx_pad(sky2->hw),
1444 gfp);
1445 if (!skb)
1446 goto nomem;
1447
1448 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1449 unsigned char *start;
1450 /*
1451 * Workaround for a bug in FIFO that cause hang
1452 * if the FIFO if the receive buffer is not 64 byte aligned.
1453 * The buffer returned from netdev_alloc_skb is
1454 * aligned except if slab debugging is enabled.
1455 */
1456 start = PTR_ALIGN(skb->data, 8);
1457 skb_reserve(skb, start - skb->data);
1458 } else
1459 skb_reserve(skb, NET_IP_ALIGN);
1460
1461 for (i = 0; i < sky2->rx_nfrags; i++) {
1462 struct page *page = alloc_page(gfp);
1463
1464 if (!page)
1465 goto free_partial;
1466 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1467 }
1468
1469 return skb;
1470 free_partial:
1471 kfree_skb(skb);
1472 nomem:
1473 return NULL;
1474 }
1475
1476 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1477 {
1478 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1479 }
1480
1481 static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1482 {
1483 struct sky2_hw *hw = sky2->hw;
1484 unsigned i;
1485
1486 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1487
1488 /* Fill Rx ring */
1489 for (i = 0; i < sky2->rx_pending; i++) {
1490 struct rx_ring_info *re = sky2->rx_ring + i;
1491
1492 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL);
1493 if (!re->skb)
1494 return -ENOMEM;
1495
1496 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1497 dev_kfree_skb(re->skb);
1498 re->skb = NULL;
1499 return -ENOMEM;
1500 }
1501 }
1502 return 0;
1503 }
1504
1505 /*
1506 * Setup receiver buffer pool.
1507 * Normal case this ends up creating one list element for skb
1508 * in the receive ring. Worst case if using large MTU and each
1509 * allocation falls on a different 64 bit region, that results
1510 * in 6 list elements per ring entry.
1511 * One element is used for checksum enable/disable, and one
1512 * extra to avoid wrap.
1513 */
1514 static void sky2_rx_start(struct sky2_port *sky2)
1515 {
1516 struct sky2_hw *hw = sky2->hw;
1517 struct rx_ring_info *re;
1518 unsigned rxq = rxqaddr[sky2->port];
1519 unsigned i, thresh;
1520
1521 sky2->rx_put = sky2->rx_next = 0;
1522 sky2_qset(hw, rxq);
1523
1524 /* On PCI express lowering the watermark gives better performance */
1525 if (pci_is_pcie(hw->pdev))
1526 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1527
1528 /* These chips have no ram buffer?
1529 * MAC Rx RAM Read is controlled by hardware */
1530 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1531 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
1532 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1533
1534 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1535
1536 if (!(hw->flags & SKY2_HW_NEW_LE))
1537 rx_set_checksum(sky2);
1538
1539 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1540 rx_set_rss(sky2->netdev, sky2->netdev->features);
1541
1542 /* submit Rx ring */
1543 for (i = 0; i < sky2->rx_pending; i++) {
1544 re = sky2->rx_ring + i;
1545 sky2_rx_submit(sky2, re);
1546 }
1547
1548 /*
1549 * The receiver hangs if it receives frames larger than the
1550 * packet buffer. As a workaround, truncate oversize frames, but
1551 * the register is limited to 9 bits, so if you do frames > 2052
1552 * you better get the MTU right!
1553 */
1554 thresh = sky2_get_rx_threshold(sky2);
1555 if (thresh > 0x1ff)
1556 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1557 else {
1558 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1559 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1560 }
1561
1562 /* Tell chip about available buffers */
1563 sky2_rx_update(sky2, rxq);
1564
1565 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1566 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1567 /*
1568 * Disable flushing of non ASF packets;
1569 * must be done after initializing the BMUs;
1570 * drivers without ASF support should do this too, otherwise
1571 * it may happen that they cannot run on ASF devices;
1572 * remember that the MAC FIFO isn't reset during initialization.
1573 */
1574 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1575 }
1576
1577 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1578 /* Enable RX Home Address & Routing Header checksum fix */
1579 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1580 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1581
1582 /* Enable TX Home Address & Routing Header checksum fix */
1583 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1584 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1585 }
1586 }
1587
1588 static int sky2_alloc_buffers(struct sky2_port *sky2)
1589 {
1590 struct sky2_hw *hw = sky2->hw;
1591
1592 /* must be power of 2 */
1593 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1594 sky2->tx_ring_size *
1595 sizeof(struct sky2_tx_le),
1596 &sky2->tx_le_map);
1597 if (!sky2->tx_le)
1598 goto nomem;
1599
1600 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1601 GFP_KERNEL);
1602 if (!sky2->tx_ring)
1603 goto nomem;
1604
1605 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1606 &sky2->rx_le_map);
1607 if (!sky2->rx_le)
1608 goto nomem;
1609 memset(sky2->rx_le, 0, RX_LE_BYTES);
1610
1611 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1612 GFP_KERNEL);
1613 if (!sky2->rx_ring)
1614 goto nomem;
1615
1616 return sky2_alloc_rx_skbs(sky2);
1617 nomem:
1618 return -ENOMEM;
1619 }
1620
1621 static void sky2_free_buffers(struct sky2_port *sky2)
1622 {
1623 struct sky2_hw *hw = sky2->hw;
1624
1625 sky2_rx_clean(sky2);
1626
1627 if (sky2->rx_le) {
1628 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1629 sky2->rx_le, sky2->rx_le_map);
1630 sky2->rx_le = NULL;
1631 }
1632 if (sky2->tx_le) {
1633 pci_free_consistent(hw->pdev,
1634 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1635 sky2->tx_le, sky2->tx_le_map);
1636 sky2->tx_le = NULL;
1637 }
1638 kfree(sky2->tx_ring);
1639 kfree(sky2->rx_ring);
1640
1641 sky2->tx_ring = NULL;
1642 sky2->rx_ring = NULL;
1643 }
1644
1645 static void sky2_hw_up(struct sky2_port *sky2)
1646 {
1647 struct sky2_hw *hw = sky2->hw;
1648 unsigned port = sky2->port;
1649 u32 ramsize;
1650 int cap;
1651 struct net_device *otherdev = hw->dev[sky2->port^1];
1652
1653 tx_init(sky2);
1654
1655 /*
1656 * On dual port PCI-X card, there is an problem where status
1657 * can be received out of order due to split transactions
1658 */
1659 if (otherdev && netif_running(otherdev) &&
1660 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1661 u16 cmd;
1662
1663 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1664 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1665 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1666 }
1667
1668 sky2_mac_init(hw, port);
1669
1670 /* Register is number of 4K blocks on internal RAM buffer. */
1671 ramsize = sky2_read8(hw, B2_E_0) * 4;
1672 if (ramsize > 0) {
1673 u32 rxspace;
1674
1675 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
1676 if (ramsize < 16)
1677 rxspace = ramsize / 2;
1678 else
1679 rxspace = 8 + (2*(ramsize - 16))/3;
1680
1681 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1682 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1683
1684 /* Make sure SyncQ is disabled */
1685 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1686 RB_RST_SET);
1687 }
1688
1689 sky2_qset(hw, txqaddr[port]);
1690
1691 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1692 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1693 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1694
1695 /* Set almost empty threshold */
1696 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1697 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1698 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1699
1700 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1701 sky2->tx_ring_size - 1);
1702
1703 sky2_vlan_mode(sky2->netdev, sky2->netdev->features);
1704 netdev_update_features(sky2->netdev);
1705
1706 sky2_rx_start(sky2);
1707 }
1708
1709 /* Setup device IRQ and enable napi to process */
1710 static int sky2_setup_irq(struct sky2_hw *hw, const char *name)
1711 {
1712 struct pci_dev *pdev = hw->pdev;
1713 int err;
1714
1715 err = request_irq(pdev->irq, sky2_intr,
1716 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
1717 name, hw);
1718 if (err)
1719 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
1720 else {
1721 napi_enable(&hw->napi);
1722 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
1723 sky2_read32(hw, B0_IMSK);
1724 }
1725
1726 return err;
1727 }
1728
1729
1730 /* Bring up network interface. */
1731 static int sky2_open(struct net_device *dev)
1732 {
1733 struct sky2_port *sky2 = netdev_priv(dev);
1734 struct sky2_hw *hw = sky2->hw;
1735 unsigned port = sky2->port;
1736 u32 imask;
1737 int err;
1738
1739 netif_carrier_off(dev);
1740
1741 err = sky2_alloc_buffers(sky2);
1742 if (err)
1743 goto err_out;
1744
1745 /* With single port, IRQ is setup when device is brought up */
1746 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name)))
1747 goto err_out;
1748
1749 sky2_hw_up(sky2);
1750
1751 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
1752 hw->chip_id == CHIP_ID_YUKON_PRM ||
1753 hw->chip_id == CHIP_ID_YUKON_OP_2)
1754 imask |= Y2_IS_PHY_QLNK; /* enable PHY Quick Link */
1755
1756 /* Enable interrupts from phy/mac for port */
1757 imask = sky2_read32(hw, B0_IMSK);
1758 imask |= portirq_msk[port];
1759 sky2_write32(hw, B0_IMSK, imask);
1760 sky2_read32(hw, B0_IMSK);
1761
1762 netif_info(sky2, ifup, dev, "enabling interface\n");
1763
1764 return 0;
1765
1766 err_out:
1767 sky2_free_buffers(sky2);
1768 return err;
1769 }
1770
1771 /* Modular subtraction in ring */
1772 static inline int tx_inuse(const struct sky2_port *sky2)
1773 {
1774 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1775 }
1776
1777 /* Number of list elements available for next tx */
1778 static inline int tx_avail(const struct sky2_port *sky2)
1779 {
1780 return sky2->tx_pending - tx_inuse(sky2);
1781 }
1782
1783 /* Estimate of number of transmit list elements required */
1784 static unsigned tx_le_req(const struct sk_buff *skb)
1785 {
1786 unsigned count;
1787
1788 count = (skb_shinfo(skb)->nr_frags + 1)
1789 * (sizeof(dma_addr_t) / sizeof(u32));
1790
1791 if (skb_is_gso(skb))
1792 ++count;
1793 else if (sizeof(dma_addr_t) == sizeof(u32))
1794 ++count; /* possible vlan */
1795
1796 if (skb->ip_summed == CHECKSUM_PARTIAL)
1797 ++count;
1798
1799 return count;
1800 }
1801
1802 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1803 {
1804 if (re->flags & TX_MAP_SINGLE)
1805 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1806 dma_unmap_len(re, maplen),
1807 PCI_DMA_TODEVICE);
1808 else if (re->flags & TX_MAP_PAGE)
1809 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1810 dma_unmap_len(re, maplen),
1811 PCI_DMA_TODEVICE);
1812 re->flags = 0;
1813 }
1814
1815 /*
1816 * Put one packet in ring for transmit.
1817 * A single packet can generate multiple list elements, and
1818 * the number of ring elements will probably be less than the number
1819 * of list elements used.
1820 */
1821 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1822 struct net_device *dev)
1823 {
1824 struct sky2_port *sky2 = netdev_priv(dev);
1825 struct sky2_hw *hw = sky2->hw;
1826 struct sky2_tx_le *le = NULL;
1827 struct tx_ring_info *re;
1828 unsigned i, len;
1829 dma_addr_t mapping;
1830 u32 upper;
1831 u16 slot;
1832 u16 mss;
1833 u8 ctrl;
1834
1835 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1836 return NETDEV_TX_BUSY;
1837
1838 len = skb_headlen(skb);
1839 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1840
1841 if (pci_dma_mapping_error(hw->pdev, mapping))
1842 goto mapping_error;
1843
1844 slot = sky2->tx_prod;
1845 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1846 "tx queued, slot %u, len %d\n", slot, skb->len);
1847
1848 /* Send high bits if needed */
1849 upper = upper_32_bits(mapping);
1850 if (upper != sky2->tx_last_upper) {
1851 le = get_tx_le(sky2, &slot);
1852 le->addr = cpu_to_le32(upper);
1853 sky2->tx_last_upper = upper;
1854 le->opcode = OP_ADDR64 | HW_OWNER;
1855 }
1856
1857 /* Check for TCP Segmentation Offload */
1858 mss = skb_shinfo(skb)->gso_size;
1859 if (mss != 0) {
1860
1861 if (!(hw->flags & SKY2_HW_NEW_LE))
1862 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1863
1864 if (mss != sky2->tx_last_mss) {
1865 le = get_tx_le(sky2, &slot);
1866 le->addr = cpu_to_le32(mss);
1867
1868 if (hw->flags & SKY2_HW_NEW_LE)
1869 le->opcode = OP_MSS | HW_OWNER;
1870 else
1871 le->opcode = OP_LRGLEN | HW_OWNER;
1872 sky2->tx_last_mss = mss;
1873 }
1874 }
1875
1876 ctrl = 0;
1877
1878 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1879 if (vlan_tx_tag_present(skb)) {
1880 if (!le) {
1881 le = get_tx_le(sky2, &slot);
1882 le->addr = 0;
1883 le->opcode = OP_VLAN|HW_OWNER;
1884 } else
1885 le->opcode |= OP_VLAN;
1886 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1887 ctrl |= INS_VLAN;
1888 }
1889
1890 /* Handle TCP checksum offload */
1891 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1892 /* On Yukon EX (some versions) encoding change. */
1893 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1894 ctrl |= CALSUM; /* auto checksum */
1895 else {
1896 const unsigned offset = skb_transport_offset(skb);
1897 u32 tcpsum;
1898
1899 tcpsum = offset << 16; /* sum start */
1900 tcpsum |= offset + skb->csum_offset; /* sum write */
1901
1902 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1903 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1904 ctrl |= UDPTCP;
1905
1906 if (tcpsum != sky2->tx_tcpsum) {
1907 sky2->tx_tcpsum = tcpsum;
1908
1909 le = get_tx_le(sky2, &slot);
1910 le->addr = cpu_to_le32(tcpsum);
1911 le->length = 0; /* initial checksum value */
1912 le->ctrl = 1; /* one packet */
1913 le->opcode = OP_TCPLISW | HW_OWNER;
1914 }
1915 }
1916 }
1917
1918 re = sky2->tx_ring + slot;
1919 re->flags = TX_MAP_SINGLE;
1920 dma_unmap_addr_set(re, mapaddr, mapping);
1921 dma_unmap_len_set(re, maplen, len);
1922
1923 le = get_tx_le(sky2, &slot);
1924 le->addr = cpu_to_le32(lower_32_bits(mapping));
1925 le->length = cpu_to_le16(len);
1926 le->ctrl = ctrl;
1927 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1928
1929
1930 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1931 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1932
1933 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
1934 skb_frag_size(frag), DMA_TO_DEVICE);
1935
1936 if (dma_mapping_error(&hw->pdev->dev, mapping))
1937 goto mapping_unwind;
1938
1939 upper = upper_32_bits(mapping);
1940 if (upper != sky2->tx_last_upper) {
1941 le = get_tx_le(sky2, &slot);
1942 le->addr = cpu_to_le32(upper);
1943 sky2->tx_last_upper = upper;
1944 le->opcode = OP_ADDR64 | HW_OWNER;
1945 }
1946
1947 re = sky2->tx_ring + slot;
1948 re->flags = TX_MAP_PAGE;
1949 dma_unmap_addr_set(re, mapaddr, mapping);
1950 dma_unmap_len_set(re, maplen, skb_frag_size(frag));
1951
1952 le = get_tx_le(sky2, &slot);
1953 le->addr = cpu_to_le32(lower_32_bits(mapping));
1954 le->length = cpu_to_le16(skb_frag_size(frag));
1955 le->ctrl = ctrl;
1956 le->opcode = OP_BUFFER | HW_OWNER;
1957 }
1958
1959 re->skb = skb;
1960 le->ctrl |= EOP;
1961
1962 sky2->tx_prod = slot;
1963
1964 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1965 netif_stop_queue(dev);
1966
1967 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1968
1969 return NETDEV_TX_OK;
1970
1971 mapping_unwind:
1972 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1973 re = sky2->tx_ring + i;
1974
1975 sky2_tx_unmap(hw->pdev, re);
1976 }
1977
1978 mapping_error:
1979 if (net_ratelimit())
1980 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1981 dev_kfree_skb(skb);
1982 return NETDEV_TX_OK;
1983 }
1984
1985 /*
1986 * Free ring elements from starting at tx_cons until "done"
1987 *
1988 * NB:
1989 * 1. The hardware will tell us about partial completion of multi-part
1990 * buffers so make sure not to free skb to early.
1991 * 2. This may run in parallel start_xmit because the it only
1992 * looks at the tail of the queue of FIFO (tx_cons), not
1993 * the head (tx_prod)
1994 */
1995 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1996 {
1997 struct net_device *dev = sky2->netdev;
1998 unsigned idx;
1999
2000 BUG_ON(done >= sky2->tx_ring_size);
2001
2002 for (idx = sky2->tx_cons; idx != done;
2003 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
2004 struct tx_ring_info *re = sky2->tx_ring + idx;
2005 struct sk_buff *skb = re->skb;
2006
2007 sky2_tx_unmap(sky2->hw->pdev, re);
2008
2009 if (skb) {
2010 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
2011 "tx done %u\n", idx);
2012
2013 u64_stats_update_begin(&sky2->tx_stats.syncp);
2014 ++sky2->tx_stats.packets;
2015 sky2->tx_stats.bytes += skb->len;
2016 u64_stats_update_end(&sky2->tx_stats.syncp);
2017
2018 re->skb = NULL;
2019 dev_kfree_skb_any(skb);
2020
2021 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
2022 }
2023 }
2024
2025 sky2->tx_cons = idx;
2026 smp_mb();
2027 }
2028
2029 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
2030 {
2031 /* Disable Force Sync bit and Enable Alloc bit */
2032 sky2_write8(hw, SK_REG(port, TXA_CTRL),
2033 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2034
2035 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2036 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2037 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2038
2039 /* Reset the PCI FIFO of the async Tx queue */
2040 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
2041 BMU_RST_SET | BMU_FIFO_RST);
2042
2043 /* Reset the Tx prefetch units */
2044 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
2045 PREF_UNIT_RST_SET);
2046
2047 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2048 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2049
2050 sky2_read32(hw, B0_CTST);
2051 }
2052
2053 static void sky2_hw_down(struct sky2_port *sky2)
2054 {
2055 struct sky2_hw *hw = sky2->hw;
2056 unsigned port = sky2->port;
2057 u16 ctrl;
2058
2059 /* Force flow control off */
2060 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2061
2062 /* Stop transmitter */
2063 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
2064 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
2065
2066 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2067 RB_RST_SET | RB_DIS_OP_MD);
2068
2069 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2070 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
2071 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2072
2073 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2074
2075 /* Workaround shared GMAC reset */
2076 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
2077 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
2078 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2079
2080 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2081
2082 /* Force any delayed status interrupt and NAPI */
2083 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
2084 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
2085 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
2086 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
2087
2088 sky2_rx_stop(sky2);
2089
2090 spin_lock_bh(&sky2->phy_lock);
2091 sky2_phy_power_down(hw, port);
2092 spin_unlock_bh(&sky2->phy_lock);
2093
2094 sky2_tx_reset(hw, port);
2095
2096 /* Free any pending frames stuck in HW queue */
2097 sky2_tx_complete(sky2, sky2->tx_prod);
2098 }
2099
2100 /* Network shutdown */
2101 static int sky2_close(struct net_device *dev)
2102 {
2103 struct sky2_port *sky2 = netdev_priv(dev);
2104 struct sky2_hw *hw = sky2->hw;
2105
2106 /* Never really got started! */
2107 if (!sky2->tx_le)
2108 return 0;
2109
2110 netif_info(sky2, ifdown, dev, "disabling interface\n");
2111
2112 if (hw->ports == 1) {
2113 sky2_write32(hw, B0_IMSK, 0);
2114 sky2_read32(hw, B0_IMSK);
2115
2116 napi_disable(&hw->napi);
2117 free_irq(hw->pdev->irq, hw);
2118 } else {
2119 u32 imask;
2120
2121 /* Disable port IRQ */
2122 imask = sky2_read32(hw, B0_IMSK);
2123 imask &= ~portirq_msk[sky2->port];
2124 sky2_write32(hw, B0_IMSK, imask);
2125 sky2_read32(hw, B0_IMSK);
2126
2127 synchronize_irq(hw->pdev->irq);
2128 napi_synchronize(&hw->napi);
2129 }
2130
2131 sky2_hw_down(sky2);
2132
2133 sky2_free_buffers(sky2);
2134
2135 return 0;
2136 }
2137
2138 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2139 {
2140 if (hw->flags & SKY2_HW_FIBRE_PHY)
2141 return SPEED_1000;
2142
2143 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2144 if (aux & PHY_M_PS_SPEED_100)
2145 return SPEED_100;
2146 else
2147 return SPEED_10;
2148 }
2149
2150 switch (aux & PHY_M_PS_SPEED_MSK) {
2151 case PHY_M_PS_SPEED_1000:
2152 return SPEED_1000;
2153 case PHY_M_PS_SPEED_100:
2154 return SPEED_100;
2155 default:
2156 return SPEED_10;
2157 }
2158 }
2159
2160 static void sky2_link_up(struct sky2_port *sky2)
2161 {
2162 struct sky2_hw *hw = sky2->hw;
2163 unsigned port = sky2->port;
2164 static const char *fc_name[] = {
2165 [FC_NONE] = "none",
2166 [FC_TX] = "tx",
2167 [FC_RX] = "rx",
2168 [FC_BOTH] = "both",
2169 };
2170
2171 sky2_set_ipg(sky2);
2172
2173 sky2_enable_rx_tx(sky2);
2174
2175 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2176
2177 netif_carrier_on(sky2->netdev);
2178
2179 mod_timer(&hw->watchdog_timer, jiffies + 1);
2180
2181 /* Turn on link LED */
2182 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2183 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2184
2185 netif_info(sky2, link, sky2->netdev,
2186 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2187 sky2->speed,
2188 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2189 fc_name[sky2->flow_status]);
2190 }
2191
2192 static void sky2_link_down(struct sky2_port *sky2)
2193 {
2194 struct sky2_hw *hw = sky2->hw;
2195 unsigned port = sky2->port;
2196 u16 reg;
2197
2198 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2199
2200 reg = gma_read16(hw, port, GM_GP_CTRL);
2201 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2202 gma_write16(hw, port, GM_GP_CTRL, reg);
2203
2204 netif_carrier_off(sky2->netdev);
2205
2206 /* Turn off link LED */
2207 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2208
2209 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2210
2211 sky2_phy_init(hw, port);
2212 }
2213
2214 static enum flow_control sky2_flow(int rx, int tx)
2215 {
2216 if (rx)
2217 return tx ? FC_BOTH : FC_RX;
2218 else
2219 return tx ? FC_TX : FC_NONE;
2220 }
2221
2222 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2223 {
2224 struct sky2_hw *hw = sky2->hw;
2225 unsigned port = sky2->port;
2226 u16 advert, lpa;
2227
2228 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2229 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2230 if (lpa & PHY_M_AN_RF) {
2231 netdev_err(sky2->netdev, "remote fault\n");
2232 return -1;
2233 }
2234
2235 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2236 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
2237 return -1;
2238 }
2239
2240 sky2->speed = sky2_phy_speed(hw, aux);
2241 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2242
2243 /* Since the pause result bits seem to in different positions on
2244 * different chips. look at registers.
2245 */
2246 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2247 /* Shift for bits in fiber PHY */
2248 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2249 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2250
2251 if (advert & ADVERTISE_1000XPAUSE)
2252 advert |= ADVERTISE_PAUSE_CAP;
2253 if (advert & ADVERTISE_1000XPSE_ASYM)
2254 advert |= ADVERTISE_PAUSE_ASYM;
2255 if (lpa & LPA_1000XPAUSE)
2256 lpa |= LPA_PAUSE_CAP;
2257 if (lpa & LPA_1000XPAUSE_ASYM)
2258 lpa |= LPA_PAUSE_ASYM;
2259 }
2260
2261 sky2->flow_status = FC_NONE;
2262 if (advert & ADVERTISE_PAUSE_CAP) {
2263 if (lpa & LPA_PAUSE_CAP)
2264 sky2->flow_status = FC_BOTH;
2265 else if (advert & ADVERTISE_PAUSE_ASYM)
2266 sky2->flow_status = FC_RX;
2267 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2268 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2269 sky2->flow_status = FC_TX;
2270 }
2271
2272 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2273 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2274 sky2->flow_status = FC_NONE;
2275
2276 if (sky2->flow_status & FC_TX)
2277 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2278 else
2279 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2280
2281 return 0;
2282 }
2283
2284 /* Interrupt from PHY */
2285 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2286 {
2287 struct net_device *dev = hw->dev[port];
2288 struct sky2_port *sky2 = netdev_priv(dev);
2289 u16 istatus, phystat;
2290
2291 if (!netif_running(dev))
2292 return;
2293
2294 spin_lock(&sky2->phy_lock);
2295 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2296 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2297
2298 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2299 istatus, phystat);
2300
2301 if (istatus & PHY_M_IS_AN_COMPL) {
2302 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2303 !netif_carrier_ok(dev))
2304 sky2_link_up(sky2);
2305 goto out;
2306 }
2307
2308 if (istatus & PHY_M_IS_LSP_CHANGE)
2309 sky2->speed = sky2_phy_speed(hw, phystat);
2310
2311 if (istatus & PHY_M_IS_DUP_CHANGE)
2312 sky2->duplex =
2313 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2314
2315 if (istatus & PHY_M_IS_LST_CHANGE) {
2316 if (phystat & PHY_M_PS_LINK_UP)
2317 sky2_link_up(sky2);
2318 else
2319 sky2_link_down(sky2);
2320 }
2321 out:
2322 spin_unlock(&sky2->phy_lock);
2323 }
2324
2325 /* Special quick link interrupt (Yukon-2 Optima only) */
2326 static void sky2_qlink_intr(struct sky2_hw *hw)
2327 {
2328 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2329 u32 imask;
2330 u16 phy;
2331
2332 /* disable irq */
2333 imask = sky2_read32(hw, B0_IMSK);
2334 imask &= ~Y2_IS_PHY_QLNK;
2335 sky2_write32(hw, B0_IMSK, imask);
2336
2337 /* reset PHY Link Detect */
2338 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2339 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2340 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2341 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2342
2343 sky2_link_up(sky2);
2344 }
2345
2346 /* Transmit timeout is only called if we are running, carrier is up
2347 * and tx queue is full (stopped).
2348 */
2349 static void sky2_tx_timeout(struct net_device *dev)
2350 {
2351 struct sky2_port *sky2 = netdev_priv(dev);
2352 struct sky2_hw *hw = sky2->hw;
2353
2354 netif_err(sky2, timer, dev, "tx timeout\n");
2355
2356 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2357 sky2->tx_cons, sky2->tx_prod,
2358 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2359 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2360
2361 /* can't restart safely under softirq */
2362 schedule_work(&hw->restart_work);
2363 }
2364
2365 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2366 {
2367 struct sky2_port *sky2 = netdev_priv(dev);
2368 struct sky2_hw *hw = sky2->hw;
2369 unsigned port = sky2->port;
2370 int err;
2371 u16 ctl, mode;
2372 u32 imask;
2373
2374 /* MTU size outside the spec */
2375 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2376 return -EINVAL;
2377
2378 /* MTU > 1500 on yukon FE and FE+ not allowed */
2379 if (new_mtu > ETH_DATA_LEN &&
2380 (hw->chip_id == CHIP_ID_YUKON_FE ||
2381 hw->chip_id == CHIP_ID_YUKON_FE_P))
2382 return -EINVAL;
2383
2384 if (!netif_running(dev)) {
2385 dev->mtu = new_mtu;
2386 netdev_update_features(dev);
2387 return 0;
2388 }
2389
2390 imask = sky2_read32(hw, B0_IMSK);
2391 sky2_write32(hw, B0_IMSK, 0);
2392
2393 dev->trans_start = jiffies; /* prevent tx timeout */
2394 napi_disable(&hw->napi);
2395 netif_tx_disable(dev);
2396
2397 synchronize_irq(hw->pdev->irq);
2398
2399 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2400 sky2_set_tx_stfwd(hw, port);
2401
2402 ctl = gma_read16(hw, port, GM_GP_CTRL);
2403 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2404 sky2_rx_stop(sky2);
2405 sky2_rx_clean(sky2);
2406
2407 dev->mtu = new_mtu;
2408 netdev_update_features(dev);
2409
2410 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA;
2411 if (sky2->speed > SPEED_100)
2412 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
2413 else
2414 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
2415
2416 if (dev->mtu > ETH_DATA_LEN)
2417 mode |= GM_SMOD_JUMBO_ENA;
2418
2419 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2420
2421 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2422
2423 err = sky2_alloc_rx_skbs(sky2);
2424 if (!err)
2425 sky2_rx_start(sky2);
2426 else
2427 sky2_rx_clean(sky2);
2428 sky2_write32(hw, B0_IMSK, imask);
2429
2430 sky2_read32(hw, B0_Y2_SP_LISR);
2431 napi_enable(&hw->napi);
2432
2433 if (err)
2434 dev_close(dev);
2435 else {
2436 gma_write16(hw, port, GM_GP_CTRL, ctl);
2437
2438 netif_wake_queue(dev);
2439 }
2440
2441 return err;
2442 }
2443
2444 /* For small just reuse existing skb for next receive */
2445 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2446 const struct rx_ring_info *re,
2447 unsigned length)
2448 {
2449 struct sk_buff *skb;
2450
2451 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2452 if (likely(skb)) {
2453 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2454 length, PCI_DMA_FROMDEVICE);
2455 skb_copy_from_linear_data(re->skb, skb->data, length);
2456 skb->ip_summed = re->skb->ip_summed;
2457 skb->csum = re->skb->csum;
2458 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2459 length, PCI_DMA_FROMDEVICE);
2460 re->skb->ip_summed = CHECKSUM_NONE;
2461 skb_put(skb, length);
2462 }
2463 return skb;
2464 }
2465
2466 /* Adjust length of skb with fragments to match received data */
2467 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2468 unsigned int length)
2469 {
2470 int i, num_frags;
2471 unsigned int size;
2472
2473 /* put header into skb */
2474 size = min(length, hdr_space);
2475 skb->tail += size;
2476 skb->len += size;
2477 length -= size;
2478
2479 num_frags = skb_shinfo(skb)->nr_frags;
2480 for (i = 0; i < num_frags; i++) {
2481 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2482
2483 if (length == 0) {
2484 /* don't need this page */
2485 __skb_frag_unref(frag);
2486 --skb_shinfo(skb)->nr_frags;
2487 } else {
2488 size = min(length, (unsigned) PAGE_SIZE);
2489
2490 skb_frag_size_set(frag, size);
2491 skb->data_len += size;
2492 skb->truesize += PAGE_SIZE;
2493 skb->len += size;
2494 length -= size;
2495 }
2496 }
2497 }
2498
2499 /* Normal packet - take skb from ring element and put in a new one */
2500 static struct sk_buff *receive_new(struct sky2_port *sky2,
2501 struct rx_ring_info *re,
2502 unsigned int length)
2503 {
2504 struct sk_buff *skb;
2505 struct rx_ring_info nre;
2506 unsigned hdr_space = sky2->rx_data_size;
2507
2508 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC);
2509 if (unlikely(!nre.skb))
2510 goto nobuf;
2511
2512 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2513 goto nomap;
2514
2515 skb = re->skb;
2516 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2517 prefetch(skb->data);
2518 *re = nre;
2519
2520 if (skb_shinfo(skb)->nr_frags)
2521 skb_put_frags(skb, hdr_space, length);
2522 else
2523 skb_put(skb, length);
2524 return skb;
2525
2526 nomap:
2527 dev_kfree_skb(nre.skb);
2528 nobuf:
2529 return NULL;
2530 }
2531
2532 /*
2533 * Receive one packet.
2534 * For larger packets, get new buffer.
2535 */
2536 static struct sk_buff *sky2_receive(struct net_device *dev,
2537 u16 length, u32 status)
2538 {
2539 struct sky2_port *sky2 = netdev_priv(dev);
2540 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2541 struct sk_buff *skb = NULL;
2542 u16 count = (status & GMR_FS_LEN) >> 16;
2543
2544 if (status & GMR_FS_VLAN)
2545 count -= VLAN_HLEN; /* Account for vlan tag */
2546
2547 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2548 "rx slot %u status 0x%x len %d\n",
2549 sky2->rx_next, status, length);
2550
2551 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2552 prefetch(sky2->rx_ring + sky2->rx_next);
2553
2554 /* This chip has hardware problems that generates bogus status.
2555 * So do only marginal checking and expect higher level protocols
2556 * to handle crap frames.
2557 */
2558 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2559 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2560 length != count)
2561 goto okay;
2562
2563 if (status & GMR_FS_ANY_ERR)
2564 goto error;
2565
2566 if (!(status & GMR_FS_RX_OK))
2567 goto resubmit;
2568
2569 /* if length reported by DMA does not match PHY, packet was truncated */
2570 if (length != count)
2571 goto error;
2572
2573 okay:
2574 if (length < copybreak)
2575 skb = receive_copy(sky2, re, length);
2576 else
2577 skb = receive_new(sky2, re, length);
2578
2579 dev->stats.rx_dropped += (skb == NULL);
2580
2581 resubmit:
2582 sky2_rx_submit(sky2, re);
2583
2584 return skb;
2585
2586 error:
2587 ++dev->stats.rx_errors;
2588
2589 if (net_ratelimit())
2590 netif_info(sky2, rx_err, dev,
2591 "rx error, status 0x%x length %d\n", status, length);
2592
2593 goto resubmit;
2594 }
2595
2596 /* Transmit complete */
2597 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2598 {
2599 struct sky2_port *sky2 = netdev_priv(dev);
2600
2601 if (netif_running(dev)) {
2602 sky2_tx_complete(sky2, last);
2603
2604 /* Wake unless it's detached, and called e.g. from sky2_close() */
2605 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2606 netif_wake_queue(dev);
2607 }
2608 }
2609
2610 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2611 u32 status, struct sk_buff *skb)
2612 {
2613 if (status & GMR_FS_VLAN)
2614 __vlan_hwaccel_put_tag(skb, be16_to_cpu(sky2->rx_tag));
2615
2616 if (skb->ip_summed == CHECKSUM_NONE)
2617 netif_receive_skb(skb);
2618 else
2619 napi_gro_receive(&sky2->hw->napi, skb);
2620 }
2621
2622 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2623 unsigned packets, unsigned bytes)
2624 {
2625 struct net_device *dev = hw->dev[port];
2626 struct sky2_port *sky2 = netdev_priv(dev);
2627
2628 if (packets == 0)
2629 return;
2630
2631 u64_stats_update_begin(&sky2->rx_stats.syncp);
2632 sky2->rx_stats.packets += packets;
2633 sky2->rx_stats.bytes += bytes;
2634 u64_stats_update_end(&sky2->rx_stats.syncp);
2635
2636 dev->last_rx = jiffies;
2637 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2638 }
2639
2640 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2641 {
2642 /* If this happens then driver assuming wrong format for chip type */
2643 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2644
2645 /* Both checksum counters are programmed to start at
2646 * the same offset, so unless there is a problem they
2647 * should match. This failure is an early indication that
2648 * hardware receive checksumming won't work.
2649 */
2650 if (likely((u16)(status >> 16) == (u16)status)) {
2651 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2652 skb->ip_summed = CHECKSUM_COMPLETE;
2653 skb->csum = le16_to_cpu(status);
2654 } else {
2655 dev_notice(&sky2->hw->pdev->dev,
2656 "%s: receive checksum problem (status = %#x)\n",
2657 sky2->netdev->name, status);
2658
2659 /* Disable checksum offload
2660 * It will be reenabled on next ndo_set_features, but if it's
2661 * really broken, will get disabled again
2662 */
2663 sky2->netdev->features &= ~NETIF_F_RXCSUM;
2664 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2665 BMU_DIS_RX_CHKSUM);
2666 }
2667 }
2668
2669 static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2670 {
2671 struct sk_buff *skb;
2672
2673 skb = sky2->rx_ring[sky2->rx_next].skb;
2674 skb->rxhash = le32_to_cpu(status);
2675 }
2676
2677 /* Process status response ring */
2678 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2679 {
2680 int work_done = 0;
2681 unsigned int total_bytes[2] = { 0 };
2682 unsigned int total_packets[2] = { 0 };
2683
2684 rmb();
2685 do {
2686 struct sky2_port *sky2;
2687 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2688 unsigned port;
2689 struct net_device *dev;
2690 struct sk_buff *skb;
2691 u32 status;
2692 u16 length;
2693 u8 opcode = le->opcode;
2694
2695 if (!(opcode & HW_OWNER))
2696 break;
2697
2698 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
2699
2700 port = le->css & CSS_LINK_BIT;
2701 dev = hw->dev[port];
2702 sky2 = netdev_priv(dev);
2703 length = le16_to_cpu(le->length);
2704 status = le32_to_cpu(le->status);
2705
2706 le->opcode = 0;
2707 switch (opcode & ~HW_OWNER) {
2708 case OP_RXSTAT:
2709 total_packets[port]++;
2710 total_bytes[port] += length;
2711
2712 skb = sky2_receive(dev, length, status);
2713 if (!skb)
2714 break;
2715
2716 /* This chip reports checksum status differently */
2717 if (hw->flags & SKY2_HW_NEW_LE) {
2718 if ((dev->features & NETIF_F_RXCSUM) &&
2719 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2720 (le->css & CSS_TCPUDPCSOK))
2721 skb->ip_summed = CHECKSUM_UNNECESSARY;
2722 else
2723 skb->ip_summed = CHECKSUM_NONE;
2724 }
2725
2726 skb->protocol = eth_type_trans(skb, dev);
2727
2728 sky2_skb_rx(sky2, status, skb);
2729
2730 /* Stop after net poll weight */
2731 if (++work_done >= to_do)
2732 goto exit_loop;
2733 break;
2734
2735 case OP_RXVLAN:
2736 sky2->rx_tag = length;
2737 break;
2738
2739 case OP_RXCHKSVLAN:
2740 sky2->rx_tag = length;
2741 /* fall through */
2742 case OP_RXCHKS:
2743 if (likely(dev->features & NETIF_F_RXCSUM))
2744 sky2_rx_checksum(sky2, status);
2745 break;
2746
2747 case OP_RSS_HASH:
2748 sky2_rx_hash(sky2, status);
2749 break;
2750
2751 case OP_TXINDEXLE:
2752 /* TX index reports status for both ports */
2753 sky2_tx_done(hw->dev[0], status & 0xfff);
2754 if (hw->dev[1])
2755 sky2_tx_done(hw->dev[1],
2756 ((status >> 24) & 0xff)
2757 | (u16)(length & 0xf) << 8);
2758 break;
2759
2760 default:
2761 if (net_ratelimit())
2762 pr_warning("unknown status opcode 0x%x\n", opcode);
2763 }
2764 } while (hw->st_idx != idx);
2765
2766 /* Fully processed status ring so clear irq */
2767 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2768
2769 exit_loop:
2770 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2771 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2772
2773 return work_done;
2774 }
2775
2776 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2777 {
2778 struct net_device *dev = hw->dev[port];
2779
2780 if (net_ratelimit())
2781 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
2782
2783 if (status & Y2_IS_PAR_RD1) {
2784 if (net_ratelimit())
2785 netdev_err(dev, "ram data read parity error\n");
2786 /* Clear IRQ */
2787 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2788 }
2789
2790 if (status & Y2_IS_PAR_WR1) {
2791 if (net_ratelimit())
2792 netdev_err(dev, "ram data write parity error\n");
2793
2794 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2795 }
2796
2797 if (status & Y2_IS_PAR_MAC1) {
2798 if (net_ratelimit())
2799 netdev_err(dev, "MAC parity error\n");
2800 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2801 }
2802
2803 if (status & Y2_IS_PAR_RX1) {
2804 if (net_ratelimit())
2805 netdev_err(dev, "RX parity error\n");
2806 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2807 }
2808
2809 if (status & Y2_IS_TCP_TXA1) {
2810 if (net_ratelimit())
2811 netdev_err(dev, "TCP segmentation error\n");
2812 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2813 }
2814 }
2815
2816 static void sky2_hw_intr(struct sky2_hw *hw)
2817 {
2818 struct pci_dev *pdev = hw->pdev;
2819 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2820 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2821
2822 status &= hwmsk;
2823
2824 if (status & Y2_IS_TIST_OV)
2825 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2826
2827 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2828 u16 pci_err;
2829
2830 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2831 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2832 if (net_ratelimit())
2833 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2834 pci_err);
2835
2836 sky2_pci_write16(hw, PCI_STATUS,
2837 pci_err | PCI_STATUS_ERROR_BITS);
2838 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2839 }
2840
2841 if (status & Y2_IS_PCI_EXP) {
2842 /* PCI-Express uncorrectable Error occurred */
2843 u32 err;
2844
2845 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2846 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2847 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2848 0xfffffffful);
2849 if (net_ratelimit())
2850 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2851
2852 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2853 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2854 }
2855
2856 if (status & Y2_HWE_L1_MASK)
2857 sky2_hw_error(hw, 0, status);
2858 status >>= 8;
2859 if (status & Y2_HWE_L1_MASK)
2860 sky2_hw_error(hw, 1, status);
2861 }
2862
2863 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2864 {
2865 struct net_device *dev = hw->dev[port];
2866 struct sky2_port *sky2 = netdev_priv(dev);
2867 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2868
2869 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
2870
2871 if (status & GM_IS_RX_CO_OV)
2872 gma_read16(hw, port, GM_RX_IRQ_SRC);
2873
2874 if (status & GM_IS_TX_CO_OV)
2875 gma_read16(hw, port, GM_TX_IRQ_SRC);
2876
2877 if (status & GM_IS_RX_FF_OR) {
2878 ++dev->stats.rx_fifo_errors;
2879 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2880 }
2881
2882 if (status & GM_IS_TX_FF_UR) {
2883 ++dev->stats.tx_fifo_errors;
2884 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2885 }
2886 }
2887
2888 /* This should never happen it is a bug. */
2889 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2890 {
2891 struct net_device *dev = hw->dev[port];
2892 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2893
2894 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
2895 dev->name, (unsigned) q, (unsigned) idx,
2896 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2897
2898 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2899 }
2900
2901 static int sky2_rx_hung(struct net_device *dev)
2902 {
2903 struct sky2_port *sky2 = netdev_priv(dev);
2904 struct sky2_hw *hw = sky2->hw;
2905 unsigned port = sky2->port;
2906 unsigned rxq = rxqaddr[port];
2907 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2908 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2909 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2910 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2911
2912 /* If idle and MAC or PCI is stuck */
2913 if (sky2->check.last == dev->last_rx &&
2914 ((mac_rp == sky2->check.mac_rp &&
2915 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2916 /* Check if the PCI RX hang */
2917 (fifo_rp == sky2->check.fifo_rp &&
2918 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2919 netdev_printk(KERN_DEBUG, dev,
2920 "hung mac %d:%d fifo %d (%d:%d)\n",
2921 mac_lev, mac_rp, fifo_lev,
2922 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2923 return 1;
2924 } else {
2925 sky2->check.last = dev->last_rx;
2926 sky2->check.mac_rp = mac_rp;
2927 sky2->check.mac_lev = mac_lev;
2928 sky2->check.fifo_rp = fifo_rp;
2929 sky2->check.fifo_lev = fifo_lev;
2930 return 0;
2931 }
2932 }
2933
2934 static void sky2_watchdog(unsigned long arg)
2935 {
2936 struct sky2_hw *hw = (struct sky2_hw *) arg;
2937
2938 /* Check for lost IRQ once a second */
2939 if (sky2_read32(hw, B0_ISRC)) {
2940 napi_schedule(&hw->napi);
2941 } else {
2942 int i, active = 0;
2943
2944 for (i = 0; i < hw->ports; i++) {
2945 struct net_device *dev = hw->dev[i];
2946 if (!netif_running(dev))
2947 continue;
2948 ++active;
2949
2950 /* For chips with Rx FIFO, check if stuck */
2951 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2952 sky2_rx_hung(dev)) {
2953 netdev_info(dev, "receiver hang detected\n");
2954 schedule_work(&hw->restart_work);
2955 return;
2956 }
2957 }
2958
2959 if (active == 0)
2960 return;
2961 }
2962
2963 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2964 }
2965
2966 /* Hardware/software error handling */
2967 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2968 {
2969 if (net_ratelimit())
2970 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2971
2972 if (status & Y2_IS_HW_ERR)
2973 sky2_hw_intr(hw);
2974
2975 if (status & Y2_IS_IRQ_MAC1)
2976 sky2_mac_intr(hw, 0);
2977
2978 if (status & Y2_IS_IRQ_MAC2)
2979 sky2_mac_intr(hw, 1);
2980
2981 if (status & Y2_IS_CHK_RX1)
2982 sky2_le_error(hw, 0, Q_R1);
2983
2984 if (status & Y2_IS_CHK_RX2)
2985 sky2_le_error(hw, 1, Q_R2);
2986
2987 if (status & Y2_IS_CHK_TXA1)
2988 sky2_le_error(hw, 0, Q_XA1);
2989
2990 if (status & Y2_IS_CHK_TXA2)
2991 sky2_le_error(hw, 1, Q_XA2);
2992 }
2993
2994 static int sky2_poll(struct napi_struct *napi, int work_limit)
2995 {
2996 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2997 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2998 int work_done = 0;
2999 u16 idx;
3000
3001 if (unlikely(status & Y2_IS_ERROR))
3002 sky2_err_intr(hw, status);
3003
3004 if (status & Y2_IS_IRQ_PHY1)
3005 sky2_phy_intr(hw, 0);
3006
3007 if (status & Y2_IS_IRQ_PHY2)
3008 sky2_phy_intr(hw, 1);
3009
3010 if (status & Y2_IS_PHY_QLNK)
3011 sky2_qlink_intr(hw);
3012
3013 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
3014 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
3015
3016 if (work_done >= work_limit)
3017 goto done;
3018 }
3019
3020 napi_complete(napi);
3021 sky2_read32(hw, B0_Y2_SP_LISR);
3022 done:
3023
3024 return work_done;
3025 }
3026
3027 static irqreturn_t sky2_intr(int irq, void *dev_id)
3028 {
3029 struct sky2_hw *hw = dev_id;
3030 u32 status;
3031
3032 /* Reading this mask interrupts as side effect */
3033 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3034 if (status == 0 || status == ~0)
3035 return IRQ_NONE;
3036
3037 prefetch(&hw->st_le[hw->st_idx]);
3038
3039 napi_schedule(&hw->napi);
3040
3041 return IRQ_HANDLED;
3042 }
3043
3044 #ifdef CONFIG_NET_POLL_CONTROLLER
3045 static void sky2_netpoll(struct net_device *dev)
3046 {
3047 struct sky2_port *sky2 = netdev_priv(dev);
3048
3049 napi_schedule(&sky2->hw->napi);
3050 }
3051 #endif
3052
3053 /* Chip internal frequency for clock calculations */
3054 static u32 sky2_mhz(const struct sky2_hw *hw)
3055 {
3056 switch (hw->chip_id) {
3057 case CHIP_ID_YUKON_EC:
3058 case CHIP_ID_YUKON_EC_U:
3059 case CHIP_ID_YUKON_EX:
3060 case CHIP_ID_YUKON_SUPR:
3061 case CHIP_ID_YUKON_UL_2:
3062 case CHIP_ID_YUKON_OPT:
3063 case CHIP_ID_YUKON_PRM:
3064 case CHIP_ID_YUKON_OP_2:
3065 return 125;
3066
3067 case CHIP_ID_YUKON_FE:
3068 return 100;
3069
3070 case CHIP_ID_YUKON_FE_P:
3071 return 50;
3072
3073 case CHIP_ID_YUKON_XL:
3074 return 156;
3075
3076 default:
3077 BUG();
3078 }
3079 }
3080
3081 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
3082 {
3083 return sky2_mhz(hw) * us;
3084 }
3085
3086 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
3087 {
3088 return clk / sky2_mhz(hw);
3089 }
3090
3091
3092 static int __devinit sky2_init(struct sky2_hw *hw)
3093 {
3094 u8 t8;
3095
3096 /* Enable all clocks and check for bad PCI access */
3097 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3098
3099 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3100
3101 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
3102 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3103
3104 switch (hw->chip_id) {
3105 case CHIP_ID_YUKON_XL:
3106 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
3107 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3108 hw->flags |= SKY2_HW_RSS_BROKEN;
3109 break;
3110
3111 case CHIP_ID_YUKON_EC_U:
3112 hw->flags = SKY2_HW_GIGABIT
3113 | SKY2_HW_NEWER_PHY
3114 | SKY2_HW_ADV_POWER_CTL;
3115 break;
3116
3117 case CHIP_ID_YUKON_EX:
3118 hw->flags = SKY2_HW_GIGABIT
3119 | SKY2_HW_NEWER_PHY
3120 | SKY2_HW_NEW_LE
3121 | SKY2_HW_ADV_POWER_CTL
3122 | SKY2_HW_RSS_CHKSUM;
3123
3124 /* New transmit checksum */
3125 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3126 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3127 break;
3128
3129 case CHIP_ID_YUKON_EC:
3130 /* This rev is really old, and requires untested workarounds */
3131 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3132 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3133 return -EOPNOTSUPP;
3134 }
3135 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
3136 break;
3137
3138 case CHIP_ID_YUKON_FE:
3139 hw->flags = SKY2_HW_RSS_BROKEN;
3140 break;
3141
3142 case CHIP_ID_YUKON_FE_P:
3143 hw->flags = SKY2_HW_NEWER_PHY
3144 | SKY2_HW_NEW_LE
3145 | SKY2_HW_AUTO_TX_SUM
3146 | SKY2_HW_ADV_POWER_CTL;
3147
3148 /* The workaround for status conflicts VLAN tag detection. */
3149 if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
3150 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM;
3151 break;
3152
3153 case CHIP_ID_YUKON_SUPR:
3154 hw->flags = SKY2_HW_GIGABIT
3155 | SKY2_HW_NEWER_PHY
3156 | SKY2_HW_NEW_LE
3157 | SKY2_HW_AUTO_TX_SUM
3158 | SKY2_HW_ADV_POWER_CTL;
3159
3160 if (hw->chip_rev == CHIP_REV_YU_SU_A0)
3161 hw->flags |= SKY2_HW_RSS_CHKSUM;
3162 break;
3163
3164 case CHIP_ID_YUKON_UL_2:
3165 hw->flags = SKY2_HW_GIGABIT
3166 | SKY2_HW_ADV_POWER_CTL;
3167 break;
3168
3169 case CHIP_ID_YUKON_OPT:
3170 case CHIP_ID_YUKON_PRM:
3171 case CHIP_ID_YUKON_OP_2:
3172 hw->flags = SKY2_HW_GIGABIT
3173 | SKY2_HW_NEW_LE
3174 | SKY2_HW_ADV_POWER_CTL;
3175 break;
3176
3177 default:
3178 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3179 hw->chip_id);
3180 return -EOPNOTSUPP;
3181 }
3182
3183 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3184 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3185 hw->flags |= SKY2_HW_FIBRE_PHY;
3186
3187 hw->ports = 1;
3188 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3189 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3190 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3191 ++hw->ports;
3192 }
3193
3194 if (sky2_read8(hw, B2_E_0))
3195 hw->flags |= SKY2_HW_RAM_BUFFER;
3196
3197 return 0;
3198 }
3199
3200 static void sky2_reset(struct sky2_hw *hw)
3201 {
3202 struct pci_dev *pdev = hw->pdev;
3203 u16 status;
3204 int i;
3205 u32 hwe_mask = Y2_HWE_ALL_MASK;
3206
3207 /* disable ASF */
3208 if (hw->chip_id == CHIP_ID_YUKON_EX
3209 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3210 sky2_write32(hw, CPU_WDOG, 0);
3211 status = sky2_read16(hw, HCU_CCSR);
3212 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3213 HCU_CCSR_UC_STATE_MSK);
3214 /*
3215 * CPU clock divider shouldn't be used because
3216 * - ASF firmware may malfunction
3217 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3218 */
3219 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3220 sky2_write16(hw, HCU_CCSR, status);
3221 sky2_write32(hw, CPU_WDOG, 0);
3222 } else
3223 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3224 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3225
3226 /* do a SW reset */
3227 sky2_write8(hw, B0_CTST, CS_RST_SET);
3228 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3229
3230 /* allow writes to PCI config */
3231 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3232
3233 /* clear PCI errors, if any */
3234 status = sky2_pci_read16(hw, PCI_STATUS);
3235 status |= PCI_STATUS_ERROR_BITS;
3236 sky2_pci_write16(hw, PCI_STATUS, status);
3237
3238 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3239
3240 if (pci_is_pcie(pdev)) {
3241 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3242 0xfffffffful);
3243
3244 /* If error bit is stuck on ignore it */
3245 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3246 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3247 else
3248 hwe_mask |= Y2_IS_PCI_EXP;
3249 }
3250
3251 sky2_power_on(hw);
3252 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3253
3254 for (i = 0; i < hw->ports; i++) {
3255 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3256 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3257
3258 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3259 hw->chip_id == CHIP_ID_YUKON_SUPR)
3260 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3261 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3262 | GMC_BYP_RETR_ON);
3263
3264 }
3265
3266 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3267 /* enable MACSec clock gating */
3268 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3269 }
3270
3271 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
3272 hw->chip_id == CHIP_ID_YUKON_PRM ||
3273 hw->chip_id == CHIP_ID_YUKON_OP_2) {
3274 u16 reg;
3275
3276 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
3277 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3278 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3279
3280 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3281 reg = 10;
3282
3283 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3284 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3285 } else {
3286 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3287 reg = 3;
3288 }
3289
3290 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3291 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT;
3292
3293 /* reset PHY Link Detect */
3294 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3295 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3296
3297 /* check if PSMv2 was running before */
3298 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3299 if (reg & PCI_EXP_LNKCTL_ASPMC)
3300 /* restore the PCIe Link Control register */
3301 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3302 reg);
3303
3304 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3305
3306 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3307 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3308 }
3309
3310 /* Clear I2C IRQ noise */
3311 sky2_write32(hw, B2_I2C_IRQ, 1);
3312
3313 /* turn off hardware timer (unused) */
3314 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3315 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3316
3317 /* Turn off descriptor polling */
3318 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3319
3320 /* Turn off receive timestamp */
3321 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3322 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3323
3324 /* enable the Tx Arbiters */
3325 for (i = 0; i < hw->ports; i++)
3326 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3327
3328 /* Initialize ram interface */
3329 for (i = 0; i < hw->ports; i++) {
3330 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3331
3332 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3333 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3334 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3335 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3336 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3337 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3338 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3339 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3340 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3341 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3342 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3343 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3344 }
3345
3346 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3347
3348 for (i = 0; i < hw->ports; i++)
3349 sky2_gmac_reset(hw, i);
3350
3351 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
3352 hw->st_idx = 0;
3353
3354 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3355 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3356
3357 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3358 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3359
3360 /* Set the list last index */
3361 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
3362
3363 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3364 sky2_write8(hw, STAT_FIFO_WM, 16);
3365
3366 /* set Status-FIFO ISR watermark */
3367 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3368 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3369 else
3370 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3371
3372 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3373 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3374 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3375
3376 /* enable status unit */
3377 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3378
3379 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3380 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3381 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3382 }
3383
3384 /* Take device down (offline).
3385 * Equivalent to doing dev_stop() but this does not
3386 * inform upper layers of the transition.
3387 */
3388 static void sky2_detach(struct net_device *dev)
3389 {
3390 if (netif_running(dev)) {
3391 netif_tx_lock(dev);
3392 netif_device_detach(dev); /* stop txq */
3393 netif_tx_unlock(dev);
3394 sky2_close(dev);
3395 }
3396 }
3397
3398 /* Bring device back after doing sky2_detach */
3399 static int sky2_reattach(struct net_device *dev)
3400 {
3401 int err = 0;
3402
3403 if (netif_running(dev)) {
3404 err = sky2_open(dev);
3405 if (err) {
3406 netdev_info(dev, "could not restart %d\n", err);
3407 dev_close(dev);
3408 } else {
3409 netif_device_attach(dev);
3410 sky2_set_multicast(dev);
3411 }
3412 }
3413
3414 return err;
3415 }
3416
3417 static void sky2_all_down(struct sky2_hw *hw)
3418 {
3419 int i;
3420
3421 sky2_read32(hw, B0_IMSK);
3422 sky2_write32(hw, B0_IMSK, 0);
3423
3424 if (hw->ports > 1 || netif_running(hw->dev[0]))
3425 synchronize_irq(hw->pdev->irq);
3426 napi_disable(&hw->napi);
3427
3428 for (i = 0; i < hw->ports; i++) {
3429 struct net_device *dev = hw->dev[i];
3430 struct sky2_port *sky2 = netdev_priv(dev);
3431
3432 if (!netif_running(dev))
3433 continue;
3434
3435 netif_carrier_off(dev);
3436 netif_tx_disable(dev);
3437 sky2_hw_down(sky2);
3438 }
3439 }
3440
3441 static void sky2_all_up(struct sky2_hw *hw)
3442 {
3443 u32 imask = 0;
3444 int i;
3445
3446 for (i = 0; i < hw->ports; i++) {
3447 struct net_device *dev = hw->dev[i];
3448 struct sky2_port *sky2 = netdev_priv(dev);
3449
3450 if (!netif_running(dev))
3451 continue;
3452
3453 sky2_hw_up(sky2);
3454 sky2_set_multicast(dev);
3455 imask |= portirq_msk[i];
3456 netif_wake_queue(dev);
3457 }
3458
3459 if (imask || hw->ports > 1) {
3460 imask |= Y2_IS_BASE;
3461 sky2_write32(hw, B0_IMSK, imask);
3462 sky2_read32(hw, B0_IMSK);
3463 sky2_read32(hw, B0_Y2_SP_LISR);
3464 napi_enable(&hw->napi);
3465 }
3466 }
3467
3468 static void sky2_restart(struct work_struct *work)
3469 {
3470 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3471
3472 rtnl_lock();
3473
3474 sky2_all_down(hw);
3475 sky2_reset(hw);
3476 sky2_all_up(hw);
3477
3478 rtnl_unlock();
3479 }
3480
3481 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3482 {
3483 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3484 }
3485
3486 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3487 {
3488 const struct sky2_port *sky2 = netdev_priv(dev);
3489
3490 wol->supported = sky2_wol_supported(sky2->hw);
3491 wol->wolopts = sky2->wol;
3492 }
3493
3494 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3495 {
3496 struct sky2_port *sky2 = netdev_priv(dev);
3497 struct sky2_hw *hw = sky2->hw;
3498 bool enable_wakeup = false;
3499 int i;
3500
3501 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3502 !device_can_wakeup(&hw->pdev->dev))
3503 return -EOPNOTSUPP;
3504
3505 sky2->wol = wol->wolopts;
3506
3507 for (i = 0; i < hw->ports; i++) {
3508 struct net_device *dev = hw->dev[i];
3509 struct sky2_port *sky2 = netdev_priv(dev);
3510
3511 if (sky2->wol)
3512 enable_wakeup = true;
3513 }
3514 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3515
3516 return 0;
3517 }
3518
3519 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3520 {
3521 if (sky2_is_copper(hw)) {
3522 u32 modes = SUPPORTED_10baseT_Half
3523 | SUPPORTED_10baseT_Full
3524 | SUPPORTED_100baseT_Half
3525 | SUPPORTED_100baseT_Full;
3526
3527 if (hw->flags & SKY2_HW_GIGABIT)
3528 modes |= SUPPORTED_1000baseT_Half
3529 | SUPPORTED_1000baseT_Full;
3530 return modes;
3531 } else
3532 return SUPPORTED_1000baseT_Half
3533 | SUPPORTED_1000baseT_Full;
3534 }
3535
3536 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3537 {
3538 struct sky2_port *sky2 = netdev_priv(dev);
3539 struct sky2_hw *hw = sky2->hw;
3540
3541 ecmd->transceiver = XCVR_INTERNAL;
3542 ecmd->supported = sky2_supported_modes(hw);
3543 ecmd->phy_address = PHY_ADDR_MARV;
3544 if (sky2_is_copper(hw)) {
3545 ecmd->port = PORT_TP;
3546 ethtool_cmd_speed_set(ecmd, sky2->speed);
3547 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP;
3548 } else {
3549 ethtool_cmd_speed_set(ecmd, SPEED_1000);
3550 ecmd->port = PORT_FIBRE;
3551 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE;
3552 }
3553
3554 ecmd->advertising = sky2->advertising;
3555 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3556 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3557 ecmd->duplex = sky2->duplex;
3558 return 0;
3559 }
3560
3561 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3562 {
3563 struct sky2_port *sky2 = netdev_priv(dev);
3564 const struct sky2_hw *hw = sky2->hw;
3565 u32 supported = sky2_supported_modes(hw);
3566
3567 if (ecmd->autoneg == AUTONEG_ENABLE) {
3568 if (ecmd->advertising & ~supported)
3569 return -EINVAL;
3570
3571 if (sky2_is_copper(hw))
3572 sky2->advertising = ecmd->advertising |
3573 ADVERTISED_TP |
3574 ADVERTISED_Autoneg;
3575 else
3576 sky2->advertising = ecmd->advertising |
3577 ADVERTISED_FIBRE |
3578 ADVERTISED_Autoneg;
3579
3580 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3581 sky2->duplex = -1;
3582 sky2->speed = -1;
3583 } else {
3584 u32 setting;
3585 u32 speed = ethtool_cmd_speed(ecmd);
3586
3587 switch (speed) {
3588 case SPEED_1000:
3589 if (ecmd->duplex == DUPLEX_FULL)
3590 setting = SUPPORTED_1000baseT_Full;
3591 else if (ecmd->duplex == DUPLEX_HALF)
3592 setting = SUPPORTED_1000baseT_Half;
3593 else
3594 return -EINVAL;
3595 break;
3596 case SPEED_100:
3597 if (ecmd->duplex == DUPLEX_FULL)
3598 setting = SUPPORTED_100baseT_Full;
3599 else if (ecmd->duplex == DUPLEX_HALF)
3600 setting = SUPPORTED_100baseT_Half;
3601 else
3602 return -EINVAL;
3603 break;
3604
3605 case SPEED_10:
3606 if (ecmd->duplex == DUPLEX_FULL)
3607 setting = SUPPORTED_10baseT_Full;
3608 else if (ecmd->duplex == DUPLEX_HALF)
3609 setting = SUPPORTED_10baseT_Half;
3610 else
3611 return -EINVAL;
3612 break;
3613 default:
3614 return -EINVAL;
3615 }
3616
3617 if ((setting & supported) == 0)
3618 return -EINVAL;
3619
3620 sky2->speed = speed;
3621 sky2->duplex = ecmd->duplex;
3622 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3623 }
3624
3625 if (netif_running(dev)) {
3626 sky2_phy_reinit(sky2);
3627 sky2_set_multicast(dev);
3628 }
3629
3630 return 0;
3631 }
3632
3633 static void sky2_get_drvinfo(struct net_device *dev,
3634 struct ethtool_drvinfo *info)
3635 {
3636 struct sky2_port *sky2 = netdev_priv(dev);
3637
3638 strcpy(info->driver, DRV_NAME);
3639 strcpy(info->version, DRV_VERSION);
3640 strcpy(info->fw_version, "N/A");
3641 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3642 }
3643
3644 static const struct sky2_stat {
3645 char name[ETH_GSTRING_LEN];
3646 u16 offset;
3647 } sky2_stats[] = {
3648 { "tx_bytes", GM_TXO_OK_HI },
3649 { "rx_bytes", GM_RXO_OK_HI },
3650 { "tx_broadcast", GM_TXF_BC_OK },
3651 { "rx_broadcast", GM_RXF_BC_OK },
3652 { "tx_multicast", GM_TXF_MC_OK },
3653 { "rx_multicast", GM_RXF_MC_OK },
3654 { "tx_unicast", GM_TXF_UC_OK },
3655 { "rx_unicast", GM_RXF_UC_OK },
3656 { "tx_mac_pause", GM_TXF_MPAUSE },
3657 { "rx_mac_pause", GM_RXF_MPAUSE },
3658 { "collisions", GM_TXF_COL },
3659 { "late_collision",GM_TXF_LAT_COL },
3660 { "aborted", GM_TXF_ABO_COL },
3661 { "single_collisions", GM_TXF_SNG_COL },
3662 { "multi_collisions", GM_TXF_MUL_COL },
3663
3664 { "rx_short", GM_RXF_SHT },
3665 { "rx_runt", GM_RXE_FRAG },
3666 { "rx_64_byte_packets", GM_RXF_64B },
3667 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3668 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3669 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3670 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3671 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3672 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3673 { "rx_too_long", GM_RXF_LNG_ERR },
3674 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3675 { "rx_jabber", GM_RXF_JAB_PKT },
3676 { "rx_fcs_error", GM_RXF_FCS_ERR },
3677
3678 { "tx_64_byte_packets", GM_TXF_64B },
3679 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3680 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3681 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3682 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3683 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3684 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3685 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3686 };
3687
3688 static u32 sky2_get_msglevel(struct net_device *netdev)
3689 {
3690 struct sky2_port *sky2 = netdev_priv(netdev);
3691 return sky2->msg_enable;
3692 }
3693
3694 static int sky2_nway_reset(struct net_device *dev)
3695 {
3696 struct sky2_port *sky2 = netdev_priv(dev);
3697
3698 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3699 return -EINVAL;
3700
3701 sky2_phy_reinit(sky2);
3702 sky2_set_multicast(dev);
3703
3704 return 0;
3705 }
3706
3707 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3708 {
3709 struct sky2_hw *hw = sky2->hw;
3710 unsigned port = sky2->port;
3711 int i;
3712
3713 data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3714 data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
3715
3716 for (i = 2; i < count; i++)
3717 data[i] = get_stats32(hw, port, sky2_stats[i].offset);
3718 }
3719
3720 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3721 {
3722 struct sky2_port *sky2 = netdev_priv(netdev);
3723 sky2->msg_enable = value;
3724 }
3725
3726 static int sky2_get_sset_count(struct net_device *dev, int sset)
3727 {
3728 switch (sset) {
3729 case ETH_SS_STATS:
3730 return ARRAY_SIZE(sky2_stats);
3731 default:
3732 return -EOPNOTSUPP;
3733 }
3734 }
3735
3736 static void sky2_get_ethtool_stats(struct net_device *dev,
3737 struct ethtool_stats *stats, u64 * data)
3738 {
3739 struct sky2_port *sky2 = netdev_priv(dev);
3740
3741 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3742 }
3743
3744 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3745 {
3746 int i;
3747
3748 switch (stringset) {
3749 case ETH_SS_STATS:
3750 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3751 memcpy(data + i * ETH_GSTRING_LEN,
3752 sky2_stats[i].name, ETH_GSTRING_LEN);
3753 break;
3754 }
3755 }
3756
3757 static int sky2_set_mac_address(struct net_device *dev, void *p)
3758 {
3759 struct sky2_port *sky2 = netdev_priv(dev);
3760 struct sky2_hw *hw = sky2->hw;
3761 unsigned port = sky2->port;
3762 const struct sockaddr *addr = p;
3763
3764 if (!is_valid_ether_addr(addr->sa_data))
3765 return -EADDRNOTAVAIL;
3766
3767 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3768 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3769 dev->dev_addr, ETH_ALEN);
3770 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3771 dev->dev_addr, ETH_ALEN);
3772
3773 /* virtual address for data */
3774 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3775
3776 /* physical address: used for pause frames */
3777 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3778
3779 return 0;
3780 }
3781
3782 static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
3783 {
3784 u32 bit;
3785
3786 bit = ether_crc(ETH_ALEN, addr) & 63;
3787 filter[bit >> 3] |= 1 << (bit & 7);
3788 }
3789
3790 static void sky2_set_multicast(struct net_device *dev)
3791 {
3792 struct sky2_port *sky2 = netdev_priv(dev);
3793 struct sky2_hw *hw = sky2->hw;
3794 unsigned port = sky2->port;
3795 struct netdev_hw_addr *ha;
3796 u16 reg;
3797 u8 filter[8];
3798 int rx_pause;
3799 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3800
3801 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3802 memset(filter, 0, sizeof(filter));
3803
3804 reg = gma_read16(hw, port, GM_RX_CTRL);
3805 reg |= GM_RXCR_UCF_ENA;
3806
3807 if (dev->flags & IFF_PROMISC) /* promiscuous */
3808 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3809 else if (dev->flags & IFF_ALLMULTI)
3810 memset(filter, 0xff, sizeof(filter));
3811 else if (netdev_mc_empty(dev) && !rx_pause)
3812 reg &= ~GM_RXCR_MCF_ENA;
3813 else {
3814 reg |= GM_RXCR_MCF_ENA;
3815
3816 if (rx_pause)
3817 sky2_add_filter(filter, pause_mc_addr);
3818
3819 netdev_for_each_mc_addr(ha, dev)
3820 sky2_add_filter(filter, ha->addr);
3821 }
3822
3823 gma_write16(hw, port, GM_MC_ADDR_H1,
3824 (u16) filter[0] | ((u16) filter[1] << 8));
3825 gma_write16(hw, port, GM_MC_ADDR_H2,
3826 (u16) filter[2] | ((u16) filter[3] << 8));
3827 gma_write16(hw, port, GM_MC_ADDR_H3,
3828 (u16) filter[4] | ((u16) filter[5] << 8));
3829 gma_write16(hw, port, GM_MC_ADDR_H4,
3830 (u16) filter[6] | ((u16) filter[7] << 8));
3831
3832 gma_write16(hw, port, GM_RX_CTRL, reg);
3833 }
3834
3835 static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev,
3836 struct rtnl_link_stats64 *stats)
3837 {
3838 struct sky2_port *sky2 = netdev_priv(dev);
3839 struct sky2_hw *hw = sky2->hw;
3840 unsigned port = sky2->port;
3841 unsigned int start;
3842 u64 _bytes, _packets;
3843
3844 do {
3845 start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp);
3846 _bytes = sky2->rx_stats.bytes;
3847 _packets = sky2->rx_stats.packets;
3848 } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start));
3849
3850 stats->rx_packets = _packets;
3851 stats->rx_bytes = _bytes;
3852
3853 do {
3854 start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp);
3855 _bytes = sky2->tx_stats.bytes;
3856 _packets = sky2->tx_stats.packets;
3857 } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start));
3858
3859 stats->tx_packets = _packets;
3860 stats->tx_bytes = _bytes;
3861
3862 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3863 + get_stats32(hw, port, GM_RXF_BC_OK);
3864
3865 stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3866
3867 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3868 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3869 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3870 + get_stats32(hw, port, GM_RXE_FRAG);
3871 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3872
3873 stats->rx_dropped = dev->stats.rx_dropped;
3874 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3875 stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3876
3877 return stats;
3878 }
3879
3880 /* Can have one global because blinking is controlled by
3881 * ethtool and that is always under RTNL mutex
3882 */
3883 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3884 {
3885 struct sky2_hw *hw = sky2->hw;
3886 unsigned port = sky2->port;
3887
3888 spin_lock_bh(&sky2->phy_lock);
3889 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3890 hw->chip_id == CHIP_ID_YUKON_EX ||
3891 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3892 u16 pg;
3893 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3894 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3895
3896 switch (mode) {
3897 case MO_LED_OFF:
3898 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3899 PHY_M_LEDC_LOS_CTRL(8) |
3900 PHY_M_LEDC_INIT_CTRL(8) |
3901 PHY_M_LEDC_STA1_CTRL(8) |
3902 PHY_M_LEDC_STA0_CTRL(8));
3903 break;
3904 case MO_LED_ON:
3905 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3906 PHY_M_LEDC_LOS_CTRL(9) |
3907 PHY_M_LEDC_INIT_CTRL(9) |
3908 PHY_M_LEDC_STA1_CTRL(9) |
3909 PHY_M_LEDC_STA0_CTRL(9));
3910 break;
3911 case MO_LED_BLINK:
3912 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3913 PHY_M_LEDC_LOS_CTRL(0xa) |
3914 PHY_M_LEDC_INIT_CTRL(0xa) |
3915 PHY_M_LEDC_STA1_CTRL(0xa) |
3916 PHY_M_LEDC_STA0_CTRL(0xa));
3917 break;
3918 case MO_LED_NORM:
3919 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3920 PHY_M_LEDC_LOS_CTRL(1) |
3921 PHY_M_LEDC_INIT_CTRL(8) |
3922 PHY_M_LEDC_STA1_CTRL(7) |
3923 PHY_M_LEDC_STA0_CTRL(7));
3924 }
3925
3926 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3927 } else
3928 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3929 PHY_M_LED_MO_DUP(mode) |
3930 PHY_M_LED_MO_10(mode) |
3931 PHY_M_LED_MO_100(mode) |
3932 PHY_M_LED_MO_1000(mode) |
3933 PHY_M_LED_MO_RX(mode) |
3934 PHY_M_LED_MO_TX(mode));
3935
3936 spin_unlock_bh(&sky2->phy_lock);
3937 }
3938
3939 /* blink LED's for finding board */
3940 static int sky2_set_phys_id(struct net_device *dev,
3941 enum ethtool_phys_id_state state)
3942 {
3943 struct sky2_port *sky2 = netdev_priv(dev);
3944
3945 switch (state) {
3946 case ETHTOOL_ID_ACTIVE:
3947 return 1; /* cycle on/off once per second */
3948 case ETHTOOL_ID_INACTIVE:
3949 sky2_led(sky2, MO_LED_NORM);
3950 break;
3951 case ETHTOOL_ID_ON:
3952 sky2_led(sky2, MO_LED_ON);
3953 break;
3954 case ETHTOOL_ID_OFF:
3955 sky2_led(sky2, MO_LED_OFF);
3956 break;
3957 }
3958
3959 return 0;
3960 }
3961
3962 static void sky2_get_pauseparam(struct net_device *dev,
3963 struct ethtool_pauseparam *ecmd)
3964 {
3965 struct sky2_port *sky2 = netdev_priv(dev);
3966
3967 switch (sky2->flow_mode) {
3968 case FC_NONE:
3969 ecmd->tx_pause = ecmd->rx_pause = 0;
3970 break;
3971 case FC_TX:
3972 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3973 break;
3974 case FC_RX:
3975 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3976 break;
3977 case FC_BOTH:
3978 ecmd->tx_pause = ecmd->rx_pause = 1;
3979 }
3980
3981 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3982 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3983 }
3984
3985 static int sky2_set_pauseparam(struct net_device *dev,
3986 struct ethtool_pauseparam *ecmd)
3987 {
3988 struct sky2_port *sky2 = netdev_priv(dev);
3989
3990 if (ecmd->autoneg == AUTONEG_ENABLE)
3991 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3992 else
3993 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3994
3995 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3996
3997 if (netif_running(dev))
3998 sky2_phy_reinit(sky2);
3999
4000 return 0;
4001 }
4002
4003 static int sky2_get_coalesce(struct net_device *dev,
4004 struct ethtool_coalesce *ecmd)
4005 {
4006 struct sky2_port *sky2 = netdev_priv(dev);
4007 struct sky2_hw *hw = sky2->hw;
4008
4009 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
4010 ecmd->tx_coalesce_usecs = 0;
4011 else {
4012 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
4013 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
4014 }
4015 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
4016
4017 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
4018 ecmd->rx_coalesce_usecs = 0;
4019 else {
4020 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
4021 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
4022 }
4023 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
4024
4025 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
4026 ecmd->rx_coalesce_usecs_irq = 0;
4027 else {
4028 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
4029 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
4030 }
4031
4032 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
4033
4034 return 0;
4035 }
4036
4037 /* Note: this affect both ports */
4038 static int sky2_set_coalesce(struct net_device *dev,
4039 struct ethtool_coalesce *ecmd)
4040 {
4041 struct sky2_port *sky2 = netdev_priv(dev);
4042 struct sky2_hw *hw = sky2->hw;
4043 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
4044
4045 if (ecmd->tx_coalesce_usecs > tmax ||
4046 ecmd->rx_coalesce_usecs > tmax ||
4047 ecmd->rx_coalesce_usecs_irq > tmax)
4048 return -EINVAL;
4049
4050 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
4051 return -EINVAL;
4052 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
4053 return -EINVAL;
4054 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
4055 return -EINVAL;
4056
4057 if (ecmd->tx_coalesce_usecs == 0)
4058 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
4059 else {
4060 sky2_write32(hw, STAT_TX_TIMER_INI,
4061 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
4062 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
4063 }
4064 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
4065
4066 if (ecmd->rx_coalesce_usecs == 0)
4067 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
4068 else {
4069 sky2_write32(hw, STAT_LEV_TIMER_INI,
4070 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
4071 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
4072 }
4073 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
4074
4075 if (ecmd->rx_coalesce_usecs_irq == 0)
4076 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
4077 else {
4078 sky2_write32(hw, STAT_ISR_TIMER_INI,
4079 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
4080 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
4081 }
4082 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
4083 return 0;
4084 }
4085
4086 static void sky2_get_ringparam(struct net_device *dev,
4087 struct ethtool_ringparam *ering)
4088 {
4089 struct sky2_port *sky2 = netdev_priv(dev);
4090
4091 ering->rx_max_pending = RX_MAX_PENDING;
4092 ering->tx_max_pending = TX_MAX_PENDING;
4093
4094 ering->rx_pending = sky2->rx_pending;
4095 ering->tx_pending = sky2->tx_pending;
4096 }
4097
4098 static int sky2_set_ringparam(struct net_device *dev,
4099 struct ethtool_ringparam *ering)
4100 {
4101 struct sky2_port *sky2 = netdev_priv(dev);
4102
4103 if (ering->rx_pending > RX_MAX_PENDING ||
4104 ering->rx_pending < 8 ||
4105 ering->tx_pending < TX_MIN_PENDING ||
4106 ering->tx_pending > TX_MAX_PENDING)
4107 return -EINVAL;
4108
4109 sky2_detach(dev);
4110
4111 sky2->rx_pending = ering->rx_pending;
4112 sky2->tx_pending = ering->tx_pending;
4113 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
4114
4115 return sky2_reattach(dev);
4116 }
4117
4118 static int sky2_get_regs_len(struct net_device *dev)
4119 {
4120 return 0x4000;
4121 }
4122
4123 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4124 {
4125 /* This complicated switch statement is to make sure and
4126 * only access regions that are unreserved.
4127 * Some blocks are only valid on dual port cards.
4128 */
4129 switch (b) {
4130 /* second port */
4131 case 5: /* Tx Arbiter 2 */
4132 case 9: /* RX2 */
4133 case 14 ... 15: /* TX2 */
4134 case 17: case 19: /* Ram Buffer 2 */
4135 case 22 ... 23: /* Tx Ram Buffer 2 */
4136 case 25: /* Rx MAC Fifo 1 */
4137 case 27: /* Tx MAC Fifo 2 */
4138 case 31: /* GPHY 2 */
4139 case 40 ... 47: /* Pattern Ram 2 */
4140 case 52: case 54: /* TCP Segmentation 2 */
4141 case 112 ... 116: /* GMAC 2 */
4142 return hw->ports > 1;
4143
4144 case 0: /* Control */
4145 case 2: /* Mac address */
4146 case 4: /* Tx Arbiter 1 */
4147 case 7: /* PCI express reg */
4148 case 8: /* RX1 */
4149 case 12 ... 13: /* TX1 */
4150 case 16: case 18:/* Rx Ram Buffer 1 */
4151 case 20 ... 21: /* Tx Ram Buffer 1 */
4152 case 24: /* Rx MAC Fifo 1 */
4153 case 26: /* Tx MAC Fifo 1 */
4154 case 28 ... 29: /* Descriptor and status unit */
4155 case 30: /* GPHY 1*/
4156 case 32 ... 39: /* Pattern Ram 1 */
4157 case 48: case 50: /* TCP Segmentation 1 */
4158 case 56 ... 60: /* PCI space */
4159 case 80 ... 84: /* GMAC 1 */
4160 return 1;
4161
4162 default:
4163 return 0;
4164 }
4165 }
4166
4167 /*
4168 * Returns copy of control register region
4169 * Note: ethtool_get_regs always provides full size (16k) buffer
4170 */
4171 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4172 void *p)
4173 {
4174 const struct sky2_port *sky2 = netdev_priv(dev);
4175 const void __iomem *io = sky2->hw->regs;
4176 unsigned int b;
4177
4178 regs->version = 1;
4179
4180 for (b = 0; b < 128; b++) {
4181 /* skip poisonous diagnostic ram region in block 3 */
4182 if (b == 3)
4183 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
4184 else if (sky2_reg_access_ok(sky2->hw, b))
4185 memcpy_fromio(p, io, 128);
4186 else
4187 memset(p, 0, 128);
4188
4189 p += 128;
4190 io += 128;
4191 }
4192 }
4193
4194 static int sky2_get_eeprom_len(struct net_device *dev)
4195 {
4196 struct sky2_port *sky2 = netdev_priv(dev);
4197 struct sky2_hw *hw = sky2->hw;
4198 u16 reg2;
4199
4200 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4201 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4202 }
4203
4204 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
4205 {
4206 unsigned long start = jiffies;
4207
4208 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4209 /* Can take up to 10.6 ms for write */
4210 if (time_after(jiffies, start + HZ/4)) {
4211 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
4212 return -ETIMEDOUT;
4213 }
4214 mdelay(1);
4215 }
4216
4217 return 0;
4218 }
4219
4220 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4221 u16 offset, size_t length)
4222 {
4223 int rc = 0;
4224
4225 while (length > 0) {
4226 u32 val;
4227
4228 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4229 rc = sky2_vpd_wait(hw, cap, 0);
4230 if (rc)
4231 break;
4232
4233 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4234
4235 memcpy(data, &val, min(sizeof(val), length));
4236 offset += sizeof(u32);
4237 data += sizeof(u32);
4238 length -= sizeof(u32);
4239 }
4240
4241 return rc;
4242 }
4243
4244 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4245 u16 offset, unsigned int length)
4246 {
4247 unsigned int i;
4248 int rc = 0;
4249
4250 for (i = 0; i < length; i += sizeof(u32)) {
4251 u32 val = *(u32 *)(data + i);
4252
4253 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4254 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4255
4256 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4257 if (rc)
4258 break;
4259 }
4260 return rc;
4261 }
4262
4263 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4264 u8 *data)
4265 {
4266 struct sky2_port *sky2 = netdev_priv(dev);
4267 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4268
4269 if (!cap)
4270 return -EINVAL;
4271
4272 eeprom->magic = SKY2_EEPROM_MAGIC;
4273
4274 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4275 }
4276
4277 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4278 u8 *data)
4279 {
4280 struct sky2_port *sky2 = netdev_priv(dev);
4281 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4282
4283 if (!cap)
4284 return -EINVAL;
4285
4286 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4287 return -EINVAL;
4288
4289 /* Partial writes not supported */
4290 if ((eeprom->offset & 3) || (eeprom->len & 3))
4291 return -EINVAL;
4292
4293 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4294 }
4295
4296 static u32 sky2_fix_features(struct net_device *dev, u32 features)
4297 {
4298 const struct sky2_port *sky2 = netdev_priv(dev);
4299 const struct sky2_hw *hw = sky2->hw;
4300
4301 /* In order to do Jumbo packets on these chips, need to turn off the
4302 * transmit store/forward. Therefore checksum offload won't work.
4303 */
4304 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) {
4305 netdev_info(dev, "checksum offload not possible with jumbo frames\n");
4306 features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
4307 }
4308
4309 /* Some hardware requires receive checksum for RSS to work. */
4310 if ( (features & NETIF_F_RXHASH) &&
4311 !(features & NETIF_F_RXCSUM) &&
4312 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) {
4313 netdev_info(dev, "receive hashing forces receive checksum\n");
4314 features |= NETIF_F_RXCSUM;
4315 }
4316
4317 return features;
4318 }
4319
4320 static int sky2_set_features(struct net_device *dev, u32 features)
4321 {
4322 struct sky2_port *sky2 = netdev_priv(dev);
4323 u32 changed = dev->features ^ features;
4324
4325 if (changed & NETIF_F_RXCSUM) {
4326 u32 on = features & NETIF_F_RXCSUM;
4327 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
4328 on ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
4329 }
4330
4331 if (changed & NETIF_F_RXHASH)
4332 rx_set_rss(dev, features);
4333
4334 if (changed & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4335 sky2_vlan_mode(dev, features);
4336
4337 return 0;
4338 }
4339
4340 static const struct ethtool_ops sky2_ethtool_ops = {
4341 .get_settings = sky2_get_settings,
4342 .set_settings = sky2_set_settings,
4343 .get_drvinfo = sky2_get_drvinfo,
4344 .get_wol = sky2_get_wol,
4345 .set_wol = sky2_set_wol,
4346 .get_msglevel = sky2_get_msglevel,
4347 .set_msglevel = sky2_set_msglevel,
4348 .nway_reset = sky2_nway_reset,
4349 .get_regs_len = sky2_get_regs_len,
4350 .get_regs = sky2_get_regs,
4351 .get_link = ethtool_op_get_link,
4352 .get_eeprom_len = sky2_get_eeprom_len,
4353 .get_eeprom = sky2_get_eeprom,
4354 .set_eeprom = sky2_set_eeprom,
4355 .get_strings = sky2_get_strings,
4356 .get_coalesce = sky2_get_coalesce,
4357 .set_coalesce = sky2_set_coalesce,
4358 .get_ringparam = sky2_get_ringparam,
4359 .set_ringparam = sky2_set_ringparam,
4360 .get_pauseparam = sky2_get_pauseparam,
4361 .set_pauseparam = sky2_set_pauseparam,
4362 .set_phys_id = sky2_set_phys_id,
4363 .get_sset_count = sky2_get_sset_count,
4364 .get_ethtool_stats = sky2_get_ethtool_stats,
4365 };
4366
4367 #ifdef CONFIG_SKY2_DEBUG
4368
4369 static struct dentry *sky2_debug;
4370
4371
4372 /*
4373 * Read and parse the first part of Vital Product Data
4374 */
4375 #define VPD_SIZE 128
4376 #define VPD_MAGIC 0x82
4377
4378 static const struct vpd_tag {
4379 char tag[2];
4380 char *label;
4381 } vpd_tags[] = {
4382 { "PN", "Part Number" },
4383 { "EC", "Engineering Level" },
4384 { "MN", "Manufacturer" },
4385 { "SN", "Serial Number" },
4386 { "YA", "Asset Tag" },
4387 { "VL", "First Error Log Message" },
4388 { "VF", "Second Error Log Message" },
4389 { "VB", "Boot Agent ROM Configuration" },
4390 { "VE", "EFI UNDI Configuration" },
4391 };
4392
4393 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4394 {
4395 size_t vpd_size;
4396 loff_t offs;
4397 u8 len;
4398 unsigned char *buf;
4399 u16 reg2;
4400
4401 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4402 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4403
4404 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4405 buf = kmalloc(vpd_size, GFP_KERNEL);
4406 if (!buf) {
4407 seq_puts(seq, "no memory!\n");
4408 return;
4409 }
4410
4411 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4412 seq_puts(seq, "VPD read failed\n");
4413 goto out;
4414 }
4415
4416 if (buf[0] != VPD_MAGIC) {
4417 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4418 goto out;
4419 }
4420 len = buf[1];
4421 if (len == 0 || len > vpd_size - 4) {
4422 seq_printf(seq, "Invalid id length: %d\n", len);
4423 goto out;
4424 }
4425
4426 seq_printf(seq, "%.*s\n", len, buf + 3);
4427 offs = len + 3;
4428
4429 while (offs < vpd_size - 4) {
4430 int i;
4431
4432 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4433 break;
4434 len = buf[offs + 2];
4435 if (offs + len + 3 >= vpd_size)
4436 break;
4437
4438 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4439 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4440 seq_printf(seq, " %s: %.*s\n",
4441 vpd_tags[i].label, len, buf + offs + 3);
4442 break;
4443 }
4444 }
4445 offs += len + 3;
4446 }
4447 out:
4448 kfree(buf);
4449 }
4450
4451 static int sky2_debug_show(struct seq_file *seq, void *v)
4452 {
4453 struct net_device *dev = seq->private;
4454 const struct sky2_port *sky2 = netdev_priv(dev);
4455 struct sky2_hw *hw = sky2->hw;
4456 unsigned port = sky2->port;
4457 unsigned idx, last;
4458 int sop;
4459
4460 sky2_show_vpd(seq, hw);
4461
4462 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4463 sky2_read32(hw, B0_ISRC),
4464 sky2_read32(hw, B0_IMSK),
4465 sky2_read32(hw, B0_Y2_SP_ICR));
4466
4467 if (!netif_running(dev)) {
4468 seq_printf(seq, "network not running\n");
4469 return 0;
4470 }
4471
4472 napi_disable(&hw->napi);
4473 last = sky2_read16(hw, STAT_PUT_IDX);
4474
4475 seq_printf(seq, "Status ring %u\n", hw->st_size);
4476 if (hw->st_idx == last)
4477 seq_puts(seq, "Status ring (empty)\n");
4478 else {
4479 seq_puts(seq, "Status ring\n");
4480 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4481 idx = RING_NEXT(idx, hw->st_size)) {
4482 const struct sky2_status_le *le = hw->st_le + idx;
4483 seq_printf(seq, "[%d] %#x %d %#x\n",
4484 idx, le->opcode, le->length, le->status);
4485 }
4486 seq_puts(seq, "\n");
4487 }
4488
4489 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4490 sky2->tx_cons, sky2->tx_prod,
4491 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4492 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4493
4494 /* Dump contents of tx ring */
4495 sop = 1;
4496 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4497 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4498 const struct sky2_tx_le *le = sky2->tx_le + idx;
4499 u32 a = le32_to_cpu(le->addr);
4500
4501 if (sop)
4502 seq_printf(seq, "%u:", idx);
4503 sop = 0;
4504
4505 switch (le->opcode & ~HW_OWNER) {
4506 case OP_ADDR64:
4507 seq_printf(seq, " %#x:", a);
4508 break;
4509 case OP_LRGLEN:
4510 seq_printf(seq, " mtu=%d", a);
4511 break;
4512 case OP_VLAN:
4513 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4514 break;
4515 case OP_TCPLISW:
4516 seq_printf(seq, " csum=%#x", a);
4517 break;
4518 case OP_LARGESEND:
4519 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4520 break;
4521 case OP_PACKET:
4522 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4523 break;
4524 case OP_BUFFER:
4525 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4526 break;
4527 default:
4528 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4529 a, le16_to_cpu(le->length));
4530 }
4531
4532 if (le->ctrl & EOP) {
4533 seq_putc(seq, '\n');
4534 sop = 1;
4535 }
4536 }
4537
4538 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4539 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4540 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4541 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4542
4543 sky2_read32(hw, B0_Y2_SP_LISR);
4544 napi_enable(&hw->napi);
4545 return 0;
4546 }
4547
4548 static int sky2_debug_open(struct inode *inode, struct file *file)
4549 {
4550 return single_open(file, sky2_debug_show, inode->i_private);
4551 }
4552
4553 static const struct file_operations sky2_debug_fops = {
4554 .owner = THIS_MODULE,
4555 .open = sky2_debug_open,
4556 .read = seq_read,
4557 .llseek = seq_lseek,
4558 .release = single_release,
4559 };
4560
4561 /*
4562 * Use network device events to create/remove/rename
4563 * debugfs file entries
4564 */
4565 static int sky2_device_event(struct notifier_block *unused,
4566 unsigned long event, void *ptr)
4567 {
4568 struct net_device *dev = ptr;
4569 struct sky2_port *sky2 = netdev_priv(dev);
4570
4571 if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug)
4572 return NOTIFY_DONE;
4573
4574 switch (event) {
4575 case NETDEV_CHANGENAME:
4576 if (sky2->debugfs) {
4577 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4578 sky2_debug, dev->name);
4579 }
4580 break;
4581
4582 case NETDEV_GOING_DOWN:
4583 if (sky2->debugfs) {
4584 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
4585 debugfs_remove(sky2->debugfs);
4586 sky2->debugfs = NULL;
4587 }
4588 break;
4589
4590 case NETDEV_UP:
4591 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4592 sky2_debug, dev,
4593 &sky2_debug_fops);
4594 if (IS_ERR(sky2->debugfs))
4595 sky2->debugfs = NULL;
4596 }
4597
4598 return NOTIFY_DONE;
4599 }
4600
4601 static struct notifier_block sky2_notifier = {
4602 .notifier_call = sky2_device_event,
4603 };
4604
4605
4606 static __init void sky2_debug_init(void)
4607 {
4608 struct dentry *ent;
4609
4610 ent = debugfs_create_dir("sky2", NULL);
4611 if (!ent || IS_ERR(ent))
4612 return;
4613
4614 sky2_debug = ent;
4615 register_netdevice_notifier(&sky2_notifier);
4616 }
4617
4618 static __exit void sky2_debug_cleanup(void)
4619 {
4620 if (sky2_debug) {
4621 unregister_netdevice_notifier(&sky2_notifier);
4622 debugfs_remove(sky2_debug);
4623 sky2_debug = NULL;
4624 }
4625 }
4626
4627 #else
4628 #define sky2_debug_init()
4629 #define sky2_debug_cleanup()
4630 #endif
4631
4632 /* Two copies of network device operations to handle special case of
4633 not allowing netpoll on second port */
4634 static const struct net_device_ops sky2_netdev_ops[2] = {
4635 {
4636 .ndo_open = sky2_open,
4637 .ndo_stop = sky2_close,
4638 .ndo_start_xmit = sky2_xmit_frame,
4639 .ndo_do_ioctl = sky2_ioctl,
4640 .ndo_validate_addr = eth_validate_addr,
4641 .ndo_set_mac_address = sky2_set_mac_address,
4642 .ndo_set_rx_mode = sky2_set_multicast,
4643 .ndo_change_mtu = sky2_change_mtu,
4644 .ndo_fix_features = sky2_fix_features,
4645 .ndo_set_features = sky2_set_features,
4646 .ndo_tx_timeout = sky2_tx_timeout,
4647 .ndo_get_stats64 = sky2_get_stats,
4648 #ifdef CONFIG_NET_POLL_CONTROLLER
4649 .ndo_poll_controller = sky2_netpoll,
4650 #endif
4651 },
4652 {
4653 .ndo_open = sky2_open,
4654 .ndo_stop = sky2_close,
4655 .ndo_start_xmit = sky2_xmit_frame,
4656 .ndo_do_ioctl = sky2_ioctl,
4657 .ndo_validate_addr = eth_validate_addr,
4658 .ndo_set_mac_address = sky2_set_mac_address,
4659 .ndo_set_rx_mode = sky2_set_multicast,
4660 .ndo_change_mtu = sky2_change_mtu,
4661 .ndo_fix_features = sky2_fix_features,
4662 .ndo_set_features = sky2_set_features,
4663 .ndo_tx_timeout = sky2_tx_timeout,
4664 .ndo_get_stats64 = sky2_get_stats,
4665 },
4666 };
4667
4668 /* Initialize network device */
4669 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4670 unsigned port,
4671 int highmem, int wol)
4672 {
4673 struct sky2_port *sky2;
4674 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4675
4676 if (!dev) {
4677 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4678 return NULL;
4679 }
4680
4681 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4682 dev->irq = hw->pdev->irq;
4683 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4684 dev->watchdog_timeo = TX_WATCHDOG;
4685 dev->netdev_ops = &sky2_netdev_ops[port];
4686
4687 sky2 = netdev_priv(dev);
4688 sky2->netdev = dev;
4689 sky2->hw = hw;
4690 sky2->msg_enable = netif_msg_init(debug, default_msg);
4691
4692 /* Auto speed and flow control */
4693 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4694 if (hw->chip_id != CHIP_ID_YUKON_XL)
4695 dev->hw_features |= NETIF_F_RXCSUM;
4696
4697 sky2->flow_mode = FC_BOTH;
4698
4699 sky2->duplex = -1;
4700 sky2->speed = -1;
4701 sky2->advertising = sky2_supported_modes(hw);
4702 sky2->wol = wol;
4703
4704 spin_lock_init(&sky2->phy_lock);
4705
4706 sky2->tx_pending = TX_DEF_PENDING;
4707 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
4708 sky2->rx_pending = RX_DEF_PENDING;
4709
4710 hw->dev[port] = dev;
4711
4712 sky2->port = port;
4713
4714 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO;
4715
4716 if (highmem)
4717 dev->features |= NETIF_F_HIGHDMA;
4718
4719 /* Enable receive hashing unless hardware is known broken */
4720 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4721 dev->hw_features |= NETIF_F_RXHASH;
4722
4723 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4724 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4725 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
4726 }
4727
4728 dev->features |= dev->hw_features;
4729
4730 /* read the mac address */
4731 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4732 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4733
4734 return dev;
4735 }
4736
4737 static void __devinit sky2_show_addr(struct net_device *dev)
4738 {
4739 const struct sky2_port *sky2 = netdev_priv(dev);
4740
4741 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
4742 }
4743
4744 /* Handle software interrupt used during MSI test */
4745 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4746 {
4747 struct sky2_hw *hw = dev_id;
4748 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4749
4750 if (status == 0)
4751 return IRQ_NONE;
4752
4753 if (status & Y2_IS_IRQ_SW) {
4754 hw->flags |= SKY2_HW_USE_MSI;
4755 wake_up(&hw->msi_wait);
4756 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4757 }
4758 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4759
4760 return IRQ_HANDLED;
4761 }
4762
4763 /* Test interrupt path by forcing a a software IRQ */
4764 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4765 {
4766 struct pci_dev *pdev = hw->pdev;
4767 int err;
4768
4769 init_waitqueue_head(&hw->msi_wait);
4770
4771 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4772
4773 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4774 if (err) {
4775 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4776 return err;
4777 }
4778
4779 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4780 sky2_read8(hw, B0_CTST);
4781
4782 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4783
4784 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4785 /* MSI test failed, go back to INTx mode */
4786 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4787 "switching to INTx mode.\n");
4788
4789 err = -EOPNOTSUPP;
4790 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4791 }
4792
4793 sky2_write32(hw, B0_IMSK, 0);
4794 sky2_read32(hw, B0_IMSK);
4795
4796 free_irq(pdev->irq, hw);
4797
4798 return err;
4799 }
4800
4801 /* This driver supports yukon2 chipset only */
4802 static const char *sky2_name(u8 chipid, char *buf, int sz)
4803 {
4804 const char *name[] = {
4805 "XL", /* 0xb3 */
4806 "EC Ultra", /* 0xb4 */
4807 "Extreme", /* 0xb5 */
4808 "EC", /* 0xb6 */
4809 "FE", /* 0xb7 */
4810 "FE+", /* 0xb8 */
4811 "Supreme", /* 0xb9 */
4812 "UL 2", /* 0xba */
4813 "Unknown", /* 0xbb */
4814 "Optima", /* 0xbc */
4815 "Optima Prime", /* 0xbd */
4816 "Optima 2", /* 0xbe */
4817 };
4818
4819 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2)
4820 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4821 else
4822 snprintf(buf, sz, "(chip %#x)", chipid);
4823 return buf;
4824 }
4825
4826 static int __devinit sky2_probe(struct pci_dev *pdev,
4827 const struct pci_device_id *ent)
4828 {
4829 struct net_device *dev, *dev1;
4830 struct sky2_hw *hw;
4831 int err, using_dac = 0, wol_default;
4832 u32 reg;
4833 char buf1[16];
4834
4835 err = pci_enable_device(pdev);
4836 if (err) {
4837 dev_err(&pdev->dev, "cannot enable PCI device\n");
4838 goto err_out;
4839 }
4840
4841 /* Get configuration information
4842 * Note: only regular PCI config access once to test for HW issues
4843 * other PCI access through shared memory for speed and to
4844 * avoid MMCONFIG problems.
4845 */
4846 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4847 if (err) {
4848 dev_err(&pdev->dev, "PCI read config failed\n");
4849 goto err_out;
4850 }
4851
4852 if (~reg == 0) {
4853 dev_err(&pdev->dev, "PCI configuration read error\n");
4854 goto err_out;
4855 }
4856
4857 err = pci_request_regions(pdev, DRV_NAME);
4858 if (err) {
4859 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4860 goto err_out_disable;
4861 }
4862
4863 pci_set_master(pdev);
4864
4865 if (sizeof(dma_addr_t) > sizeof(u32) &&
4866 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4867 using_dac = 1;
4868 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4869 if (err < 0) {
4870 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4871 "for consistent allocations\n");
4872 goto err_out_free_regions;
4873 }
4874 } else {
4875 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4876 if (err) {
4877 dev_err(&pdev->dev, "no usable DMA configuration\n");
4878 goto err_out_free_regions;
4879 }
4880 }
4881
4882
4883 #ifdef __BIG_ENDIAN
4884 /* The sk98lin vendor driver uses hardware byte swapping but
4885 * this driver uses software swapping.
4886 */
4887 reg &= ~PCI_REV_DESC;
4888 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
4889 if (err) {
4890 dev_err(&pdev->dev, "PCI write config failed\n");
4891 goto err_out_free_regions;
4892 }
4893 #endif
4894
4895 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4896
4897 err = -ENOMEM;
4898
4899 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4900 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4901 if (!hw) {
4902 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4903 goto err_out_free_regions;
4904 }
4905
4906 hw->pdev = pdev;
4907 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4908
4909 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4910 if (!hw->regs) {
4911 dev_err(&pdev->dev, "cannot map device registers\n");
4912 goto err_out_free_hw;
4913 }
4914
4915 err = sky2_init(hw);
4916 if (err)
4917 goto err_out_iounmap;
4918
4919 /* ring for status responses */
4920 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
4921 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4922 &hw->st_dma);
4923 if (!hw->st_le)
4924 goto err_out_reset;
4925
4926 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4927 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4928
4929 sky2_reset(hw);
4930
4931 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4932 if (!dev) {
4933 err = -ENOMEM;
4934 goto err_out_free_pci;
4935 }
4936
4937 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4938 err = sky2_test_msi(hw);
4939 if (err == -EOPNOTSUPP)
4940 pci_disable_msi(pdev);
4941 else if (err)
4942 goto err_out_free_netdev;
4943 }
4944
4945 err = register_netdev(dev);
4946 if (err) {
4947 dev_err(&pdev->dev, "cannot register net device\n");
4948 goto err_out_free_netdev;
4949 }
4950
4951 netif_carrier_off(dev);
4952
4953 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4954
4955 sky2_show_addr(dev);
4956
4957 if (hw->ports > 1) {
4958 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4959 if (!dev1) {
4960 err = -ENOMEM;
4961 goto err_out_unregister;
4962 }
4963
4964 err = register_netdev(dev1);
4965 if (err) {
4966 dev_err(&pdev->dev, "cannot register second net device\n");
4967 goto err_out_free_dev1;
4968 }
4969
4970 err = sky2_setup_irq(hw, hw->irq_name);
4971 if (err)
4972 goto err_out_unregister_dev1;
4973
4974 sky2_show_addr(dev1);
4975 }
4976
4977 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4978 INIT_WORK(&hw->restart_work, sky2_restart);
4979
4980 pci_set_drvdata(pdev, hw);
4981 pdev->d3_delay = 150;
4982
4983 return 0;
4984
4985 err_out_unregister_dev1:
4986 unregister_netdev(dev1);
4987 err_out_free_dev1:
4988 free_netdev(dev1);
4989 err_out_unregister:
4990 if (hw->flags & SKY2_HW_USE_MSI)
4991 pci_disable_msi(pdev);
4992 unregister_netdev(dev);
4993 err_out_free_netdev:
4994 free_netdev(dev);
4995 err_out_free_pci:
4996 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4997 hw->st_le, hw->st_dma);
4998 err_out_reset:
4999 sky2_write8(hw, B0_CTST, CS_RST_SET);
5000 err_out_iounmap:
5001 iounmap(hw->regs);
5002 err_out_free_hw:
5003 kfree(hw);
5004 err_out_free_regions:
5005 pci_release_regions(pdev);
5006 err_out_disable:
5007 pci_disable_device(pdev);
5008 err_out:
5009 pci_set_drvdata(pdev, NULL);
5010 return err;
5011 }
5012
5013 static void __devexit sky2_remove(struct pci_dev *pdev)
5014 {
5015 struct sky2_hw *hw = pci_get_drvdata(pdev);
5016 int i;
5017
5018 if (!hw)
5019 return;
5020
5021 del_timer_sync(&hw->watchdog_timer);
5022 cancel_work_sync(&hw->restart_work);
5023
5024 for (i = hw->ports-1; i >= 0; --i)
5025 unregister_netdev(hw->dev[i]);
5026
5027 sky2_write32(hw, B0_IMSK, 0);
5028 sky2_read32(hw, B0_IMSK);
5029
5030 sky2_power_aux(hw);
5031
5032 sky2_write8(hw, B0_CTST, CS_RST_SET);
5033 sky2_read8(hw, B0_CTST);
5034
5035 if (hw->ports > 1) {
5036 napi_disable(&hw->napi);
5037 free_irq(pdev->irq, hw);
5038 }
5039
5040 if (hw->flags & SKY2_HW_USE_MSI)
5041 pci_disable_msi(pdev);
5042 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5043 hw->st_le, hw->st_dma);
5044 pci_release_regions(pdev);
5045 pci_disable_device(pdev);
5046
5047 for (i = hw->ports-1; i >= 0; --i)
5048 free_netdev(hw->dev[i]);
5049
5050 iounmap(hw->regs);
5051 kfree(hw);
5052
5053 pci_set_drvdata(pdev, NULL);
5054 }
5055
5056 static int sky2_suspend(struct device *dev)
5057 {
5058 struct pci_dev *pdev = to_pci_dev(dev);
5059 struct sky2_hw *hw = pci_get_drvdata(pdev);
5060 int i;
5061
5062 if (!hw)
5063 return 0;
5064
5065 del_timer_sync(&hw->watchdog_timer);
5066 cancel_work_sync(&hw->restart_work);
5067
5068 rtnl_lock();
5069
5070 sky2_all_down(hw);
5071 for (i = 0; i < hw->ports; i++) {
5072 struct net_device *dev = hw->dev[i];
5073 struct sky2_port *sky2 = netdev_priv(dev);
5074
5075 if (sky2->wol)
5076 sky2_wol_init(sky2);
5077 }
5078
5079 sky2_power_aux(hw);
5080 rtnl_unlock();
5081
5082 return 0;
5083 }
5084
5085 #ifdef CONFIG_PM_SLEEP
5086 static int sky2_resume(struct device *dev)
5087 {
5088 struct pci_dev *pdev = to_pci_dev(dev);
5089 struct sky2_hw *hw = pci_get_drvdata(pdev);
5090 int err;
5091
5092 if (!hw)
5093 return 0;
5094
5095 /* Re-enable all clocks */
5096 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
5097 if (err) {
5098 dev_err(&pdev->dev, "PCI write config failed\n");
5099 goto out;
5100 }
5101
5102 rtnl_lock();
5103 sky2_reset(hw);
5104 sky2_all_up(hw);
5105 rtnl_unlock();
5106
5107 return 0;
5108 out:
5109
5110 dev_err(&pdev->dev, "resume failed (%d)\n", err);
5111 pci_disable_device(pdev);
5112 return err;
5113 }
5114
5115 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
5116 #define SKY2_PM_OPS (&sky2_pm_ops)
5117
5118 #else
5119
5120 #define SKY2_PM_OPS NULL
5121 #endif
5122
5123 static void sky2_shutdown(struct pci_dev *pdev)
5124 {
5125 sky2_suspend(&pdev->dev);
5126 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
5127 pci_set_power_state(pdev, PCI_D3hot);
5128 }
5129
5130 static struct pci_driver sky2_driver = {
5131 .name = DRV_NAME,
5132 .id_table = sky2_id_table,
5133 .probe = sky2_probe,
5134 .remove = __devexit_p(sky2_remove),
5135 .shutdown = sky2_shutdown,
5136 .driver.pm = SKY2_PM_OPS,
5137 };
5138
5139 static int __init sky2_init_module(void)
5140 {
5141 pr_info("driver version " DRV_VERSION "\n");
5142
5143 sky2_debug_init();
5144 return pci_register_driver(&sky2_driver);
5145 }
5146
5147 static void __exit sky2_cleanup_module(void)
5148 {
5149 pci_unregister_driver(&sky2_driver);
5150 sky2_debug_cleanup();
5151 }
5152
5153 module_init(sky2_init_module);
5154 module_exit(sky2_cleanup_module);
5155
5156 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
5157 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
5158 MODULE_LICENSE("GPL");
5159 MODULE_VERSION(DRV_VERSION);
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