2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/pci.h>
20 #include <net/cfg80211.h>
21 #include <net/mac80211.h>
23 #include <brcmu_utils.h>
32 #include "brcms_trace_events.h"
35 * dma register field offset calculation
37 #define DMA64REGOFFS(field) offsetof(struct dma64regs, field)
38 #define DMA64TXREGOFFS(di, field) (di->d64txregbase + DMA64REGOFFS(field))
39 #define DMA64RXREGOFFS(di, field) (di->d64rxregbase + DMA64REGOFFS(field))
42 * DMA hardware requires each descriptor ring to be 8kB aligned, and fit within
43 * a contiguous 8kB physical address.
45 #define D64RINGALIGN_BITS 13
46 #define D64MAXRINGSZ (1 << D64RINGALIGN_BITS)
47 #define D64RINGALIGN (1 << D64RINGALIGN_BITS)
49 #define D64MAXDD (D64MAXRINGSZ / sizeof(struct dma64desc))
51 /* transmit channel control */
52 #define D64_XC_XE 0x00000001 /* transmit enable */
53 #define D64_XC_SE 0x00000002 /* transmit suspend request */
54 #define D64_XC_LE 0x00000004 /* loopback enable */
55 #define D64_XC_FL 0x00000010 /* flush request */
56 #define D64_XC_PD 0x00000800 /* parity check disable */
57 #define D64_XC_AE 0x00030000 /* address extension bits */
58 #define D64_XC_AE_SHIFT 16
60 /* transmit descriptor table pointer */
61 #define D64_XP_LD_MASK 0x00000fff /* last valid descriptor */
63 /* transmit channel status */
64 #define D64_XS0_CD_MASK 0x00001fff /* current descriptor pointer */
65 #define D64_XS0_XS_MASK 0xf0000000 /* transmit state */
66 #define D64_XS0_XS_SHIFT 28
67 #define D64_XS0_XS_DISABLED 0x00000000 /* disabled */
68 #define D64_XS0_XS_ACTIVE 0x10000000 /* active */
69 #define D64_XS0_XS_IDLE 0x20000000 /* idle wait */
70 #define D64_XS0_XS_STOPPED 0x30000000 /* stopped */
71 #define D64_XS0_XS_SUSP 0x40000000 /* suspend pending */
73 #define D64_XS1_AD_MASK 0x00001fff /* active descriptor */
74 #define D64_XS1_XE_MASK 0xf0000000 /* transmit errors */
75 #define D64_XS1_XE_SHIFT 28
76 #define D64_XS1_XE_NOERR 0x00000000 /* no error */
77 #define D64_XS1_XE_DPE 0x10000000 /* descriptor protocol error */
78 #define D64_XS1_XE_DFU 0x20000000 /* data fifo underrun */
79 #define D64_XS1_XE_DTE 0x30000000 /* data transfer error */
80 #define D64_XS1_XE_DESRE 0x40000000 /* descriptor read error */
81 #define D64_XS1_XE_COREE 0x50000000 /* core error */
83 /* receive channel control */
85 #define D64_RC_RE 0x00000001
86 /* receive frame offset */
87 #define D64_RC_RO_MASK 0x000000fe
88 #define D64_RC_RO_SHIFT 1
89 /* direct fifo receive (pio) mode */
90 #define D64_RC_FM 0x00000100
91 /* separate rx header descriptor enable */
92 #define D64_RC_SH 0x00000200
93 /* overflow continue */
94 #define D64_RC_OC 0x00000400
95 /* parity check disable */
96 #define D64_RC_PD 0x00000800
97 /* address extension bits */
98 #define D64_RC_AE 0x00030000
99 #define D64_RC_AE_SHIFT 16
101 /* flags for dma controller */
103 #define DMA_CTRL_PEN (1 << 0)
104 /* rx overflow continue */
105 #define DMA_CTRL_ROC (1 << 1)
106 /* allow rx scatter to multiple descriptors */
107 #define DMA_CTRL_RXMULTI (1 << 2)
108 /* Unframed Rx/Tx data */
109 #define DMA_CTRL_UNFRAMED (1 << 3)
111 /* receive descriptor table pointer */
112 #define D64_RP_LD_MASK 0x00000fff /* last valid descriptor */
114 /* receive channel status */
115 #define D64_RS0_CD_MASK 0x00001fff /* current descriptor pointer */
116 #define D64_RS0_RS_MASK 0xf0000000 /* receive state */
117 #define D64_RS0_RS_SHIFT 28
118 #define D64_RS0_RS_DISABLED 0x00000000 /* disabled */
119 #define D64_RS0_RS_ACTIVE 0x10000000 /* active */
120 #define D64_RS0_RS_IDLE 0x20000000 /* idle wait */
121 #define D64_RS0_RS_STOPPED 0x30000000 /* stopped */
122 #define D64_RS0_RS_SUSP 0x40000000 /* suspend pending */
124 #define D64_RS1_AD_MASK 0x0001ffff /* active descriptor */
125 #define D64_RS1_RE_MASK 0xf0000000 /* receive errors */
126 #define D64_RS1_RE_SHIFT 28
127 #define D64_RS1_RE_NOERR 0x00000000 /* no error */
128 #define D64_RS1_RE_DPO 0x10000000 /* descriptor protocol error */
129 #define D64_RS1_RE_DFU 0x20000000 /* data fifo overflow */
130 #define D64_RS1_RE_DTE 0x30000000 /* data transfer error */
131 #define D64_RS1_RE_DESRE 0x40000000 /* descriptor read error */
132 #define D64_RS1_RE_COREE 0x50000000 /* core error */
135 #define D64_FA_OFF_MASK 0xffff /* offset */
136 #define D64_FA_SEL_MASK 0xf0000 /* select */
137 #define D64_FA_SEL_SHIFT 16
138 #define D64_FA_SEL_XDD 0x00000 /* transmit dma data */
139 #define D64_FA_SEL_XDP 0x10000 /* transmit dma pointers */
140 #define D64_FA_SEL_RDD 0x40000 /* receive dma data */
141 #define D64_FA_SEL_RDP 0x50000 /* receive dma pointers */
142 #define D64_FA_SEL_XFD 0x80000 /* transmit fifo data */
143 #define D64_FA_SEL_XFP 0x90000 /* transmit fifo pointers */
144 #define D64_FA_SEL_RFD 0xc0000 /* receive fifo data */
145 #define D64_FA_SEL_RFP 0xd0000 /* receive fifo pointers */
146 #define D64_FA_SEL_RSD 0xe0000 /* receive frame status data */
147 #define D64_FA_SEL_RSP 0xf0000 /* receive frame status pointers */
149 /* descriptor control flags 1 */
150 #define D64_CTRL_COREFLAGS 0x0ff00000 /* core specific flags */
151 #define D64_CTRL1_EOT ((u32)1 << 28) /* end of descriptor table */
152 #define D64_CTRL1_IOC ((u32)1 << 29) /* interrupt on completion */
153 #define D64_CTRL1_EOF ((u32)1 << 30) /* end of frame */
154 #define D64_CTRL1_SOF ((u32)1 << 31) /* start of frame */
156 /* descriptor control flags 2 */
157 /* buffer byte count. real data len must <= 16KB */
158 #define D64_CTRL2_BC_MASK 0x00007fff
159 /* address extension bits */
160 #define D64_CTRL2_AE 0x00030000
161 #define D64_CTRL2_AE_SHIFT 16
163 #define D64_CTRL2_PARITY 0x00040000
165 /* control flags in the range [27:20] are core-specific and not defined here */
166 #define D64_CTRL_CORE_MASK 0x0ff00000
168 #define D64_RX_FRM_STS_LEN 0x0000ffff /* frame length mask */
169 #define D64_RX_FRM_STS_OVFL 0x00800000 /* RxOverFlow */
170 #define D64_RX_FRM_STS_DSCRCNT 0x0f000000 /* no. of descriptors used - 1 */
171 #define D64_RX_FRM_STS_DATATYPE 0xf0000000 /* core-dependent data type */
174 * packet headroom necessary to accommodate the largest header
175 * in the system, (i.e TXOFF). By doing, we avoid the need to
176 * allocate an extra buffer for the header when bridging to WL.
177 * There is a compile time check in wlc.c which ensure that this
178 * value is at least as big as TXOFF. This value is used in
182 #define BCMEXTRAHDROOM 172
184 #define MAXNAMEL 8 /* 8 char names */
186 /* macros to convert between byte offsets and indexes */
187 #define B2I(bytes, type) ((bytes) / sizeof(type))
188 #define I2B(index, type) ((index) * sizeof(type))
190 #define PCI32ADDR_HIGH 0xc0000000 /* address[31:30] */
191 #define PCI32ADDR_HIGH_SHIFT 30 /* address[31:30] */
193 #define PCI64ADDR_HIGH 0x80000000 /* address[63] */
194 #define PCI64ADDR_HIGH_SHIFT 31 /* address[63] */
198 * Descriptors are only read by the hardware, never written back.
201 __le32 ctrl1
; /* misc control bits & bufcount */
202 __le32 ctrl2
; /* buffer count and address extension */
203 __le32 addrlow
; /* memory address of the date buffer, bits 31:0 */
204 __le32 addrhigh
; /* memory address of the date buffer, bits 63:32 */
207 /* dma engine software state */
209 struct dma_pub dma
; /* exported structure */
210 char name
[MAXNAMEL
]; /* callers name for diag msgs */
212 struct bcma_device
*core
;
213 struct device
*dmadev
;
215 /* session information for AMPDU */
216 struct brcms_ampdu_session ampdu_session
;
218 bool dma64
; /* this dma engine is operating in 64-bit mode */
219 bool addrext
; /* this dma engine supports DmaExtendedAddrChanges */
221 /* 64-bit dma tx engine registers */
223 /* 64-bit dma rx engine registers */
225 /* pointer to dma64 tx descriptor ring */
226 struct dma64desc
*txd64
;
227 /* pointer to dma64 rx descriptor ring */
228 struct dma64desc
*rxd64
;
230 u16 dmadesc_align
; /* alignment requirement for dma descriptors */
232 u16 ntxd
; /* # tx descriptors tunable */
233 u16 txin
; /* index of next descriptor to reclaim */
234 u16 txout
; /* index of next descriptor to post */
235 /* pointer to parallel array of pointers to packets */
236 struct sk_buff
**txp
;
237 /* Aligned physical address of descriptor ring */
239 /* Original physical address of descriptor ring */
240 dma_addr_t txdpaorig
;
241 u16 txdalign
; /* #bytes added to alloc'd mem to align txd */
242 u32 txdalloc
; /* #bytes allocated for the ring */
243 u32 xmtptrbase
; /* When using unaligned descriptors, the ptr register
244 * is not just an index, it needs all 13 bits to be
245 * an offset from the addr register.
248 u16 nrxd
; /* # rx descriptors tunable */
249 u16 rxin
; /* index of next descriptor to reclaim */
250 u16 rxout
; /* index of next descriptor to post */
251 /* pointer to parallel array of pointers to packets */
252 struct sk_buff
**rxp
;
253 /* Aligned physical address of descriptor ring */
255 /* Original physical address of descriptor ring */
256 dma_addr_t rxdpaorig
;
257 u16 rxdalign
; /* #bytes added to alloc'd mem to align rxd */
258 u32 rxdalloc
; /* #bytes allocated for the ring */
259 u32 rcvptrbase
; /* Base for ptr reg when using unaligned descriptors */
262 unsigned int rxbufsize
; /* rx buffer size in bytes, not including
265 uint rxextrahdrroom
; /* extra rx headroom, reverseved to assist upper
266 * stack, e.g. some rx pkt buffers will be
267 * bridged to tx side without byte copying.
268 * The extra headroom needs to be large enough
269 * to fit txheader needs. Some dongle driver may
272 uint nrxpost
; /* # rx buffers to keep posted */
273 unsigned int rxoffset
; /* rxcontrol offset */
274 /* add to get dma address of descriptor ring, low 32 bits */
278 /* add to get dma address of data buffer, low 32 bits */
282 /* descriptor base need to be aligned or not */
286 /* Check for odd number of 1's */
287 static u32
parity32(__le32 data
)
289 /* no swap needed for counting 1's */
290 u32 par_data
= *(u32
*)&data
;
292 par_data
^= par_data
>> 16;
293 par_data
^= par_data
>> 8;
294 par_data
^= par_data
>> 4;
295 par_data
^= par_data
>> 2;
296 par_data
^= par_data
>> 1;
301 static bool dma64_dd_parity(struct dma64desc
*dd
)
303 return parity32(dd
->addrlow
^ dd
->addrhigh
^ dd
->ctrl1
^ dd
->ctrl2
);
306 /* descriptor bumping functions */
308 static uint
xxd(uint x
, uint n
)
310 return x
& (n
- 1); /* faster than %, but n must be power of 2 */
313 static uint
txd(struct dma_info
*di
, uint x
)
315 return xxd(x
, di
->ntxd
);
318 static uint
rxd(struct dma_info
*di
, uint x
)
320 return xxd(x
, di
->nrxd
);
323 static uint
nexttxd(struct dma_info
*di
, uint i
)
325 return txd(di
, i
+ 1);
328 static uint
prevtxd(struct dma_info
*di
, uint i
)
330 return txd(di
, i
- 1);
333 static uint
nextrxd(struct dma_info
*di
, uint i
)
335 return rxd(di
, i
+ 1);
338 static uint
ntxdactive(struct dma_info
*di
, uint h
, uint t
)
343 static uint
nrxdactive(struct dma_info
*di
, uint h
, uint t
)
348 static uint
_dma_ctrlflags(struct dma_info
*di
, uint mask
, uint flags
)
353 brcms_dbg_dma(di
->core
, "NULL dma handle\n");
357 dmactrlflags
= di
->dma
.dmactrlflags
;
358 dmactrlflags
&= ~mask
;
359 dmactrlflags
|= flags
;
361 /* If trying to enable parity, check if parity is actually supported */
362 if (dmactrlflags
& DMA_CTRL_PEN
) {
365 control
= bcma_read32(di
->core
, DMA64TXREGOFFS(di
, control
));
366 bcma_write32(di
->core
, DMA64TXREGOFFS(di
, control
),
367 control
| D64_XC_PD
);
368 if (bcma_read32(di
->core
, DMA64TXREGOFFS(di
, control
)) &
370 /* We *can* disable it so it is supported,
371 * restore control register
373 bcma_write32(di
->core
, DMA64TXREGOFFS(di
, control
),
376 /* Not supported, don't allow it to be enabled */
377 dmactrlflags
&= ~DMA_CTRL_PEN
;
380 di
->dma
.dmactrlflags
= dmactrlflags
;
385 static bool _dma64_addrext(struct dma_info
*di
, uint ctrl_offset
)
388 bcma_set32(di
->core
, ctrl_offset
, D64_XC_AE
);
389 w
= bcma_read32(di
->core
, ctrl_offset
);
390 bcma_mask32(di
->core
, ctrl_offset
, ~D64_XC_AE
);
391 return (w
& D64_XC_AE
) == D64_XC_AE
;
395 * return true if this dma engine supports DmaExtendedAddrChanges,
398 static bool _dma_isaddrext(struct dma_info
*di
)
400 /* DMA64 supports full 32- or 64-bit operation. AE is always valid */
402 /* not all tx or rx channel are available */
403 if (di
->d64txregbase
!= 0) {
404 if (!_dma64_addrext(di
, DMA64TXREGOFFS(di
, control
)))
405 brcms_dbg_dma(di
->core
,
406 "%s: DMA64 tx doesn't have AE set\n",
409 } else if (di
->d64rxregbase
!= 0) {
410 if (!_dma64_addrext(di
, DMA64RXREGOFFS(di
, control
)))
411 brcms_dbg_dma(di
->core
,
412 "%s: DMA64 rx doesn't have AE set\n",
420 static bool _dma_descriptor_align(struct dma_info
*di
)
424 /* Check to see if the descriptors need to be aligned on 4K/8K or not */
425 if (di
->d64txregbase
!= 0) {
426 bcma_write32(di
->core
, DMA64TXREGOFFS(di
, addrlow
), 0xff0);
427 addrl
= bcma_read32(di
->core
, DMA64TXREGOFFS(di
, addrlow
));
430 } else if (di
->d64rxregbase
!= 0) {
431 bcma_write32(di
->core
, DMA64RXREGOFFS(di
, addrlow
), 0xff0);
432 addrl
= bcma_read32(di
->core
, DMA64RXREGOFFS(di
, addrlow
));
440 * Descriptor table must start at the DMA hardware dictated alignment, so
441 * allocated memory must be large enough to support this requirement.
443 static void *dma_alloc_consistent(struct dma_info
*di
, uint size
,
444 u16 align_bits
, uint
*alloced
,
448 u16 align
= (1 << align_bits
);
449 if (!IS_ALIGNED(PAGE_SIZE
, align
))
453 return dma_alloc_coherent(di
->dmadev
, size
, pap
, GFP_ATOMIC
);
457 u8
dma_align_sizetobits(uint size
)
465 /* This function ensures that the DMA descriptor ring will not get allocated
466 * across Page boundary. If the allocation is done across the page boundary
467 * at the first time, then it is freed and the allocation is done at
468 * descriptor ring size aligned location. This will ensure that the ring will
469 * not cross page boundary
471 static void *dma_ringalloc(struct dma_info
*di
, u32 boundary
, uint size
,
472 u16
*alignbits
, uint
*alloced
,
477 u32 alignbytes
= 1 << *alignbits
;
479 va
= dma_alloc_consistent(di
, size
, *alignbits
, alloced
, descpa
);
484 desc_strtaddr
= (u32
) roundup((unsigned long)va
, alignbytes
);
485 if (((desc_strtaddr
+ size
- 1) & boundary
) != (desc_strtaddr
487 *alignbits
= dma_align_sizetobits(size
);
488 dma_free_coherent(di
->dmadev
, size
, va
, *descpa
);
489 va
= dma_alloc_consistent(di
, size
, *alignbits
,
495 static bool dma64_alloc(struct dma_info
*di
, uint direction
)
504 ddlen
= sizeof(struct dma64desc
);
506 size
= (direction
== DMA_TX
) ? (di
->ntxd
* ddlen
) : (di
->nrxd
* ddlen
);
507 align_bits
= di
->dmadesc_align
;
508 align
= (1 << align_bits
);
510 if (direction
== DMA_TX
) {
511 va
= dma_ringalloc(di
, D64RINGALIGN
, size
, &align_bits
,
512 &alloced
, &di
->txdpaorig
);
514 brcms_dbg_dma(di
->core
,
515 "%s: DMA_ALLOC_CONSISTENT(ntxd) failed\n",
519 align
= (1 << align_bits
);
520 di
->txd64
= (struct dma64desc
*)
521 roundup((unsigned long)va
, align
);
522 di
->txdalign
= (uint
) ((s8
*)di
->txd64
- (s8
*) va
);
523 di
->txdpa
= di
->txdpaorig
+ di
->txdalign
;
524 di
->txdalloc
= alloced
;
526 va
= dma_ringalloc(di
, D64RINGALIGN
, size
, &align_bits
,
527 &alloced
, &di
->rxdpaorig
);
529 brcms_dbg_dma(di
->core
,
530 "%s: DMA_ALLOC_CONSISTENT(nrxd) failed\n",
534 align
= (1 << align_bits
);
535 di
->rxd64
= (struct dma64desc
*)
536 roundup((unsigned long)va
, align
);
537 di
->rxdalign
= (uint
) ((s8
*)di
->rxd64
- (s8
*) va
);
538 di
->rxdpa
= di
->rxdpaorig
+ di
->rxdalign
;
539 di
->rxdalloc
= alloced
;
545 static bool _dma_alloc(struct dma_info
*di
, uint direction
)
547 return dma64_alloc(di
, direction
);
550 struct dma_pub
*dma_attach(char *name
, struct brcms_c_info
*wlc
,
551 uint txregbase
, uint rxregbase
, uint ntxd
, uint nrxd
,
552 uint rxbufsize
, int rxextheadroom
,
553 uint nrxpost
, uint rxoffset
)
555 struct si_pub
*sih
= wlc
->hw
->sih
;
556 struct bcma_device
*core
= wlc
->hw
->d11core
;
558 u8 rev
= core
->id
.rev
;
560 struct si_info
*sii
= container_of(sih
, struct si_info
, pub
);
562 /* allocate private info structure */
563 di
= kzalloc(sizeof(struct dma_info
), GFP_ATOMIC
);
568 ((bcma_aread32(core
, BCMA_IOST
) & SISF_DMA64
) == SISF_DMA64
);
570 /* init dma reg info */
572 di
->d64txregbase
= txregbase
;
573 di
->d64rxregbase
= rxregbase
;
576 * Default flags (which can be changed by the driver calling
577 * dma_ctrlflags before enable): For backwards compatibility
578 * both Rx Overflow Continue and Parity are DISABLED.
580 _dma_ctrlflags(di
, DMA_CTRL_ROC
| DMA_CTRL_PEN
, 0);
582 brcms_dbg_dma(di
->core
, "%s: %s flags 0x%x ntxd %d nrxd %d "
583 "rxbufsize %d rxextheadroom %d nrxpost %d rxoffset %d "
584 "txregbase %u rxregbase %u\n", name
, "DMA64",
585 di
->dma
.dmactrlflags
, ntxd
, nrxd
, rxbufsize
,
586 rxextheadroom
, nrxpost
, rxoffset
, txregbase
, rxregbase
);
588 /* make a private copy of our callers name */
589 strncpy(di
->name
, name
, MAXNAMEL
);
590 di
->name
[MAXNAMEL
- 1] = '\0';
592 di
->dmadev
= core
->dma_dev
;
595 di
->ntxd
= (u16
) ntxd
;
596 di
->nrxd
= (u16
) nrxd
;
598 /* the actual dma size doesn't include the extra headroom */
600 (rxextheadroom
== -1) ? BCMEXTRAHDROOM
: rxextheadroom
;
601 if (rxbufsize
> BCMEXTRAHDROOM
)
602 di
->rxbufsize
= (u16
) (rxbufsize
- di
->rxextrahdrroom
);
604 di
->rxbufsize
= (u16
) rxbufsize
;
606 di
->nrxpost
= (u16
) nrxpost
;
607 di
->rxoffset
= (u8
) rxoffset
;
610 * figure out the DMA physical address offset for dd and data
611 * PCI/PCIE: they map silicon backplace address to zero
612 * based memory, need offset
613 * Other bus: use zero SI_BUS BIGENDIAN kludge: use sdram
614 * swapped region for data buffer, not descriptor
617 di
->dataoffsetlow
= 0;
618 /* for pci bus, add offset */
619 if (sii
->icbus
->hosttype
== BCMA_HOSTTYPE_PCI
) {
620 /* add offset for pcie with DMA64 bus */
622 di
->ddoffsethigh
= SI_PCIE_DMA_H32
;
624 di
->dataoffsetlow
= di
->ddoffsetlow
;
625 di
->dataoffsethigh
= di
->ddoffsethigh
;
627 /* WAR64450 : DMACtl.Addr ext fields are not supported in SDIOD core. */
628 if ((core
->id
.id
== BCMA_CORE_SDIO_DEV
)
629 && ((rev
> 0) && (rev
<= 2)))
631 else if ((core
->id
.id
== BCMA_CORE_I2S
) &&
632 ((rev
== 0) || (rev
== 1)))
635 di
->addrext
= _dma_isaddrext(di
);
637 /* does the descriptor need to be aligned and if yes, on 4K/8K or not */
638 di
->aligndesc_4k
= _dma_descriptor_align(di
);
639 if (di
->aligndesc_4k
) {
640 di
->dmadesc_align
= D64RINGALIGN_BITS
;
641 if ((ntxd
< D64MAXDD
/ 2) && (nrxd
< D64MAXDD
/ 2))
642 /* for smaller dd table, HW relax alignment reqmnt */
643 di
->dmadesc_align
= D64RINGALIGN_BITS
- 1;
645 di
->dmadesc_align
= 4; /* 16 byte alignment */
648 brcms_dbg_dma(di
->core
, "DMA descriptor align_needed %d, align %d\n",
649 di
->aligndesc_4k
, di
->dmadesc_align
);
651 /* allocate tx packet pointer vector */
653 size
= ntxd
* sizeof(void *);
654 di
->txp
= kzalloc(size
, GFP_ATOMIC
);
659 /* allocate rx packet pointer vector */
661 size
= nrxd
* sizeof(void *);
662 di
->rxp
= kzalloc(size
, GFP_ATOMIC
);
668 * allocate transmit descriptor ring, only need ntxd descriptors
669 * but it must be aligned
672 if (!_dma_alloc(di
, DMA_TX
))
677 * allocate receive descriptor ring, only need nrxd descriptors
678 * but it must be aligned
681 if (!_dma_alloc(di
, DMA_RX
))
685 if ((di
->ddoffsetlow
!= 0) && !di
->addrext
) {
686 if (di
->txdpa
> SI_PCI_DMA_SZ
) {
687 brcms_dbg_dma(di
->core
,
688 "%s: txdpa 0x%x: addrext not supported\n",
689 di
->name
, (u32
)di
->txdpa
);
692 if (di
->rxdpa
> SI_PCI_DMA_SZ
) {
693 brcms_dbg_dma(di
->core
,
694 "%s: rxdpa 0x%x: addrext not supported\n",
695 di
->name
, (u32
)di
->rxdpa
);
700 /* Initialize AMPDU session */
701 brcms_c_ampdu_reset_session(&di
->ampdu_session
, wlc
);
703 brcms_dbg_dma(di
->core
,
704 "ddoffsetlow 0x%x ddoffsethigh 0x%x dataoffsetlow 0x%x dataoffsethigh 0x%x addrext %d\n",
705 di
->ddoffsetlow
, di
->ddoffsethigh
,
706 di
->dataoffsetlow
, di
->dataoffsethigh
,
709 return (struct dma_pub
*) di
;
712 dma_detach((struct dma_pub
*)di
);
717 dma64_dd_upd(struct dma_info
*di
, struct dma64desc
*ddring
,
718 dma_addr_t pa
, uint outidx
, u32
*flags
, u32 bufcount
)
720 u32 ctrl2
= bufcount
& D64_CTRL2_BC_MASK
;
722 /* PCI bus with big(>1G) physical address, use address extension */
723 if ((di
->dataoffsetlow
== 0) || !(pa
& PCI32ADDR_HIGH
)) {
724 ddring
[outidx
].addrlow
= cpu_to_le32(pa
+ di
->dataoffsetlow
);
725 ddring
[outidx
].addrhigh
= cpu_to_le32(di
->dataoffsethigh
);
726 ddring
[outidx
].ctrl1
= cpu_to_le32(*flags
);
727 ddring
[outidx
].ctrl2
= cpu_to_le32(ctrl2
);
729 /* address extension for 32-bit PCI */
732 ae
= (pa
& PCI32ADDR_HIGH
) >> PCI32ADDR_HIGH_SHIFT
;
733 pa
&= ~PCI32ADDR_HIGH
;
735 ctrl2
|= (ae
<< D64_CTRL2_AE_SHIFT
) & D64_CTRL2_AE
;
736 ddring
[outidx
].addrlow
= cpu_to_le32(pa
+ di
->dataoffsetlow
);
737 ddring
[outidx
].addrhigh
= cpu_to_le32(di
->dataoffsethigh
);
738 ddring
[outidx
].ctrl1
= cpu_to_le32(*flags
);
739 ddring
[outidx
].ctrl2
= cpu_to_le32(ctrl2
);
741 if (di
->dma
.dmactrlflags
& DMA_CTRL_PEN
) {
742 if (dma64_dd_parity(&ddring
[outidx
]))
743 ddring
[outidx
].ctrl2
=
744 cpu_to_le32(ctrl2
| D64_CTRL2_PARITY
);
748 /* !! may be called with core in reset */
749 void dma_detach(struct dma_pub
*pub
)
751 struct dma_info
*di
= (struct dma_info
*)pub
;
753 brcms_dbg_dma(di
->core
, "%s:\n", di
->name
);
755 /* free dma descriptor rings */
757 dma_free_coherent(di
->dmadev
, di
->txdalloc
,
758 ((s8
*)di
->txd64
- di
->txdalign
),
761 dma_free_coherent(di
->dmadev
, di
->rxdalloc
,
762 ((s8
*)di
->rxd64
- di
->rxdalign
),
765 /* free packet pointer vectors */
769 /* free our private info structure */
774 /* initialize descriptor table base address */
776 _dma_ddtable_init(struct dma_info
*di
, uint direction
, dma_addr_t pa
)
778 if (!di
->aligndesc_4k
) {
779 if (direction
== DMA_TX
)
785 if ((di
->ddoffsetlow
== 0)
786 || !(pa
& PCI32ADDR_HIGH
)) {
787 if (direction
== DMA_TX
) {
788 bcma_write32(di
->core
, DMA64TXREGOFFS(di
, addrlow
),
789 pa
+ di
->ddoffsetlow
);
790 bcma_write32(di
->core
, DMA64TXREGOFFS(di
, addrhigh
),
793 bcma_write32(di
->core
, DMA64RXREGOFFS(di
, addrlow
),
794 pa
+ di
->ddoffsetlow
);
795 bcma_write32(di
->core
, DMA64RXREGOFFS(di
, addrhigh
),
799 /* DMA64 32bits address extension */
802 /* shift the high bit(s) from pa to ae */
803 ae
= (pa
& PCI32ADDR_HIGH
) >> PCI32ADDR_HIGH_SHIFT
;
804 pa
&= ~PCI32ADDR_HIGH
;
806 if (direction
== DMA_TX
) {
807 bcma_write32(di
->core
, DMA64TXREGOFFS(di
, addrlow
),
808 pa
+ di
->ddoffsetlow
);
809 bcma_write32(di
->core
, DMA64TXREGOFFS(di
, addrhigh
),
811 bcma_maskset32(di
->core
, DMA64TXREGOFFS(di
, control
),
812 D64_XC_AE
, (ae
<< D64_XC_AE_SHIFT
));
814 bcma_write32(di
->core
, DMA64RXREGOFFS(di
, addrlow
),
815 pa
+ di
->ddoffsetlow
);
816 bcma_write32(di
->core
, DMA64RXREGOFFS(di
, addrhigh
),
818 bcma_maskset32(di
->core
, DMA64RXREGOFFS(di
, control
),
819 D64_RC_AE
, (ae
<< D64_RC_AE_SHIFT
));
824 static void _dma_rxenable(struct dma_info
*di
)
826 uint dmactrlflags
= di
->dma
.dmactrlflags
;
829 brcms_dbg_dma(di
->core
, "%s:\n", di
->name
);
831 control
= D64_RC_RE
| (bcma_read32(di
->core
,
832 DMA64RXREGOFFS(di
, control
)) &
835 if ((dmactrlflags
& DMA_CTRL_PEN
) == 0)
836 control
|= D64_RC_PD
;
838 if (dmactrlflags
& DMA_CTRL_ROC
)
839 control
|= D64_RC_OC
;
841 bcma_write32(di
->core
, DMA64RXREGOFFS(di
, control
),
842 ((di
->rxoffset
<< D64_RC_RO_SHIFT
) | control
));
845 void dma_rxinit(struct dma_pub
*pub
)
847 struct dma_info
*di
= (struct dma_info
*)pub
;
849 brcms_dbg_dma(di
->core
, "%s:\n", di
->name
);
854 di
->rxin
= di
->rxout
= 0;
856 /* clear rx descriptor ring */
857 memset(di
->rxd64
, '\0', di
->nrxd
* sizeof(struct dma64desc
));
859 /* DMA engine with out alignment requirement requires table to be inited
860 * before enabling the engine
862 if (!di
->aligndesc_4k
)
863 _dma_ddtable_init(di
, DMA_RX
, di
->rxdpa
);
867 if (di
->aligndesc_4k
)
868 _dma_ddtable_init(di
, DMA_RX
, di
->rxdpa
);
871 static struct sk_buff
*dma64_getnextrxp(struct dma_info
*di
, bool forceall
)
879 /* return if no packets posted */
884 B2I(((bcma_read32(di
->core
,
885 DMA64RXREGOFFS(di
, status0
)) & D64_RS0_CD_MASK
) -
886 di
->rcvptrbase
) & D64_RS0_CD_MASK
, struct dma64desc
);
888 /* ignore curr if forceall */
889 if (!forceall
&& (i
== curr
))
892 /* get the packet pointer that corresponds to the rx descriptor */
896 pa
= le32_to_cpu(di
->rxd64
[i
].addrlow
) - di
->dataoffsetlow
;
898 /* clear this packet from the descriptor ring */
899 dma_unmap_single(di
->dmadev
, pa
, di
->rxbufsize
, DMA_FROM_DEVICE
);
901 di
->rxd64
[i
].addrlow
= cpu_to_le32(0xdeadbeef);
902 di
->rxd64
[i
].addrhigh
= cpu_to_le32(0xdeadbeef);
904 di
->rxin
= nextrxd(di
, i
);
909 static struct sk_buff
*_dma_getnextrxp(struct dma_info
*di
, bool forceall
)
914 return dma64_getnextrxp(di
, forceall
);
918 * !! rx entry routine
919 * returns the number packages in the next frame, or 0 if there are no more
920 * if DMA_CTRL_RXMULTI is defined, DMA scattering(multiple buffers) is
921 * supported with pkts chain
922 * otherwise, it's treated as giant pkt and will be tossed.
923 * The DMA scattering starts with normal DMA header, followed by first
924 * buffer data. After it reaches the max size of buffer, the data continues
925 * in next DMA descriptor buffer WITHOUT DMA header
927 int dma_rx(struct dma_pub
*pub
, struct sk_buff_head
*skb_list
)
929 struct dma_info
*di
= (struct dma_info
*)pub
;
930 struct sk_buff_head dma_frames
;
931 struct sk_buff
*p
, *next
;
937 skb_queue_head_init(&dma_frames
);
939 p
= _dma_getnextrxp(di
, false);
943 len
= le16_to_cpu(*(__le16
*) (p
->data
));
944 brcms_dbg_dma(di
->core
, "%s: dma_rx len %d\n", di
->name
, len
);
945 dma_spin_for_len(len
, p
);
947 /* set actual length */
948 pkt_len
= min((di
->rxoffset
+ len
), di
->rxbufsize
);
949 __skb_trim(p
, pkt_len
);
950 skb_queue_tail(&dma_frames
, p
);
951 resid
= len
- (di
->rxbufsize
- di
->rxoffset
);
953 /* check for single or multi-buffer rx */
955 while ((resid
> 0) && (p
= _dma_getnextrxp(di
, false))) {
956 pkt_len
= min_t(uint
, resid
, di
->rxbufsize
);
957 __skb_trim(p
, pkt_len
);
958 skb_queue_tail(&dma_frames
, p
);
959 resid
-= di
->rxbufsize
;
967 B2I(((bcma_read32(di
->core
,
968 DMA64RXREGOFFS(di
, status0
)) &
969 D64_RS0_CD_MASK
) - di
->rcvptrbase
) &
970 D64_RS0_CD_MASK
, struct dma64desc
);
971 brcms_dbg_dma(di
->core
,
972 "rxin %d rxout %d, hw_curr %d\n",
973 di
->rxin
, di
->rxout
, cur
);
977 if ((di
->dma
.dmactrlflags
& DMA_CTRL_RXMULTI
) == 0) {
978 brcms_dbg_dma(di
->core
, "%s: bad frame length (%d)\n",
980 skb_queue_walk_safe(&dma_frames
, p
, next
) {
981 skb_unlink(p
, &dma_frames
);
982 brcmu_pkt_buf_free_skb(p
);
990 skb_queue_splice_tail(&dma_frames
, skb_list
);
994 static bool dma64_rxidle(struct dma_info
*di
)
996 brcms_dbg_dma(di
->core
, "%s:\n", di
->name
);
1001 return ((bcma_read32(di
->core
,
1002 DMA64RXREGOFFS(di
, status0
)) & D64_RS0_CD_MASK
) ==
1003 (bcma_read32(di
->core
, DMA64RXREGOFFS(di
, ptr
)) &
1007 static bool dma64_txidle(struct dma_info
*di
)
1012 return ((bcma_read32(di
->core
,
1013 DMA64TXREGOFFS(di
, status0
)) & D64_XS0_CD_MASK
) ==
1014 (bcma_read32(di
->core
, DMA64TXREGOFFS(di
, ptr
)) &
1019 * post receive buffers
1020 * return false is refill failed completely and ring is empty this will stall
1021 * the rx dma and user might want to call rxfill again asap. This unlikely
1022 * happens on memory-rich NIC, but often on memory-constrained dongle
1024 bool dma_rxfill(struct dma_pub
*pub
)
1026 struct dma_info
*di
= (struct dma_info
*)pub
;
1033 uint extra_offset
= 0;
1039 * Determine how many receive buffers we're lacking
1040 * from the full complement, allocate, initialize,
1041 * and post them, then update the chip rx lastdscr.
1047 n
= di
->nrxpost
- nrxdactive(di
, rxin
, rxout
);
1049 brcms_dbg_dma(di
->core
, "%s: post %d\n", di
->name
, n
);
1051 if (di
->rxbufsize
> BCMEXTRAHDROOM
)
1052 extra_offset
= di
->rxextrahdrroom
;
1054 for (i
= 0; i
< n
; i
++) {
1056 * the di->rxbufsize doesn't include the extra headroom,
1057 * we need to add it to the size to be allocated
1059 p
= brcmu_pkt_buf_get_skb(di
->rxbufsize
+ extra_offset
);
1062 brcms_dbg_dma(di
->core
, "%s: out of rxbufs\n",
1064 if (i
== 0 && dma64_rxidle(di
)) {
1065 brcms_dbg_dma(di
->core
, "%s: ring is empty !\n",
1072 /* reserve an extra headroom, if applicable */
1074 skb_pull(p
, extra_offset
);
1076 /* Do a cached write instead of uncached write since DMA_MAP
1077 * will flush the cache.
1079 *(u32
*) (p
->data
) = 0;
1081 pa
= dma_map_single(di
->dmadev
, p
->data
, di
->rxbufsize
,
1084 /* save the free packet pointer */
1087 /* reset flags for each descriptor */
1089 if (rxout
== (di
->nrxd
- 1))
1090 flags
= D64_CTRL1_EOT
;
1092 dma64_dd_upd(di
, di
->rxd64
, pa
, rxout
, &flags
,
1094 rxout
= nextrxd(di
, rxout
);
1099 /* update the chip lastdscr pointer */
1100 bcma_write32(di
->core
, DMA64RXREGOFFS(di
, ptr
),
1101 di
->rcvptrbase
+ I2B(rxout
, struct dma64desc
));
1106 void dma_rxreclaim(struct dma_pub
*pub
)
1108 struct dma_info
*di
= (struct dma_info
*)pub
;
1111 brcms_dbg_dma(di
->core
, "%s:\n", di
->name
);
1113 while ((p
= _dma_getnextrxp(di
, true)))
1114 brcmu_pkt_buf_free_skb(p
);
1117 void dma_counterreset(struct dma_pub
*pub
)
1119 /* reset all software counters */
1125 /* get the address of the var in order to change later */
1126 unsigned long dma_getvar(struct dma_pub
*pub
, const char *name
)
1128 struct dma_info
*di
= (struct dma_info
*)pub
;
1130 if (!strcmp(name
, "&txavail"))
1131 return (unsigned long)&(di
->dma
.txavail
);
1135 /* 64-bit DMA functions */
1137 void dma_txinit(struct dma_pub
*pub
)
1139 struct dma_info
*di
= (struct dma_info
*)pub
;
1140 u32 control
= D64_XC_XE
;
1142 brcms_dbg_dma(di
->core
, "%s:\n", di
->name
);
1147 di
->txin
= di
->txout
= 0;
1148 di
->dma
.txavail
= di
->ntxd
- 1;
1150 /* clear tx descriptor ring */
1151 memset(di
->txd64
, '\0', (di
->ntxd
* sizeof(struct dma64desc
)));
1153 /* DMA engine with out alignment requirement requires table to be inited
1154 * before enabling the engine
1156 if (!di
->aligndesc_4k
)
1157 _dma_ddtable_init(di
, DMA_TX
, di
->txdpa
);
1159 if ((di
->dma
.dmactrlflags
& DMA_CTRL_PEN
) == 0)
1160 control
|= D64_XC_PD
;
1161 bcma_set32(di
->core
, DMA64TXREGOFFS(di
, control
), control
);
1163 /* DMA engine with alignment requirement requires table to be inited
1164 * before enabling the engine
1166 if (di
->aligndesc_4k
)
1167 _dma_ddtable_init(di
, DMA_TX
, di
->txdpa
);
1170 void dma_txsuspend(struct dma_pub
*pub
)
1172 struct dma_info
*di
= (struct dma_info
*)pub
;
1174 brcms_dbg_dma(di
->core
, "%s:\n", di
->name
);
1179 bcma_set32(di
->core
, DMA64TXREGOFFS(di
, control
), D64_XC_SE
);
1182 void dma_txresume(struct dma_pub
*pub
)
1184 struct dma_info
*di
= (struct dma_info
*)pub
;
1186 brcms_dbg_dma(di
->core
, "%s:\n", di
->name
);
1191 bcma_mask32(di
->core
, DMA64TXREGOFFS(di
, control
), ~D64_XC_SE
);
1194 bool dma_txsuspended(struct dma_pub
*pub
)
1196 struct dma_info
*di
= (struct dma_info
*)pub
;
1198 return (di
->ntxd
== 0) ||
1199 ((bcma_read32(di
->core
,
1200 DMA64TXREGOFFS(di
, control
)) & D64_XC_SE
) ==
1204 void dma_txreclaim(struct dma_pub
*pub
, enum txd_range range
)
1206 struct dma_info
*di
= (struct dma_info
*)pub
;
1209 brcms_dbg_dma(di
->core
, "%s: %s\n",
1211 range
== DMA_RANGE_ALL
? "all" :
1212 range
== DMA_RANGE_TRANSMITTED
? "transmitted" :
1215 if (di
->txin
== di
->txout
)
1218 while ((p
= dma_getnexttxp(pub
, range
))) {
1219 /* For unframed data, we don't have any packets to free */
1220 if (!(di
->dma
.dmactrlflags
& DMA_CTRL_UNFRAMED
))
1221 brcmu_pkt_buf_free_skb(p
);
1225 bool dma_txreset(struct dma_pub
*pub
)
1227 struct dma_info
*di
= (struct dma_info
*)pub
;
1233 /* suspend tx DMA first */
1234 bcma_write32(di
->core
, DMA64TXREGOFFS(di
, control
), D64_XC_SE
);
1236 (bcma_read32(di
->core
, DMA64TXREGOFFS(di
, status0
)) &
1237 D64_XS0_XS_MASK
)) != D64_XS0_XS_DISABLED
) &&
1238 (status
!= D64_XS0_XS_IDLE
) && (status
!= D64_XS0_XS_STOPPED
),
1241 bcma_write32(di
->core
, DMA64TXREGOFFS(di
, control
), 0);
1243 (bcma_read32(di
->core
, DMA64TXREGOFFS(di
, status0
)) &
1244 D64_XS0_XS_MASK
)) != D64_XS0_XS_DISABLED
), 10000);
1246 /* wait for the last transaction to complete */
1249 return status
== D64_XS0_XS_DISABLED
;
1252 bool dma_rxreset(struct dma_pub
*pub
)
1254 struct dma_info
*di
= (struct dma_info
*)pub
;
1260 bcma_write32(di
->core
, DMA64RXREGOFFS(di
, control
), 0);
1262 (bcma_read32(di
->core
, DMA64RXREGOFFS(di
, status0
)) &
1263 D64_RS0_RS_MASK
)) != D64_RS0_RS_DISABLED
), 10000);
1265 return status
== D64_RS0_RS_DISABLED
;
1268 static void dma_txenq(struct dma_info
*di
, struct sk_buff
*p
)
1270 unsigned char *data
;
1278 if (WARN_ON(nexttxd(di
, txout
) == di
->txin
))
1282 * obtain and initialize transmit descriptor entry.
1287 /* get physical address of buffer start */
1288 pa
= dma_map_single(di
->dmadev
, data
, len
, DMA_TO_DEVICE
);
1290 /* With a DMA segment list, Descriptor table is filled
1291 * using the segment list instead of looping over
1292 * buffers in multi-chain DMA. Therefore, EOF for SGLIST
1293 * is when end of segment list is reached.
1295 flags
= D64_CTRL1_SOF
| D64_CTRL1_IOC
| D64_CTRL1_EOF
;
1296 if (txout
== (di
->ntxd
- 1))
1297 flags
|= D64_CTRL1_EOT
;
1299 dma64_dd_upd(di
, di
->txd64
, pa
, txout
, &flags
, len
);
1301 txout
= nexttxd(di
, txout
);
1303 /* save the packet */
1304 di
->txp
[prevtxd(di
, txout
)] = p
;
1306 /* bump the tx descriptor index */
1310 static void ampdu_finalize(struct dma_info
*di
)
1312 struct brcms_ampdu_session
*session
= &di
->ampdu_session
;
1315 trace_brcms_ampdu_session(&session
->wlc
->hw
->d11core
->dev
,
1316 session
->max_ampdu_len
,
1317 session
->max_ampdu_frames
,
1319 skb_queue_len(&session
->skb_list
),
1322 if (WARN_ON(skb_queue_empty(&session
->skb_list
)))
1325 brcms_c_ampdu_finalize(session
);
1327 while (!skb_queue_empty(&session
->skb_list
)) {
1328 p
= skb_dequeue(&session
->skb_list
);
1332 bcma_write32(di
->core
, DMA64TXREGOFFS(di
, ptr
),
1333 di
->xmtptrbase
+ I2B(di
->txout
, struct dma64desc
));
1334 brcms_c_ampdu_reset_session(session
, session
->wlc
);
1337 static void prep_ampdu_frame(struct dma_info
*di
, struct sk_buff
*p
)
1339 struct brcms_ampdu_session
*session
= &di
->ampdu_session
;
1342 ret
= brcms_c_ampdu_add_frame(session
, p
);
1343 if (ret
== -ENOSPC
) {
1345 * AMPDU cannot accomodate this frame. Close out the in-
1346 * progress AMPDU session and start a new one.
1349 ret
= brcms_c_ampdu_add_frame(session
, p
);
1355 /* Update count of available tx descriptors based on current DMA state */
1356 static void dma_update_txavail(struct dma_info
*di
)
1359 * Available space is number of descriptors less the number of
1360 * active descriptors and the number of queued AMPDU frames.
1362 di
->dma
.txavail
= di
->ntxd
- ntxdactive(di
, di
->txin
, di
->txout
) -
1363 skb_queue_len(&di
->ampdu_session
.skb_list
) - 1;
1367 * !! tx entry routine
1368 * WARNING: call must check the return value for error.
1369 * the error(toss frames) could be fatal and cause many subsequent hard
1372 int dma_txfast(struct brcms_c_info
*wlc
, struct dma_pub
*pub
,
1375 struct dma_info
*di
= (struct dma_info
*)pub
;
1376 struct brcms_ampdu_session
*session
= &di
->ampdu_session
;
1377 struct ieee80211_tx_info
*tx_info
;
1380 /* no use to transmit a zero length packet */
1384 /* return nonzero if out of tx descriptors */
1385 if (di
->dma
.txavail
== 0 || nexttxd(di
, di
->txout
) == di
->txin
)
1388 tx_info
= IEEE80211_SKB_CB(p
);
1389 is_ampdu
= tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
;
1391 prep_ampdu_frame(di
, p
);
1395 /* tx flow control */
1396 dma_update_txavail(di
);
1401 * Start sending data if we've got a full AMPDU, there's
1402 * no more space in the DMA ring, or the ring isn't
1403 * currently transmitting.
1405 if (skb_queue_len(&session
->skb_list
) == session
->max_ampdu_frames
||
1406 di
->dma
.txavail
== 0 || dma64_txidle(di
))
1409 bcma_write32(di
->core
, DMA64TXREGOFFS(di
, ptr
),
1410 di
->xmtptrbase
+ I2B(di
->txout
, struct dma64desc
));
1416 brcms_dbg_dma(di
->core
, "%s: out of txds !!!\n", di
->name
);
1417 brcmu_pkt_buf_free_skb(p
);
1418 di
->dma
.txavail
= 0;
1423 void dma_txflush(struct dma_pub
*pub
)
1425 struct dma_info
*di
= (struct dma_info
*)pub
;
1426 struct brcms_ampdu_session
*session
= &di
->ampdu_session
;
1428 if (!skb_queue_empty(&session
->skb_list
))
1432 int dma_txpending(struct dma_pub
*pub
)
1434 struct dma_info
*di
= (struct dma_info
*)pub
;
1435 return ntxdactive(di
, di
->txin
, di
->txout
);
1439 * If we have an active AMPDU session and are not transmitting,
1440 * this function will force tx to start.
1442 void dma_kick_tx(struct dma_pub
*pub
)
1444 struct dma_info
*di
= (struct dma_info
*)pub
;
1445 struct brcms_ampdu_session
*session
= &di
->ampdu_session
;
1447 if (!skb_queue_empty(&session
->skb_list
) && dma64_txidle(di
))
1452 * Reclaim next completed txd (txds if using chained buffers) in the range
1453 * specified and return associated packet.
1454 * If range is DMA_RANGE_TRANSMITTED, reclaim descriptors that have be
1455 * transmitted as noted by the hardware "CurrDescr" pointer.
1456 * If range is DMA_RANGE_TRANSFERED, reclaim descriptors that have be
1457 * transferred by the DMA as noted by the hardware "ActiveDescr" pointer.
1458 * If range is DMA_RANGE_ALL, reclaim all txd(s) posted to the ring and
1459 * return associated packet regardless of the value of hardware pointers.
1461 struct sk_buff
*dma_getnexttxp(struct dma_pub
*pub
, enum txd_range range
)
1463 struct dma_info
*di
= (struct dma_info
*)pub
;
1466 struct sk_buff
*txp
;
1468 brcms_dbg_dma(di
->core
, "%s: %s\n",
1470 range
== DMA_RANGE_ALL
? "all" :
1471 range
== DMA_RANGE_TRANSMITTED
? "transmitted" :
1480 if (range
== DMA_RANGE_ALL
)
1483 end
= (u16
) (B2I(((bcma_read32(di
->core
,
1484 DMA64TXREGOFFS(di
, status0
)) &
1485 D64_XS0_CD_MASK
) - di
->xmtptrbase
) &
1486 D64_XS0_CD_MASK
, struct dma64desc
));
1488 if (range
== DMA_RANGE_TRANSFERED
) {
1490 (u16
)(bcma_read32(di
->core
,
1491 DMA64TXREGOFFS(di
, status1
)) &
1494 (active_desc
- di
->xmtptrbase
) & D64_XS0_CD_MASK
;
1495 active_desc
= B2I(active_desc
, struct dma64desc
);
1496 if (end
!= active_desc
)
1497 end
= prevtxd(di
, active_desc
);
1501 if ((start
== 0) && (end
> di
->txout
))
1504 for (i
= start
; i
!= end
&& !txp
; i
= nexttxd(di
, i
)) {
1508 pa
= le32_to_cpu(di
->txd64
[i
].addrlow
) - di
->dataoffsetlow
;
1511 (le32_to_cpu(di
->txd64
[i
].ctrl2
) &
1514 di
->txd64
[i
].addrlow
= cpu_to_le32(0xdeadbeef);
1515 di
->txd64
[i
].addrhigh
= cpu_to_le32(0xdeadbeef);
1520 dma_unmap_single(di
->dmadev
, pa
, size
, DMA_TO_DEVICE
);
1525 /* tx flow control */
1526 dma_update_txavail(di
);
1531 brcms_dbg_dma(di
->core
, "bogus curr: start %d end %d txout %d\n",
1532 start
, end
, di
->txout
);
1537 * Mac80211 initiated actions sometimes require packets in the DMA queue to be
1538 * modified. The modified portion of the packet is not under control of the DMA
1539 * engine. This function calls a caller-supplied function for each packet in
1540 * the caller specified dma chain.
1542 void dma_walk_packets(struct dma_pub
*dmah
, void (*callback_fnc
)
1543 (void *pkt
, void *arg_a
), void *arg_a
)
1545 struct dma_info
*di
= (struct dma_info
*) dmah
;
1547 uint end
= di
->txout
;
1548 struct sk_buff
*skb
;
1549 struct ieee80211_tx_info
*tx_info
;
1554 tx_info
= (struct ieee80211_tx_info
*)skb
->cb
;
1555 (callback_fnc
)(tx_info
, arg_a
);