2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/string.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/amba/bus.h>
25 #include <linux/amba/pl330.h>
26 #include <linux/scatterlist.h>
28 #include <linux/of_dma.h>
29 #include <linux/err.h>
31 #include "dmaengine.h"
32 #define PL330_MAX_CHAN 8
33 #define PL330_MAX_IRQS 32
34 #define PL330_MAX_PERI 32
36 enum pl330_srccachectrl
{
37 SCCTRL0
, /* Noncacheable and nonbufferable */
38 SCCTRL1
, /* Bufferable only */
39 SCCTRL2
, /* Cacheable, but do not allocate */
40 SCCTRL3
, /* Cacheable and bufferable, but do not allocate */
43 SCCTRL6
, /* Cacheable write-through, allocate on reads only */
44 SCCTRL7
, /* Cacheable write-back, allocate on reads only */
47 enum pl330_dstcachectrl
{
48 DCCTRL0
, /* Noncacheable and nonbufferable */
49 DCCTRL1
, /* Bufferable only */
50 DCCTRL2
, /* Cacheable, but do not allocate */
51 DCCTRL3
, /* Cacheable and bufferable, but do not allocate */
52 DINVALID1
, /* AWCACHE = 0x1000 */
54 DCCTRL6
, /* Cacheable write-through, allocate on writes only */
55 DCCTRL7
, /* Cacheable write-back, allocate on writes only */
73 /* Register and Bit field Definitions */
75 #define DS_ST_STOP 0x0
76 #define DS_ST_EXEC 0x1
77 #define DS_ST_CMISS 0x2
78 #define DS_ST_UPDTPC 0x3
80 #define DS_ST_ATBRR 0x5
81 #define DS_ST_QBUSY 0x6
83 #define DS_ST_KILL 0x8
84 #define DS_ST_CMPLT 0x9
85 #define DS_ST_FLTCMP 0xe
86 #define DS_ST_FAULT 0xf
91 #define INTSTATUS 0x28
98 #define FTC(n) (_FTC + (n)*0x4)
101 #define CS(n) (_CS + (n)*0x8)
102 #define CS_CNS (1 << 21)
105 #define CPC(n) (_CPC + (n)*0x8)
108 #define SA(n) (_SA + (n)*0x20)
111 #define DA(n) (_DA + (n)*0x20)
114 #define CC(n) (_CC + (n)*0x20)
116 #define CC_SRCINC (1 << 0)
117 #define CC_DSTINC (1 << 14)
118 #define CC_SRCPRI (1 << 8)
119 #define CC_DSTPRI (1 << 22)
120 #define CC_SRCNS (1 << 9)
121 #define CC_DSTNS (1 << 23)
122 #define CC_SRCIA (1 << 10)
123 #define CC_DSTIA (1 << 24)
124 #define CC_SRCBRSTLEN_SHFT 4
125 #define CC_DSTBRSTLEN_SHFT 18
126 #define CC_SRCBRSTSIZE_SHFT 1
127 #define CC_DSTBRSTSIZE_SHFT 15
128 #define CC_SRCCCTRL_SHFT 11
129 #define CC_SRCCCTRL_MASK 0x7
130 #define CC_DSTCCTRL_SHFT 25
131 #define CC_DRCCCTRL_MASK 0x7
132 #define CC_SWAP_SHFT 28
135 #define LC0(n) (_LC0 + (n)*0x20)
138 #define LC1(n) (_LC1 + (n)*0x20)
140 #define DBGSTATUS 0xd00
141 #define DBG_BUSY (1 << 0)
144 #define DBGINST0 0xd08
145 #define DBGINST1 0xd0c
154 #define PERIPH_ID 0xfe0
155 #define PERIPH_REV_SHIFT 20
156 #define PERIPH_REV_MASK 0xf
157 #define PERIPH_REV_R0P0 0
158 #define PERIPH_REV_R1P0 1
159 #define PERIPH_REV_R1P1 2
161 #define CR0_PERIPH_REQ_SET (1 << 0)
162 #define CR0_BOOT_EN_SET (1 << 1)
163 #define CR0_BOOT_MAN_NS (1 << 2)
164 #define CR0_NUM_CHANS_SHIFT 4
165 #define CR0_NUM_CHANS_MASK 0x7
166 #define CR0_NUM_PERIPH_SHIFT 12
167 #define CR0_NUM_PERIPH_MASK 0x1f
168 #define CR0_NUM_EVENTS_SHIFT 17
169 #define CR0_NUM_EVENTS_MASK 0x1f
171 #define CR1_ICACHE_LEN_SHIFT 0
172 #define CR1_ICACHE_LEN_MASK 0x7
173 #define CR1_NUM_ICACHELINES_SHIFT 4
174 #define CR1_NUM_ICACHELINES_MASK 0xf
176 #define CRD_DATA_WIDTH_SHIFT 0
177 #define CRD_DATA_WIDTH_MASK 0x7
178 #define CRD_WR_CAP_SHIFT 4
179 #define CRD_WR_CAP_MASK 0x7
180 #define CRD_WR_Q_DEP_SHIFT 8
181 #define CRD_WR_Q_DEP_MASK 0xf
182 #define CRD_RD_CAP_SHIFT 12
183 #define CRD_RD_CAP_MASK 0x7
184 #define CRD_RD_Q_DEP_SHIFT 16
185 #define CRD_RD_Q_DEP_MASK 0xf
186 #define CRD_DATA_BUFF_SHIFT 20
187 #define CRD_DATA_BUFF_MASK 0x3ff
190 #define DESIGNER 0x41
192 #define INTEG_CFG 0x0
193 #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
195 #define PL330_STATE_STOPPED (1 << 0)
196 #define PL330_STATE_EXECUTING (1 << 1)
197 #define PL330_STATE_WFE (1 << 2)
198 #define PL330_STATE_FAULTING (1 << 3)
199 #define PL330_STATE_COMPLETING (1 << 4)
200 #define PL330_STATE_WFP (1 << 5)
201 #define PL330_STATE_KILLING (1 << 6)
202 #define PL330_STATE_FAULT_COMPLETING (1 << 7)
203 #define PL330_STATE_CACHEMISS (1 << 8)
204 #define PL330_STATE_UPDTPC (1 << 9)
205 #define PL330_STATE_ATBARRIER (1 << 10)
206 #define PL330_STATE_QUEUEBUSY (1 << 11)
207 #define PL330_STATE_INVALID (1 << 15)
209 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
210 | PL330_STATE_WFE | PL330_STATE_FAULTING)
212 #define CMD_DMAADDH 0x54
213 #define CMD_DMAEND 0x00
214 #define CMD_DMAFLUSHP 0x35
215 #define CMD_DMAGO 0xa0
216 #define CMD_DMALD 0x04
217 #define CMD_DMALDP 0x25
218 #define CMD_DMALP 0x20
219 #define CMD_DMALPEND 0x28
220 #define CMD_DMAKILL 0x01
221 #define CMD_DMAMOV 0xbc
222 #define CMD_DMANOP 0x18
223 #define CMD_DMARMB 0x12
224 #define CMD_DMASEV 0x34
225 #define CMD_DMAST 0x08
226 #define CMD_DMASTP 0x29
227 #define CMD_DMASTZ 0x0c
228 #define CMD_DMAWFE 0x36
229 #define CMD_DMAWFP 0x30
230 #define CMD_DMAWMB 0x13
234 #define SZ_DMAFLUSHP 2
238 #define SZ_DMALPEND 2
252 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
253 #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
255 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
256 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
259 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
260 * at 1byte/burst for P<->M and M<->M respectively.
261 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
262 * should be enough for P<->M and M<->M respectively.
264 #define MCODE_BUFF_PER_REQ 256
266 /* If the _pl330_req is available to the client */
267 #define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND)
269 /* Use this _only_ to wait on transient states */
270 #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
272 #ifdef PL330_DEBUG_MCGEN
273 static unsigned cmd_line
;
274 #define PL330_DBGCMD_DUMP(off, x...) do { \
275 printk("%x:", cmd_line); \
279 #define PL330_DBGMC_START(addr) (cmd_line = addr)
281 #define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
282 #define PL330_DBGMC_START(addr) do {} while (0)
285 /* The number of default descriptors */
287 #define NR_DEFAULT_DESC 16
289 /* Populated by the PL330 core driver for DMA API driver's info */
290 struct pl330_config
{
292 #define DMAC_MODE_NS (1 << 0)
294 unsigned int data_bus_width
:10; /* In number of bits */
295 unsigned int data_buf_dep
:10;
296 unsigned int num_chan
:4;
297 unsigned int num_peri
:6;
299 unsigned int num_events
:6;
303 /* Handle to the DMAC provided to the PL330 core */
307 /* Size of MicroCode buffers for each channel. */
309 /* ioremap'ed address of PL330 registers. */
311 /* Client can freely use it. */
313 /* PL330 core data, Client must not touch it. */
315 /* Populated by the PL330 core driver during pl330_add */
316 struct pl330_config pcfg
;
318 * If the DMAC has some reset mechanism, then the
319 * client may want to provide pointer to the method.
321 void (*dmac_reset
)(struct pl330_info
*pi
);
325 * Request Configuration.
326 * The PL330 core does not modify this and uses the last
327 * working configuration if the request doesn't provide any.
329 * The Client may want to provide this info only for the
330 * first request and a request with new settings.
332 struct pl330_reqcfg
{
333 /* Address Incrementing */
338 * For now, the SRC & DST protection levels
339 * and burst size/length are assumed same.
345 unsigned brst_size
:3; /* in power of 2 */
347 enum pl330_dstcachectrl dcctl
;
348 enum pl330_srccachectrl scctl
;
349 enum pl330_byteswap swap
;
350 struct pl330_config
*pcfg
;
354 * One cycle of DMAC operation.
355 * There may be more than one xfer in a request.
363 * Pointer to next xfer in the list.
364 * The last xfer in the req must point to NULL.
366 struct pl330_xfer
*next
;
369 /* The xfer callbacks are made with one of these arguments. */
371 /* The all xfers in the request were success. */
373 /* If req aborted due to global error. */
375 /* If req failed due to problem with Channel. */
379 /* A request defining Scatter-Gather List ending with NULL xfer. */
381 enum pl330_reqtype rqtype
;
382 /* Index of peripheral for the xfer. */
384 /* Unique token for this xfer, set by the client. */
386 /* Callback to be called after xfer. */
387 void (*xfer_cb
)(void *token
, enum pl330_op_err err
);
388 /* If NULL, req will be done at last set parameters. */
389 struct pl330_reqcfg
*cfg
;
390 /* Pointer to first xfer in the request. */
391 struct pl330_xfer
*x
;
392 /* Hook to attach to DMAC's list of reqs with due callback */
393 struct list_head rqd
;
397 * To know the status of the channel and DMAC, the client
398 * provides a pointer to this structure. The PL330 core
399 * fills it with current information.
401 struct pl330_chanstatus
{
403 * If the DMAC engine halted due to some error,
404 * the client should remove-add DMAC.
408 * If channel is halted due to some error,
409 * the client should ABORT/FLUSH and START the channel.
412 /* Location of last load */
414 /* Location of last store */
417 * Pointer to the currently active req, NULL if channel is
418 * inactive, even though the requests may be present.
420 struct pl330_req
*top_req
;
421 /* Pointer to req waiting second in the queue if any. */
422 struct pl330_req
*wait_req
;
426 /* Start the channel */
428 /* Abort the active xfer */
430 /* Stop xfer and flush queue */
437 struct pl330_xfer
*x
;
460 /* Number of bytes taken to setup MC for the req */
465 /* ToBeDone for tasklet */
473 struct pl330_thread
{
476 /* If the channel is not yet acquired by any client */
479 struct pl330_dmac
*dmac
;
480 /* Only two at a time */
481 struct _pl330_req req
[2];
482 /* Index of the last enqueued request */
484 /* Index of the last submitted request or -1 if the DMA is stopped */
488 enum pl330_dmac_state
{
497 /* Holds list of reqs with due callbacks */
498 struct list_head req_done
;
499 /* Pointer to platform specific stuff */
500 struct pl330_info
*pinfo
;
501 /* Maximum possible events/irqs */
503 /* BUS address of MicroCode buffer */
504 dma_addr_t mcode_bus
;
505 /* CPU address of MicroCode buffer */
507 /* List of all Channel threads */
508 struct pl330_thread
*channels
;
509 /* Pointer to the MANAGER thread */
510 struct pl330_thread
*manager
;
511 /* To handle bad news in interrupt */
512 struct tasklet_struct tasks
;
513 struct _pl330_tbd dmac_tbd
;
514 /* State of DMAC operation */
515 enum pl330_dmac_state state
;
519 /* In the DMAC pool */
522 * Allocated to some channel during prep_xxx
523 * Also may be sitting on the work_list.
527 * Sitting on the work_list and already submitted
528 * to the PL330 core. Not more than two descriptors
529 * of a channel can be BUSY at any time.
533 * Sitting on the channel work_list but xfer done
539 struct dma_pl330_chan
{
540 /* Schedule desc completion */
541 struct tasklet_struct task
;
543 /* DMA-Engine Channel */
544 struct dma_chan chan
;
546 /* List of to be xfered descriptors */
547 struct list_head work_list
;
548 /* List of completed descriptors */
549 struct list_head completed_list
;
551 /* Pointer to the DMAC that manages this channel,
552 * NULL if the channel is available to be acquired.
553 * As the parent, this DMAC also provides descriptors
556 struct dma_pl330_dmac
*dmac
;
558 /* To protect channel manipulation */
561 /* Token of a hardware channel thread of PL330 DMAC
562 * NULL if the channel is available to be acquired.
566 /* For D-to-M and M-to-D channels */
567 int burst_sz
; /* the peripheral fifo width */
568 int burst_len
; /* the number of burst */
569 dma_addr_t fifo_addr
;
571 /* for cyclic capability */
575 struct dma_pl330_dmac
{
576 struct pl330_info pif
;
578 /* DMA-Engine Device */
579 struct dma_device ddma
;
581 /* Pool of descriptors available for the DMAC's channels */
582 struct list_head desc_pool
;
583 /* To protect desc_pool manipulation */
584 spinlock_t pool_lock
;
586 /* Peripheral channels connected to this DMAC */
587 struct dma_pl330_chan
*peripherals
; /* keep at end */
590 struct dma_pl330_desc
{
591 /* To attach to a queue as child */
592 struct list_head node
;
594 /* Descriptor for the DMA Engine API */
595 struct dma_async_tx_descriptor txd
;
597 /* Xfer for PL330 core */
598 struct pl330_xfer px
;
600 struct pl330_reqcfg rqcfg
;
601 struct pl330_req req
;
603 enum desc_status status
;
605 /* The channel which currently holds this desc */
606 struct dma_pl330_chan
*pchan
;
609 struct dma_pl330_filter_args
{
610 struct dma_pl330_dmac
*pdmac
;
611 unsigned int chan_id
;
614 static inline void _callback(struct pl330_req
*r
, enum pl330_op_err err
)
617 r
->xfer_cb(r
->token
, err
);
620 static inline bool _queue_empty(struct pl330_thread
*thrd
)
622 return (IS_FREE(&thrd
->req
[0]) && IS_FREE(&thrd
->req
[1]))
626 static inline bool _queue_full(struct pl330_thread
*thrd
)
628 return (IS_FREE(&thrd
->req
[0]) || IS_FREE(&thrd
->req
[1]))
632 static inline bool is_manager(struct pl330_thread
*thrd
)
634 struct pl330_dmac
*pl330
= thrd
->dmac
;
636 /* MANAGER is indexed at the end */
637 if (thrd
->id
== pl330
->pinfo
->pcfg
.num_chan
)
643 /* If manager of the thread is in Non-Secure mode */
644 static inline bool _manager_ns(struct pl330_thread
*thrd
)
646 struct pl330_dmac
*pl330
= thrd
->dmac
;
648 return (pl330
->pinfo
->pcfg
.mode
& DMAC_MODE_NS
) ? true : false;
651 static inline u32
get_revision(u32 periph_id
)
653 return (periph_id
>> PERIPH_REV_SHIFT
) & PERIPH_REV_MASK
;
656 static inline u32
_emit_ADDH(unsigned dry_run
, u8 buf
[],
657 enum pl330_dst da
, u16 val
)
662 buf
[0] = CMD_DMAADDH
;
664 *((u16
*)&buf
[1]) = val
;
666 PL330_DBGCMD_DUMP(SZ_DMAADDH
, "\tDMAADDH %s %u\n",
667 da
== 1 ? "DA" : "SA", val
);
672 static inline u32
_emit_END(unsigned dry_run
, u8 buf
[])
679 PL330_DBGCMD_DUMP(SZ_DMAEND
, "\tDMAEND\n");
684 static inline u32
_emit_FLUSHP(unsigned dry_run
, u8 buf
[], u8 peri
)
689 buf
[0] = CMD_DMAFLUSHP
;
695 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP
, "\tDMAFLUSHP %u\n", peri
>> 3);
700 static inline u32
_emit_LD(unsigned dry_run
, u8 buf
[], enum pl330_cond cond
)
708 buf
[0] |= (0 << 1) | (1 << 0);
709 else if (cond
== BURST
)
710 buf
[0] |= (1 << 1) | (1 << 0);
712 PL330_DBGCMD_DUMP(SZ_DMALD
, "\tDMALD%c\n",
713 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'));
718 static inline u32
_emit_LDP(unsigned dry_run
, u8 buf
[],
719 enum pl330_cond cond
, u8 peri
)
733 PL330_DBGCMD_DUMP(SZ_DMALDP
, "\tDMALDP%c %u\n",
734 cond
== SINGLE
? 'S' : 'B', peri
>> 3);
739 static inline u32
_emit_LP(unsigned dry_run
, u8 buf
[],
740 unsigned loop
, u8 cnt
)
750 cnt
--; /* DMAC increments by 1 internally */
753 PL330_DBGCMD_DUMP(SZ_DMALP
, "\tDMALP_%c %u\n", loop
? '1' : '0', cnt
);
759 enum pl330_cond cond
;
765 static inline u32
_emit_LPEND(unsigned dry_run
, u8 buf
[],
766 const struct _arg_LPEND
*arg
)
768 enum pl330_cond cond
= arg
->cond
;
769 bool forever
= arg
->forever
;
770 unsigned loop
= arg
->loop
;
771 u8 bjump
= arg
->bjump
;
776 buf
[0] = CMD_DMALPEND
;
785 buf
[0] |= (0 << 1) | (1 << 0);
786 else if (cond
== BURST
)
787 buf
[0] |= (1 << 1) | (1 << 0);
791 PL330_DBGCMD_DUMP(SZ_DMALPEND
, "\tDMALP%s%c_%c bjmpto_%x\n",
792 forever
? "FE" : "END",
793 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'),
800 static inline u32
_emit_KILL(unsigned dry_run
, u8 buf
[])
805 buf
[0] = CMD_DMAKILL
;
810 static inline u32
_emit_MOV(unsigned dry_run
, u8 buf
[],
811 enum dmamov_dst dst
, u32 val
)
818 *((u32
*)&buf
[2]) = val
;
820 PL330_DBGCMD_DUMP(SZ_DMAMOV
, "\tDMAMOV %s 0x%x\n",
821 dst
== SAR
? "SAR" : (dst
== DAR
? "DAR" : "CCR"), val
);
826 static inline u32
_emit_NOP(unsigned dry_run
, u8 buf
[])
833 PL330_DBGCMD_DUMP(SZ_DMANOP
, "\tDMANOP\n");
838 static inline u32
_emit_RMB(unsigned dry_run
, u8 buf
[])
845 PL330_DBGCMD_DUMP(SZ_DMARMB
, "\tDMARMB\n");
850 static inline u32
_emit_SEV(unsigned dry_run
, u8 buf
[], u8 ev
)
861 PL330_DBGCMD_DUMP(SZ_DMASEV
, "\tDMASEV %u\n", ev
>> 3);
866 static inline u32
_emit_ST(unsigned dry_run
, u8 buf
[], enum pl330_cond cond
)
874 buf
[0] |= (0 << 1) | (1 << 0);
875 else if (cond
== BURST
)
876 buf
[0] |= (1 << 1) | (1 << 0);
878 PL330_DBGCMD_DUMP(SZ_DMAST
, "\tDMAST%c\n",
879 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'A'));
884 static inline u32
_emit_STP(unsigned dry_run
, u8 buf
[],
885 enum pl330_cond cond
, u8 peri
)
899 PL330_DBGCMD_DUMP(SZ_DMASTP
, "\tDMASTP%c %u\n",
900 cond
== SINGLE
? 'S' : 'B', peri
>> 3);
905 static inline u32
_emit_STZ(unsigned dry_run
, u8 buf
[])
912 PL330_DBGCMD_DUMP(SZ_DMASTZ
, "\tDMASTZ\n");
917 static inline u32
_emit_WFE(unsigned dry_run
, u8 buf
[], u8 ev
,
932 PL330_DBGCMD_DUMP(SZ_DMAWFE
, "\tDMAWFE %u%s\n",
933 ev
>> 3, invalidate
? ", I" : "");
938 static inline u32
_emit_WFP(unsigned dry_run
, u8 buf
[],
939 enum pl330_cond cond
, u8 peri
)
947 buf
[0] |= (0 << 1) | (0 << 0);
948 else if (cond
== BURST
)
949 buf
[0] |= (1 << 1) | (0 << 0);
951 buf
[0] |= (0 << 1) | (1 << 0);
957 PL330_DBGCMD_DUMP(SZ_DMAWFP
, "\tDMAWFP%c %u\n",
958 cond
== SINGLE
? 'S' : (cond
== BURST
? 'B' : 'P'), peri
>> 3);
963 static inline u32
_emit_WMB(unsigned dry_run
, u8 buf
[])
970 PL330_DBGCMD_DUMP(SZ_DMAWMB
, "\tDMAWMB\n");
981 static inline u32
_emit_GO(unsigned dry_run
, u8 buf
[],
982 const struct _arg_GO
*arg
)
985 u32 addr
= arg
->addr
;
986 unsigned ns
= arg
->ns
;
996 *((u32
*)&buf
[2]) = addr
;
1001 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
1003 /* Returns Time-Out */
1004 static bool _until_dmac_idle(struct pl330_thread
*thrd
)
1006 void __iomem
*regs
= thrd
->dmac
->pinfo
->base
;
1007 unsigned long loops
= msecs_to_loops(5);
1010 /* Until Manager is Idle */
1011 if (!(readl(regs
+ DBGSTATUS
) & DBG_BUSY
))
1023 static inline void _execute_DBGINSN(struct pl330_thread
*thrd
,
1024 u8 insn
[], bool as_manager
)
1026 void __iomem
*regs
= thrd
->dmac
->pinfo
->base
;
1029 val
= (insn
[0] << 16) | (insn
[1] << 24);
1032 val
|= (thrd
->id
<< 8); /* Channel Number */
1034 writel(val
, regs
+ DBGINST0
);
1036 val
= *((u32
*)&insn
[2]);
1037 writel(val
, regs
+ DBGINST1
);
1039 /* If timed out due to halted state-machine */
1040 if (_until_dmac_idle(thrd
)) {
1041 dev_err(thrd
->dmac
->pinfo
->dev
, "DMAC halted!\n");
1046 writel(0, regs
+ DBGCMD
);
1050 * Mark a _pl330_req as free.
1051 * We do it by writing DMAEND as the first instruction
1052 * because no valid request is going to have DMAEND as
1053 * its first instruction to execute.
1055 static void mark_free(struct pl330_thread
*thrd
, int idx
)
1057 struct _pl330_req
*req
= &thrd
->req
[idx
];
1059 _emit_END(0, req
->mc_cpu
);
1062 thrd
->req_running
= -1;
1065 static inline u32
_state(struct pl330_thread
*thrd
)
1067 void __iomem
*regs
= thrd
->dmac
->pinfo
->base
;
1070 if (is_manager(thrd
))
1071 val
= readl(regs
+ DS
) & 0xf;
1073 val
= readl(regs
+ CS(thrd
->id
)) & 0xf;
1077 return PL330_STATE_STOPPED
;
1079 return PL330_STATE_EXECUTING
;
1081 return PL330_STATE_CACHEMISS
;
1083 return PL330_STATE_UPDTPC
;
1085 return PL330_STATE_WFE
;
1087 return PL330_STATE_FAULTING
;
1089 if (is_manager(thrd
))
1090 return PL330_STATE_INVALID
;
1092 return PL330_STATE_ATBARRIER
;
1094 if (is_manager(thrd
))
1095 return PL330_STATE_INVALID
;
1097 return PL330_STATE_QUEUEBUSY
;
1099 if (is_manager(thrd
))
1100 return PL330_STATE_INVALID
;
1102 return PL330_STATE_WFP
;
1104 if (is_manager(thrd
))
1105 return PL330_STATE_INVALID
;
1107 return PL330_STATE_KILLING
;
1109 if (is_manager(thrd
))
1110 return PL330_STATE_INVALID
;
1112 return PL330_STATE_COMPLETING
;
1114 if (is_manager(thrd
))
1115 return PL330_STATE_INVALID
;
1117 return PL330_STATE_FAULT_COMPLETING
;
1119 return PL330_STATE_INVALID
;
1123 static void _stop(struct pl330_thread
*thrd
)
1125 void __iomem
*regs
= thrd
->dmac
->pinfo
->base
;
1126 u8 insn
[6] = {0, 0, 0, 0, 0, 0};
1128 if (_state(thrd
) == PL330_STATE_FAULT_COMPLETING
)
1129 UNTIL(thrd
, PL330_STATE_FAULTING
| PL330_STATE_KILLING
);
1131 /* Return if nothing needs to be done */
1132 if (_state(thrd
) == PL330_STATE_COMPLETING
1133 || _state(thrd
) == PL330_STATE_KILLING
1134 || _state(thrd
) == PL330_STATE_STOPPED
)
1137 _emit_KILL(0, insn
);
1139 /* Stop generating interrupts for SEV */
1140 writel(readl(regs
+ INTEN
) & ~(1 << thrd
->ev
), regs
+ INTEN
);
1142 _execute_DBGINSN(thrd
, insn
, is_manager(thrd
));
1145 /* Start doing req 'idx' of thread 'thrd' */
1146 static bool _trigger(struct pl330_thread
*thrd
)
1148 void __iomem
*regs
= thrd
->dmac
->pinfo
->base
;
1149 struct _pl330_req
*req
;
1150 struct pl330_req
*r
;
1153 u8 insn
[6] = {0, 0, 0, 0, 0, 0};
1156 /* Return if already ACTIVE */
1157 if (_state(thrd
) != PL330_STATE_STOPPED
)
1160 idx
= 1 - thrd
->lstenq
;
1161 if (!IS_FREE(&thrd
->req
[idx
]))
1162 req
= &thrd
->req
[idx
];
1165 if (!IS_FREE(&thrd
->req
[idx
]))
1166 req
= &thrd
->req
[idx
];
1171 /* Return if no request */
1172 if (!req
|| !req
->r
)
1178 ns
= r
->cfg
->nonsecure
? 1 : 0;
1179 else if (readl(regs
+ CS(thrd
->id
)) & CS_CNS
)
1184 /* See 'Abort Sources' point-4 at Page 2-25 */
1185 if (_manager_ns(thrd
) && !ns
)
1186 dev_info(thrd
->dmac
->pinfo
->dev
, "%s:%d Recipe for ABORT!\n",
1187 __func__
, __LINE__
);
1190 go
.addr
= req
->mc_bus
;
1192 _emit_GO(0, insn
, &go
);
1194 /* Set to generate interrupts for SEV */
1195 writel(readl(regs
+ INTEN
) | (1 << thrd
->ev
), regs
+ INTEN
);
1197 /* Only manager can execute GO */
1198 _execute_DBGINSN(thrd
, insn
, true);
1200 thrd
->req_running
= idx
;
1205 static bool _start(struct pl330_thread
*thrd
)
1207 switch (_state(thrd
)) {
1208 case PL330_STATE_FAULT_COMPLETING
:
1209 UNTIL(thrd
, PL330_STATE_FAULTING
| PL330_STATE_KILLING
);
1211 if (_state(thrd
) == PL330_STATE_KILLING
)
1212 UNTIL(thrd
, PL330_STATE_STOPPED
)
1214 case PL330_STATE_FAULTING
:
1217 case PL330_STATE_KILLING
:
1218 case PL330_STATE_COMPLETING
:
1219 UNTIL(thrd
, PL330_STATE_STOPPED
)
1221 case PL330_STATE_STOPPED
:
1222 return _trigger(thrd
);
1224 case PL330_STATE_WFP
:
1225 case PL330_STATE_QUEUEBUSY
:
1226 case PL330_STATE_ATBARRIER
:
1227 case PL330_STATE_UPDTPC
:
1228 case PL330_STATE_CACHEMISS
:
1229 case PL330_STATE_EXECUTING
:
1232 case PL330_STATE_WFE
: /* For RESUME, nothing yet */
1238 static inline int _ldst_memtomem(unsigned dry_run
, u8 buf
[],
1239 const struct _xfer_spec
*pxs
, int cyc
)
1242 struct pl330_config
*pcfg
= pxs
->r
->cfg
->pcfg
;
1244 /* check lock-up free version */
1245 if (get_revision(pcfg
->periph_id
) >= PERIPH_REV_R1P0
) {
1247 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1248 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1252 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1253 off
+= _emit_RMB(dry_run
, &buf
[off
]);
1254 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1255 off
+= _emit_WMB(dry_run
, &buf
[off
]);
1262 static inline int _ldst_devtomem(unsigned dry_run
, u8 buf
[],
1263 const struct _xfer_spec
*pxs
, int cyc
)
1268 off
+= _emit_WFP(dry_run
, &buf
[off
], SINGLE
, pxs
->r
->peri
);
1269 off
+= _emit_LDP(dry_run
, &buf
[off
], SINGLE
, pxs
->r
->peri
);
1270 off
+= _emit_ST(dry_run
, &buf
[off
], ALWAYS
);
1271 off
+= _emit_FLUSHP(dry_run
, &buf
[off
], pxs
->r
->peri
);
1277 static inline int _ldst_memtodev(unsigned dry_run
, u8 buf
[],
1278 const struct _xfer_spec
*pxs
, int cyc
)
1283 off
+= _emit_WFP(dry_run
, &buf
[off
], SINGLE
, pxs
->r
->peri
);
1284 off
+= _emit_LD(dry_run
, &buf
[off
], ALWAYS
);
1285 off
+= _emit_STP(dry_run
, &buf
[off
], SINGLE
, pxs
->r
->peri
);
1286 off
+= _emit_FLUSHP(dry_run
, &buf
[off
], pxs
->r
->peri
);
1292 static int _bursts(unsigned dry_run
, u8 buf
[],
1293 const struct _xfer_spec
*pxs
, int cyc
)
1297 switch (pxs
->r
->rqtype
) {
1299 off
+= _ldst_memtodev(dry_run
, &buf
[off
], pxs
, cyc
);
1302 off
+= _ldst_devtomem(dry_run
, &buf
[off
], pxs
, cyc
);
1305 off
+= _ldst_memtomem(dry_run
, &buf
[off
], pxs
, cyc
);
1308 off
+= 0x40000000; /* Scare off the Client */
1315 /* Returns bytes consumed and updates bursts */
1316 static inline int _loop(unsigned dry_run
, u8 buf
[],
1317 unsigned long *bursts
, const struct _xfer_spec
*pxs
)
1319 int cyc
, cycmax
, szlp
, szlpend
, szbrst
, off
;
1320 unsigned lcnt0
, lcnt1
, ljmp0
, ljmp1
;
1321 struct _arg_LPEND lpend
;
1323 /* Max iterations possible in DMALP is 256 */
1324 if (*bursts
>= 256*256) {
1327 cyc
= *bursts
/ lcnt1
/ lcnt0
;
1328 } else if (*bursts
> 256) {
1330 lcnt0
= *bursts
/ lcnt1
;
1338 szlp
= _emit_LP(1, buf
, 0, 0);
1339 szbrst
= _bursts(1, buf
, pxs
, 1);
1341 lpend
.cond
= ALWAYS
;
1342 lpend
.forever
= false;
1345 szlpend
= _emit_LPEND(1, buf
, &lpend
);
1353 * Max bursts that we can unroll due to limit on the
1354 * size of backward jump that can be encoded in DMALPEND
1355 * which is 8-bits and hence 255
1357 cycmax
= (255 - (szlp
+ szlpend
)) / szbrst
;
1359 cyc
= (cycmax
< cyc
) ? cycmax
: cyc
;
1364 off
+= _emit_LP(dry_run
, &buf
[off
], 0, lcnt0
);
1368 off
+= _emit_LP(dry_run
, &buf
[off
], 1, lcnt1
);
1371 off
+= _bursts(dry_run
, &buf
[off
], pxs
, cyc
);
1373 lpend
.cond
= ALWAYS
;
1374 lpend
.forever
= false;
1376 lpend
.bjump
= off
- ljmp1
;
1377 off
+= _emit_LPEND(dry_run
, &buf
[off
], &lpend
);
1380 lpend
.cond
= ALWAYS
;
1381 lpend
.forever
= false;
1383 lpend
.bjump
= off
- ljmp0
;
1384 off
+= _emit_LPEND(dry_run
, &buf
[off
], &lpend
);
1387 *bursts
= lcnt1
* cyc
;
1394 static inline int _setup_loops(unsigned dry_run
, u8 buf
[],
1395 const struct _xfer_spec
*pxs
)
1397 struct pl330_xfer
*x
= pxs
->x
;
1399 unsigned long c
, bursts
= BYTE_TO_BURST(x
->bytes
, ccr
);
1404 off
+= _loop(dry_run
, &buf
[off
], &c
, pxs
);
1411 static inline int _setup_xfer(unsigned dry_run
, u8 buf
[],
1412 const struct _xfer_spec
*pxs
)
1414 struct pl330_xfer
*x
= pxs
->x
;
1417 /* DMAMOV SAR, x->src_addr */
1418 off
+= _emit_MOV(dry_run
, &buf
[off
], SAR
, x
->src_addr
);
1419 /* DMAMOV DAR, x->dst_addr */
1420 off
+= _emit_MOV(dry_run
, &buf
[off
], DAR
, x
->dst_addr
);
1423 off
+= _setup_loops(dry_run
, &buf
[off
], pxs
);
1429 * A req is a sequence of one or more xfer units.
1430 * Returns the number of bytes taken to setup the MC for the req.
1432 static int _setup_req(unsigned dry_run
, struct pl330_thread
*thrd
,
1433 unsigned index
, struct _xfer_spec
*pxs
)
1435 struct _pl330_req
*req
= &thrd
->req
[index
];
1436 struct pl330_xfer
*x
;
1437 u8
*buf
= req
->mc_cpu
;
1440 PL330_DBGMC_START(req
->mc_bus
);
1442 /* DMAMOV CCR, ccr */
1443 off
+= _emit_MOV(dry_run
, &buf
[off
], CCR
, pxs
->ccr
);
1447 /* Error if xfer length is not aligned at burst size */
1448 if (x
->bytes
% (BRST_SIZE(pxs
->ccr
) * BRST_LEN(pxs
->ccr
)))
1452 off
+= _setup_xfer(dry_run
, &buf
[off
], pxs
);
1457 /* DMASEV peripheral/event */
1458 off
+= _emit_SEV(dry_run
, &buf
[off
], thrd
->ev
);
1460 off
+= _emit_END(dry_run
, &buf
[off
]);
1465 static inline u32
_prepare_ccr(const struct pl330_reqcfg
*rqc
)
1475 /* We set same protection levels for Src and DST for now */
1476 if (rqc
->privileged
)
1477 ccr
|= CC_SRCPRI
| CC_DSTPRI
;
1479 ccr
|= CC_SRCNS
| CC_DSTNS
;
1480 if (rqc
->insnaccess
)
1481 ccr
|= CC_SRCIA
| CC_DSTIA
;
1483 ccr
|= (((rqc
->brst_len
- 1) & 0xf) << CC_SRCBRSTLEN_SHFT
);
1484 ccr
|= (((rqc
->brst_len
- 1) & 0xf) << CC_DSTBRSTLEN_SHFT
);
1486 ccr
|= (rqc
->brst_size
<< CC_SRCBRSTSIZE_SHFT
);
1487 ccr
|= (rqc
->brst_size
<< CC_DSTBRSTSIZE_SHFT
);
1489 ccr
|= (rqc
->scctl
<< CC_SRCCCTRL_SHFT
);
1490 ccr
|= (rqc
->dcctl
<< CC_DSTCCTRL_SHFT
);
1492 ccr
|= (rqc
->swap
<< CC_SWAP_SHFT
);
1497 static inline bool _is_valid(u32 ccr
)
1499 enum pl330_dstcachectrl dcctl
;
1500 enum pl330_srccachectrl scctl
;
1502 dcctl
= (ccr
>> CC_DSTCCTRL_SHFT
) & CC_DRCCCTRL_MASK
;
1503 scctl
= (ccr
>> CC_SRCCCTRL_SHFT
) & CC_SRCCCTRL_MASK
;
1505 if (dcctl
== DINVALID1
|| dcctl
== DINVALID2
1506 || scctl
== SINVALID1
|| scctl
== SINVALID2
)
1513 * Submit a list of xfers after which the client wants notification.
1514 * Client is not notified after each xfer unit, just once after all
1515 * xfer units are done or some error occurs.
1517 static int pl330_submit_req(void *ch_id
, struct pl330_req
*r
)
1519 struct pl330_thread
*thrd
= ch_id
;
1520 struct pl330_dmac
*pl330
;
1521 struct pl330_info
*pi
;
1522 struct _xfer_spec xs
;
1523 unsigned long flags
;
1529 /* No Req or Unacquired Channel or DMAC */
1530 if (!r
|| !thrd
|| thrd
->free
)
1537 if (pl330
->state
== DYING
1538 || pl330
->dmac_tbd
.reset_chan
& (1 << thrd
->id
)) {
1539 dev_info(thrd
->dmac
->pinfo
->dev
, "%s:%d\n",
1540 __func__
, __LINE__
);
1544 /* If request for non-existing peripheral */
1545 if (r
->rqtype
!= MEMTOMEM
&& r
->peri
>= pi
->pcfg
.num_peri
) {
1546 dev_info(thrd
->dmac
->pinfo
->dev
,
1547 "%s:%d Invalid peripheral(%u)!\n",
1548 __func__
, __LINE__
, r
->peri
);
1552 spin_lock_irqsave(&pl330
->lock
, flags
);
1554 if (_queue_full(thrd
)) {
1560 /* Use last settings, if not provided */
1562 /* Prefer Secure Channel */
1563 if (!_manager_ns(thrd
))
1564 r
->cfg
->nonsecure
= 0;
1566 r
->cfg
->nonsecure
= 1;
1568 ccr
= _prepare_ccr(r
->cfg
);
1570 ccr
= readl(regs
+ CC(thrd
->id
));
1573 /* If this req doesn't have valid xfer settings */
1574 if (!_is_valid(ccr
)) {
1576 dev_info(thrd
->dmac
->pinfo
->dev
, "%s:%d Invalid CCR(%x)!\n",
1577 __func__
, __LINE__
, ccr
);
1581 idx
= IS_FREE(&thrd
->req
[0]) ? 0 : 1;
1586 /* First dry run to check if req is acceptable */
1587 ret
= _setup_req(1, thrd
, idx
, &xs
);
1591 if (ret
> pi
->mcbufsz
/ 2) {
1592 dev_info(thrd
->dmac
->pinfo
->dev
,
1593 "%s:%d Trying increasing mcbufsz\n",
1594 __func__
, __LINE__
);
1599 /* Hook the request */
1601 thrd
->req
[idx
].mc_len
= _setup_req(0, thrd
, idx
, &xs
);
1602 thrd
->req
[idx
].r
= r
;
1607 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1612 static void pl330_dotask(unsigned long data
)
1614 struct pl330_dmac
*pl330
= (struct pl330_dmac
*) data
;
1615 struct pl330_info
*pi
= pl330
->pinfo
;
1616 unsigned long flags
;
1619 spin_lock_irqsave(&pl330
->lock
, flags
);
1621 /* The DMAC itself gone nuts */
1622 if (pl330
->dmac_tbd
.reset_dmac
) {
1623 pl330
->state
= DYING
;
1624 /* Reset the manager too */
1625 pl330
->dmac_tbd
.reset_mngr
= true;
1626 /* Clear the reset flag */
1627 pl330
->dmac_tbd
.reset_dmac
= false;
1630 if (pl330
->dmac_tbd
.reset_mngr
) {
1631 _stop(pl330
->manager
);
1632 /* Reset all channels */
1633 pl330
->dmac_tbd
.reset_chan
= (1 << pi
->pcfg
.num_chan
) - 1;
1634 /* Clear the reset flag */
1635 pl330
->dmac_tbd
.reset_mngr
= false;
1638 for (i
= 0; i
< pi
->pcfg
.num_chan
; i
++) {
1640 if (pl330
->dmac_tbd
.reset_chan
& (1 << i
)) {
1641 struct pl330_thread
*thrd
= &pl330
->channels
[i
];
1642 void __iomem
*regs
= pi
->base
;
1643 enum pl330_op_err err
;
1647 if (readl(regs
+ FSC
) & (1 << thrd
->id
))
1648 err
= PL330_ERR_FAIL
;
1650 err
= PL330_ERR_ABORT
;
1652 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1654 _callback(thrd
->req
[1 - thrd
->lstenq
].r
, err
);
1655 _callback(thrd
->req
[thrd
->lstenq
].r
, err
);
1657 spin_lock_irqsave(&pl330
->lock
, flags
);
1659 thrd
->req
[0].r
= NULL
;
1660 thrd
->req
[1].r
= NULL
;
1664 /* Clear the reset flag */
1665 pl330
->dmac_tbd
.reset_chan
&= ~(1 << i
);
1669 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1674 /* Returns 1 if state was updated, 0 otherwise */
1675 static int pl330_update(const struct pl330_info
*pi
)
1677 struct pl330_req
*rqdone
, *tmp
;
1678 struct pl330_dmac
*pl330
;
1679 unsigned long flags
;
1682 int id
, ev
, ret
= 0;
1684 if (!pi
|| !pi
->pl330_data
)
1688 pl330
= pi
->pl330_data
;
1690 spin_lock_irqsave(&pl330
->lock
, flags
);
1692 val
= readl(regs
+ FSM
) & 0x1;
1694 pl330
->dmac_tbd
.reset_mngr
= true;
1696 pl330
->dmac_tbd
.reset_mngr
= false;
1698 val
= readl(regs
+ FSC
) & ((1 << pi
->pcfg
.num_chan
) - 1);
1699 pl330
->dmac_tbd
.reset_chan
|= val
;
1702 while (i
< pi
->pcfg
.num_chan
) {
1703 if (val
& (1 << i
)) {
1705 "Reset Channel-%d\t CS-%x FTC-%x\n",
1706 i
, readl(regs
+ CS(i
)),
1707 readl(regs
+ FTC(i
)));
1708 _stop(&pl330
->channels
[i
]);
1714 /* Check which event happened i.e, thread notified */
1715 val
= readl(regs
+ ES
);
1716 if (pi
->pcfg
.num_events
< 32
1717 && val
& ~((1 << pi
->pcfg
.num_events
) - 1)) {
1718 pl330
->dmac_tbd
.reset_dmac
= true;
1719 dev_err(pi
->dev
, "%s:%d Unexpected!\n", __func__
, __LINE__
);
1724 for (ev
= 0; ev
< pi
->pcfg
.num_events
; ev
++) {
1725 if (val
& (1 << ev
)) { /* Event occurred */
1726 struct pl330_thread
*thrd
;
1727 u32 inten
= readl(regs
+ INTEN
);
1730 /* Clear the event */
1731 if (inten
& (1 << ev
))
1732 writel(1 << ev
, regs
+ INTCLR
);
1736 id
= pl330
->events
[ev
];
1738 thrd
= &pl330
->channels
[id
];
1740 active
= thrd
->req_running
;
1741 if (active
== -1) /* Aborted */
1744 /* Detach the req */
1745 rqdone
= thrd
->req
[active
].r
;
1746 thrd
->req
[active
].r
= NULL
;
1748 mark_free(thrd
, active
);
1750 /* Get going again ASAP */
1753 /* For now, just make a list of callbacks to be done */
1754 list_add_tail(&rqdone
->rqd
, &pl330
->req_done
);
1758 /* Now that we are in no hurry, do the callbacks */
1759 list_for_each_entry_safe(rqdone
, tmp
, &pl330
->req_done
, rqd
) {
1760 list_del(&rqdone
->rqd
);
1762 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1763 _callback(rqdone
, PL330_ERR_NONE
);
1764 spin_lock_irqsave(&pl330
->lock
, flags
);
1768 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1770 if (pl330
->dmac_tbd
.reset_dmac
1771 || pl330
->dmac_tbd
.reset_mngr
1772 || pl330
->dmac_tbd
.reset_chan
) {
1774 tasklet_schedule(&pl330
->tasks
);
1780 static int pl330_chan_ctrl(void *ch_id
, enum pl330_chan_op op
)
1782 struct pl330_thread
*thrd
= ch_id
;
1783 struct pl330_dmac
*pl330
;
1784 unsigned long flags
;
1785 int ret
= 0, active
;
1787 if (!thrd
|| thrd
->free
|| thrd
->dmac
->state
== DYING
)
1791 active
= thrd
->req_running
;
1793 spin_lock_irqsave(&pl330
->lock
, flags
);
1796 case PL330_OP_FLUSH
:
1797 /* Make sure the channel is stopped */
1800 thrd
->req
[0].r
= NULL
;
1801 thrd
->req
[1].r
= NULL
;
1806 case PL330_OP_ABORT
:
1807 /* Make sure the channel is stopped */
1810 /* ABORT is only for the active req */
1814 thrd
->req
[active
].r
= NULL
;
1815 mark_free(thrd
, active
);
1817 /* Start the next */
1818 case PL330_OP_START
:
1819 if ((active
== -1) && !_start(thrd
))
1827 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1831 /* Reserve an event */
1832 static inline int _alloc_event(struct pl330_thread
*thrd
)
1834 struct pl330_dmac
*pl330
= thrd
->dmac
;
1835 struct pl330_info
*pi
= pl330
->pinfo
;
1838 for (ev
= 0; ev
< pi
->pcfg
.num_events
; ev
++)
1839 if (pl330
->events
[ev
] == -1) {
1840 pl330
->events
[ev
] = thrd
->id
;
1847 static bool _chan_ns(const struct pl330_info
*pi
, int i
)
1849 return pi
->pcfg
.irq_ns
& (1 << i
);
1852 /* Upon success, returns IdentityToken for the
1853 * allocated channel, NULL otherwise.
1855 static void *pl330_request_channel(const struct pl330_info
*pi
)
1857 struct pl330_thread
*thrd
= NULL
;
1858 struct pl330_dmac
*pl330
;
1859 unsigned long flags
;
1862 if (!pi
|| !pi
->pl330_data
)
1865 pl330
= pi
->pl330_data
;
1867 if (pl330
->state
== DYING
)
1870 chans
= pi
->pcfg
.num_chan
;
1872 spin_lock_irqsave(&pl330
->lock
, flags
);
1874 for (i
= 0; i
< chans
; i
++) {
1875 thrd
= &pl330
->channels
[i
];
1876 if ((thrd
->free
) && (!_manager_ns(thrd
) ||
1878 thrd
->ev
= _alloc_event(thrd
);
1879 if (thrd
->ev
>= 0) {
1882 thrd
->req
[0].r
= NULL
;
1884 thrd
->req
[1].r
= NULL
;
1892 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1897 /* Release an event */
1898 static inline void _free_event(struct pl330_thread
*thrd
, int ev
)
1900 struct pl330_dmac
*pl330
= thrd
->dmac
;
1901 struct pl330_info
*pi
= pl330
->pinfo
;
1903 /* If the event is valid and was held by the thread */
1904 if (ev
>= 0 && ev
< pi
->pcfg
.num_events
1905 && pl330
->events
[ev
] == thrd
->id
)
1906 pl330
->events
[ev
] = -1;
1909 static void pl330_release_channel(void *ch_id
)
1911 struct pl330_thread
*thrd
= ch_id
;
1912 struct pl330_dmac
*pl330
;
1913 unsigned long flags
;
1915 if (!thrd
|| thrd
->free
)
1920 _callback(thrd
->req
[1 - thrd
->lstenq
].r
, PL330_ERR_ABORT
);
1921 _callback(thrd
->req
[thrd
->lstenq
].r
, PL330_ERR_ABORT
);
1925 spin_lock_irqsave(&pl330
->lock
, flags
);
1926 _free_event(thrd
, thrd
->ev
);
1928 spin_unlock_irqrestore(&pl330
->lock
, flags
);
1931 /* Initialize the structure for PL330 configuration, that can be used
1932 * by the client driver the make best use of the DMAC
1934 static void read_dmac_config(struct pl330_info
*pi
)
1936 void __iomem
*regs
= pi
->base
;
1939 val
= readl(regs
+ CRD
) >> CRD_DATA_WIDTH_SHIFT
;
1940 val
&= CRD_DATA_WIDTH_MASK
;
1941 pi
->pcfg
.data_bus_width
= 8 * (1 << val
);
1943 val
= readl(regs
+ CRD
) >> CRD_DATA_BUFF_SHIFT
;
1944 val
&= CRD_DATA_BUFF_MASK
;
1945 pi
->pcfg
.data_buf_dep
= val
+ 1;
1947 val
= readl(regs
+ CR0
) >> CR0_NUM_CHANS_SHIFT
;
1948 val
&= CR0_NUM_CHANS_MASK
;
1950 pi
->pcfg
.num_chan
= val
;
1952 val
= readl(regs
+ CR0
);
1953 if (val
& CR0_PERIPH_REQ_SET
) {
1954 val
= (val
>> CR0_NUM_PERIPH_SHIFT
) & CR0_NUM_PERIPH_MASK
;
1956 pi
->pcfg
.num_peri
= val
;
1957 pi
->pcfg
.peri_ns
= readl(regs
+ CR4
);
1959 pi
->pcfg
.num_peri
= 0;
1962 val
= readl(regs
+ CR0
);
1963 if (val
& CR0_BOOT_MAN_NS
)
1964 pi
->pcfg
.mode
|= DMAC_MODE_NS
;
1966 pi
->pcfg
.mode
&= ~DMAC_MODE_NS
;
1968 val
= readl(regs
+ CR0
) >> CR0_NUM_EVENTS_SHIFT
;
1969 val
&= CR0_NUM_EVENTS_MASK
;
1971 pi
->pcfg
.num_events
= val
;
1973 pi
->pcfg
.irq_ns
= readl(regs
+ CR3
);
1976 static inline void _reset_thread(struct pl330_thread
*thrd
)
1978 struct pl330_dmac
*pl330
= thrd
->dmac
;
1979 struct pl330_info
*pi
= pl330
->pinfo
;
1981 thrd
->req
[0].mc_cpu
= pl330
->mcode_cpu
1982 + (thrd
->id
* pi
->mcbufsz
);
1983 thrd
->req
[0].mc_bus
= pl330
->mcode_bus
1984 + (thrd
->id
* pi
->mcbufsz
);
1985 thrd
->req
[0].r
= NULL
;
1988 thrd
->req
[1].mc_cpu
= thrd
->req
[0].mc_cpu
1990 thrd
->req
[1].mc_bus
= thrd
->req
[0].mc_bus
1992 thrd
->req
[1].r
= NULL
;
1996 static int dmac_alloc_threads(struct pl330_dmac
*pl330
)
1998 struct pl330_info
*pi
= pl330
->pinfo
;
1999 int chans
= pi
->pcfg
.num_chan
;
2000 struct pl330_thread
*thrd
;
2003 /* Allocate 1 Manager and 'chans' Channel threads */
2004 pl330
->channels
= kzalloc((1 + chans
) * sizeof(*thrd
),
2006 if (!pl330
->channels
)
2009 /* Init Channel threads */
2010 for (i
= 0; i
< chans
; i
++) {
2011 thrd
= &pl330
->channels
[i
];
2014 _reset_thread(thrd
);
2018 /* MANAGER is indexed at the end */
2019 thrd
= &pl330
->channels
[chans
];
2023 pl330
->manager
= thrd
;
2028 static int dmac_alloc_resources(struct pl330_dmac
*pl330
)
2030 struct pl330_info
*pi
= pl330
->pinfo
;
2031 int chans
= pi
->pcfg
.num_chan
;
2035 * Alloc MicroCode buffer for 'chans' Channel threads.
2036 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
2038 pl330
->mcode_cpu
= dma_alloc_coherent(pi
->dev
,
2039 chans
* pi
->mcbufsz
,
2040 &pl330
->mcode_bus
, GFP_KERNEL
);
2041 if (!pl330
->mcode_cpu
) {
2042 dev_err(pi
->dev
, "%s:%d Can't allocate memory!\n",
2043 __func__
, __LINE__
);
2047 ret
= dmac_alloc_threads(pl330
);
2049 dev_err(pi
->dev
, "%s:%d Can't to create channels for DMAC!\n",
2050 __func__
, __LINE__
);
2051 dma_free_coherent(pi
->dev
,
2052 chans
* pi
->mcbufsz
,
2053 pl330
->mcode_cpu
, pl330
->mcode_bus
);
2060 static int pl330_add(struct pl330_info
*pi
)
2062 struct pl330_dmac
*pl330
;
2066 if (!pi
|| !pi
->dev
)
2069 /* If already added */
2074 * If the SoC can perform reset on the DMAC, then do it
2075 * before reading its configuration.
2082 /* Check if we can handle this DMAC */
2083 if ((pi
->pcfg
.periph_id
& 0xfffff) != PERIPH_ID_VAL
) {
2084 dev_err(pi
->dev
, "PERIPH_ID 0x%x !\n", pi
->pcfg
.periph_id
);
2088 /* Read the configuration of the DMAC */
2089 read_dmac_config(pi
);
2091 if (pi
->pcfg
.num_events
== 0) {
2092 dev_err(pi
->dev
, "%s:%d Can't work without events!\n",
2093 __func__
, __LINE__
);
2097 pl330
= kzalloc(sizeof(*pl330
), GFP_KERNEL
);
2099 dev_err(pi
->dev
, "%s:%d Can't allocate memory!\n",
2100 __func__
, __LINE__
);
2104 /* Assign the info structure and private data */
2106 pi
->pl330_data
= pl330
;
2108 spin_lock_init(&pl330
->lock
);
2110 INIT_LIST_HEAD(&pl330
->req_done
);
2112 /* Use default MC buffer size if not provided */
2114 pi
->mcbufsz
= MCODE_BUFF_PER_REQ
* 2;
2116 /* Mark all events as free */
2117 for (i
= 0; i
< pi
->pcfg
.num_events
; i
++)
2118 pl330
->events
[i
] = -1;
2120 /* Allocate resources needed by the DMAC */
2121 ret
= dmac_alloc_resources(pl330
);
2123 dev_err(pi
->dev
, "Unable to create channels for DMAC\n");
2128 tasklet_init(&pl330
->tasks
, pl330_dotask
, (unsigned long) pl330
);
2130 pl330
->state
= INIT
;
2135 static int dmac_free_threads(struct pl330_dmac
*pl330
)
2137 struct pl330_info
*pi
= pl330
->pinfo
;
2138 int chans
= pi
->pcfg
.num_chan
;
2139 struct pl330_thread
*thrd
;
2142 /* Release Channel threads */
2143 for (i
= 0; i
< chans
; i
++) {
2144 thrd
= &pl330
->channels
[i
];
2145 pl330_release_channel((void *)thrd
);
2149 kfree(pl330
->channels
);
2154 static void dmac_free_resources(struct pl330_dmac
*pl330
)
2156 struct pl330_info
*pi
= pl330
->pinfo
;
2157 int chans
= pi
->pcfg
.num_chan
;
2159 dmac_free_threads(pl330
);
2161 dma_free_coherent(pi
->dev
, chans
* pi
->mcbufsz
,
2162 pl330
->mcode_cpu
, pl330
->mcode_bus
);
2165 static void pl330_del(struct pl330_info
*pi
)
2167 struct pl330_dmac
*pl330
;
2169 if (!pi
|| !pi
->pl330_data
)
2172 pl330
= pi
->pl330_data
;
2174 pl330
->state
= UNINIT
;
2176 tasklet_kill(&pl330
->tasks
);
2178 /* Free DMAC resources */
2179 dmac_free_resources(pl330
);
2182 pi
->pl330_data
= NULL
;
2185 /* forward declaration */
2186 static struct amba_driver pl330_driver
;
2188 static inline struct dma_pl330_chan
*
2189 to_pchan(struct dma_chan
*ch
)
2194 return container_of(ch
, struct dma_pl330_chan
, chan
);
2197 static inline struct dma_pl330_desc
*
2198 to_desc(struct dma_async_tx_descriptor
*tx
)
2200 return container_of(tx
, struct dma_pl330_desc
, txd
);
2203 static inline void fill_queue(struct dma_pl330_chan
*pch
)
2205 struct dma_pl330_desc
*desc
;
2208 list_for_each_entry(desc
, &pch
->work_list
, node
) {
2210 /* If already submitted */
2211 if (desc
->status
== BUSY
)
2214 ret
= pl330_submit_req(pch
->pl330_chid
,
2217 desc
->status
= BUSY
;
2218 } else if (ret
== -EAGAIN
) {
2219 /* QFull or DMAC Dying */
2222 /* Unacceptable request */
2223 desc
->status
= DONE
;
2224 dev_err(pch
->dmac
->pif
.dev
, "%s:%d Bad Desc(%d)\n",
2225 __func__
, __LINE__
, desc
->txd
.cookie
);
2226 tasklet_schedule(&pch
->task
);
2231 static void pl330_tasklet(unsigned long data
)
2233 struct dma_pl330_chan
*pch
= (struct dma_pl330_chan
*)data
;
2234 struct dma_pl330_desc
*desc
, *_dt
;
2235 unsigned long flags
;
2237 spin_lock_irqsave(&pch
->lock
, flags
);
2239 /* Pick up ripe tomatoes */
2240 list_for_each_entry_safe(desc
, _dt
, &pch
->work_list
, node
)
2241 if (desc
->status
== DONE
) {
2243 dma_cookie_complete(&desc
->txd
);
2244 list_move_tail(&desc
->node
, &pch
->completed_list
);
2247 /* Try to submit a req imm. next to the last completed cookie */
2250 /* Make sure the PL330 Channel thread is active */
2251 pl330_chan_ctrl(pch
->pl330_chid
, PL330_OP_START
);
2253 while (!list_empty(&pch
->completed_list
)) {
2254 dma_async_tx_callback callback
;
2255 void *callback_param
;
2257 desc
= list_first_entry(&pch
->completed_list
,
2258 struct dma_pl330_desc
, node
);
2260 callback
= desc
->txd
.callback
;
2261 callback_param
= desc
->txd
.callback_param
;
2264 desc
->status
= PREP
;
2265 list_move_tail(&desc
->node
, &pch
->work_list
);
2267 desc
->status
= FREE
;
2268 list_move_tail(&desc
->node
, &pch
->dmac
->desc_pool
);
2272 spin_unlock_irqrestore(&pch
->lock
, flags
);
2273 callback(callback_param
);
2274 spin_lock_irqsave(&pch
->lock
, flags
);
2277 spin_unlock_irqrestore(&pch
->lock
, flags
);
2280 static void dma_pl330_rqcb(void *token
, enum pl330_op_err err
)
2282 struct dma_pl330_desc
*desc
= token
;
2283 struct dma_pl330_chan
*pch
= desc
->pchan
;
2284 unsigned long flags
;
2286 /* If desc aborted */
2290 spin_lock_irqsave(&pch
->lock
, flags
);
2292 desc
->status
= DONE
;
2294 spin_unlock_irqrestore(&pch
->lock
, flags
);
2296 tasklet_schedule(&pch
->task
);
2299 static bool pl330_dt_filter(struct dma_chan
*chan
, void *param
)
2301 struct dma_pl330_filter_args
*fargs
= param
;
2303 if (chan
->device
!= &fargs
->pdmac
->ddma
)
2306 return (chan
->chan_id
== fargs
->chan_id
);
2309 bool pl330_filter(struct dma_chan
*chan
, void *param
)
2313 if (chan
->device
->dev
->driver
!= &pl330_driver
.drv
)
2316 peri_id
= chan
->private;
2317 return *peri_id
== (unsigned)param
;
2319 EXPORT_SYMBOL(pl330_filter
);
2321 static struct dma_chan
*of_dma_pl330_xlate(struct of_phandle_args
*dma_spec
,
2322 struct of_dma
*ofdma
)
2324 int count
= dma_spec
->args_count
;
2325 struct dma_pl330_dmac
*pdmac
= ofdma
->of_dma_data
;
2326 struct dma_pl330_filter_args fargs
;
2335 fargs
.pdmac
= pdmac
;
2336 fargs
.chan_id
= dma_spec
->args
[0];
2339 dma_cap_set(DMA_SLAVE
, cap
);
2340 dma_cap_set(DMA_CYCLIC
, cap
);
2342 return dma_request_channel(cap
, pl330_dt_filter
, &fargs
);
2345 static int pl330_alloc_chan_resources(struct dma_chan
*chan
)
2347 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2348 struct dma_pl330_dmac
*pdmac
= pch
->dmac
;
2349 unsigned long flags
;
2351 spin_lock_irqsave(&pch
->lock
, flags
);
2353 dma_cookie_init(chan
);
2354 pch
->cyclic
= false;
2356 pch
->pl330_chid
= pl330_request_channel(&pdmac
->pif
);
2357 if (!pch
->pl330_chid
) {
2358 spin_unlock_irqrestore(&pch
->lock
, flags
);
2362 tasklet_init(&pch
->task
, pl330_tasklet
, (unsigned long) pch
);
2364 spin_unlock_irqrestore(&pch
->lock
, flags
);
2369 static int pl330_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
, unsigned long arg
)
2371 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2372 struct dma_pl330_desc
*desc
;
2373 unsigned long flags
;
2374 struct dma_pl330_dmac
*pdmac
= pch
->dmac
;
2375 struct dma_slave_config
*slave_config
;
2379 case DMA_TERMINATE_ALL
:
2380 spin_lock_irqsave(&pch
->lock
, flags
);
2382 /* FLUSH the PL330 Channel thread */
2383 pl330_chan_ctrl(pch
->pl330_chid
, PL330_OP_FLUSH
);
2385 /* Mark all desc done */
2386 list_for_each_entry(desc
, &pch
->work_list
, node
) {
2387 desc
->status
= FREE
;
2388 dma_cookie_complete(&desc
->txd
);
2391 list_for_each_entry(desc
, &pch
->completed_list
, node
) {
2392 desc
->status
= FREE
;
2393 dma_cookie_complete(&desc
->txd
);
2396 list_splice_tail_init(&pch
->work_list
, &pdmac
->desc_pool
);
2397 list_splice_tail_init(&pch
->completed_list
, &pdmac
->desc_pool
);
2398 spin_unlock_irqrestore(&pch
->lock
, flags
);
2400 case DMA_SLAVE_CONFIG
:
2401 slave_config
= (struct dma_slave_config
*)arg
;
2403 if (slave_config
->direction
== DMA_MEM_TO_DEV
) {
2404 if (slave_config
->dst_addr
)
2405 pch
->fifo_addr
= slave_config
->dst_addr
;
2406 if (slave_config
->dst_addr_width
)
2407 pch
->burst_sz
= __ffs(slave_config
->dst_addr_width
);
2408 if (slave_config
->dst_maxburst
)
2409 pch
->burst_len
= slave_config
->dst_maxburst
;
2410 } else if (slave_config
->direction
== DMA_DEV_TO_MEM
) {
2411 if (slave_config
->src_addr
)
2412 pch
->fifo_addr
= slave_config
->src_addr
;
2413 if (slave_config
->src_addr_width
)
2414 pch
->burst_sz
= __ffs(slave_config
->src_addr_width
);
2415 if (slave_config
->src_maxburst
)
2416 pch
->burst_len
= slave_config
->src_maxburst
;
2420 dev_err(pch
->dmac
->pif
.dev
, "Not supported command.\n");
2427 static void pl330_free_chan_resources(struct dma_chan
*chan
)
2429 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2430 unsigned long flags
;
2432 tasklet_kill(&pch
->task
);
2434 spin_lock_irqsave(&pch
->lock
, flags
);
2436 pl330_release_channel(pch
->pl330_chid
);
2437 pch
->pl330_chid
= NULL
;
2440 list_splice_tail_init(&pch
->work_list
, &pch
->dmac
->desc_pool
);
2442 spin_unlock_irqrestore(&pch
->lock
, flags
);
2445 static enum dma_status
2446 pl330_tx_status(struct dma_chan
*chan
, dma_cookie_t cookie
,
2447 struct dma_tx_state
*txstate
)
2449 return dma_cookie_status(chan
, cookie
, txstate
);
2452 static void pl330_issue_pending(struct dma_chan
*chan
)
2454 pl330_tasklet((unsigned long) to_pchan(chan
));
2458 * We returned the last one of the circular list of descriptor(s)
2459 * from prep_xxx, so the argument to submit corresponds to the last
2460 * descriptor of the list.
2462 static dma_cookie_t
pl330_tx_submit(struct dma_async_tx_descriptor
*tx
)
2464 struct dma_pl330_desc
*desc
, *last
= to_desc(tx
);
2465 struct dma_pl330_chan
*pch
= to_pchan(tx
->chan
);
2466 dma_cookie_t cookie
;
2467 unsigned long flags
;
2469 spin_lock_irqsave(&pch
->lock
, flags
);
2471 /* Assign cookies to all nodes */
2472 while (!list_empty(&last
->node
)) {
2473 desc
= list_entry(last
->node
.next
, struct dma_pl330_desc
, node
);
2475 desc
->txd
.callback
= last
->txd
.callback
;
2476 desc
->txd
.callback_param
= last
->txd
.callback_param
;
2479 dma_cookie_assign(&desc
->txd
);
2481 list_move_tail(&desc
->node
, &pch
->work_list
);
2484 cookie
= dma_cookie_assign(&last
->txd
);
2485 list_add_tail(&last
->node
, &pch
->work_list
);
2486 spin_unlock_irqrestore(&pch
->lock
, flags
);
2491 static inline void _init_desc(struct dma_pl330_desc
*desc
)
2494 desc
->req
.x
= &desc
->px
;
2495 desc
->req
.token
= desc
;
2496 desc
->rqcfg
.swap
= SWAP_NO
;
2497 desc
->rqcfg
.privileged
= 0;
2498 desc
->rqcfg
.insnaccess
= 0;
2499 desc
->rqcfg
.scctl
= SCCTRL0
;
2500 desc
->rqcfg
.dcctl
= DCCTRL0
;
2501 desc
->req
.cfg
= &desc
->rqcfg
;
2502 desc
->req
.xfer_cb
= dma_pl330_rqcb
;
2503 desc
->txd
.tx_submit
= pl330_tx_submit
;
2505 INIT_LIST_HEAD(&desc
->node
);
2508 /* Returns the number of descriptors added to the DMAC pool */
2509 static int add_desc(struct dma_pl330_dmac
*pdmac
, gfp_t flg
, int count
)
2511 struct dma_pl330_desc
*desc
;
2512 unsigned long flags
;
2518 desc
= kmalloc(count
* sizeof(*desc
), flg
);
2522 spin_lock_irqsave(&pdmac
->pool_lock
, flags
);
2524 for (i
= 0; i
< count
; i
++) {
2525 _init_desc(&desc
[i
]);
2526 list_add_tail(&desc
[i
].node
, &pdmac
->desc_pool
);
2529 spin_unlock_irqrestore(&pdmac
->pool_lock
, flags
);
2534 static struct dma_pl330_desc
*
2535 pluck_desc(struct dma_pl330_dmac
*pdmac
)
2537 struct dma_pl330_desc
*desc
= NULL
;
2538 unsigned long flags
;
2543 spin_lock_irqsave(&pdmac
->pool_lock
, flags
);
2545 if (!list_empty(&pdmac
->desc_pool
)) {
2546 desc
= list_entry(pdmac
->desc_pool
.next
,
2547 struct dma_pl330_desc
, node
);
2549 list_del_init(&desc
->node
);
2551 desc
->status
= PREP
;
2552 desc
->txd
.callback
= NULL
;
2555 spin_unlock_irqrestore(&pdmac
->pool_lock
, flags
);
2560 static struct dma_pl330_desc
*pl330_get_desc(struct dma_pl330_chan
*pch
)
2562 struct dma_pl330_dmac
*pdmac
= pch
->dmac
;
2563 u8
*peri_id
= pch
->chan
.private;
2564 struct dma_pl330_desc
*desc
;
2566 /* Pluck one desc from the pool of DMAC */
2567 desc
= pluck_desc(pdmac
);
2569 /* If the DMAC pool is empty, alloc new */
2571 if (!add_desc(pdmac
, GFP_ATOMIC
, 1))
2575 desc
= pluck_desc(pdmac
);
2577 dev_err(pch
->dmac
->pif
.dev
,
2578 "%s:%d ALERT!\n", __func__
, __LINE__
);
2583 /* Initialize the descriptor */
2585 desc
->txd
.cookie
= 0;
2586 async_tx_ack(&desc
->txd
);
2588 desc
->req
.peri
= peri_id
? pch
->chan
.chan_id
: 0;
2589 desc
->rqcfg
.pcfg
= &pch
->dmac
->pif
.pcfg
;
2591 dma_async_tx_descriptor_init(&desc
->txd
, &pch
->chan
);
2596 static inline void fill_px(struct pl330_xfer
*px
,
2597 dma_addr_t dst
, dma_addr_t src
, size_t len
)
2605 static struct dma_pl330_desc
*
2606 __pl330_prep_dma_memcpy(struct dma_pl330_chan
*pch
, dma_addr_t dst
,
2607 dma_addr_t src
, size_t len
)
2609 struct dma_pl330_desc
*desc
= pl330_get_desc(pch
);
2612 dev_err(pch
->dmac
->pif
.dev
, "%s:%d Unable to fetch desc\n",
2613 __func__
, __LINE__
);
2618 * Ideally we should lookout for reqs bigger than
2619 * those that can be programmed with 256 bytes of
2620 * MC buffer, but considering a req size is seldom
2621 * going to be word-unaligned and more than 200MB,
2623 * Also, should the limit is reached we'd rather
2624 * have the platform increase MC buffer size than
2625 * complicating this API driver.
2627 fill_px(&desc
->px
, dst
, src
, len
);
2632 /* Call after fixing burst size */
2633 static inline int get_burst_len(struct dma_pl330_desc
*desc
, size_t len
)
2635 struct dma_pl330_chan
*pch
= desc
->pchan
;
2636 struct pl330_info
*pi
= &pch
->dmac
->pif
;
2639 burst_len
= pi
->pcfg
.data_bus_width
/ 8;
2640 burst_len
*= pi
->pcfg
.data_buf_dep
;
2641 burst_len
>>= desc
->rqcfg
.brst_size
;
2643 /* src/dst_burst_len can't be more than 16 */
2647 while (burst_len
> 1) {
2648 if (!(len
% (burst_len
<< desc
->rqcfg
.brst_size
)))
2656 static struct dma_async_tx_descriptor
*pl330_prep_dma_cyclic(
2657 struct dma_chan
*chan
, dma_addr_t dma_addr
, size_t len
,
2658 size_t period_len
, enum dma_transfer_direction direction
,
2659 unsigned long flags
, void *context
)
2661 struct dma_pl330_desc
*desc
= NULL
, *first
= NULL
;
2662 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2663 struct dma_pl330_dmac
*pdmac
= pch
->dmac
;
2668 if (len
% period_len
!= 0)
2671 if (!is_slave_direction(direction
)) {
2672 dev_err(pch
->dmac
->pif
.dev
, "%s:%d Invalid dma direction\n",
2673 __func__
, __LINE__
);
2677 for (i
= 0; i
< len
/ period_len
; i
++) {
2678 desc
= pl330_get_desc(pch
);
2680 dev_err(pch
->dmac
->pif
.dev
, "%s:%d Unable to fetch desc\n",
2681 __func__
, __LINE__
);
2686 spin_lock_irqsave(&pdmac
->pool_lock
, flags
);
2688 while (!list_empty(&first
->node
)) {
2689 desc
= list_entry(first
->node
.next
,
2690 struct dma_pl330_desc
, node
);
2691 list_move_tail(&desc
->node
, &pdmac
->desc_pool
);
2694 list_move_tail(&first
->node
, &pdmac
->desc_pool
);
2696 spin_unlock_irqrestore(&pdmac
->pool_lock
, flags
);
2701 switch (direction
) {
2702 case DMA_MEM_TO_DEV
:
2703 desc
->rqcfg
.src_inc
= 1;
2704 desc
->rqcfg
.dst_inc
= 0;
2705 desc
->req
.rqtype
= MEMTODEV
;
2707 dst
= pch
->fifo_addr
;
2709 case DMA_DEV_TO_MEM
:
2710 desc
->rqcfg
.src_inc
= 0;
2711 desc
->rqcfg
.dst_inc
= 1;
2712 desc
->req
.rqtype
= DEVTOMEM
;
2713 src
= pch
->fifo_addr
;
2720 desc
->rqcfg
.brst_size
= pch
->burst_sz
;
2721 desc
->rqcfg
.brst_len
= 1;
2722 fill_px(&desc
->px
, dst
, src
, period_len
);
2727 list_add_tail(&desc
->node
, &first
->node
);
2729 dma_addr
+= period_len
;
2736 desc
->txd
.flags
= flags
;
2741 static struct dma_async_tx_descriptor
*
2742 pl330_prep_dma_memcpy(struct dma_chan
*chan
, dma_addr_t dst
,
2743 dma_addr_t src
, size_t len
, unsigned long flags
)
2745 struct dma_pl330_desc
*desc
;
2746 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2747 struct pl330_info
*pi
;
2750 if (unlikely(!pch
|| !len
))
2753 pi
= &pch
->dmac
->pif
;
2755 desc
= __pl330_prep_dma_memcpy(pch
, dst
, src
, len
);
2759 desc
->rqcfg
.src_inc
= 1;
2760 desc
->rqcfg
.dst_inc
= 1;
2761 desc
->req
.rqtype
= MEMTOMEM
;
2763 /* Select max possible burst size */
2764 burst
= pi
->pcfg
.data_bus_width
/ 8;
2772 desc
->rqcfg
.brst_size
= 0;
2773 while (burst
!= (1 << desc
->rqcfg
.brst_size
))
2774 desc
->rqcfg
.brst_size
++;
2776 desc
->rqcfg
.brst_len
= get_burst_len(desc
, len
);
2778 desc
->txd
.flags
= flags
;
2783 static void __pl330_giveback_desc(struct dma_pl330_dmac
*pdmac
,
2784 struct dma_pl330_desc
*first
)
2786 unsigned long flags
;
2787 struct dma_pl330_desc
*desc
;
2792 spin_lock_irqsave(&pdmac
->pool_lock
, flags
);
2794 while (!list_empty(&first
->node
)) {
2795 desc
= list_entry(first
->node
.next
,
2796 struct dma_pl330_desc
, node
);
2797 list_move_tail(&desc
->node
, &pdmac
->desc_pool
);
2800 list_move_tail(&first
->node
, &pdmac
->desc_pool
);
2802 spin_unlock_irqrestore(&pdmac
->pool_lock
, flags
);
2805 static struct dma_async_tx_descriptor
*
2806 pl330_prep_slave_sg(struct dma_chan
*chan
, struct scatterlist
*sgl
,
2807 unsigned int sg_len
, enum dma_transfer_direction direction
,
2808 unsigned long flg
, void *context
)
2810 struct dma_pl330_desc
*first
, *desc
= NULL
;
2811 struct dma_pl330_chan
*pch
= to_pchan(chan
);
2812 struct scatterlist
*sg
;
2816 if (unlikely(!pch
|| !sgl
|| !sg_len
))
2819 addr
= pch
->fifo_addr
;
2823 for_each_sg(sgl
, sg
, sg_len
, i
) {
2825 desc
= pl330_get_desc(pch
);
2827 struct dma_pl330_dmac
*pdmac
= pch
->dmac
;
2829 dev_err(pch
->dmac
->pif
.dev
,
2830 "%s:%d Unable to fetch desc\n",
2831 __func__
, __LINE__
);
2832 __pl330_giveback_desc(pdmac
, first
);
2840 list_add_tail(&desc
->node
, &first
->node
);
2842 if (direction
== DMA_MEM_TO_DEV
) {
2843 desc
->rqcfg
.src_inc
= 1;
2844 desc
->rqcfg
.dst_inc
= 0;
2845 desc
->req
.rqtype
= MEMTODEV
;
2847 addr
, sg_dma_address(sg
), sg_dma_len(sg
));
2849 desc
->rqcfg
.src_inc
= 0;
2850 desc
->rqcfg
.dst_inc
= 1;
2851 desc
->req
.rqtype
= DEVTOMEM
;
2853 sg_dma_address(sg
), addr
, sg_dma_len(sg
));
2856 desc
->rqcfg
.brst_size
= pch
->burst_sz
;
2857 desc
->rqcfg
.brst_len
= 1;
2860 /* Return the last desc in the chain */
2861 desc
->txd
.flags
= flg
;
2865 static irqreturn_t
pl330_irq_handler(int irq
, void *data
)
2867 if (pl330_update(data
))
2873 #define PL330_DMA_BUSWIDTHS \
2874 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2875 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2876 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2877 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2878 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2880 static int pl330_dma_device_slave_caps(struct dma_chan
*dchan
,
2881 struct dma_slave_caps
*caps
)
2883 caps
->src_addr_widths
= PL330_DMA_BUSWIDTHS
;
2884 caps
->dstn_addr_widths
= PL330_DMA_BUSWIDTHS
;
2885 caps
->directions
= BIT(DMA_DEV_TO_MEM
) | BIT(DMA_MEM_TO_DEV
);
2886 caps
->cmd_pause
= false;
2887 caps
->cmd_terminate
= true;
2893 pl330_probe(struct amba_device
*adev
, const struct amba_id
*id
)
2895 struct dma_pl330_platdata
*pdat
;
2896 struct dma_pl330_dmac
*pdmac
;
2897 struct dma_pl330_chan
*pch
, *_p
;
2898 struct pl330_info
*pi
;
2899 struct dma_device
*pd
;
2900 struct resource
*res
;
2904 pdat
= dev_get_platdata(&adev
->dev
);
2906 ret
= dma_set_mask_and_coherent(&adev
->dev
, DMA_BIT_MASK(32));
2910 /* Allocate a new DMAC and its Channels */
2911 pdmac
= devm_kzalloc(&adev
->dev
, sizeof(*pdmac
), GFP_KERNEL
);
2913 dev_err(&adev
->dev
, "unable to allocate mem\n");
2918 pi
->dev
= &adev
->dev
;
2919 pi
->pl330_data
= NULL
;
2920 pi
->mcbufsz
= pdat
? pdat
->mcbuf_sz
: 0;
2923 pi
->base
= devm_ioremap_resource(&adev
->dev
, res
);
2924 if (IS_ERR(pi
->base
))
2925 return PTR_ERR(pi
->base
);
2927 amba_set_drvdata(adev
, pdmac
);
2930 ret
= request_irq(irq
, pl330_irq_handler
, 0,
2931 dev_name(&adev
->dev
), pi
);
2935 pi
->pcfg
.periph_id
= adev
->periphid
;
2936 ret
= pl330_add(pi
);
2940 INIT_LIST_HEAD(&pdmac
->desc_pool
);
2941 spin_lock_init(&pdmac
->pool_lock
);
2943 /* Create a descriptor pool of default size */
2944 if (!add_desc(pdmac
, GFP_KERNEL
, NR_DEFAULT_DESC
))
2945 dev_warn(&adev
->dev
, "unable to allocate desc\n");
2948 INIT_LIST_HEAD(&pd
->channels
);
2950 /* Initialize channel parameters */
2952 num_chan
= max_t(int, pdat
->nr_valid_peri
, pi
->pcfg
.num_chan
);
2954 num_chan
= max_t(int, pi
->pcfg
.num_peri
, pi
->pcfg
.num_chan
);
2956 pdmac
->peripherals
= kzalloc(num_chan
* sizeof(*pch
), GFP_KERNEL
);
2957 if (!pdmac
->peripherals
) {
2959 dev_err(&adev
->dev
, "unable to allocate pdmac->peripherals\n");
2963 for (i
= 0; i
< num_chan
; i
++) {
2964 pch
= &pdmac
->peripherals
[i
];
2965 if (!adev
->dev
.of_node
)
2966 pch
->chan
.private = pdat
? &pdat
->peri_id
[i
] : NULL
;
2968 pch
->chan
.private = adev
->dev
.of_node
;
2970 INIT_LIST_HEAD(&pch
->work_list
);
2971 INIT_LIST_HEAD(&pch
->completed_list
);
2972 spin_lock_init(&pch
->lock
);
2973 pch
->pl330_chid
= NULL
;
2974 pch
->chan
.device
= pd
;
2977 /* Add the channel to the DMAC list */
2978 list_add_tail(&pch
->chan
.device_node
, &pd
->channels
);
2981 pd
->dev
= &adev
->dev
;
2983 pd
->cap_mask
= pdat
->cap_mask
;
2985 dma_cap_set(DMA_MEMCPY
, pd
->cap_mask
);
2986 if (pi
->pcfg
.num_peri
) {
2987 dma_cap_set(DMA_SLAVE
, pd
->cap_mask
);
2988 dma_cap_set(DMA_CYCLIC
, pd
->cap_mask
);
2989 dma_cap_set(DMA_PRIVATE
, pd
->cap_mask
);
2993 pd
->device_alloc_chan_resources
= pl330_alloc_chan_resources
;
2994 pd
->device_free_chan_resources
= pl330_free_chan_resources
;
2995 pd
->device_prep_dma_memcpy
= pl330_prep_dma_memcpy
;
2996 pd
->device_prep_dma_cyclic
= pl330_prep_dma_cyclic
;
2997 pd
->device_tx_status
= pl330_tx_status
;
2998 pd
->device_prep_slave_sg
= pl330_prep_slave_sg
;
2999 pd
->device_control
= pl330_control
;
3000 pd
->device_issue_pending
= pl330_issue_pending
;
3001 pd
->device_slave_caps
= pl330_dma_device_slave_caps
;
3003 ret
= dma_async_device_register(pd
);
3005 dev_err(&adev
->dev
, "unable to register DMAC\n");
3009 if (adev
->dev
.of_node
) {
3010 ret
= of_dma_controller_register(adev
->dev
.of_node
,
3011 of_dma_pl330_xlate
, pdmac
);
3014 "unable to register DMA to the generic DT DMA helpers\n");
3018 * This is the limit for transfers with a buswidth of 1, larger
3019 * buswidths will have larger limits.
3021 ret
= dma_set_max_seg_size(&adev
->dev
, 1900800);
3023 dev_err(&adev
->dev
, "unable to set the seg size\n");
3026 dev_info(&adev
->dev
,
3027 "Loaded driver for PL330 DMAC-%d\n", adev
->periphid
);
3028 dev_info(&adev
->dev
,
3029 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
3030 pi
->pcfg
.data_buf_dep
,
3031 pi
->pcfg
.data_bus_width
/ 8, pi
->pcfg
.num_chan
,
3032 pi
->pcfg
.num_peri
, pi
->pcfg
.num_events
);
3036 amba_set_drvdata(adev
, NULL
);
3039 list_for_each_entry_safe(pch
, _p
, &pdmac
->ddma
.channels
,
3042 /* Remove the channel */
3043 list_del(&pch
->chan
.device_node
);
3045 /* Flush the channel */
3046 pl330_control(&pch
->chan
, DMA_TERMINATE_ALL
, 0);
3047 pl330_free_chan_resources(&pch
->chan
);
3057 static int pl330_remove(struct amba_device
*adev
)
3059 struct dma_pl330_dmac
*pdmac
= amba_get_drvdata(adev
);
3060 struct dma_pl330_chan
*pch
, *_p
;
3061 struct pl330_info
*pi
;
3067 if (adev
->dev
.of_node
)
3068 of_dma_controller_free(adev
->dev
.of_node
);
3070 dma_async_device_unregister(&pdmac
->ddma
);
3071 amba_set_drvdata(adev
, NULL
);
3074 list_for_each_entry_safe(pch
, _p
, &pdmac
->ddma
.channels
,
3077 /* Remove the channel */
3078 list_del(&pch
->chan
.device_node
);
3080 /* Flush the channel */
3081 pl330_control(&pch
->chan
, DMA_TERMINATE_ALL
, 0);
3082 pl330_free_chan_resources(&pch
->chan
);
3095 static struct amba_id pl330_ids
[] = {
3103 MODULE_DEVICE_TABLE(amba
, pl330_ids
);
3105 static struct amba_driver pl330_driver
= {
3107 .owner
= THIS_MODULE
,
3108 .name
= "dma-pl330",
3110 .id_table
= pl330_ids
,
3111 .probe
= pl330_probe
,
3112 .remove
= pl330_remove
,
3115 module_amba_driver(pl330_driver
);
3117 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
3118 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3119 MODULE_LICENSE("GPL");