arch/arm/mach-s5pc100/dma.c

   1 /* linux/arch/arm/mach-s5pc100/dma.c
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * Copyright (C) 2010 Samsung Electronics Co. Ltd.
   7  *      Jaswinder Singh <jassi.brar@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  */
  23
  24 #include <linux/dma-mapping.h>
  25 #include <linux/amba/bus.h>
  26 #include <linux/amba/pl330.h>
  27
  28 #include <asm/irq.h>
  29 #include <plat/devs.h>
  30 #include <plat/irqs.h>
  31
  32 #include <mach/map.h>
  33 #include <mach/irqs.h>
  34 #include <mach/dma.h>
  35
  36 static u64 dma_dmamask = DMA_BIT_MASK(32);
  37
  38 static u8 pdma0_peri[] = {
  39         DMACH_UART0_RX,
  40         DMACH_UART0_TX,
  41         DMACH_UART1_RX,
  42         DMACH_UART1_TX,
  43         DMACH_UART2_RX,
  44         DMACH_UART2_TX,
  45         DMACH_UART3_RX,
  46         DMACH_UART3_TX,
  47         DMACH_IRDA,
  48         DMACH_I2S0_RX,
  49         DMACH_I2S0_TX,
  50         DMACH_I2S0S_TX,
  51         DMACH_I2S1_RX,
  52         DMACH_I2S1_TX,
  53         DMACH_I2S2_RX,
  54         DMACH_I2S2_TX,
  55         DMACH_SPI0_RX,
  56         DMACH_SPI0_TX,
  57         DMACH_SPI1_RX,
  58         DMACH_SPI1_TX,
  59         DMACH_SPI2_RX,
  60         DMACH_SPI2_TX,
  61         DMACH_AC97_MICIN,
  62         DMACH_AC97_PCMIN,
  63         DMACH_AC97_PCMOUT,
  64         DMACH_EXTERNAL,
  65         DMACH_PWM,
  66         DMACH_SPDIF,
  67         DMACH_HSI_RX,
  68         DMACH_HSI_TX,
  69 };
  70
  71 static struct dma_pl330_platdata s5pc100_pdma0_pdata = {
  72         .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
  73         .peri_id = pdma0_peri,
  74 };
  75
  76 static AMBA_AHB_DEVICE(s5pc100_pdma0,  "dma-pl330.0", 0x00041330,
  77         S5PC100_PA_PDMA0, {IRQ_PDMA0}, &s5pc100_pdma0_pdata);
  78
  79 static u8 pdma1_peri[] = {
  80         DMACH_UART0_RX,
  81         DMACH_UART0_TX,
  82         DMACH_UART1_RX,
  83         DMACH_UART1_TX,
  84         DMACH_UART2_RX,
  85         DMACH_UART2_TX,
  86         DMACH_UART3_RX,
  87         DMACH_UART3_TX,
  88         DMACH_IRDA,
  89         DMACH_I2S0_RX,
  90         DMACH_I2S0_TX,
  91         DMACH_I2S0S_TX,
  92         DMACH_I2S1_RX,
  93         DMACH_I2S1_TX,
  94         DMACH_I2S2_RX,
  95         DMACH_I2S2_TX,
  96         DMACH_SPI0_RX,
  97         DMACH_SPI0_TX,
  98         DMACH_SPI1_RX,
  99         DMACH_SPI1_TX,
 100         DMACH_SPI2_RX,
 101         DMACH_SPI2_TX,
 102         DMACH_PCM0_RX,
 103         DMACH_PCM0_TX,
 104         DMACH_PCM1_RX,
 105         DMACH_PCM1_TX,
 106         DMACH_MSM_REQ0,
 107         DMACH_MSM_REQ1,
 108         DMACH_MSM_REQ2,
 109         DMACH_MSM_REQ3,
 110 };
 111
 112 static struct dma_pl330_platdata s5pc100_pdma1_pdata = {
 113         .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
 114         .peri_id = pdma1_peri,
 115 };
 116
 117 static AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330,
 118         S5PC100_PA_PDMA1, {IRQ_PDMA1}, &s5pc100_pdma1_pdata);
 119
 120 static int __init s5pc100_dma_init(void)
 121 {
 122         dma_cap_set(DMA_SLAVE, s5pc100_pdma0_pdata.cap_mask);
 123         dma_cap_set(DMA_CYCLIC, s5pc100_pdma0_pdata.cap_mask);
 124         amba_device_register(&s5pc100_pdma0_device, &iomem_resource);
 125
 126         dma_cap_set(DMA_SLAVE, s5pc100_pdma1_pdata.cap_mask);
 127         dma_cap_set(DMA_CYCLIC, s5pc100_pdma1_pdata.cap_mask);
 128         amba_device_register(&s5pc100_pdma1_device, &iomem_resource);
 129
 130         return 0;
 131 }
 132 arch_initcall(s5pc100_dma_init);