2 * sata_mv.c - Marvell SATA support
4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
8 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 * --> Develop a low-power-consumption strategy, and implement it.
33 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
35 * --> [Experiment, Marvell value added] Is it possible to use target
36 * mode to cross-connect two Linux boxes with Marvell cards? If so,
37 * creating LibATA target mode support would be very interesting.
39 * Target mode, for those without docs, is the ability to directly
40 * connect two SATA ports.
44 * 80x1-B2 errata PCI#11:
46 * Users of the 6041/6081 Rev.B2 chips (current is C0)
47 * should be careful to insert those cards only onto PCI-X bus #0,
48 * and only in device slots 0..7, not higher. The chips may not
49 * work correctly otherwise (note: this is a pretty rare condition).
52 #include <linux/kernel.h>
53 #include <linux/module.h>
54 #include <linux/pci.h>
55 #include <linux/init.h>
56 #include <linux/blkdev.h>
57 #include <linux/delay.h>
58 #include <linux/interrupt.h>
59 #include <linux/dmapool.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/device.h>
62 #include <linux/clk.h>
63 #include <linux/platform_device.h>
64 #include <linux/ata_platform.h>
65 #include <linux/mbus.h>
66 #include <linux/bitops.h>
67 #include <scsi/scsi_host.h>
68 #include <scsi/scsi_cmnd.h>
69 #include <scsi/scsi_device.h>
70 #include <linux/libata.h>
72 #define DRV_NAME "sata_mv"
73 #define DRV_VERSION "1.28"
81 module_param(msi
, int, S_IRUGO
);
82 MODULE_PARM_DESC(msi
, "Enable use of PCI MSI (0=off, 1=on)");
85 static int irq_coalescing_io_count
;
86 module_param(irq_coalescing_io_count
, int, S_IRUGO
);
87 MODULE_PARM_DESC(irq_coalescing_io_count
,
88 "IRQ coalescing I/O count threshold (0..255)");
90 static int irq_coalescing_usecs
;
91 module_param(irq_coalescing_usecs
, int, S_IRUGO
);
92 MODULE_PARM_DESC(irq_coalescing_usecs
,
93 "IRQ coalescing time threshold in usecs");
96 /* BAR's are enumerated in terms of pci_resource_start() terms */
97 MV_PRIMARY_BAR
= 0, /* offset 0x10: memory space */
98 MV_IO_BAR
= 2, /* offset 0x18: IO space */
99 MV_MISC_BAR
= 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
101 MV_MAJOR_REG_AREA_SZ
= 0x10000, /* 64KB */
102 MV_MINOR_REG_AREA_SZ
= 0x2000, /* 8KB */
104 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
105 COAL_CLOCKS_PER_USEC
= 150, /* for calculating COAL_TIMEs */
106 MAX_COAL_TIME_THRESHOLD
= ((1 << 24) - 1), /* internal clocks count */
107 MAX_COAL_IO_COUNT
= 255, /* completed I/O count */
112 * Per-chip ("all ports") interrupt coalescing feature.
113 * This is only for GEN_II / GEN_IIE hardware.
115 * Coalescing defers the interrupt until either the IO_THRESHOLD
116 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
118 COAL_REG_BASE
= 0x18000,
119 IRQ_COAL_CAUSE
= (COAL_REG_BASE
+ 0x08),
120 ALL_PORTS_COAL_IRQ
= (1 << 4), /* all ports irq event */
122 IRQ_COAL_IO_THRESHOLD
= (COAL_REG_BASE
+ 0xcc),
123 IRQ_COAL_TIME_THRESHOLD
= (COAL_REG_BASE
+ 0xd0),
126 * Registers for the (unused here) transaction coalescing feature:
128 TRAN_COAL_CAUSE_LO
= (COAL_REG_BASE
+ 0x88),
129 TRAN_COAL_CAUSE_HI
= (COAL_REG_BASE
+ 0x8c),
131 SATAHC0_REG_BASE
= 0x20000,
133 GPIO_PORT_CTL
= 0x104f0,
136 MV_PCI_REG_SZ
= MV_MAJOR_REG_AREA_SZ
,
137 MV_SATAHC_REG_SZ
= MV_MAJOR_REG_AREA_SZ
,
138 MV_SATAHC_ARBTR_REG_SZ
= MV_MINOR_REG_AREA_SZ
, /* arbiter */
139 MV_PORT_REG_SZ
= MV_MINOR_REG_AREA_SZ
,
142 MV_MAX_Q_DEPTH_MASK
= MV_MAX_Q_DEPTH
- 1,
144 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
145 * CRPB needs alignment on a 256B boundary. Size == 256B
146 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
148 MV_CRQB_Q_SZ
= (32 * MV_MAX_Q_DEPTH
),
149 MV_CRPB_Q_SZ
= (8 * MV_MAX_Q_DEPTH
),
151 MV_SG_TBL_SZ
= (16 * MV_MAX_SG_CT
),
153 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
154 MV_PORT_HC_SHIFT
= 2,
155 MV_PORTS_PER_HC
= (1 << MV_PORT_HC_SHIFT
), /* 4 */
156 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
157 MV_PORT_MASK
= (MV_PORTS_PER_HC
- 1), /* 3 */
160 MV_FLAG_DUAL_HC
= (1 << 30), /* two SATA Host Controllers */
162 MV_COMMON_FLAGS
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
163 ATA_FLAG_MMIO
| ATA_FLAG_PIO_POLLING
,
165 MV_GEN_I_FLAGS
= MV_COMMON_FLAGS
| ATA_FLAG_NO_ATAPI
,
167 MV_GEN_II_FLAGS
= MV_COMMON_FLAGS
| ATA_FLAG_NCQ
|
168 ATA_FLAG_PMP
| ATA_FLAG_ACPI_SATA
,
170 MV_GEN_IIE_FLAGS
= MV_GEN_II_FLAGS
| ATA_FLAG_AN
,
172 CRQB_FLAG_READ
= (1 << 0),
174 CRQB_IOID_SHIFT
= 6, /* CRQB Gen-II/IIE IO Id shift */
175 CRQB_PMP_SHIFT
= 12, /* CRQB Gen-II/IIE PMP shift */
176 CRQB_HOSTQ_SHIFT
= 17, /* CRQB Gen-II/IIE HostQueTag shift */
177 CRQB_CMD_ADDR_SHIFT
= 8,
178 CRQB_CMD_CS
= (0x2 << 11),
179 CRQB_CMD_LAST
= (1 << 15),
181 CRPB_FLAG_STATUS_SHIFT
= 8,
182 CRPB_IOID_SHIFT_6
= 5, /* CRPB Gen-II IO Id shift */
183 CRPB_IOID_SHIFT_7
= 7, /* CRPB Gen-IIE IO Id shift */
185 EPRD_FLAG_END_OF_TBL
= (1 << 31),
187 /* PCI interface registers */
189 MV_PCI_COMMAND
= 0xc00,
190 MV_PCI_COMMAND_MWRCOM
= (1 << 4), /* PCI Master Write Combining */
191 MV_PCI_COMMAND_MRDTRIG
= (1 << 7), /* PCI Master Read Trigger */
193 PCI_MAIN_CMD_STS
= 0xd30,
194 STOP_PCI_MASTER
= (1 << 2),
195 PCI_MASTER_EMPTY
= (1 << 3),
196 GLOB_SFT_RST
= (1 << 4),
199 MV_PCI_MODE_MASK
= 0x30,
201 MV_PCI_EXP_ROM_BAR_CTL
= 0xd2c,
202 MV_PCI_DISC_TIMER
= 0xd04,
203 MV_PCI_MSI_TRIGGER
= 0xc38,
204 MV_PCI_SERR_MASK
= 0xc28,
205 MV_PCI_XBAR_TMOUT
= 0x1d04,
206 MV_PCI_ERR_LOW_ADDRESS
= 0x1d40,
207 MV_PCI_ERR_HIGH_ADDRESS
= 0x1d44,
208 MV_PCI_ERR_ATTRIBUTE
= 0x1d48,
209 MV_PCI_ERR_COMMAND
= 0x1d50,
211 PCI_IRQ_CAUSE
= 0x1d58,
212 PCI_IRQ_MASK
= 0x1d5c,
213 PCI_UNMASK_ALL_IRQS
= 0x7fffff, /* bits 22-0 */
215 PCIE_IRQ_CAUSE
= 0x1900,
216 PCIE_IRQ_MASK
= 0x1910,
217 PCIE_UNMASK_ALL_IRQS
= 0x40a, /* assorted bits */
219 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
220 PCI_HC_MAIN_IRQ_CAUSE
= 0x1d60,
221 PCI_HC_MAIN_IRQ_MASK
= 0x1d64,
222 SOC_HC_MAIN_IRQ_CAUSE
= 0x20020,
223 SOC_HC_MAIN_IRQ_MASK
= 0x20024,
224 ERR_IRQ
= (1 << 0), /* shift by (2 * port #) */
225 DONE_IRQ
= (1 << 1), /* shift by (2 * port #) */
226 HC0_IRQ_PEND
= 0x1ff, /* bits 0-8 = HC0's ports */
227 HC_SHIFT
= 9, /* bits 9-17 = HC1's ports */
228 DONE_IRQ_0_3
= 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
229 DONE_IRQ_4_7
= (DONE_IRQ_0_3
<< HC_SHIFT
), /* 4,5,6,7 */
231 TRAN_COAL_LO_DONE
= (1 << 19), /* transaction coalescing */
232 TRAN_COAL_HI_DONE
= (1 << 20), /* transaction coalescing */
233 PORTS_0_3_COAL_DONE
= (1 << 8), /* HC0 IRQ coalescing */
234 PORTS_4_7_COAL_DONE
= (1 << 17), /* HC1 IRQ coalescing */
235 ALL_PORTS_COAL_DONE
= (1 << 21), /* GEN_II(E) IRQ coalescing */
236 GPIO_INT
= (1 << 22),
237 SELF_INT
= (1 << 23),
238 TWSI_INT
= (1 << 24),
239 HC_MAIN_RSVD
= (0x7f << 25), /* bits 31-25 */
240 HC_MAIN_RSVD_5
= (0x1fff << 19), /* bits 31-19 */
241 HC_MAIN_RSVD_SOC
= (0x3fffffb << 6), /* bits 31-9, 7-6 */
243 /* SATAHC registers */
247 DMA_IRQ
= (1 << 0), /* shift by port # */
248 HC_COAL_IRQ
= (1 << 4), /* IRQ coalescing */
249 DEV_IRQ
= (1 << 8), /* shift by port # */
252 * Per-HC (Host-Controller) interrupt coalescing feature.
253 * This is present on all chip generations.
255 * Coalescing defers the interrupt until either the IO_THRESHOLD
256 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
258 HC_IRQ_COAL_IO_THRESHOLD
= 0x000c,
259 HC_IRQ_COAL_TIME_THRESHOLD
= 0x0010,
262 SOC_LED_CTRL_BLINK
= (1 << 0), /* Active LED blink */
263 SOC_LED_CTRL_ACT_PRESENCE
= (1 << 2), /* Multiplex dev presence */
264 /* with dev activity LED */
266 /* Shadow block registers */
268 SHD_CTL_AST
= 0x20, /* ofs from SHD_BLK */
271 SATA_STATUS
= 0x300, /* ctrl, err regs follow status */
273 FIS_IRQ_CAUSE
= 0x364,
274 FIS_IRQ_CAUSE_AN
= (1 << 9), /* async notification */
276 LTMODE
= 0x30c, /* requires read-after-write */
277 LTMODE_BIT8
= (1 << 8), /* unknown, but necessary */
282 PHY_MODE4
= 0x314, /* requires read-after-write */
283 PHY_MODE4_CFG_MASK
= 0x00000003, /* phy internal config field */
284 PHY_MODE4_CFG_VALUE
= 0x00000001, /* phy internal config field */
285 PHY_MODE4_RSVD_ZEROS
= 0x5de3fffa, /* Gen2e always write zeros */
286 PHY_MODE4_RSVD_ONES
= 0x00000005, /* Gen2e always write ones */
289 SATA_TESTCTL
= 0x348,
291 VENDOR_UNIQUE_FIS
= 0x35c,
294 FISCFG_WAIT_DEV_ERR
= (1 << 8), /* wait for host on DevErr */
295 FISCFG_SINGLE_SYNC
= (1 << 16), /* SYNC on DMA activation */
297 PHY_MODE9_GEN2
= 0x398,
298 PHY_MODE9_GEN1
= 0x39c,
299 PHYCFG_OFS
= 0x3a0, /* only in 65n devices */
306 MV_M2_PREAMP_MASK
= 0x7e0,
310 EDMA_CFG_Q_DEPTH
= 0x1f, /* max device queue depth */
311 EDMA_CFG_NCQ
= (1 << 5), /* for R/W FPDMA queued */
312 EDMA_CFG_NCQ_GO_ON_ERR
= (1 << 14), /* continue on error */
313 EDMA_CFG_RD_BRST_EXT
= (1 << 11), /* read burst 512B */
314 EDMA_CFG_WR_BUFF_LEN
= (1 << 13), /* write buffer 512B */
315 EDMA_CFG_EDMA_FBS
= (1 << 16), /* EDMA FIS-Based Switching */
316 EDMA_CFG_FBS
= (1 << 26), /* FIS-Based Switching */
318 EDMA_ERR_IRQ_CAUSE
= 0x8,
319 EDMA_ERR_IRQ_MASK
= 0xc,
320 EDMA_ERR_D_PAR
= (1 << 0), /* UDMA data parity err */
321 EDMA_ERR_PRD_PAR
= (1 << 1), /* UDMA PRD parity err */
322 EDMA_ERR_DEV
= (1 << 2), /* device error */
323 EDMA_ERR_DEV_DCON
= (1 << 3), /* device disconnect */
324 EDMA_ERR_DEV_CON
= (1 << 4), /* device connected */
325 EDMA_ERR_SERR
= (1 << 5), /* SError bits [WBDST] raised */
326 EDMA_ERR_SELF_DIS
= (1 << 7), /* Gen II/IIE self-disable */
327 EDMA_ERR_SELF_DIS_5
= (1 << 8), /* Gen I self-disable */
328 EDMA_ERR_BIST_ASYNC
= (1 << 8), /* BIST FIS or Async Notify */
329 EDMA_ERR_TRANS_IRQ_7
= (1 << 8), /* Gen IIE transprt layer irq */
330 EDMA_ERR_CRQB_PAR
= (1 << 9), /* CRQB parity error */
331 EDMA_ERR_CRPB_PAR
= (1 << 10), /* CRPB parity error */
332 EDMA_ERR_INTRL_PAR
= (1 << 11), /* internal parity error */
333 EDMA_ERR_IORDY
= (1 << 12), /* IORdy timeout */
335 EDMA_ERR_LNK_CTRL_RX
= (0xf << 13), /* link ctrl rx error */
336 EDMA_ERR_LNK_CTRL_RX_0
= (1 << 13), /* transient: CRC err */
337 EDMA_ERR_LNK_CTRL_RX_1
= (1 << 14), /* transient: FIFO err */
338 EDMA_ERR_LNK_CTRL_RX_2
= (1 << 15), /* fatal: caught SYNC */
339 EDMA_ERR_LNK_CTRL_RX_3
= (1 << 16), /* transient: FIS rx err */
341 EDMA_ERR_LNK_DATA_RX
= (0xf << 17), /* link data rx error */
343 EDMA_ERR_LNK_CTRL_TX
= (0x1f << 21), /* link ctrl tx error */
344 EDMA_ERR_LNK_CTRL_TX_0
= (1 << 21), /* transient: CRC err */
345 EDMA_ERR_LNK_CTRL_TX_1
= (1 << 22), /* transient: FIFO err */
346 EDMA_ERR_LNK_CTRL_TX_2
= (1 << 23), /* transient: caught SYNC */
347 EDMA_ERR_LNK_CTRL_TX_3
= (1 << 24), /* transient: caught DMAT */
348 EDMA_ERR_LNK_CTRL_TX_4
= (1 << 25), /* transient: FIS collision */
350 EDMA_ERR_LNK_DATA_TX
= (0x1f << 26), /* link data tx error */
352 EDMA_ERR_TRANS_PROTO
= (1 << 31), /* transport protocol error */
353 EDMA_ERR_OVERRUN_5
= (1 << 5),
354 EDMA_ERR_UNDERRUN_5
= (1 << 6),
356 EDMA_ERR_IRQ_TRANSIENT
= EDMA_ERR_LNK_CTRL_RX_0
|
357 EDMA_ERR_LNK_CTRL_RX_1
|
358 EDMA_ERR_LNK_CTRL_RX_3
|
359 EDMA_ERR_LNK_CTRL_TX
,
361 EDMA_EH_FREEZE
= EDMA_ERR_D_PAR
|
371 EDMA_ERR_LNK_CTRL_RX_2
|
372 EDMA_ERR_LNK_DATA_RX
|
373 EDMA_ERR_LNK_DATA_TX
|
374 EDMA_ERR_TRANS_PROTO
,
376 EDMA_EH_FREEZE_5
= EDMA_ERR_D_PAR
|
381 EDMA_ERR_UNDERRUN_5
|
382 EDMA_ERR_SELF_DIS_5
|
388 EDMA_REQ_Q_BASE_HI
= 0x10,
389 EDMA_REQ_Q_IN_PTR
= 0x14, /* also contains BASE_LO */
391 EDMA_REQ_Q_OUT_PTR
= 0x18,
392 EDMA_REQ_Q_PTR_SHIFT
= 5,
394 EDMA_RSP_Q_BASE_HI
= 0x1c,
395 EDMA_RSP_Q_IN_PTR
= 0x20,
396 EDMA_RSP_Q_OUT_PTR
= 0x24, /* also contains BASE_LO */
397 EDMA_RSP_Q_PTR_SHIFT
= 3,
399 EDMA_CMD
= 0x28, /* EDMA command register */
400 EDMA_EN
= (1 << 0), /* enable EDMA */
401 EDMA_DS
= (1 << 1), /* disable EDMA; self-negated */
402 EDMA_RESET
= (1 << 2), /* reset eng/trans/link/phy */
404 EDMA_STATUS
= 0x30, /* EDMA engine status */
405 EDMA_STATUS_CACHE_EMPTY
= (1 << 6), /* GenIIe command cache empty */
406 EDMA_STATUS_IDLE
= (1 << 7), /* GenIIe EDMA enabled/idle */
408 EDMA_IORDY_TMOUT
= 0x34,
411 EDMA_HALTCOND
= 0x60, /* GenIIe halt conditions */
412 EDMA_UNKNOWN_RSVD
= 0x6C, /* GenIIe unknown/reserved */
414 BMDMA_CMD
= 0x224, /* bmdma command register */
415 BMDMA_STATUS
= 0x228, /* bmdma status register */
416 BMDMA_PRD_LOW
= 0x22c, /* bmdma PRD addr 31:0 */
417 BMDMA_PRD_HIGH
= 0x230, /* bmdma PRD addr 63:32 */
419 /* Host private flags (hp_flags) */
420 MV_HP_FLAG_MSI
= (1 << 0),
421 MV_HP_ERRATA_50XXB0
= (1 << 1),
422 MV_HP_ERRATA_50XXB2
= (1 << 2),
423 MV_HP_ERRATA_60X1B2
= (1 << 3),
424 MV_HP_ERRATA_60X1C0
= (1 << 4),
425 MV_HP_GEN_I
= (1 << 6), /* Generation I: 50xx */
426 MV_HP_GEN_II
= (1 << 7), /* Generation II: 60xx */
427 MV_HP_GEN_IIE
= (1 << 8), /* Generation IIE: 6042/7042 */
428 MV_HP_PCIE
= (1 << 9), /* PCIe bus/regs: 7042 */
429 MV_HP_CUT_THROUGH
= (1 << 10), /* can use EDMA cut-through */
430 MV_HP_FLAG_SOC
= (1 << 11), /* SystemOnChip, no PCI */
431 MV_HP_QUIRK_LED_BLINK_EN
= (1 << 12), /* is led blinking enabled? */
433 /* Port private flags (pp_flags) */
434 MV_PP_FLAG_EDMA_EN
= (1 << 0), /* is EDMA engine enabled? */
435 MV_PP_FLAG_NCQ_EN
= (1 << 1), /* is EDMA set up for NCQ? */
436 MV_PP_FLAG_FBS_EN
= (1 << 2), /* is EDMA set up for FBS? */
437 MV_PP_FLAG_DELAYED_EH
= (1 << 3), /* delayed dev err handling */
438 MV_PP_FLAG_FAKE_ATA_BUSY
= (1 << 4), /* ignore initial ATA_DRDY */
441 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
442 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
443 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
444 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
445 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
447 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
448 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
451 /* DMA boundary 0xffff is required by the s/g splitting
452 * we need on /length/ in mv_fill-sg().
454 MV_DMA_BOUNDARY
= 0xffffU
,
456 /* mask of register bits containing lower 32 bits
457 * of EDMA request queue DMA address
459 EDMA_REQ_Q_BASE_LO_MASK
= 0xfffffc00U
,
461 /* ditto, for response queue */
462 EDMA_RSP_Q_BASE_LO_MASK
= 0xffffff00U
,
476 /* Command ReQuest Block: 32B */
492 /* Command ResPonse Block: 8B */
499 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
508 * We keep a local cache of a few frequently accessed port
509 * registers here, to avoid having to read them (very slow)
510 * when switching between EDMA and non-EDMA modes.
512 struct mv_cached_regs
{
519 struct mv_port_priv
{
520 struct mv_crqb
*crqb
;
522 struct mv_crpb
*crpb
;
524 struct mv_sg
*sg_tbl
[MV_MAX_Q_DEPTH
];
525 dma_addr_t sg_tbl_dma
[MV_MAX_Q_DEPTH
];
527 unsigned int req_idx
;
528 unsigned int resp_idx
;
531 struct mv_cached_regs cached
;
532 unsigned int delayed_eh_pmp_map
;
535 struct mv_port_signal
{
540 struct mv_host_priv
{
542 unsigned int board_idx
;
544 struct mv_port_signal signal
[8];
545 const struct mv_hw_ops
*ops
;
548 void __iomem
*main_irq_cause_addr
;
549 void __iomem
*main_irq_mask_addr
;
550 u32 irq_cause_offset
;
554 #if defined(CONFIG_HAVE_CLK)
558 * These consistent DMA memory pools give us guaranteed
559 * alignment for hardware-accessed data structures,
560 * and less memory waste in accomplishing the alignment.
562 struct dma_pool
*crqb_pool
;
563 struct dma_pool
*crpb_pool
;
564 struct dma_pool
*sg_tbl_pool
;
568 void (*phy_errata
)(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
570 void (*enable_leds
)(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
571 void (*read_preamp
)(struct mv_host_priv
*hpriv
, int idx
,
573 int (*reset_hc
)(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
575 void (*reset_flash
)(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
576 void (*reset_bus
)(struct ata_host
*host
, void __iomem
*mmio
);
579 static int mv_scr_read(struct ata_link
*link
, unsigned int sc_reg_in
, u32
*val
);
580 static int mv_scr_write(struct ata_link
*link
, unsigned int sc_reg_in
, u32 val
);
581 static int mv5_scr_read(struct ata_link
*link
, unsigned int sc_reg_in
, u32
*val
);
582 static int mv5_scr_write(struct ata_link
*link
, unsigned int sc_reg_in
, u32 val
);
583 static int mv_port_start(struct ata_port
*ap
);
584 static void mv_port_stop(struct ata_port
*ap
);
585 static int mv_qc_defer(struct ata_queued_cmd
*qc
);
586 static void mv_qc_prep(struct ata_queued_cmd
*qc
);
587 static void mv_qc_prep_iie(struct ata_queued_cmd
*qc
);
588 static unsigned int mv_qc_issue(struct ata_queued_cmd
*qc
);
589 static int mv_hardreset(struct ata_link
*link
, unsigned int *class,
590 unsigned long deadline
);
591 static void mv_eh_freeze(struct ata_port
*ap
);
592 static void mv_eh_thaw(struct ata_port
*ap
);
593 static void mv6_dev_config(struct ata_device
*dev
);
595 static void mv5_phy_errata(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
597 static void mv5_enable_leds(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
598 static void mv5_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
600 static int mv5_reset_hc(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
602 static void mv5_reset_flash(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
603 static void mv5_reset_bus(struct ata_host
*host
, void __iomem
*mmio
);
605 static void mv6_phy_errata(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
607 static void mv6_enable_leds(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
608 static void mv6_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
610 static int mv6_reset_hc(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
612 static void mv6_reset_flash(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
613 static void mv_soc_enable_leds(struct mv_host_priv
*hpriv
,
615 static void mv_soc_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
617 static int mv_soc_reset_hc(struct mv_host_priv
*hpriv
,
618 void __iomem
*mmio
, unsigned int n_hc
);
619 static void mv_soc_reset_flash(struct mv_host_priv
*hpriv
,
621 static void mv_soc_reset_bus(struct ata_host
*host
, void __iomem
*mmio
);
622 static void mv_soc_65n_phy_errata(struct mv_host_priv
*hpriv
,
623 void __iomem
*mmio
, unsigned int port
);
624 static void mv_reset_pci_bus(struct ata_host
*host
, void __iomem
*mmio
);
625 static void mv_reset_channel(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
626 unsigned int port_no
);
627 static int mv_stop_edma(struct ata_port
*ap
);
628 static int mv_stop_edma_engine(void __iomem
*port_mmio
);
629 static void mv_edma_cfg(struct ata_port
*ap
, int want_ncq
, int want_edma
);
631 static void mv_pmp_select(struct ata_port
*ap
, int pmp
);
632 static int mv_pmp_hardreset(struct ata_link
*link
, unsigned int *class,
633 unsigned long deadline
);
634 static int mv_softreset(struct ata_link
*link
, unsigned int *class,
635 unsigned long deadline
);
636 static void mv_pmp_error_handler(struct ata_port
*ap
);
637 static void mv_process_crpb_entries(struct ata_port
*ap
,
638 struct mv_port_priv
*pp
);
640 static void mv_sff_irq_clear(struct ata_port
*ap
);
641 static int mv_check_atapi_dma(struct ata_queued_cmd
*qc
);
642 static void mv_bmdma_setup(struct ata_queued_cmd
*qc
);
643 static void mv_bmdma_start(struct ata_queued_cmd
*qc
);
644 static void mv_bmdma_stop(struct ata_queued_cmd
*qc
);
645 static u8
mv_bmdma_status(struct ata_port
*ap
);
646 static u8
mv_sff_check_status(struct ata_port
*ap
);
648 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
649 * because we have to allow room for worst case splitting of
650 * PRDs for 64K boundaries in mv_fill_sg().
652 static struct scsi_host_template mv5_sht
= {
653 ATA_BASE_SHT(DRV_NAME
),
654 .sg_tablesize
= MV_MAX_SG_CT
/ 2,
655 .dma_boundary
= MV_DMA_BOUNDARY
,
658 static struct scsi_host_template mv6_sht
= {
659 ATA_NCQ_SHT(DRV_NAME
),
660 .can_queue
= MV_MAX_Q_DEPTH
- 1,
661 .sg_tablesize
= MV_MAX_SG_CT
/ 2,
662 .dma_boundary
= MV_DMA_BOUNDARY
,
665 static struct ata_port_operations mv5_ops
= {
666 .inherits
= &ata_sff_port_ops
,
668 .lost_interrupt
= ATA_OP_NULL
,
670 .qc_defer
= mv_qc_defer
,
671 .qc_prep
= mv_qc_prep
,
672 .qc_issue
= mv_qc_issue
,
674 .freeze
= mv_eh_freeze
,
676 .hardreset
= mv_hardreset
,
677 .error_handler
= ata_std_error_handler
, /* avoid SFF EH */
678 .post_internal_cmd
= ATA_OP_NULL
,
680 .scr_read
= mv5_scr_read
,
681 .scr_write
= mv5_scr_write
,
683 .port_start
= mv_port_start
,
684 .port_stop
= mv_port_stop
,
687 static struct ata_port_operations mv6_ops
= {
688 .inherits
= &mv5_ops
,
689 .dev_config
= mv6_dev_config
,
690 .scr_read
= mv_scr_read
,
691 .scr_write
= mv_scr_write
,
693 .pmp_hardreset
= mv_pmp_hardreset
,
694 .pmp_softreset
= mv_softreset
,
695 .softreset
= mv_softreset
,
696 .error_handler
= mv_pmp_error_handler
,
698 .sff_check_status
= mv_sff_check_status
,
699 .sff_irq_clear
= mv_sff_irq_clear
,
700 .check_atapi_dma
= mv_check_atapi_dma
,
701 .bmdma_setup
= mv_bmdma_setup
,
702 .bmdma_start
= mv_bmdma_start
,
703 .bmdma_stop
= mv_bmdma_stop
,
704 .bmdma_status
= mv_bmdma_status
,
707 static struct ata_port_operations mv_iie_ops
= {
708 .inherits
= &mv6_ops
,
709 .dev_config
= ATA_OP_NULL
,
710 .qc_prep
= mv_qc_prep_iie
,
713 static const struct ata_port_info mv_port_info
[] = {
715 .flags
= MV_GEN_I_FLAGS
,
716 .pio_mask
= ATA_PIO4
,
717 .udma_mask
= ATA_UDMA6
,
718 .port_ops
= &mv5_ops
,
721 .flags
= MV_GEN_I_FLAGS
| MV_FLAG_DUAL_HC
,
722 .pio_mask
= ATA_PIO4
,
723 .udma_mask
= ATA_UDMA6
,
724 .port_ops
= &mv5_ops
,
727 .flags
= MV_GEN_I_FLAGS
| MV_FLAG_DUAL_HC
,
728 .pio_mask
= ATA_PIO4
,
729 .udma_mask
= ATA_UDMA6
,
730 .port_ops
= &mv5_ops
,
733 .flags
= MV_GEN_II_FLAGS
,
734 .pio_mask
= ATA_PIO4
,
735 .udma_mask
= ATA_UDMA6
,
736 .port_ops
= &mv6_ops
,
739 .flags
= MV_GEN_II_FLAGS
| MV_FLAG_DUAL_HC
,
740 .pio_mask
= ATA_PIO4
,
741 .udma_mask
= ATA_UDMA6
,
742 .port_ops
= &mv6_ops
,
745 .flags
= MV_GEN_IIE_FLAGS
,
746 .pio_mask
= ATA_PIO4
,
747 .udma_mask
= ATA_UDMA6
,
748 .port_ops
= &mv_iie_ops
,
751 .flags
= MV_GEN_IIE_FLAGS
,
752 .pio_mask
= ATA_PIO4
,
753 .udma_mask
= ATA_UDMA6
,
754 .port_ops
= &mv_iie_ops
,
757 .flags
= MV_GEN_IIE_FLAGS
,
758 .pio_mask
= ATA_PIO4
,
759 .udma_mask
= ATA_UDMA6
,
760 .port_ops
= &mv_iie_ops
,
764 static const struct pci_device_id mv_pci_tbl
[] = {
765 { PCI_VDEVICE(MARVELL
, 0x5040), chip_504x
},
766 { PCI_VDEVICE(MARVELL
, 0x5041), chip_504x
},
767 { PCI_VDEVICE(MARVELL
, 0x5080), chip_5080
},
768 { PCI_VDEVICE(MARVELL
, 0x5081), chip_508x
},
769 /* RocketRAID 1720/174x have different identifiers */
770 { PCI_VDEVICE(TTI
, 0x1720), chip_6042
},
771 { PCI_VDEVICE(TTI
, 0x1740), chip_6042
},
772 { PCI_VDEVICE(TTI
, 0x1742), chip_6042
},
774 { PCI_VDEVICE(MARVELL
, 0x6040), chip_604x
},
775 { PCI_VDEVICE(MARVELL
, 0x6041), chip_604x
},
776 { PCI_VDEVICE(MARVELL
, 0x6042), chip_6042
},
777 { PCI_VDEVICE(MARVELL
, 0x6080), chip_608x
},
778 { PCI_VDEVICE(MARVELL
, 0x6081), chip_608x
},
780 { PCI_VDEVICE(ADAPTEC2
, 0x0241), chip_604x
},
783 { PCI_VDEVICE(ADAPTEC2
, 0x0243), chip_7042
},
785 /* Marvell 7042 support */
786 { PCI_VDEVICE(MARVELL
, 0x7042), chip_7042
},
788 /* Highpoint RocketRAID PCIe series */
789 { PCI_VDEVICE(TTI
, 0x2300), chip_7042
},
790 { PCI_VDEVICE(TTI
, 0x2310), chip_7042
},
792 { } /* terminate list */
795 static const struct mv_hw_ops mv5xxx_ops
= {
796 .phy_errata
= mv5_phy_errata
,
797 .enable_leds
= mv5_enable_leds
,
798 .read_preamp
= mv5_read_preamp
,
799 .reset_hc
= mv5_reset_hc
,
800 .reset_flash
= mv5_reset_flash
,
801 .reset_bus
= mv5_reset_bus
,
804 static const struct mv_hw_ops mv6xxx_ops
= {
805 .phy_errata
= mv6_phy_errata
,
806 .enable_leds
= mv6_enable_leds
,
807 .read_preamp
= mv6_read_preamp
,
808 .reset_hc
= mv6_reset_hc
,
809 .reset_flash
= mv6_reset_flash
,
810 .reset_bus
= mv_reset_pci_bus
,
813 static const struct mv_hw_ops mv_soc_ops
= {
814 .phy_errata
= mv6_phy_errata
,
815 .enable_leds
= mv_soc_enable_leds
,
816 .read_preamp
= mv_soc_read_preamp
,
817 .reset_hc
= mv_soc_reset_hc
,
818 .reset_flash
= mv_soc_reset_flash
,
819 .reset_bus
= mv_soc_reset_bus
,
822 static const struct mv_hw_ops mv_soc_65n_ops
= {
823 .phy_errata
= mv_soc_65n_phy_errata
,
824 .enable_leds
= mv_soc_enable_leds
,
825 .reset_hc
= mv_soc_reset_hc
,
826 .reset_flash
= mv_soc_reset_flash
,
827 .reset_bus
= mv_soc_reset_bus
,
834 static inline void writelfl(unsigned long data
, void __iomem
*addr
)
837 (void) readl(addr
); /* flush to avoid PCI posted write */
840 static inline unsigned int mv_hc_from_port(unsigned int port
)
842 return port
>> MV_PORT_HC_SHIFT
;
845 static inline unsigned int mv_hardport_from_port(unsigned int port
)
847 return port
& MV_PORT_MASK
;
851 * Consolidate some rather tricky bit shift calculations.
852 * This is hot-path stuff, so not a function.
853 * Simple code, with two return values, so macro rather than inline.
855 * port is the sole input, in range 0..7.
856 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
857 * hardport is the other output, in range 0..3.
859 * Note that port and hardport may be the same variable in some cases.
861 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
863 shift = mv_hc_from_port(port) * HC_SHIFT; \
864 hardport = mv_hardport_from_port(port); \
865 shift += hardport * 2; \
868 static inline void __iomem
*mv_hc_base(void __iomem
*base
, unsigned int hc
)
870 return (base
+ SATAHC0_REG_BASE
+ (hc
* MV_SATAHC_REG_SZ
));
873 static inline void __iomem
*mv_hc_base_from_port(void __iomem
*base
,
876 return mv_hc_base(base
, mv_hc_from_port(port
));
879 static inline void __iomem
*mv_port_base(void __iomem
*base
, unsigned int port
)
881 return mv_hc_base_from_port(base
, port
) +
882 MV_SATAHC_ARBTR_REG_SZ
+
883 (mv_hardport_from_port(port
) * MV_PORT_REG_SZ
);
886 static void __iomem
*mv5_phy_base(void __iomem
*mmio
, unsigned int port
)
888 void __iomem
*hc_mmio
= mv_hc_base_from_port(mmio
, port
);
889 unsigned long ofs
= (mv_hardport_from_port(port
) + 1) * 0x100UL
;
891 return hc_mmio
+ ofs
;
894 static inline void __iomem
*mv_host_base(struct ata_host
*host
)
896 struct mv_host_priv
*hpriv
= host
->private_data
;
900 static inline void __iomem
*mv_ap_base(struct ata_port
*ap
)
902 return mv_port_base(mv_host_base(ap
->host
), ap
->port_no
);
905 static inline int mv_get_hc_count(unsigned long port_flags
)
907 return ((port_flags
& MV_FLAG_DUAL_HC
) ? 2 : 1);
911 * mv_save_cached_regs - (re-)initialize cached port registers
912 * @ap: the port whose registers we are caching
914 * Initialize the local cache of port registers,
915 * so that reading them over and over again can
916 * be avoided on the hotter paths of this driver.
917 * This saves a few microseconds each time we switch
918 * to/from EDMA mode to perform (eg.) a drive cache flush.
920 static void mv_save_cached_regs(struct ata_port
*ap
)
922 void __iomem
*port_mmio
= mv_ap_base(ap
);
923 struct mv_port_priv
*pp
= ap
->private_data
;
925 pp
->cached
.fiscfg
= readl(port_mmio
+ FISCFG
);
926 pp
->cached
.ltmode
= readl(port_mmio
+ LTMODE
);
927 pp
->cached
.haltcond
= readl(port_mmio
+ EDMA_HALTCOND
);
928 pp
->cached
.unknown_rsvd
= readl(port_mmio
+ EDMA_UNKNOWN_RSVD
);
932 * mv_write_cached_reg - write to a cached port register
933 * @addr: hardware address of the register
934 * @old: pointer to cached value of the register
935 * @new: new value for the register
937 * Write a new value to a cached register,
938 * but only if the value is different from before.
940 static inline void mv_write_cached_reg(void __iomem
*addr
, u32
*old
, u32
new)
946 * Workaround for 88SX60x1-B2 FEr SATA#13:
947 * Read-after-write is needed to prevent generating 64-bit
948 * write cycles on the PCI bus for SATA interface registers
949 * at offsets ending in 0x4 or 0xc.
951 * Looks like a lot of fuss, but it avoids an unnecessary
952 * +1 usec read-after-write delay for unaffected registers.
954 laddr
= (long)addr
& 0xffff;
955 if (laddr
>= 0x300 && laddr
<= 0x33c) {
957 if (laddr
== 0x4 || laddr
== 0xc) {
958 writelfl(new, addr
); /* read after write */
962 writel(new, addr
); /* unaffected by the errata */
966 static void mv_set_edma_ptrs(void __iomem
*port_mmio
,
967 struct mv_host_priv
*hpriv
,
968 struct mv_port_priv
*pp
)
973 * initialize request queue
975 pp
->req_idx
&= MV_MAX_Q_DEPTH_MASK
; /* paranoia */
976 index
= pp
->req_idx
<< EDMA_REQ_Q_PTR_SHIFT
;
978 WARN_ON(pp
->crqb_dma
& 0x3ff);
979 writel((pp
->crqb_dma
>> 16) >> 16, port_mmio
+ EDMA_REQ_Q_BASE_HI
);
980 writelfl((pp
->crqb_dma
& EDMA_REQ_Q_BASE_LO_MASK
) | index
,
981 port_mmio
+ EDMA_REQ_Q_IN_PTR
);
982 writelfl(index
, port_mmio
+ EDMA_REQ_Q_OUT_PTR
);
985 * initialize response queue
987 pp
->resp_idx
&= MV_MAX_Q_DEPTH_MASK
; /* paranoia */
988 index
= pp
->resp_idx
<< EDMA_RSP_Q_PTR_SHIFT
;
990 WARN_ON(pp
->crpb_dma
& 0xff);
991 writel((pp
->crpb_dma
>> 16) >> 16, port_mmio
+ EDMA_RSP_Q_BASE_HI
);
992 writelfl(index
, port_mmio
+ EDMA_RSP_Q_IN_PTR
);
993 writelfl((pp
->crpb_dma
& EDMA_RSP_Q_BASE_LO_MASK
) | index
,
994 port_mmio
+ EDMA_RSP_Q_OUT_PTR
);
997 static void mv_write_main_irq_mask(u32 mask
, struct mv_host_priv
*hpriv
)
1000 * When writing to the main_irq_mask in hardware,
1001 * we must ensure exclusivity between the interrupt coalescing bits
1002 * and the corresponding individual port DONE_IRQ bits.
1004 * Note that this register is really an "IRQ enable" register,
1005 * not an "IRQ mask" register as Marvell's naming might suggest.
1007 if (mask
& (ALL_PORTS_COAL_DONE
| PORTS_0_3_COAL_DONE
))
1008 mask
&= ~DONE_IRQ_0_3
;
1009 if (mask
& (ALL_PORTS_COAL_DONE
| PORTS_4_7_COAL_DONE
))
1010 mask
&= ~DONE_IRQ_4_7
;
1011 writelfl(mask
, hpriv
->main_irq_mask_addr
);
1014 static void mv_set_main_irq_mask(struct ata_host
*host
,
1015 u32 disable_bits
, u32 enable_bits
)
1017 struct mv_host_priv
*hpriv
= host
->private_data
;
1018 u32 old_mask
, new_mask
;
1020 old_mask
= hpriv
->main_irq_mask
;
1021 new_mask
= (old_mask
& ~disable_bits
) | enable_bits
;
1022 if (new_mask
!= old_mask
) {
1023 hpriv
->main_irq_mask
= new_mask
;
1024 mv_write_main_irq_mask(new_mask
, hpriv
);
1028 static void mv_enable_port_irqs(struct ata_port
*ap
,
1029 unsigned int port_bits
)
1031 unsigned int shift
, hardport
, port
= ap
->port_no
;
1032 u32 disable_bits
, enable_bits
;
1034 MV_PORT_TO_SHIFT_AND_HARDPORT(port
, shift
, hardport
);
1036 disable_bits
= (DONE_IRQ
| ERR_IRQ
) << shift
;
1037 enable_bits
= port_bits
<< shift
;
1038 mv_set_main_irq_mask(ap
->host
, disable_bits
, enable_bits
);
1041 static void mv_clear_and_enable_port_irqs(struct ata_port
*ap
,
1042 void __iomem
*port_mmio
,
1043 unsigned int port_irqs
)
1045 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
1046 int hardport
= mv_hardport_from_port(ap
->port_no
);
1047 void __iomem
*hc_mmio
= mv_hc_base_from_port(
1048 mv_host_base(ap
->host
), ap
->port_no
);
1051 /* clear EDMA event indicators, if any */
1052 writelfl(0, port_mmio
+ EDMA_ERR_IRQ_CAUSE
);
1054 /* clear pending irq events */
1055 hc_irq_cause
= ~((DEV_IRQ
| DMA_IRQ
) << hardport
);
1056 writelfl(hc_irq_cause
, hc_mmio
+ HC_IRQ_CAUSE
);
1058 /* clear FIS IRQ Cause */
1059 if (IS_GEN_IIE(hpriv
))
1060 writelfl(0, port_mmio
+ FIS_IRQ_CAUSE
);
1062 mv_enable_port_irqs(ap
, port_irqs
);
1065 static void mv_set_irq_coalescing(struct ata_host
*host
,
1066 unsigned int count
, unsigned int usecs
)
1068 struct mv_host_priv
*hpriv
= host
->private_data
;
1069 void __iomem
*mmio
= hpriv
->base
, *hc_mmio
;
1070 u32 coal_enable
= 0;
1071 unsigned long flags
;
1072 unsigned int clks
, is_dual_hc
= hpriv
->n_ports
> MV_PORTS_PER_HC
;
1073 const u32 coal_disable
= PORTS_0_3_COAL_DONE
| PORTS_4_7_COAL_DONE
|
1074 ALL_PORTS_COAL_DONE
;
1076 /* Disable IRQ coalescing if either threshold is zero */
1077 if (!usecs
|| !count
) {
1080 /* Respect maximum limits of the hardware */
1081 clks
= usecs
* COAL_CLOCKS_PER_USEC
;
1082 if (clks
> MAX_COAL_TIME_THRESHOLD
)
1083 clks
= MAX_COAL_TIME_THRESHOLD
;
1084 if (count
> MAX_COAL_IO_COUNT
)
1085 count
= MAX_COAL_IO_COUNT
;
1088 spin_lock_irqsave(&host
->lock
, flags
);
1089 mv_set_main_irq_mask(host
, coal_disable
, 0);
1091 if (is_dual_hc
&& !IS_GEN_I(hpriv
)) {
1093 * GEN_II/GEN_IIE with dual host controllers:
1094 * one set of global thresholds for the entire chip.
1096 writel(clks
, mmio
+ IRQ_COAL_TIME_THRESHOLD
);
1097 writel(count
, mmio
+ IRQ_COAL_IO_THRESHOLD
);
1098 /* clear leftover coal IRQ bit */
1099 writel(~ALL_PORTS_COAL_IRQ
, mmio
+ IRQ_COAL_CAUSE
);
1101 coal_enable
= ALL_PORTS_COAL_DONE
;
1102 clks
= count
= 0; /* force clearing of regular regs below */
1106 * All chips: independent thresholds for each HC on the chip.
1108 hc_mmio
= mv_hc_base_from_port(mmio
, 0);
1109 writel(clks
, hc_mmio
+ HC_IRQ_COAL_TIME_THRESHOLD
);
1110 writel(count
, hc_mmio
+ HC_IRQ_COAL_IO_THRESHOLD
);
1111 writel(~HC_COAL_IRQ
, hc_mmio
+ HC_IRQ_CAUSE
);
1113 coal_enable
|= PORTS_0_3_COAL_DONE
;
1115 hc_mmio
= mv_hc_base_from_port(mmio
, MV_PORTS_PER_HC
);
1116 writel(clks
, hc_mmio
+ HC_IRQ_COAL_TIME_THRESHOLD
);
1117 writel(count
, hc_mmio
+ HC_IRQ_COAL_IO_THRESHOLD
);
1118 writel(~HC_COAL_IRQ
, hc_mmio
+ HC_IRQ_CAUSE
);
1120 coal_enable
|= PORTS_4_7_COAL_DONE
;
1123 mv_set_main_irq_mask(host
, 0, coal_enable
);
1124 spin_unlock_irqrestore(&host
->lock
, flags
);
1128 * mv_start_edma - Enable eDMA engine
1129 * @base: port base address
1130 * @pp: port private data
1132 * Verify the local cache of the eDMA state is accurate with a
1136 * Inherited from caller.
1138 static void mv_start_edma(struct ata_port
*ap
, void __iomem
*port_mmio
,
1139 struct mv_port_priv
*pp
, u8 protocol
)
1141 int want_ncq
= (protocol
== ATA_PROT_NCQ
);
1143 if (pp
->pp_flags
& MV_PP_FLAG_EDMA_EN
) {
1144 int using_ncq
= ((pp
->pp_flags
& MV_PP_FLAG_NCQ_EN
) != 0);
1145 if (want_ncq
!= using_ncq
)
1148 if (!(pp
->pp_flags
& MV_PP_FLAG_EDMA_EN
)) {
1149 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
1151 mv_edma_cfg(ap
, want_ncq
, 1);
1153 mv_set_edma_ptrs(port_mmio
, hpriv
, pp
);
1154 mv_clear_and_enable_port_irqs(ap
, port_mmio
, DONE_IRQ
|ERR_IRQ
);
1156 writelfl(EDMA_EN
, port_mmio
+ EDMA_CMD
);
1157 pp
->pp_flags
|= MV_PP_FLAG_EDMA_EN
;
1161 static void mv_wait_for_edma_empty_idle(struct ata_port
*ap
)
1163 void __iomem
*port_mmio
= mv_ap_base(ap
);
1164 const u32 empty_idle
= (EDMA_STATUS_CACHE_EMPTY
| EDMA_STATUS_IDLE
);
1165 const int per_loop
= 5, timeout
= (15 * 1000 / per_loop
);
1169 * Wait for the EDMA engine to finish transactions in progress.
1170 * No idea what a good "timeout" value might be, but measurements
1171 * indicate that it often requires hundreds of microseconds
1172 * with two drives in-use. So we use the 15msec value above
1173 * as a rough guess at what even more drives might require.
1175 for (i
= 0; i
< timeout
; ++i
) {
1176 u32 edma_stat
= readl(port_mmio
+ EDMA_STATUS
);
1177 if ((edma_stat
& empty_idle
) == empty_idle
)
1181 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
1185 * mv_stop_edma_engine - Disable eDMA engine
1186 * @port_mmio: io base address
1189 * Inherited from caller.
1191 static int mv_stop_edma_engine(void __iomem
*port_mmio
)
1195 /* Disable eDMA. The disable bit auto clears. */
1196 writelfl(EDMA_DS
, port_mmio
+ EDMA_CMD
);
1198 /* Wait for the chip to confirm eDMA is off. */
1199 for (i
= 10000; i
> 0; i
--) {
1200 u32 reg
= readl(port_mmio
+ EDMA_CMD
);
1201 if (!(reg
& EDMA_EN
))
1208 static int mv_stop_edma(struct ata_port
*ap
)
1210 void __iomem
*port_mmio
= mv_ap_base(ap
);
1211 struct mv_port_priv
*pp
= ap
->private_data
;
1214 if (!(pp
->pp_flags
& MV_PP_FLAG_EDMA_EN
))
1216 pp
->pp_flags
&= ~MV_PP_FLAG_EDMA_EN
;
1217 mv_wait_for_edma_empty_idle(ap
);
1218 if (mv_stop_edma_engine(port_mmio
)) {
1219 ata_port_printk(ap
, KERN_ERR
, "Unable to stop eDMA\n");
1222 mv_edma_cfg(ap
, 0, 0);
1227 static void mv_dump_mem(void __iomem
*start
, unsigned bytes
)
1230 for (b
= 0; b
< bytes
; ) {
1231 DPRINTK("%p: ", start
+ b
);
1232 for (w
= 0; b
< bytes
&& w
< 4; w
++) {
1233 printk("%08x ", readl(start
+ b
));
1241 static void mv_dump_pci_cfg(struct pci_dev
*pdev
, unsigned bytes
)
1246 for (b
= 0; b
< bytes
; ) {
1247 DPRINTK("%02x: ", b
);
1248 for (w
= 0; b
< bytes
&& w
< 4; w
++) {
1249 (void) pci_read_config_dword(pdev
, b
, &dw
);
1250 printk("%08x ", dw
);
1257 static void mv_dump_all_regs(void __iomem
*mmio_base
, int port
,
1258 struct pci_dev
*pdev
)
1261 void __iomem
*hc_base
= mv_hc_base(mmio_base
,
1262 port
>> MV_PORT_HC_SHIFT
);
1263 void __iomem
*port_base
;
1264 int start_port
, num_ports
, p
, start_hc
, num_hcs
, hc
;
1267 start_hc
= start_port
= 0;
1268 num_ports
= 8; /* shld be benign for 4 port devs */
1271 start_hc
= port
>> MV_PORT_HC_SHIFT
;
1273 num_ports
= num_hcs
= 1;
1275 DPRINTK("All registers for port(s) %u-%u:\n", start_port
,
1276 num_ports
> 1 ? num_ports
- 1 : start_port
);
1279 DPRINTK("PCI config space regs:\n");
1280 mv_dump_pci_cfg(pdev
, 0x68);
1282 DPRINTK("PCI regs:\n");
1283 mv_dump_mem(mmio_base
+0xc00, 0x3c);
1284 mv_dump_mem(mmio_base
+0xd00, 0x34);
1285 mv_dump_mem(mmio_base
+0xf00, 0x4);
1286 mv_dump_mem(mmio_base
+0x1d00, 0x6c);
1287 for (hc
= start_hc
; hc
< start_hc
+ num_hcs
; hc
++) {
1288 hc_base
= mv_hc_base(mmio_base
, hc
);
1289 DPRINTK("HC regs (HC %i):\n", hc
);
1290 mv_dump_mem(hc_base
, 0x1c);
1292 for (p
= start_port
; p
< start_port
+ num_ports
; p
++) {
1293 port_base
= mv_port_base(mmio_base
, p
);
1294 DPRINTK("EDMA regs (port %i):\n", p
);
1295 mv_dump_mem(port_base
, 0x54);
1296 DPRINTK("SATA regs (port %i):\n", p
);
1297 mv_dump_mem(port_base
+0x300, 0x60);
1302 static unsigned int mv_scr_offset(unsigned int sc_reg_in
)
1306 switch (sc_reg_in
) {
1310 ofs
= SATA_STATUS
+ (sc_reg_in
* sizeof(u32
));
1313 ofs
= SATA_ACTIVE
; /* active is not with the others */
1322 static int mv_scr_read(struct ata_link
*link
, unsigned int sc_reg_in
, u32
*val
)
1324 unsigned int ofs
= mv_scr_offset(sc_reg_in
);
1326 if (ofs
!= 0xffffffffU
) {
1327 *val
= readl(mv_ap_base(link
->ap
) + ofs
);
1333 static int mv_scr_write(struct ata_link
*link
, unsigned int sc_reg_in
, u32 val
)
1335 unsigned int ofs
= mv_scr_offset(sc_reg_in
);
1337 if (ofs
!= 0xffffffffU
) {
1338 void __iomem
*addr
= mv_ap_base(link
->ap
) + ofs
;
1339 if (sc_reg_in
== SCR_CONTROL
) {
1341 * Workaround for 88SX60x1 FEr SATA#26:
1343 * COMRESETs have to take care not to accidently
1344 * put the drive to sleep when writing SCR_CONTROL.
1345 * Setting bits 12..15 prevents this problem.
1347 * So if we see an outbound COMMRESET, set those bits.
1348 * Ditto for the followup write that clears the reset.
1350 * The proprietary driver does this for
1351 * all chip versions, and so do we.
1353 if ((val
& 0xf) == 1 || (readl(addr
) & 0xf) == 1)
1356 writelfl(val
, addr
);
1362 static void mv6_dev_config(struct ata_device
*adev
)
1365 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1367 * Gen-II does not support NCQ over a port multiplier
1368 * (no FIS-based switching).
1370 if (adev
->flags
& ATA_DFLAG_NCQ
) {
1371 if (sata_pmp_attached(adev
->link
->ap
)) {
1372 adev
->flags
&= ~ATA_DFLAG_NCQ
;
1373 ata_dev_printk(adev
, KERN_INFO
,
1374 "NCQ disabled for command-based switching\n");
1379 static int mv_qc_defer(struct ata_queued_cmd
*qc
)
1381 struct ata_link
*link
= qc
->dev
->link
;
1382 struct ata_port
*ap
= link
->ap
;
1383 struct mv_port_priv
*pp
= ap
->private_data
;
1386 * Don't allow new commands if we're in a delayed EH state
1387 * for NCQ and/or FIS-based switching.
1389 if (pp
->pp_flags
& MV_PP_FLAG_DELAYED_EH
)
1390 return ATA_DEFER_PORT
;
1392 /* PIO commands need exclusive link: no other commands [DMA or PIO]
1393 * can run concurrently.
1394 * set excl_link when we want to send a PIO command in DMA mode
1395 * or a non-NCQ command in NCQ mode.
1396 * When we receive a command from that link, and there are no
1397 * outstanding commands, mark a flag to clear excl_link and let
1398 * the command go through.
1400 if (unlikely(ap
->excl_link
)) {
1401 if (link
== ap
->excl_link
) {
1402 if (ap
->nr_active_links
)
1403 return ATA_DEFER_PORT
;
1404 qc
->flags
|= ATA_QCFLAG_CLEAR_EXCL
;
1407 return ATA_DEFER_PORT
;
1411 * If the port is completely idle, then allow the new qc.
1413 if (ap
->nr_active_links
== 0)
1417 * The port is operating in host queuing mode (EDMA) with NCQ
1418 * enabled, allow multiple NCQ commands. EDMA also allows
1419 * queueing multiple DMA commands but libata core currently
1422 if ((pp
->pp_flags
& MV_PP_FLAG_EDMA_EN
) &&
1423 (pp
->pp_flags
& MV_PP_FLAG_NCQ_EN
)) {
1424 if (ata_is_ncq(qc
->tf
.protocol
))
1427 ap
->excl_link
= link
;
1428 return ATA_DEFER_PORT
;
1432 return ATA_DEFER_PORT
;
1435 static void mv_config_fbs(struct ata_port
*ap
, int want_ncq
, int want_fbs
)
1437 struct mv_port_priv
*pp
= ap
->private_data
;
1438 void __iomem
*port_mmio
;
1440 u32 fiscfg
, *old_fiscfg
= &pp
->cached
.fiscfg
;
1441 u32 ltmode
, *old_ltmode
= &pp
->cached
.ltmode
;
1442 u32 haltcond
, *old_haltcond
= &pp
->cached
.haltcond
;
1444 ltmode
= *old_ltmode
& ~LTMODE_BIT8
;
1445 haltcond
= *old_haltcond
| EDMA_ERR_DEV
;
1448 fiscfg
= *old_fiscfg
| FISCFG_SINGLE_SYNC
;
1449 ltmode
= *old_ltmode
| LTMODE_BIT8
;
1451 haltcond
&= ~EDMA_ERR_DEV
;
1453 fiscfg
|= FISCFG_WAIT_DEV_ERR
;
1455 fiscfg
= *old_fiscfg
& ~(FISCFG_SINGLE_SYNC
| FISCFG_WAIT_DEV_ERR
);
1458 port_mmio
= mv_ap_base(ap
);
1459 mv_write_cached_reg(port_mmio
+ FISCFG
, old_fiscfg
, fiscfg
);
1460 mv_write_cached_reg(port_mmio
+ LTMODE
, old_ltmode
, ltmode
);
1461 mv_write_cached_reg(port_mmio
+ EDMA_HALTCOND
, old_haltcond
, haltcond
);
1464 static void mv_60x1_errata_sata25(struct ata_port
*ap
, int want_ncq
)
1466 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
1469 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1470 old
= readl(hpriv
->base
+ GPIO_PORT_CTL
);
1472 new = old
| (1 << 22);
1474 new = old
& ~(1 << 22);
1476 writel(new, hpriv
->base
+ GPIO_PORT_CTL
);
1480 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1481 * @ap: Port being initialized
1483 * There are two DMA modes on these chips: basic DMA, and EDMA.
1485 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1486 * of basic DMA on the GEN_IIE versions of the chips.
1488 * This bit survives EDMA resets, and must be set for basic DMA
1489 * to function, and should be cleared when EDMA is active.
1491 static void mv_bmdma_enable_iie(struct ata_port
*ap
, int enable_bmdma
)
1493 struct mv_port_priv
*pp
= ap
->private_data
;
1494 u32
new, *old
= &pp
->cached
.unknown_rsvd
;
1500 mv_write_cached_reg(mv_ap_base(ap
) + EDMA_UNKNOWN_RSVD
, old
, new);
1504 * SOC chips have an issue whereby the HDD LEDs don't always blink
1505 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1506 * of the SOC takes care of it, generating a steady blink rate when
1507 * any drive on the chip is active.
1509 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1510 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1512 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1513 * LED operation works then, and provides better (more accurate) feedback.
1515 * Note that this code assumes that an SOC never has more than one HC onboard.
1517 static void mv_soc_led_blink_enable(struct ata_port
*ap
)
1519 struct ata_host
*host
= ap
->host
;
1520 struct mv_host_priv
*hpriv
= host
->private_data
;
1521 void __iomem
*hc_mmio
;
1524 if (hpriv
->hp_flags
& MV_HP_QUIRK_LED_BLINK_EN
)
1526 hpriv
->hp_flags
|= MV_HP_QUIRK_LED_BLINK_EN
;
1527 hc_mmio
= mv_hc_base_from_port(mv_host_base(host
), ap
->port_no
);
1528 led_ctrl
= readl(hc_mmio
+ SOC_LED_CTRL
);
1529 writel(led_ctrl
| SOC_LED_CTRL_BLINK
, hc_mmio
+ SOC_LED_CTRL
);
1532 static void mv_soc_led_blink_disable(struct ata_port
*ap
)
1534 struct ata_host
*host
= ap
->host
;
1535 struct mv_host_priv
*hpriv
= host
->private_data
;
1536 void __iomem
*hc_mmio
;
1540 if (!(hpriv
->hp_flags
& MV_HP_QUIRK_LED_BLINK_EN
))
1543 /* disable led-blink only if no ports are using NCQ */
1544 for (port
= 0; port
< hpriv
->n_ports
; port
++) {
1545 struct ata_port
*this_ap
= host
->ports
[port
];
1546 struct mv_port_priv
*pp
= this_ap
->private_data
;
1548 if (pp
->pp_flags
& MV_PP_FLAG_NCQ_EN
)
1552 hpriv
->hp_flags
&= ~MV_HP_QUIRK_LED_BLINK_EN
;
1553 hc_mmio
= mv_hc_base_from_port(mv_host_base(host
), ap
->port_no
);
1554 led_ctrl
= readl(hc_mmio
+ SOC_LED_CTRL
);
1555 writel(led_ctrl
& ~SOC_LED_CTRL_BLINK
, hc_mmio
+ SOC_LED_CTRL
);
1558 static void mv_edma_cfg(struct ata_port
*ap
, int want_ncq
, int want_edma
)
1561 struct mv_port_priv
*pp
= ap
->private_data
;
1562 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
1563 void __iomem
*port_mmio
= mv_ap_base(ap
);
1565 /* set up non-NCQ EDMA configuration */
1566 cfg
= EDMA_CFG_Q_DEPTH
; /* always 0x1f for *all* chips */
1568 ~(MV_PP_FLAG_FBS_EN
| MV_PP_FLAG_NCQ_EN
| MV_PP_FLAG_FAKE_ATA_BUSY
);
1570 if (IS_GEN_I(hpriv
))
1571 cfg
|= (1 << 8); /* enab config burst size mask */
1573 else if (IS_GEN_II(hpriv
)) {
1574 cfg
|= EDMA_CFG_RD_BRST_EXT
| EDMA_CFG_WR_BUFF_LEN
;
1575 mv_60x1_errata_sata25(ap
, want_ncq
);
1577 } else if (IS_GEN_IIE(hpriv
)) {
1578 int want_fbs
= sata_pmp_attached(ap
);
1580 * Possible future enhancement:
1582 * The chip can use FBS with non-NCQ, if we allow it,
1583 * But first we need to have the error handling in place
1584 * for this mode (datasheet section 7.3.15.4.2.3).
1585 * So disallow non-NCQ FBS for now.
1587 want_fbs
&= want_ncq
;
1589 mv_config_fbs(ap
, want_ncq
, want_fbs
);
1592 pp
->pp_flags
|= MV_PP_FLAG_FBS_EN
;
1593 cfg
|= EDMA_CFG_EDMA_FBS
; /* FIS-based switching */
1596 cfg
|= (1 << 23); /* do not mask PM field in rx'd FIS */
1598 cfg
|= (1 << 22); /* enab 4-entry host queue cache */
1600 cfg
|= (1 << 18); /* enab early completion */
1602 if (hpriv
->hp_flags
& MV_HP_CUT_THROUGH
)
1603 cfg
|= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1604 mv_bmdma_enable_iie(ap
, !want_edma
);
1606 if (IS_SOC(hpriv
)) {
1608 mv_soc_led_blink_enable(ap
);
1610 mv_soc_led_blink_disable(ap
);
1615 cfg
|= EDMA_CFG_NCQ
;
1616 pp
->pp_flags
|= MV_PP_FLAG_NCQ_EN
;
1619 writelfl(cfg
, port_mmio
+ EDMA_CFG
);
1622 static void mv_port_free_dma_mem(struct ata_port
*ap
)
1624 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
1625 struct mv_port_priv
*pp
= ap
->private_data
;
1629 dma_pool_free(hpriv
->crqb_pool
, pp
->crqb
, pp
->crqb_dma
);
1633 dma_pool_free(hpriv
->crpb_pool
, pp
->crpb
, pp
->crpb_dma
);
1637 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1638 * For later hardware, we have one unique sg_tbl per NCQ tag.
1640 for (tag
= 0; tag
< MV_MAX_Q_DEPTH
; ++tag
) {
1641 if (pp
->sg_tbl
[tag
]) {
1642 if (tag
== 0 || !IS_GEN_I(hpriv
))
1643 dma_pool_free(hpriv
->sg_tbl_pool
,
1645 pp
->sg_tbl_dma
[tag
]);
1646 pp
->sg_tbl
[tag
] = NULL
;
1652 * mv_port_start - Port specific init/start routine.
1653 * @ap: ATA channel to manipulate
1655 * Allocate and point to DMA memory, init port private memory,
1659 * Inherited from caller.
1661 static int mv_port_start(struct ata_port
*ap
)
1663 struct device
*dev
= ap
->host
->dev
;
1664 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
1665 struct mv_port_priv
*pp
;
1666 unsigned long flags
;
1669 pp
= devm_kzalloc(dev
, sizeof(*pp
), GFP_KERNEL
);
1672 ap
->private_data
= pp
;
1674 pp
->crqb
= dma_pool_alloc(hpriv
->crqb_pool
, GFP_KERNEL
, &pp
->crqb_dma
);
1677 memset(pp
->crqb
, 0, MV_CRQB_Q_SZ
);
1679 pp
->crpb
= dma_pool_alloc(hpriv
->crpb_pool
, GFP_KERNEL
, &pp
->crpb_dma
);
1681 goto out_port_free_dma_mem
;
1682 memset(pp
->crpb
, 0, MV_CRPB_Q_SZ
);
1684 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1685 if (hpriv
->hp_flags
& MV_HP_ERRATA_60X1C0
)
1686 ap
->flags
|= ATA_FLAG_AN
;
1688 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1689 * For later hardware, we need one unique sg_tbl per NCQ tag.
1691 for (tag
= 0; tag
< MV_MAX_Q_DEPTH
; ++tag
) {
1692 if (tag
== 0 || !IS_GEN_I(hpriv
)) {
1693 pp
->sg_tbl
[tag
] = dma_pool_alloc(hpriv
->sg_tbl_pool
,
1694 GFP_KERNEL
, &pp
->sg_tbl_dma
[tag
]);
1695 if (!pp
->sg_tbl
[tag
])
1696 goto out_port_free_dma_mem
;
1698 pp
->sg_tbl
[tag
] = pp
->sg_tbl
[0];
1699 pp
->sg_tbl_dma
[tag
] = pp
->sg_tbl_dma
[0];
1703 spin_lock_irqsave(ap
->lock
, flags
);
1704 mv_save_cached_regs(ap
);
1705 mv_edma_cfg(ap
, 0, 0);
1706 spin_unlock_irqrestore(ap
->lock
, flags
);
1710 out_port_free_dma_mem
:
1711 mv_port_free_dma_mem(ap
);
1716 * mv_port_stop - Port specific cleanup/stop routine.
1717 * @ap: ATA channel to manipulate
1719 * Stop DMA, cleanup port memory.
1722 * This routine uses the host lock to protect the DMA stop.
1724 static void mv_port_stop(struct ata_port
*ap
)
1726 unsigned long flags
;
1728 spin_lock_irqsave(ap
->lock
, flags
);
1730 mv_enable_port_irqs(ap
, 0);
1731 spin_unlock_irqrestore(ap
->lock
, flags
);
1732 mv_port_free_dma_mem(ap
);
1736 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1737 * @qc: queued command whose SG list to source from
1739 * Populate the SG list and mark the last entry.
1742 * Inherited from caller.
1744 static void mv_fill_sg(struct ata_queued_cmd
*qc
)
1746 struct mv_port_priv
*pp
= qc
->ap
->private_data
;
1747 struct scatterlist
*sg
;
1748 struct mv_sg
*mv_sg
, *last_sg
= NULL
;
1751 mv_sg
= pp
->sg_tbl
[qc
->tag
];
1752 for_each_sg(qc
->sg
, sg
, qc
->n_elem
, si
) {
1753 dma_addr_t addr
= sg_dma_address(sg
);
1754 u32 sg_len
= sg_dma_len(sg
);
1757 u32 offset
= addr
& 0xffff;
1760 if (offset
+ len
> 0x10000)
1761 len
= 0x10000 - offset
;
1763 mv_sg
->addr
= cpu_to_le32(addr
& 0xffffffff);
1764 mv_sg
->addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
1765 mv_sg
->flags_size
= cpu_to_le32(len
& 0xffff);
1766 mv_sg
->reserved
= 0;
1776 if (likely(last_sg
))
1777 last_sg
->flags_size
|= cpu_to_le32(EPRD_FLAG_END_OF_TBL
);
1778 mb(); /* ensure data structure is visible to the chipset */
1781 static void mv_crqb_pack_cmd(__le16
*cmdw
, u8 data
, u8 addr
, unsigned last
)
1783 u16 tmp
= data
| (addr
<< CRQB_CMD_ADDR_SHIFT
) | CRQB_CMD_CS
|
1784 (last
? CRQB_CMD_LAST
: 0);
1785 *cmdw
= cpu_to_le16(tmp
);
1789 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1790 * @ap: Port associated with this ATA transaction.
1792 * We need this only for ATAPI bmdma transactions,
1793 * as otherwise we experience spurious interrupts
1794 * after libata-sff handles the bmdma interrupts.
1796 static void mv_sff_irq_clear(struct ata_port
*ap
)
1798 mv_clear_and_enable_port_irqs(ap
, mv_ap_base(ap
), ERR_IRQ
);
1802 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1803 * @qc: queued command to check for chipset/DMA compatibility.
1805 * The bmdma engines cannot handle speculative data sizes
1806 * (bytecount under/over flow). So only allow DMA for
1807 * data transfer commands with known data sizes.
1810 * Inherited from caller.
1812 static int mv_check_atapi_dma(struct ata_queued_cmd
*qc
)
1814 struct scsi_cmnd
*scmd
= qc
->scsicmd
;
1817 switch (scmd
->cmnd
[0]) {
1825 case GPCMD_SEND_DVD_STRUCTURE
:
1826 case GPCMD_SEND_CUE_SHEET
:
1827 return 0; /* DMA is safe */
1830 return -EOPNOTSUPP
; /* use PIO instead */
1834 * mv_bmdma_setup - Set up BMDMA transaction
1835 * @qc: queued command to prepare DMA for.
1838 * Inherited from caller.
1840 static void mv_bmdma_setup(struct ata_queued_cmd
*qc
)
1842 struct ata_port
*ap
= qc
->ap
;
1843 void __iomem
*port_mmio
= mv_ap_base(ap
);
1844 struct mv_port_priv
*pp
= ap
->private_data
;
1848 /* clear all DMA cmd bits */
1849 writel(0, port_mmio
+ BMDMA_CMD
);
1851 /* load PRD table addr. */
1852 writel((pp
->sg_tbl_dma
[qc
->tag
] >> 16) >> 16,
1853 port_mmio
+ BMDMA_PRD_HIGH
);
1854 writelfl(pp
->sg_tbl_dma
[qc
->tag
],
1855 port_mmio
+ BMDMA_PRD_LOW
);
1857 /* issue r/w command */
1858 ap
->ops
->sff_exec_command(ap
, &qc
->tf
);
1862 * mv_bmdma_start - Start a BMDMA transaction
1863 * @qc: queued command to start DMA on.
1866 * Inherited from caller.
1868 static void mv_bmdma_start(struct ata_queued_cmd
*qc
)
1870 struct ata_port
*ap
= qc
->ap
;
1871 void __iomem
*port_mmio
= mv_ap_base(ap
);
1872 unsigned int rw
= (qc
->tf
.flags
& ATA_TFLAG_WRITE
);
1873 u32 cmd
= (rw
? 0 : ATA_DMA_WR
) | ATA_DMA_START
;
1875 /* start host DMA transaction */
1876 writelfl(cmd
, port_mmio
+ BMDMA_CMD
);
1880 * mv_bmdma_stop - Stop BMDMA transfer
1881 * @qc: queued command to stop DMA on.
1883 * Clears the ATA_DMA_START flag in the bmdma control register
1886 * Inherited from caller.
1888 static void mv_bmdma_stop(struct ata_queued_cmd
*qc
)
1890 struct ata_port
*ap
= qc
->ap
;
1891 void __iomem
*port_mmio
= mv_ap_base(ap
);
1894 /* clear start/stop bit */
1895 cmd
= readl(port_mmio
+ BMDMA_CMD
);
1896 cmd
&= ~ATA_DMA_START
;
1897 writelfl(cmd
, port_mmio
+ BMDMA_CMD
);
1899 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1900 ata_sff_dma_pause(ap
);
1904 * mv_bmdma_status - Read BMDMA status
1905 * @ap: port for which to retrieve DMA status.
1907 * Read and return equivalent of the sff BMDMA status register.
1910 * Inherited from caller.
1912 static u8
mv_bmdma_status(struct ata_port
*ap
)
1914 void __iomem
*port_mmio
= mv_ap_base(ap
);
1918 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1919 * and the ATA_DMA_INTR bit doesn't exist.
1921 reg
= readl(port_mmio
+ BMDMA_STATUS
);
1922 if (reg
& ATA_DMA_ACTIVE
)
1923 status
= ATA_DMA_ACTIVE
;
1925 status
= (reg
& ATA_DMA_ERR
) | ATA_DMA_INTR
;
1929 static void mv_rw_multi_errata_sata24(struct ata_queued_cmd
*qc
)
1931 struct ata_taskfile
*tf
= &qc
->tf
;
1933 * Workaround for 88SX60x1 FEr SATA#24.
1935 * Chip may corrupt WRITEs if multi_count >= 4kB.
1936 * Note that READs are unaffected.
1938 * It's not clear if this errata really means "4K bytes",
1939 * or if it always happens for multi_count > 7
1940 * regardless of device sector_size.
1942 * So, for safety, any write with multi_count > 7
1943 * gets converted here into a regular PIO write instead:
1945 if ((tf
->flags
& ATA_TFLAG_WRITE
) && is_multi_taskfile(tf
)) {
1946 if (qc
->dev
->multi_count
> 7) {
1947 switch (tf
->command
) {
1948 case ATA_CMD_WRITE_MULTI
:
1949 tf
->command
= ATA_CMD_PIO_WRITE
;
1951 case ATA_CMD_WRITE_MULTI_FUA_EXT
:
1952 tf
->flags
&= ~ATA_TFLAG_FUA
; /* ugh */
1954 case ATA_CMD_WRITE_MULTI_EXT
:
1955 tf
->command
= ATA_CMD_PIO_WRITE_EXT
;
1963 * mv_qc_prep - Host specific command preparation.
1964 * @qc: queued command to prepare
1966 * This routine simply redirects to the general purpose routine
1967 * if command is not DMA. Else, it handles prep of the CRQB
1968 * (command request block), does some sanity checking, and calls
1969 * the SG load routine.
1972 * Inherited from caller.
1974 static void mv_qc_prep(struct ata_queued_cmd
*qc
)
1976 struct ata_port
*ap
= qc
->ap
;
1977 struct mv_port_priv
*pp
= ap
->private_data
;
1979 struct ata_taskfile
*tf
= &qc
->tf
;
1983 switch (tf
->protocol
) {
1986 break; /* continue below */
1988 mv_rw_multi_errata_sata24(qc
);
1994 /* Fill in command request block
1996 if (!(tf
->flags
& ATA_TFLAG_WRITE
))
1997 flags
|= CRQB_FLAG_READ
;
1998 WARN_ON(MV_MAX_Q_DEPTH
<= qc
->tag
);
1999 flags
|= qc
->tag
<< CRQB_TAG_SHIFT
;
2000 flags
|= (qc
->dev
->link
->pmp
& 0xf) << CRQB_PMP_SHIFT
;
2002 /* get current queue index from software */
2003 in_index
= pp
->req_idx
;
2005 pp
->crqb
[in_index
].sg_addr
=
2006 cpu_to_le32(pp
->sg_tbl_dma
[qc
->tag
] & 0xffffffff);
2007 pp
->crqb
[in_index
].sg_addr_hi
=
2008 cpu_to_le32((pp
->sg_tbl_dma
[qc
->tag
] >> 16) >> 16);
2009 pp
->crqb
[in_index
].ctrl_flags
= cpu_to_le16(flags
);
2011 cw
= &pp
->crqb
[in_index
].ata_cmd
[0];
2013 /* Sadly, the CRQB cannot accomodate all registers--there are
2014 * only 11 bytes...so we must pick and choose required
2015 * registers based on the command. So, we drop feature and
2016 * hob_feature for [RW] DMA commands, but they are needed for
2017 * NCQ. NCQ will drop hob_nsect, which is not needed there
2018 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
2020 switch (tf
->command
) {
2022 case ATA_CMD_READ_EXT
:
2024 case ATA_CMD_WRITE_EXT
:
2025 case ATA_CMD_WRITE_FUA_EXT
:
2026 mv_crqb_pack_cmd(cw
++, tf
->hob_nsect
, ATA_REG_NSECT
, 0);
2028 case ATA_CMD_FPDMA_READ
:
2029 case ATA_CMD_FPDMA_WRITE
:
2030 mv_crqb_pack_cmd(cw
++, tf
->hob_feature
, ATA_REG_FEATURE
, 0);
2031 mv_crqb_pack_cmd(cw
++, tf
->feature
, ATA_REG_FEATURE
, 0);
2034 /* The only other commands EDMA supports in non-queued and
2035 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
2036 * of which are defined/used by Linux. If we get here, this
2037 * driver needs work.
2039 * FIXME: modify libata to give qc_prep a return value and
2040 * return error here.
2042 BUG_ON(tf
->command
);
2045 mv_crqb_pack_cmd(cw
++, tf
->nsect
, ATA_REG_NSECT
, 0);
2046 mv_crqb_pack_cmd(cw
++, tf
->hob_lbal
, ATA_REG_LBAL
, 0);
2047 mv_crqb_pack_cmd(cw
++, tf
->lbal
, ATA_REG_LBAL
, 0);
2048 mv_crqb_pack_cmd(cw
++, tf
->hob_lbam
, ATA_REG_LBAM
, 0);
2049 mv_crqb_pack_cmd(cw
++, tf
->lbam
, ATA_REG_LBAM
, 0);
2050 mv_crqb_pack_cmd(cw
++, tf
->hob_lbah
, ATA_REG_LBAH
, 0);
2051 mv_crqb_pack_cmd(cw
++, tf
->lbah
, ATA_REG_LBAH
, 0);
2052 mv_crqb_pack_cmd(cw
++, tf
->device
, ATA_REG_DEVICE
, 0);
2053 mv_crqb_pack_cmd(cw
++, tf
->command
, ATA_REG_CMD
, 1); /* last */
2055 if (!(qc
->flags
& ATA_QCFLAG_DMAMAP
))
2061 * mv_qc_prep_iie - Host specific command preparation.
2062 * @qc: queued command to prepare
2064 * This routine simply redirects to the general purpose routine
2065 * if command is not DMA. Else, it handles prep of the CRQB
2066 * (command request block), does some sanity checking, and calls
2067 * the SG load routine.
2070 * Inherited from caller.
2072 static void mv_qc_prep_iie(struct ata_queued_cmd
*qc
)
2074 struct ata_port
*ap
= qc
->ap
;
2075 struct mv_port_priv
*pp
= ap
->private_data
;
2076 struct mv_crqb_iie
*crqb
;
2077 struct ata_taskfile
*tf
= &qc
->tf
;
2081 if ((tf
->protocol
!= ATA_PROT_DMA
) &&
2082 (tf
->protocol
!= ATA_PROT_NCQ
))
2085 /* Fill in Gen IIE command request block */
2086 if (!(tf
->flags
& ATA_TFLAG_WRITE
))
2087 flags
|= CRQB_FLAG_READ
;
2089 WARN_ON(MV_MAX_Q_DEPTH
<= qc
->tag
);
2090 flags
|= qc
->tag
<< CRQB_TAG_SHIFT
;
2091 flags
|= qc
->tag
<< CRQB_HOSTQ_SHIFT
;
2092 flags
|= (qc
->dev
->link
->pmp
& 0xf) << CRQB_PMP_SHIFT
;
2094 /* get current queue index from software */
2095 in_index
= pp
->req_idx
;
2097 crqb
= (struct mv_crqb_iie
*) &pp
->crqb
[in_index
];
2098 crqb
->addr
= cpu_to_le32(pp
->sg_tbl_dma
[qc
->tag
] & 0xffffffff);
2099 crqb
->addr_hi
= cpu_to_le32((pp
->sg_tbl_dma
[qc
->tag
] >> 16) >> 16);
2100 crqb
->flags
= cpu_to_le32(flags
);
2102 crqb
->ata_cmd
[0] = cpu_to_le32(
2103 (tf
->command
<< 16) |
2106 crqb
->ata_cmd
[1] = cpu_to_le32(
2112 crqb
->ata_cmd
[2] = cpu_to_le32(
2113 (tf
->hob_lbal
<< 0) |
2114 (tf
->hob_lbam
<< 8) |
2115 (tf
->hob_lbah
<< 16) |
2116 (tf
->hob_feature
<< 24)
2118 crqb
->ata_cmd
[3] = cpu_to_le32(
2120 (tf
->hob_nsect
<< 8)
2123 if (!(qc
->flags
& ATA_QCFLAG_DMAMAP
))
2129 * mv_sff_check_status - fetch device status, if valid
2130 * @ap: ATA port to fetch status from
2132 * When using command issue via mv_qc_issue_fis(),
2133 * the initial ATA_BUSY state does not show up in the
2134 * ATA status (shadow) register. This can confuse libata!
2136 * So we have a hook here to fake ATA_BUSY for that situation,
2137 * until the first time a BUSY, DRQ, or ERR bit is seen.
2139 * The rest of the time, it simply returns the ATA status register.
2141 static u8
mv_sff_check_status(struct ata_port
*ap
)
2143 u8 stat
= ioread8(ap
->ioaddr
.status_addr
);
2144 struct mv_port_priv
*pp
= ap
->private_data
;
2146 if (pp
->pp_flags
& MV_PP_FLAG_FAKE_ATA_BUSY
) {
2147 if (stat
& (ATA_BUSY
| ATA_DRQ
| ATA_ERR
))
2148 pp
->pp_flags
&= ~MV_PP_FLAG_FAKE_ATA_BUSY
;
2156 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2157 * @fis: fis to be sent
2158 * @nwords: number of 32-bit words in the fis
2160 static unsigned int mv_send_fis(struct ata_port
*ap
, u32
*fis
, int nwords
)
2162 void __iomem
*port_mmio
= mv_ap_base(ap
);
2163 u32 ifctl
, old_ifctl
, ifstat
;
2164 int i
, timeout
= 200, final_word
= nwords
- 1;
2166 /* Initiate FIS transmission mode */
2167 old_ifctl
= readl(port_mmio
+ SATA_IFCTL
);
2168 ifctl
= 0x100 | (old_ifctl
& 0xf);
2169 writelfl(ifctl
, port_mmio
+ SATA_IFCTL
);
2171 /* Send all words of the FIS except for the final word */
2172 for (i
= 0; i
< final_word
; ++i
)
2173 writel(fis
[i
], port_mmio
+ VENDOR_UNIQUE_FIS
);
2175 /* Flag end-of-transmission, and then send the final word */
2176 writelfl(ifctl
| 0x200, port_mmio
+ SATA_IFCTL
);
2177 writelfl(fis
[final_word
], port_mmio
+ VENDOR_UNIQUE_FIS
);
2180 * Wait for FIS transmission to complete.
2181 * This typically takes just a single iteration.
2184 ifstat
= readl(port_mmio
+ SATA_IFSTAT
);
2185 } while (!(ifstat
& 0x1000) && --timeout
);
2187 /* Restore original port configuration */
2188 writelfl(old_ifctl
, port_mmio
+ SATA_IFCTL
);
2190 /* See if it worked */
2191 if ((ifstat
& 0x3000) != 0x1000) {
2192 ata_port_printk(ap
, KERN_WARNING
,
2193 "%s transmission error, ifstat=%08x\n",
2195 return AC_ERR_OTHER
;
2201 * mv_qc_issue_fis - Issue a command directly as a FIS
2202 * @qc: queued command to start
2204 * Note that the ATA shadow registers are not updated
2205 * after command issue, so the device will appear "READY"
2206 * if polled, even while it is BUSY processing the command.
2208 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2210 * Note: we don't get updated shadow regs on *completion*
2211 * of non-data commands. So avoid sending them via this function,
2212 * as they will appear to have completed immediately.
2214 * GEN_IIE has special registers that we could get the result tf from,
2215 * but earlier chipsets do not. For now, we ignore those registers.
2217 static unsigned int mv_qc_issue_fis(struct ata_queued_cmd
*qc
)
2219 struct ata_port
*ap
= qc
->ap
;
2220 struct mv_port_priv
*pp
= ap
->private_data
;
2221 struct ata_link
*link
= qc
->dev
->link
;
2225 ata_tf_to_fis(&qc
->tf
, link
->pmp
, 1, (void *)fis
);
2226 err
= mv_send_fis(ap
, fis
, ARRAY_SIZE(fis
));
2230 switch (qc
->tf
.protocol
) {
2231 case ATAPI_PROT_PIO
:
2232 pp
->pp_flags
|= MV_PP_FLAG_FAKE_ATA_BUSY
;
2234 case ATAPI_PROT_NODATA
:
2235 ap
->hsm_task_state
= HSM_ST_FIRST
;
2238 pp
->pp_flags
|= MV_PP_FLAG_FAKE_ATA_BUSY
;
2239 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
)
2240 ap
->hsm_task_state
= HSM_ST_FIRST
;
2242 ap
->hsm_task_state
= HSM_ST
;
2245 ap
->hsm_task_state
= HSM_ST_LAST
;
2249 if (qc
->tf
.flags
& ATA_TFLAG_POLLING
)
2250 ata_pio_queue_task(ap
, qc
, 0);
2255 * mv_qc_issue - Initiate a command to the host
2256 * @qc: queued command to start
2258 * This routine simply redirects to the general purpose routine
2259 * if command is not DMA. Else, it sanity checks our local
2260 * caches of the request producer/consumer indices then enables
2261 * DMA and bumps the request producer index.
2264 * Inherited from caller.
2266 static unsigned int mv_qc_issue(struct ata_queued_cmd
*qc
)
2268 static int limit_warnings
= 10;
2269 struct ata_port
*ap
= qc
->ap
;
2270 void __iomem
*port_mmio
= mv_ap_base(ap
);
2271 struct mv_port_priv
*pp
= ap
->private_data
;
2273 unsigned int port_irqs
;
2275 pp
->pp_flags
&= ~MV_PP_FLAG_FAKE_ATA_BUSY
; /* paranoia */
2277 switch (qc
->tf
.protocol
) {
2280 mv_start_edma(ap
, port_mmio
, pp
, qc
->tf
.protocol
);
2281 pp
->req_idx
= (pp
->req_idx
+ 1) & MV_MAX_Q_DEPTH_MASK
;
2282 in_index
= pp
->req_idx
<< EDMA_REQ_Q_PTR_SHIFT
;
2284 /* Write the request in pointer to kick the EDMA to life */
2285 writelfl((pp
->crqb_dma
& EDMA_REQ_Q_BASE_LO_MASK
) | in_index
,
2286 port_mmio
+ EDMA_REQ_Q_IN_PTR
);
2291 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2293 * Someday, we might implement special polling workarounds
2294 * for these, but it all seems rather unnecessary since we
2295 * normally use only DMA for commands which transfer more
2296 * than a single block of data.
2298 * Much of the time, this could just work regardless.
2299 * So for now, just log the incident, and allow the attempt.
2301 if (limit_warnings
> 0 && (qc
->nbytes
/ qc
->sect_size
) > 1) {
2303 ata_link_printk(qc
->dev
->link
, KERN_WARNING
, DRV_NAME
2304 ": attempting PIO w/multiple DRQ: "
2305 "this may fail due to h/w errata\n");
2308 case ATA_PROT_NODATA
:
2309 case ATAPI_PROT_PIO
:
2310 case ATAPI_PROT_NODATA
:
2311 if (ap
->flags
& ATA_FLAG_PIO_POLLING
)
2312 qc
->tf
.flags
|= ATA_TFLAG_POLLING
;
2316 if (qc
->tf
.flags
& ATA_TFLAG_POLLING
)
2317 port_irqs
= ERR_IRQ
; /* mask device interrupt when polling */
2319 port_irqs
= ERR_IRQ
| DONE_IRQ
; /* unmask all interrupts */
2322 * We're about to send a non-EDMA capable command to the
2323 * port. Turn off EDMA so there won't be problems accessing
2324 * shadow block, etc registers.
2327 mv_clear_and_enable_port_irqs(ap
, mv_ap_base(ap
), port_irqs
);
2328 mv_pmp_select(ap
, qc
->dev
->link
->pmp
);
2330 if (qc
->tf
.command
== ATA_CMD_READ_LOG_EXT
) {
2331 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
2333 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
2335 * After any NCQ error, the READ_LOG_EXT command
2336 * from libata-eh *must* use mv_qc_issue_fis().
2337 * Otherwise it might fail, due to chip errata.
2339 * Rather than special-case it, we'll just *always*
2340 * use this method here for READ_LOG_EXT, making for
2343 if (IS_GEN_II(hpriv
))
2344 return mv_qc_issue_fis(qc
);
2346 return ata_sff_qc_issue(qc
);
2349 static struct ata_queued_cmd
*mv_get_active_qc(struct ata_port
*ap
)
2351 struct mv_port_priv
*pp
= ap
->private_data
;
2352 struct ata_queued_cmd
*qc
;
2354 if (pp
->pp_flags
& MV_PP_FLAG_NCQ_EN
)
2356 qc
= ata_qc_from_tag(ap
, ap
->link
.active_tag
);
2358 if (qc
->tf
.flags
& ATA_TFLAG_POLLING
)
2360 else if (!(qc
->flags
& ATA_QCFLAG_ACTIVE
))
2366 static void mv_pmp_error_handler(struct ata_port
*ap
)
2368 unsigned int pmp
, pmp_map
;
2369 struct mv_port_priv
*pp
= ap
->private_data
;
2371 if (pp
->pp_flags
& MV_PP_FLAG_DELAYED_EH
) {
2373 * Perform NCQ error analysis on failed PMPs
2374 * before we freeze the port entirely.
2376 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2378 pmp_map
= pp
->delayed_eh_pmp_map
;
2379 pp
->pp_flags
&= ~MV_PP_FLAG_DELAYED_EH
;
2380 for (pmp
= 0; pmp_map
!= 0; pmp
++) {
2381 unsigned int this_pmp
= (1 << pmp
);
2382 if (pmp_map
& this_pmp
) {
2383 struct ata_link
*link
= &ap
->pmp_link
[pmp
];
2384 pmp_map
&= ~this_pmp
;
2385 ata_eh_analyze_ncq_error(link
);
2388 ata_port_freeze(ap
);
2390 sata_pmp_error_handler(ap
);
2393 static unsigned int mv_get_err_pmp_map(struct ata_port
*ap
)
2395 void __iomem
*port_mmio
= mv_ap_base(ap
);
2397 return readl(port_mmio
+ SATA_TESTCTL
) >> 16;
2400 static void mv_pmp_eh_prep(struct ata_port
*ap
, unsigned int pmp_map
)
2402 struct ata_eh_info
*ehi
;
2406 * Initialize EH info for PMPs which saw device errors
2408 ehi
= &ap
->link
.eh_info
;
2409 for (pmp
= 0; pmp_map
!= 0; pmp
++) {
2410 unsigned int this_pmp
= (1 << pmp
);
2411 if (pmp_map
& this_pmp
) {
2412 struct ata_link
*link
= &ap
->pmp_link
[pmp
];
2414 pmp_map
&= ~this_pmp
;
2415 ehi
= &link
->eh_info
;
2416 ata_ehi_clear_desc(ehi
);
2417 ata_ehi_push_desc(ehi
, "dev err");
2418 ehi
->err_mask
|= AC_ERR_DEV
;
2419 ehi
->action
|= ATA_EH_RESET
;
2420 ata_link_abort(link
);
2425 static int mv_req_q_empty(struct ata_port
*ap
)
2427 void __iomem
*port_mmio
= mv_ap_base(ap
);
2428 u32 in_ptr
, out_ptr
;
2430 in_ptr
= (readl(port_mmio
+ EDMA_REQ_Q_IN_PTR
)
2431 >> EDMA_REQ_Q_PTR_SHIFT
) & MV_MAX_Q_DEPTH_MASK
;
2432 out_ptr
= (readl(port_mmio
+ EDMA_REQ_Q_OUT_PTR
)
2433 >> EDMA_REQ_Q_PTR_SHIFT
) & MV_MAX_Q_DEPTH_MASK
;
2434 return (in_ptr
== out_ptr
); /* 1 == queue_is_empty */
2437 static int mv_handle_fbs_ncq_dev_err(struct ata_port
*ap
)
2439 struct mv_port_priv
*pp
= ap
->private_data
;
2441 unsigned int old_map
, new_map
;
2444 * Device error during FBS+NCQ operation:
2446 * Set a port flag to prevent further I/O being enqueued.
2447 * Leave the EDMA running to drain outstanding commands from this port.
2448 * Perform the post-mortem/EH only when all responses are complete.
2449 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2451 if (!(pp
->pp_flags
& MV_PP_FLAG_DELAYED_EH
)) {
2452 pp
->pp_flags
|= MV_PP_FLAG_DELAYED_EH
;
2453 pp
->delayed_eh_pmp_map
= 0;
2455 old_map
= pp
->delayed_eh_pmp_map
;
2456 new_map
= old_map
| mv_get_err_pmp_map(ap
);
2458 if (old_map
!= new_map
) {
2459 pp
->delayed_eh_pmp_map
= new_map
;
2460 mv_pmp_eh_prep(ap
, new_map
& ~old_map
);
2462 failed_links
= hweight16(new_map
);
2464 ata_port_printk(ap
, KERN_INFO
, "%s: pmp_map=%04x qc_map=%04x "
2465 "failed_links=%d nr_active_links=%d\n",
2466 __func__
, pp
->delayed_eh_pmp_map
,
2467 ap
->qc_active
, failed_links
,
2468 ap
->nr_active_links
);
2470 if (ap
->nr_active_links
<= failed_links
&& mv_req_q_empty(ap
)) {
2471 mv_process_crpb_entries(ap
, pp
);
2474 ata_port_printk(ap
, KERN_INFO
, "%s: done\n", __func__
);
2475 return 1; /* handled */
2477 ata_port_printk(ap
, KERN_INFO
, "%s: waiting\n", __func__
);
2478 return 1; /* handled */
2481 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port
*ap
)
2484 * Possible future enhancement:
2486 * FBS+non-NCQ operation is not yet implemented.
2487 * See related notes in mv_edma_cfg().
2489 * Device error during FBS+non-NCQ operation:
2491 * We need to snapshot the shadow registers for each failed command.
2492 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2494 return 0; /* not handled */
2497 static int mv_handle_dev_err(struct ata_port
*ap
, u32 edma_err_cause
)
2499 struct mv_port_priv
*pp
= ap
->private_data
;
2501 if (!(pp
->pp_flags
& MV_PP_FLAG_EDMA_EN
))
2502 return 0; /* EDMA was not active: not handled */
2503 if (!(pp
->pp_flags
& MV_PP_FLAG_FBS_EN
))
2504 return 0; /* FBS was not active: not handled */
2506 if (!(edma_err_cause
& EDMA_ERR_DEV
))
2507 return 0; /* non DEV error: not handled */
2508 edma_err_cause
&= ~EDMA_ERR_IRQ_TRANSIENT
;
2509 if (edma_err_cause
& ~(EDMA_ERR_DEV
| EDMA_ERR_SELF_DIS
))
2510 return 0; /* other problems: not handled */
2512 if (pp
->pp_flags
& MV_PP_FLAG_NCQ_EN
) {
2514 * EDMA should NOT have self-disabled for this case.
2515 * If it did, then something is wrong elsewhere,
2516 * and we cannot handle it here.
2518 if (edma_err_cause
& EDMA_ERR_SELF_DIS
) {
2519 ata_port_printk(ap
, KERN_WARNING
,
2520 "%s: err_cause=0x%x pp_flags=0x%x\n",
2521 __func__
, edma_err_cause
, pp
->pp_flags
);
2522 return 0; /* not handled */
2524 return mv_handle_fbs_ncq_dev_err(ap
);
2527 * EDMA should have self-disabled for this case.
2528 * If it did not, then something is wrong elsewhere,
2529 * and we cannot handle it here.
2531 if (!(edma_err_cause
& EDMA_ERR_SELF_DIS
)) {
2532 ata_port_printk(ap
, KERN_WARNING
,
2533 "%s: err_cause=0x%x pp_flags=0x%x\n",
2534 __func__
, edma_err_cause
, pp
->pp_flags
);
2535 return 0; /* not handled */
2537 return mv_handle_fbs_non_ncq_dev_err(ap
);
2539 return 0; /* not handled */
2542 static void mv_unexpected_intr(struct ata_port
*ap
, int edma_was_enabled
)
2544 struct ata_eh_info
*ehi
= &ap
->link
.eh_info
;
2545 char *when
= "idle";
2547 ata_ehi_clear_desc(ehi
);
2548 if (ap
->flags
& ATA_FLAG_DISABLED
) {
2550 } else if (edma_was_enabled
) {
2551 when
= "EDMA enabled";
2553 struct ata_queued_cmd
*qc
= ata_qc_from_tag(ap
, ap
->link
.active_tag
);
2554 if (qc
&& (qc
->tf
.flags
& ATA_TFLAG_POLLING
))
2557 ata_ehi_push_desc(ehi
, "unexpected device interrupt while %s", when
);
2558 ehi
->err_mask
|= AC_ERR_OTHER
;
2559 ehi
->action
|= ATA_EH_RESET
;
2560 ata_port_freeze(ap
);
2564 * mv_err_intr - Handle error interrupts on the port
2565 * @ap: ATA channel to manipulate
2567 * Most cases require a full reset of the chip's state machine,
2568 * which also performs a COMRESET.
2569 * Also, if the port disabled DMA, update our cached copy to match.
2572 * Inherited from caller.
2574 static void mv_err_intr(struct ata_port
*ap
)
2576 void __iomem
*port_mmio
= mv_ap_base(ap
);
2577 u32 edma_err_cause
, eh_freeze_mask
, serr
= 0;
2579 struct mv_port_priv
*pp
= ap
->private_data
;
2580 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
2581 unsigned int action
= 0, err_mask
= 0;
2582 struct ata_eh_info
*ehi
= &ap
->link
.eh_info
;
2583 struct ata_queued_cmd
*qc
;
2587 * Read and clear the SError and err_cause bits.
2588 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2589 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
2591 sata_scr_read(&ap
->link
, SCR_ERROR
, &serr
);
2592 sata_scr_write_flush(&ap
->link
, SCR_ERROR
, serr
);
2594 edma_err_cause
= readl(port_mmio
+ EDMA_ERR_IRQ_CAUSE
);
2595 if (IS_GEN_IIE(hpriv
) && (edma_err_cause
& EDMA_ERR_TRANS_IRQ_7
)) {
2596 fis_cause
= readl(port_mmio
+ FIS_IRQ_CAUSE
);
2597 writelfl(~fis_cause
, port_mmio
+ FIS_IRQ_CAUSE
);
2599 writelfl(~edma_err_cause
, port_mmio
+ EDMA_ERR_IRQ_CAUSE
);
2601 if (edma_err_cause
& EDMA_ERR_DEV
) {
2603 * Device errors during FIS-based switching operation
2604 * require special handling.
2606 if (mv_handle_dev_err(ap
, edma_err_cause
))
2610 qc
= mv_get_active_qc(ap
);
2611 ata_ehi_clear_desc(ehi
);
2612 ata_ehi_push_desc(ehi
, "edma_err_cause=%08x pp_flags=%08x",
2613 edma_err_cause
, pp
->pp_flags
);
2615 if (IS_GEN_IIE(hpriv
) && (edma_err_cause
& EDMA_ERR_TRANS_IRQ_7
)) {
2616 ata_ehi_push_desc(ehi
, "fis_cause=%08x", fis_cause
);
2617 if (fis_cause
& FIS_IRQ_CAUSE_AN
) {
2618 u32 ec
= edma_err_cause
&
2619 ~(EDMA_ERR_TRANS_IRQ_7
| EDMA_ERR_IRQ_TRANSIENT
);
2620 sata_async_notification(ap
);
2622 return; /* Just an AN; no need for the nukes */
2623 ata_ehi_push_desc(ehi
, "SDB notify");
2627 * All generations share these EDMA error cause bits:
2629 if (edma_err_cause
& EDMA_ERR_DEV
) {
2630 err_mask
|= AC_ERR_DEV
;
2631 action
|= ATA_EH_RESET
;
2632 ata_ehi_push_desc(ehi
, "dev error");
2634 if (edma_err_cause
& (EDMA_ERR_D_PAR
| EDMA_ERR_PRD_PAR
|
2635 EDMA_ERR_CRQB_PAR
| EDMA_ERR_CRPB_PAR
|
2636 EDMA_ERR_INTRL_PAR
)) {
2637 err_mask
|= AC_ERR_ATA_BUS
;
2638 action
|= ATA_EH_RESET
;
2639 ata_ehi_push_desc(ehi
, "parity error");
2641 if (edma_err_cause
& (EDMA_ERR_DEV_DCON
| EDMA_ERR_DEV_CON
)) {
2642 ata_ehi_hotplugged(ehi
);
2643 ata_ehi_push_desc(ehi
, edma_err_cause
& EDMA_ERR_DEV_DCON
?
2644 "dev disconnect" : "dev connect");
2645 action
|= ATA_EH_RESET
;
2649 * Gen-I has a different SELF_DIS bit,
2650 * different FREEZE bits, and no SERR bit:
2652 if (IS_GEN_I(hpriv
)) {
2653 eh_freeze_mask
= EDMA_EH_FREEZE_5
;
2654 if (edma_err_cause
& EDMA_ERR_SELF_DIS_5
) {
2655 pp
->pp_flags
&= ~MV_PP_FLAG_EDMA_EN
;
2656 ata_ehi_push_desc(ehi
, "EDMA self-disable");
2659 eh_freeze_mask
= EDMA_EH_FREEZE
;
2660 if (edma_err_cause
& EDMA_ERR_SELF_DIS
) {
2661 pp
->pp_flags
&= ~MV_PP_FLAG_EDMA_EN
;
2662 ata_ehi_push_desc(ehi
, "EDMA self-disable");
2664 if (edma_err_cause
& EDMA_ERR_SERR
) {
2665 ata_ehi_push_desc(ehi
, "SError=%08x", serr
);
2666 err_mask
|= AC_ERR_ATA_BUS
;
2667 action
|= ATA_EH_RESET
;
2672 err_mask
= AC_ERR_OTHER
;
2673 action
|= ATA_EH_RESET
;
2676 ehi
->serror
|= serr
;
2677 ehi
->action
|= action
;
2680 qc
->err_mask
|= err_mask
;
2682 ehi
->err_mask
|= err_mask
;
2684 if (err_mask
== AC_ERR_DEV
) {
2686 * Cannot do ata_port_freeze() here,
2687 * because it would kill PIO access,
2688 * which is needed for further diagnosis.
2692 } else if (edma_err_cause
& eh_freeze_mask
) {
2694 * Note to self: ata_port_freeze() calls ata_port_abort()
2696 ata_port_freeze(ap
);
2703 ata_link_abort(qc
->dev
->link
);
2709 static void mv_process_crpb_response(struct ata_port
*ap
,
2710 struct mv_crpb
*response
, unsigned int tag
, int ncq_enabled
)
2712 struct ata_queued_cmd
*qc
= ata_qc_from_tag(ap
, tag
);
2716 u16 edma_status
= le16_to_cpu(response
->flags
);
2718 * edma_status from a response queue entry:
2719 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
2720 * MSB is saved ATA status from command completion.
2723 u8 err_cause
= edma_status
& 0xff & ~EDMA_ERR_DEV
;
2726 * Error will be seen/handled by mv_err_intr().
2727 * So do nothing at all here.
2732 ata_status
= edma_status
>> CRPB_FLAG_STATUS_SHIFT
;
2733 if (!ac_err_mask(ata_status
))
2734 ata_qc_complete(qc
);
2735 /* else: leave it for mv_err_intr() */
2737 ata_port_printk(ap
, KERN_ERR
, "%s: no qc for tag=%d\n",
2742 static void mv_process_crpb_entries(struct ata_port
*ap
, struct mv_port_priv
*pp
)
2744 void __iomem
*port_mmio
= mv_ap_base(ap
);
2745 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
2747 bool work_done
= false;
2748 int ncq_enabled
= (pp
->pp_flags
& MV_PP_FLAG_NCQ_EN
);
2750 /* Get the hardware queue position index */
2751 in_index
= (readl(port_mmio
+ EDMA_RSP_Q_IN_PTR
)
2752 >> EDMA_RSP_Q_PTR_SHIFT
) & MV_MAX_Q_DEPTH_MASK
;
2754 /* Process new responses from since the last time we looked */
2755 while (in_index
!= pp
->resp_idx
) {
2757 struct mv_crpb
*response
= &pp
->crpb
[pp
->resp_idx
];
2759 pp
->resp_idx
= (pp
->resp_idx
+ 1) & MV_MAX_Q_DEPTH_MASK
;
2761 if (IS_GEN_I(hpriv
)) {
2762 /* 50xx: no NCQ, only one command active at a time */
2763 tag
= ap
->link
.active_tag
;
2765 /* Gen II/IIE: get command tag from CRPB entry */
2766 tag
= le16_to_cpu(response
->id
) & 0x1f;
2768 mv_process_crpb_response(ap
, response
, tag
, ncq_enabled
);
2772 /* Update the software queue position index in hardware */
2774 writelfl((pp
->crpb_dma
& EDMA_RSP_Q_BASE_LO_MASK
) |
2775 (pp
->resp_idx
<< EDMA_RSP_Q_PTR_SHIFT
),
2776 port_mmio
+ EDMA_RSP_Q_OUT_PTR
);
2779 static void mv_port_intr(struct ata_port
*ap
, u32 port_cause
)
2781 struct mv_port_priv
*pp
;
2782 int edma_was_enabled
;
2784 if (ap
->flags
& ATA_FLAG_DISABLED
) {
2785 mv_unexpected_intr(ap
, 0);
2789 * Grab a snapshot of the EDMA_EN flag setting,
2790 * so that we have a consistent view for this port,
2791 * even if something we call of our routines changes it.
2793 pp
= ap
->private_data
;
2794 edma_was_enabled
= (pp
->pp_flags
& MV_PP_FLAG_EDMA_EN
);
2796 * Process completed CRPB response(s) before other events.
2798 if (edma_was_enabled
&& (port_cause
& DONE_IRQ
)) {
2799 mv_process_crpb_entries(ap
, pp
);
2800 if (pp
->pp_flags
& MV_PP_FLAG_DELAYED_EH
)
2801 mv_handle_fbs_ncq_dev_err(ap
);
2804 * Handle chip-reported errors, or continue on to handle PIO.
2806 if (unlikely(port_cause
& ERR_IRQ
)) {
2808 } else if (!edma_was_enabled
) {
2809 struct ata_queued_cmd
*qc
= mv_get_active_qc(ap
);
2811 ata_sff_host_intr(ap
, qc
);
2813 mv_unexpected_intr(ap
, edma_was_enabled
);
2818 * mv_host_intr - Handle all interrupts on the given host controller
2819 * @host: host specific structure
2820 * @main_irq_cause: Main interrupt cause register for the chip.
2823 * Inherited from caller.
2825 static int mv_host_intr(struct ata_host
*host
, u32 main_irq_cause
)
2827 struct mv_host_priv
*hpriv
= host
->private_data
;
2828 void __iomem
*mmio
= hpriv
->base
, *hc_mmio
;
2829 unsigned int handled
= 0, port
;
2831 /* If asserted, clear the "all ports" IRQ coalescing bit */
2832 if (main_irq_cause
& ALL_PORTS_COAL_DONE
)
2833 writel(~ALL_PORTS_COAL_IRQ
, mmio
+ IRQ_COAL_CAUSE
);
2835 for (port
= 0; port
< hpriv
->n_ports
; port
++) {
2836 struct ata_port
*ap
= host
->ports
[port
];
2837 unsigned int p
, shift
, hardport
, port_cause
;
2839 MV_PORT_TO_SHIFT_AND_HARDPORT(port
, shift
, hardport
);
2841 * Each hc within the host has its own hc_irq_cause register,
2842 * where the interrupting ports bits get ack'd.
2844 if (hardport
== 0) { /* first port on this hc ? */
2845 u32 hc_cause
= (main_irq_cause
>> shift
) & HC0_IRQ_PEND
;
2846 u32 port_mask
, ack_irqs
;
2848 * Skip this entire hc if nothing pending for any ports
2851 port
+= MV_PORTS_PER_HC
- 1;
2855 * We don't need/want to read the hc_irq_cause register,
2856 * because doing so hurts performance, and
2857 * main_irq_cause already gives us everything we need.
2859 * But we do have to *write* to the hc_irq_cause to ack
2860 * the ports that we are handling this time through.
2862 * This requires that we create a bitmap for those
2863 * ports which interrupted us, and use that bitmap
2864 * to ack (only) those ports via hc_irq_cause.
2867 if (hc_cause
& PORTS_0_3_COAL_DONE
)
2868 ack_irqs
= HC_COAL_IRQ
;
2869 for (p
= 0; p
< MV_PORTS_PER_HC
; ++p
) {
2870 if ((port
+ p
) >= hpriv
->n_ports
)
2872 port_mask
= (DONE_IRQ
| ERR_IRQ
) << (p
* 2);
2873 if (hc_cause
& port_mask
)
2874 ack_irqs
|= (DMA_IRQ
| DEV_IRQ
) << p
;
2876 hc_mmio
= mv_hc_base_from_port(mmio
, port
);
2877 writelfl(~ack_irqs
, hc_mmio
+ HC_IRQ_CAUSE
);
2881 * Handle interrupts signalled for this port:
2883 port_cause
= (main_irq_cause
>> shift
) & (DONE_IRQ
| ERR_IRQ
);
2885 mv_port_intr(ap
, port_cause
);
2890 static int mv_pci_error(struct ata_host
*host
, void __iomem
*mmio
)
2892 struct mv_host_priv
*hpriv
= host
->private_data
;
2893 struct ata_port
*ap
;
2894 struct ata_queued_cmd
*qc
;
2895 struct ata_eh_info
*ehi
;
2896 unsigned int i
, err_mask
, printed
= 0;
2899 err_cause
= readl(mmio
+ hpriv
->irq_cause_offset
);
2901 dev_printk(KERN_ERR
, host
->dev
, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2904 DPRINTK("All regs @ PCI error\n");
2905 mv_dump_all_regs(mmio
, -1, to_pci_dev(host
->dev
));
2907 writelfl(0, mmio
+ hpriv
->irq_cause_offset
);
2909 for (i
= 0; i
< host
->n_ports
; i
++) {
2910 ap
= host
->ports
[i
];
2911 if (!ata_link_offline(&ap
->link
)) {
2912 ehi
= &ap
->link
.eh_info
;
2913 ata_ehi_clear_desc(ehi
);
2915 ata_ehi_push_desc(ehi
,
2916 "PCI err cause 0x%08x", err_cause
);
2917 err_mask
= AC_ERR_HOST_BUS
;
2918 ehi
->action
= ATA_EH_RESET
;
2919 qc
= ata_qc_from_tag(ap
, ap
->link
.active_tag
);
2921 qc
->err_mask
|= err_mask
;
2923 ehi
->err_mask
|= err_mask
;
2925 ata_port_freeze(ap
);
2928 return 1; /* handled */
2932 * mv_interrupt - Main interrupt event handler
2934 * @dev_instance: private data; in this case the host structure
2936 * Read the read only register to determine if any host
2937 * controllers have pending interrupts. If so, call lower level
2938 * routine to handle. Also check for PCI errors which are only
2942 * This routine holds the host lock while processing pending
2945 static irqreturn_t
mv_interrupt(int irq
, void *dev_instance
)
2947 struct ata_host
*host
= dev_instance
;
2948 struct mv_host_priv
*hpriv
= host
->private_data
;
2949 unsigned int handled
= 0;
2950 int using_msi
= hpriv
->hp_flags
& MV_HP_FLAG_MSI
;
2951 u32 main_irq_cause
, pending_irqs
;
2953 spin_lock(&host
->lock
);
2955 /* for MSI: block new interrupts while in here */
2957 mv_write_main_irq_mask(0, hpriv
);
2959 main_irq_cause
= readl(hpriv
->main_irq_cause_addr
);
2960 pending_irqs
= main_irq_cause
& hpriv
->main_irq_mask
;
2962 * Deal with cases where we either have nothing pending, or have read
2963 * a bogus register value which can indicate HW removal or PCI fault.
2965 if (pending_irqs
&& main_irq_cause
!= 0xffffffffU
) {
2966 if (unlikely((pending_irqs
& PCI_ERR
) && !IS_SOC(hpriv
)))
2967 handled
= mv_pci_error(host
, hpriv
->base
);
2969 handled
= mv_host_intr(host
, pending_irqs
);
2972 /* for MSI: unmask; interrupt cause bits will retrigger now */
2974 mv_write_main_irq_mask(hpriv
->main_irq_mask
, hpriv
);
2976 spin_unlock(&host
->lock
);
2978 return IRQ_RETVAL(handled
);
2981 static unsigned int mv5_scr_offset(unsigned int sc_reg_in
)
2985 switch (sc_reg_in
) {
2989 ofs
= sc_reg_in
* sizeof(u32
);
2998 static int mv5_scr_read(struct ata_link
*link
, unsigned int sc_reg_in
, u32
*val
)
3000 struct mv_host_priv
*hpriv
= link
->ap
->host
->private_data
;
3001 void __iomem
*mmio
= hpriv
->base
;
3002 void __iomem
*addr
= mv5_phy_base(mmio
, link
->ap
->port_no
);
3003 unsigned int ofs
= mv5_scr_offset(sc_reg_in
);
3005 if (ofs
!= 0xffffffffU
) {
3006 *val
= readl(addr
+ ofs
);
3012 static int mv5_scr_write(struct ata_link
*link
, unsigned int sc_reg_in
, u32 val
)
3014 struct mv_host_priv
*hpriv
= link
->ap
->host
->private_data
;
3015 void __iomem
*mmio
= hpriv
->base
;
3016 void __iomem
*addr
= mv5_phy_base(mmio
, link
->ap
->port_no
);
3017 unsigned int ofs
= mv5_scr_offset(sc_reg_in
);
3019 if (ofs
!= 0xffffffffU
) {
3020 writelfl(val
, addr
+ ofs
);
3026 static void mv5_reset_bus(struct ata_host
*host
, void __iomem
*mmio
)
3028 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
3031 early_5080
= (pdev
->device
== 0x5080) && (pdev
->revision
== 0);
3034 u32 tmp
= readl(mmio
+ MV_PCI_EXP_ROM_BAR_CTL
);
3036 writel(tmp
, mmio
+ MV_PCI_EXP_ROM_BAR_CTL
);
3039 mv_reset_pci_bus(host
, mmio
);
3042 static void mv5_reset_flash(struct mv_host_priv
*hpriv
, void __iomem
*mmio
)
3044 writel(0x0fcfffff, mmio
+ FLASH_CTL
);
3047 static void mv5_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
3050 void __iomem
*phy_mmio
= mv5_phy_base(mmio
, idx
);
3053 tmp
= readl(phy_mmio
+ MV5_PHY_MODE
);
3055 hpriv
->signal
[idx
].pre
= tmp
& 0x1800; /* bits 12:11 */
3056 hpriv
->signal
[idx
].amps
= tmp
& 0xe0; /* bits 7:5 */
3059 static void mv5_enable_leds(struct mv_host_priv
*hpriv
, void __iomem
*mmio
)
3063 writel(0, mmio
+ GPIO_PORT_CTL
);
3065 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
3067 tmp
= readl(mmio
+ MV_PCI_EXP_ROM_BAR_CTL
);
3069 writel(tmp
, mmio
+ MV_PCI_EXP_ROM_BAR_CTL
);
3072 static void mv5_phy_errata(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
3075 void __iomem
*phy_mmio
= mv5_phy_base(mmio
, port
);
3076 const u32 mask
= (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
3078 int fix_apm_sq
= (hpriv
->hp_flags
& MV_HP_ERRATA_50XXB0
);
3081 tmp
= readl(phy_mmio
+ MV5_LTMODE
);
3083 writel(tmp
, phy_mmio
+ MV5_LTMODE
);
3085 tmp
= readl(phy_mmio
+ MV5_PHY_CTL
);
3088 writel(tmp
, phy_mmio
+ MV5_PHY_CTL
);
3091 tmp
= readl(phy_mmio
+ MV5_PHY_MODE
);
3093 tmp
|= hpriv
->signal
[port
].pre
;
3094 tmp
|= hpriv
->signal
[port
].amps
;
3095 writel(tmp
, phy_mmio
+ MV5_PHY_MODE
);
3100 #define ZERO(reg) writel(0, port_mmio + (reg))
3101 static void mv5_reset_hc_port(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
3104 void __iomem
*port_mmio
= mv_port_base(mmio
, port
);
3106 mv_reset_channel(hpriv
, mmio
, port
);
3108 ZERO(0x028); /* command */
3109 writel(0x11f, port_mmio
+ EDMA_CFG
);
3110 ZERO(0x004); /* timer */
3111 ZERO(0x008); /* irq err cause */
3112 ZERO(0x00c); /* irq err mask */
3113 ZERO(0x010); /* rq bah */
3114 ZERO(0x014); /* rq inp */
3115 ZERO(0x018); /* rq outp */
3116 ZERO(0x01c); /* respq bah */
3117 ZERO(0x024); /* respq outp */
3118 ZERO(0x020); /* respq inp */
3119 ZERO(0x02c); /* test control */
3120 writel(0xbc, port_mmio
+ EDMA_IORDY_TMOUT
);
3124 #define ZERO(reg) writel(0, hc_mmio + (reg))
3125 static void mv5_reset_one_hc(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
3128 void __iomem
*hc_mmio
= mv_hc_base(mmio
, hc
);
3136 tmp
= readl(hc_mmio
+ 0x20);
3139 writel(tmp
, hc_mmio
+ 0x20);
3143 static int mv5_reset_hc(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
3146 unsigned int hc
, port
;
3148 for (hc
= 0; hc
< n_hc
; hc
++) {
3149 for (port
= 0; port
< MV_PORTS_PER_HC
; port
++)
3150 mv5_reset_hc_port(hpriv
, mmio
,
3151 (hc
* MV_PORTS_PER_HC
) + port
);
3153 mv5_reset_one_hc(hpriv
, mmio
, hc
);
3160 #define ZERO(reg) writel(0, mmio + (reg))
3161 static void mv_reset_pci_bus(struct ata_host
*host
, void __iomem
*mmio
)
3163 struct mv_host_priv
*hpriv
= host
->private_data
;
3166 tmp
= readl(mmio
+ MV_PCI_MODE
);
3168 writel(tmp
, mmio
+ MV_PCI_MODE
);
3170 ZERO(MV_PCI_DISC_TIMER
);
3171 ZERO(MV_PCI_MSI_TRIGGER
);
3172 writel(0x000100ff, mmio
+ MV_PCI_XBAR_TMOUT
);
3173 ZERO(MV_PCI_SERR_MASK
);
3174 ZERO(hpriv
->irq_cause_offset
);
3175 ZERO(hpriv
->irq_mask_offset
);
3176 ZERO(MV_PCI_ERR_LOW_ADDRESS
);
3177 ZERO(MV_PCI_ERR_HIGH_ADDRESS
);
3178 ZERO(MV_PCI_ERR_ATTRIBUTE
);
3179 ZERO(MV_PCI_ERR_COMMAND
);
3183 static void mv6_reset_flash(struct mv_host_priv
*hpriv
, void __iomem
*mmio
)
3187 mv5_reset_flash(hpriv
, mmio
);
3189 tmp
= readl(mmio
+ GPIO_PORT_CTL
);
3191 tmp
|= (1 << 5) | (1 << 6);
3192 writel(tmp
, mmio
+ GPIO_PORT_CTL
);
3196 * mv6_reset_hc - Perform the 6xxx global soft reset
3197 * @mmio: base address of the HBA
3199 * This routine only applies to 6xxx parts.
3202 * Inherited from caller.
3204 static int mv6_reset_hc(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
3207 void __iomem
*reg
= mmio
+ PCI_MAIN_CMD_STS
;
3211 /* Following procedure defined in PCI "main command and status
3215 writel(t
| STOP_PCI_MASTER
, reg
);
3217 for (i
= 0; i
< 1000; i
++) {
3220 if (PCI_MASTER_EMPTY
& t
)
3223 if (!(PCI_MASTER_EMPTY
& t
)) {
3224 printk(KERN_ERR DRV_NAME
": PCI master won't flush\n");
3232 writel(t
| GLOB_SFT_RST
, reg
);
3235 } while (!(GLOB_SFT_RST
& t
) && (i
-- > 0));
3237 if (!(GLOB_SFT_RST
& t
)) {
3238 printk(KERN_ERR DRV_NAME
": can't set global reset\n");
3243 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3246 writel(t
& ~(GLOB_SFT_RST
| STOP_PCI_MASTER
), reg
);
3249 } while ((GLOB_SFT_RST
& t
) && (i
-- > 0));
3251 if (GLOB_SFT_RST
& t
) {
3252 printk(KERN_ERR DRV_NAME
": can't clear global reset\n");
3259 static void mv6_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
3262 void __iomem
*port_mmio
;
3265 tmp
= readl(mmio
+ RESET_CFG
);
3266 if ((tmp
& (1 << 0)) == 0) {
3267 hpriv
->signal
[idx
].amps
= 0x7 << 8;
3268 hpriv
->signal
[idx
].pre
= 0x1 << 5;
3272 port_mmio
= mv_port_base(mmio
, idx
);
3273 tmp
= readl(port_mmio
+ PHY_MODE2
);
3275 hpriv
->signal
[idx
].amps
= tmp
& 0x700; /* bits 10:8 */
3276 hpriv
->signal
[idx
].pre
= tmp
& 0xe0; /* bits 7:5 */
3279 static void mv6_enable_leds(struct mv_host_priv
*hpriv
, void __iomem
*mmio
)
3281 writel(0x00000060, mmio
+ GPIO_PORT_CTL
);
3284 static void mv6_phy_errata(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
3287 void __iomem
*port_mmio
= mv_port_base(mmio
, port
);
3289 u32 hp_flags
= hpriv
->hp_flags
;
3291 hp_flags
& (MV_HP_ERRATA_60X1B2
| MV_HP_ERRATA_60X1C0
);
3293 hp_flags
& (MV_HP_ERRATA_60X1B2
| MV_HP_ERRATA_60X1C0
);
3296 if (fix_phy_mode2
) {
3297 m2
= readl(port_mmio
+ PHY_MODE2
);
3300 writel(m2
, port_mmio
+ PHY_MODE2
);
3304 m2
= readl(port_mmio
+ PHY_MODE2
);
3305 m2
&= ~((1 << 16) | (1 << 31));
3306 writel(m2
, port_mmio
+ PHY_MODE2
);
3312 * Gen-II/IIe PHY_MODE3 errata RM#2:
3313 * Achieves better receiver noise performance than the h/w default:
3315 m3
= readl(port_mmio
+ PHY_MODE3
);
3316 m3
= (m3
& 0x1f) | (0x5555601 << 5);
3318 /* Guideline 88F5182 (GL# SATA-S11) */
3322 if (fix_phy_mode4
) {
3323 u32 m4
= readl(port_mmio
+ PHY_MODE4
);
3325 * Enforce reserved-bit restrictions on GenIIe devices only.
3326 * For earlier chipsets, force only the internal config field
3327 * (workaround for errata FEr SATA#10 part 1).
3329 if (IS_GEN_IIE(hpriv
))
3330 m4
= (m4
& ~PHY_MODE4_RSVD_ZEROS
) | PHY_MODE4_RSVD_ONES
;
3332 m4
= (m4
& ~PHY_MODE4_CFG_MASK
) | PHY_MODE4_CFG_VALUE
;
3333 writel(m4
, port_mmio
+ PHY_MODE4
);
3336 * Workaround for 60x1-B2 errata SATA#13:
3337 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3338 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
3339 * Or ensure we use writelfl() when writing PHY_MODE4.
3341 writel(m3
, port_mmio
+ PHY_MODE3
);
3343 /* Revert values of pre-emphasis and signal amps to the saved ones */
3344 m2
= readl(port_mmio
+ PHY_MODE2
);
3346 m2
&= ~MV_M2_PREAMP_MASK
;
3347 m2
|= hpriv
->signal
[port
].amps
;
3348 m2
|= hpriv
->signal
[port
].pre
;
3351 /* according to mvSata 3.6.1, some IIE values are fixed */
3352 if (IS_GEN_IIE(hpriv
)) {
3357 writel(m2
, port_mmio
+ PHY_MODE2
);
3360 /* TODO: use the generic LED interface to configure the SATA Presence */
3361 /* & Acitivy LEDs on the board */
3362 static void mv_soc_enable_leds(struct mv_host_priv
*hpriv
,
3368 static void mv_soc_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
3371 void __iomem
*port_mmio
;
3374 port_mmio
= mv_port_base(mmio
, idx
);
3375 tmp
= readl(port_mmio
+ PHY_MODE2
);
3377 hpriv
->signal
[idx
].amps
= tmp
& 0x700; /* bits 10:8 */
3378 hpriv
->signal
[idx
].pre
= tmp
& 0xe0; /* bits 7:5 */
3382 #define ZERO(reg) writel(0, port_mmio + (reg))
3383 static void mv_soc_reset_hc_port(struct mv_host_priv
*hpriv
,
3384 void __iomem
*mmio
, unsigned int port
)
3386 void __iomem
*port_mmio
= mv_port_base(mmio
, port
);
3388 mv_reset_channel(hpriv
, mmio
, port
);
3390 ZERO(0x028); /* command */
3391 writel(0x101f, port_mmio
+ EDMA_CFG
);
3392 ZERO(0x004); /* timer */
3393 ZERO(0x008); /* irq err cause */
3394 ZERO(0x00c); /* irq err mask */
3395 ZERO(0x010); /* rq bah */
3396 ZERO(0x014); /* rq inp */
3397 ZERO(0x018); /* rq outp */
3398 ZERO(0x01c); /* respq bah */
3399 ZERO(0x024); /* respq outp */
3400 ZERO(0x020); /* respq inp */
3401 ZERO(0x02c); /* test control */
3402 writel(0x800, port_mmio
+ EDMA_IORDY_TMOUT
);
3407 #define ZERO(reg) writel(0, hc_mmio + (reg))
3408 static void mv_soc_reset_one_hc(struct mv_host_priv
*hpriv
,
3411 void __iomem
*hc_mmio
= mv_hc_base(mmio
, 0);
3421 static int mv_soc_reset_hc(struct mv_host_priv
*hpriv
,
3422 void __iomem
*mmio
, unsigned int n_hc
)
3426 for (port
= 0; port
< hpriv
->n_ports
; port
++)
3427 mv_soc_reset_hc_port(hpriv
, mmio
, port
);
3429 mv_soc_reset_one_hc(hpriv
, mmio
);
3434 static void mv_soc_reset_flash(struct mv_host_priv
*hpriv
,
3440 static void mv_soc_reset_bus(struct ata_host
*host
, void __iomem
*mmio
)
3445 static void mv_soc_65n_phy_errata(struct mv_host_priv
*hpriv
,
3446 void __iomem
*mmio
, unsigned int port
)
3448 void __iomem
*port_mmio
= mv_port_base(mmio
, port
);
3451 reg
= readl(port_mmio
+ PHY_MODE3
);
3452 reg
&= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
3454 reg
&= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
3456 writel(reg
, port_mmio
+ PHY_MODE3
);
3458 reg
= readl(port_mmio
+ PHY_MODE4
);
3459 reg
&= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
3461 writel(reg
, port_mmio
+ PHY_MODE4
);
3463 reg
= readl(port_mmio
+ PHY_MODE9_GEN2
);
3464 reg
&= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3466 reg
&= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3467 writel(reg
, port_mmio
+ PHY_MODE9_GEN2
);
3469 reg
= readl(port_mmio
+ PHY_MODE9_GEN1
);
3470 reg
&= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3472 reg
&= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3473 writel(reg
, port_mmio
+ PHY_MODE9_GEN1
);
3477 * soc_is_65 - check if the soc is 65 nano device
3479 * Detect the type of the SoC, this is done by reading the PHYCFG_OFS
3480 * register, this register should contain non-zero value and it exists only
3481 * in the 65 nano devices, when reading it from older devices we get 0.
3483 static bool soc_is_65n(struct mv_host_priv
*hpriv
)
3485 void __iomem
*port0_mmio
= mv_port_base(hpriv
->base
, 0);
3487 if (readl(port0_mmio
+ PHYCFG_OFS
))
3492 static void mv_setup_ifcfg(void __iomem
*port_mmio
, int want_gen2i
)
3494 u32 ifcfg
= readl(port_mmio
+ SATA_IFCFG
);
3496 ifcfg
= (ifcfg
& 0xf7f) | 0x9b1000; /* from chip spec */
3498 ifcfg
|= (1 << 7); /* enable gen2i speed */
3499 writelfl(ifcfg
, port_mmio
+ SATA_IFCFG
);
3502 static void mv_reset_channel(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
3503 unsigned int port_no
)
3505 void __iomem
*port_mmio
= mv_port_base(mmio
, port_no
);
3508 * The datasheet warns against setting EDMA_RESET when EDMA is active
3509 * (but doesn't say what the problem might be). So we first try
3510 * to disable the EDMA engine before doing the EDMA_RESET operation.
3512 mv_stop_edma_engine(port_mmio
);
3513 writelfl(EDMA_RESET
, port_mmio
+ EDMA_CMD
);
3515 if (!IS_GEN_I(hpriv
)) {
3516 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3517 mv_setup_ifcfg(port_mmio
, 1);
3520 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
3521 * link, and physical layers. It resets all SATA interface registers
3522 * (except for SATA_IFCFG), and issues a COMRESET to the dev.
3524 writelfl(EDMA_RESET
, port_mmio
+ EDMA_CMD
);
3525 udelay(25); /* allow reset propagation */
3526 writelfl(0, port_mmio
+ EDMA_CMD
);
3528 hpriv
->ops
->phy_errata(hpriv
, mmio
, port_no
);
3530 if (IS_GEN_I(hpriv
))
3534 static void mv_pmp_select(struct ata_port
*ap
, int pmp
)
3536 if (sata_pmp_supported(ap
)) {
3537 void __iomem
*port_mmio
= mv_ap_base(ap
);
3538 u32 reg
= readl(port_mmio
+ SATA_IFCTL
);
3539 int old
= reg
& 0xf;
3542 reg
= (reg
& ~0xf) | pmp
;
3543 writelfl(reg
, port_mmio
+ SATA_IFCTL
);
3548 static int mv_pmp_hardreset(struct ata_link
*link
, unsigned int *class,
3549 unsigned long deadline
)
3551 mv_pmp_select(link
->ap
, sata_srst_pmp(link
));
3552 return sata_std_hardreset(link
, class, deadline
);
3555 static int mv_softreset(struct ata_link
*link
, unsigned int *class,
3556 unsigned long deadline
)
3558 mv_pmp_select(link
->ap
, sata_srst_pmp(link
));
3559 return ata_sff_softreset(link
, class, deadline
);
3562 static int mv_hardreset(struct ata_link
*link
, unsigned int *class,
3563 unsigned long deadline
)
3565 struct ata_port
*ap
= link
->ap
;
3566 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
3567 struct mv_port_priv
*pp
= ap
->private_data
;
3568 void __iomem
*mmio
= hpriv
->base
;
3569 int rc
, attempts
= 0, extra
= 0;
3573 mv_reset_channel(hpriv
, mmio
, ap
->port_no
);
3574 pp
->pp_flags
&= ~MV_PP_FLAG_EDMA_EN
;
3576 ~(MV_PP_FLAG_FBS_EN
| MV_PP_FLAG_NCQ_EN
| MV_PP_FLAG_FAKE_ATA_BUSY
);
3578 /* Workaround for errata FEr SATA#10 (part 2) */
3580 const unsigned long *timing
=
3581 sata_ehc_deb_timing(&link
->eh_context
);
3583 rc
= sata_link_hardreset(link
, timing
, deadline
+ extra
,
3585 rc
= online
? -EAGAIN
: rc
;
3588 sata_scr_read(link
, SCR_STATUS
, &sstatus
);
3589 if (!IS_GEN_I(hpriv
) && ++attempts
>= 5 && sstatus
== 0x121) {
3590 /* Force 1.5gb/s link speed and try again */
3591 mv_setup_ifcfg(mv_ap_base(ap
), 0);
3592 if (time_after(jiffies
+ HZ
, deadline
))
3593 extra
= HZ
; /* only extend it once, max */
3595 } while (sstatus
!= 0x0 && sstatus
!= 0x113 && sstatus
!= 0x123);
3596 mv_save_cached_regs(ap
);
3597 mv_edma_cfg(ap
, 0, 0);
3602 static void mv_eh_freeze(struct ata_port
*ap
)
3605 mv_enable_port_irqs(ap
, 0);
3608 static void mv_eh_thaw(struct ata_port
*ap
)
3610 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
3611 unsigned int port
= ap
->port_no
;
3612 unsigned int hardport
= mv_hardport_from_port(port
);
3613 void __iomem
*hc_mmio
= mv_hc_base_from_port(hpriv
->base
, port
);
3614 void __iomem
*port_mmio
= mv_ap_base(ap
);
3617 /* clear EDMA errors on this port */
3618 writel(0, port_mmio
+ EDMA_ERR_IRQ_CAUSE
);
3620 /* clear pending irq events */
3621 hc_irq_cause
= ~((DEV_IRQ
| DMA_IRQ
) << hardport
);
3622 writelfl(hc_irq_cause
, hc_mmio
+ HC_IRQ_CAUSE
);
3624 mv_enable_port_irqs(ap
, ERR_IRQ
);
3628 * mv_port_init - Perform some early initialization on a single port.
3629 * @port: libata data structure storing shadow register addresses
3630 * @port_mmio: base address of the port
3632 * Initialize shadow register mmio addresses, clear outstanding
3633 * interrupts on the port, and unmask interrupts for the future
3634 * start of the port.
3637 * Inherited from caller.
3639 static void mv_port_init(struct ata_ioports
*port
, void __iomem
*port_mmio
)
3641 void __iomem
*serr
, *shd_base
= port_mmio
+ SHD_BLK
;
3643 /* PIO related setup
3645 port
->data_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_DATA
);
3647 port
->feature_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_ERR
);
3648 port
->nsect_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_NSECT
);
3649 port
->lbal_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_LBAL
);
3650 port
->lbam_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_LBAM
);
3651 port
->lbah_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_LBAH
);
3652 port
->device_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_DEVICE
);
3654 port
->command_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_STATUS
);
3655 /* special case: control/altstatus doesn't have ATA_REG_ address */
3656 port
->altstatus_addr
= port
->ctl_addr
= shd_base
+ SHD_CTL_AST
;
3659 port
->cmd_addr
= port
->bmdma_addr
= port
->scr_addr
= NULL
;
3661 /* Clear any currently outstanding port interrupt conditions */
3662 serr
= port_mmio
+ mv_scr_offset(SCR_ERROR
);
3663 writelfl(readl(serr
), serr
);
3664 writelfl(0, port_mmio
+ EDMA_ERR_IRQ_CAUSE
);
3666 /* unmask all non-transient EDMA error interrupts */
3667 writelfl(~EDMA_ERR_IRQ_TRANSIENT
, port_mmio
+ EDMA_ERR_IRQ_MASK
);
3669 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
3670 readl(port_mmio
+ EDMA_CFG
),
3671 readl(port_mmio
+ EDMA_ERR_IRQ_CAUSE
),
3672 readl(port_mmio
+ EDMA_ERR_IRQ_MASK
));
3675 static unsigned int mv_in_pcix_mode(struct ata_host
*host
)
3677 struct mv_host_priv
*hpriv
= host
->private_data
;
3678 void __iomem
*mmio
= hpriv
->base
;
3681 if (IS_SOC(hpriv
) || !IS_PCIE(hpriv
))
3682 return 0; /* not PCI-X capable */
3683 reg
= readl(mmio
+ MV_PCI_MODE
);
3684 if ((reg
& MV_PCI_MODE_MASK
) == 0)
3685 return 0; /* conventional PCI mode */
3686 return 1; /* chip is in PCI-X mode */
3689 static int mv_pci_cut_through_okay(struct ata_host
*host
)
3691 struct mv_host_priv
*hpriv
= host
->private_data
;
3692 void __iomem
*mmio
= hpriv
->base
;
3695 if (!mv_in_pcix_mode(host
)) {
3696 reg
= readl(mmio
+ MV_PCI_COMMAND
);
3697 if (reg
& MV_PCI_COMMAND_MRDTRIG
)
3698 return 0; /* not okay */
3700 return 1; /* okay */
3703 static void mv_60x1b2_errata_pci7(struct ata_host
*host
)
3705 struct mv_host_priv
*hpriv
= host
->private_data
;
3706 void __iomem
*mmio
= hpriv
->base
;
3708 /* workaround for 60x1-B2 errata PCI#7 */
3709 if (mv_in_pcix_mode(host
)) {
3710 u32 reg
= readl(mmio
+ MV_PCI_COMMAND
);
3711 writelfl(reg
& ~MV_PCI_COMMAND_MWRCOM
, mmio
+ MV_PCI_COMMAND
);
3715 static int mv_chip_id(struct ata_host
*host
, unsigned int board_idx
)
3717 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
3718 struct mv_host_priv
*hpriv
= host
->private_data
;
3719 u32 hp_flags
= hpriv
->hp_flags
;
3721 switch (board_idx
) {
3723 hpriv
->ops
= &mv5xxx_ops
;
3724 hp_flags
|= MV_HP_GEN_I
;
3726 switch (pdev
->revision
) {
3728 hp_flags
|= MV_HP_ERRATA_50XXB0
;
3731 hp_flags
|= MV_HP_ERRATA_50XXB2
;
3734 dev_printk(KERN_WARNING
, &pdev
->dev
,
3735 "Applying 50XXB2 workarounds to unknown rev\n");
3736 hp_flags
|= MV_HP_ERRATA_50XXB2
;
3743 hpriv
->ops
= &mv5xxx_ops
;
3744 hp_flags
|= MV_HP_GEN_I
;
3746 switch (pdev
->revision
) {
3748 hp_flags
|= MV_HP_ERRATA_50XXB0
;
3751 hp_flags
|= MV_HP_ERRATA_50XXB2
;
3754 dev_printk(KERN_WARNING
, &pdev
->dev
,
3755 "Applying B2 workarounds to unknown rev\n");
3756 hp_flags
|= MV_HP_ERRATA_50XXB2
;
3763 hpriv
->ops
= &mv6xxx_ops
;
3764 hp_flags
|= MV_HP_GEN_II
;
3766 switch (pdev
->revision
) {
3768 mv_60x1b2_errata_pci7(host
);
3769 hp_flags
|= MV_HP_ERRATA_60X1B2
;
3772 hp_flags
|= MV_HP_ERRATA_60X1C0
;
3775 dev_printk(KERN_WARNING
, &pdev
->dev
,
3776 "Applying B2 workarounds to unknown rev\n");
3777 hp_flags
|= MV_HP_ERRATA_60X1B2
;
3783 hp_flags
|= MV_HP_PCIE
| MV_HP_CUT_THROUGH
;
3784 if (pdev
->vendor
== PCI_VENDOR_ID_TTI
&&
3785 (pdev
->device
== 0x2300 || pdev
->device
== 0x2310))
3788 * Highpoint RocketRAID PCIe 23xx series cards:
3790 * Unconfigured drives are treated as "Legacy"
3791 * by the BIOS, and it overwrites sector 8 with
3792 * a "Lgcy" metadata block prior to Linux boot.
3794 * Configured drives (RAID or JBOD) leave sector 8
3795 * alone, but instead overwrite a high numbered
3796 * sector for the RAID metadata. This sector can
3797 * be determined exactly, by truncating the physical
3798 * drive capacity to a nice even GB value.
3800 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3802 * Warn the user, lest they think we're just buggy.
3804 printk(KERN_WARNING DRV_NAME
": Highpoint RocketRAID"
3805 " BIOS CORRUPTS DATA on all attached drives,"
3806 " regardless of if/how they are configured."
3808 printk(KERN_WARNING DRV_NAME
": For data safety, do not"
3809 " use sectors 8-9 on \"Legacy\" drives,"
3810 " and avoid the final two gigabytes on"
3811 " all RocketRAID BIOS initialized drives.\n");
3815 hpriv
->ops
= &mv6xxx_ops
;
3816 hp_flags
|= MV_HP_GEN_IIE
;
3817 if (board_idx
== chip_6042
&& mv_pci_cut_through_okay(host
))
3818 hp_flags
|= MV_HP_CUT_THROUGH
;
3820 switch (pdev
->revision
) {
3821 case 0x2: /* Rev.B0: the first/only public release */
3822 hp_flags
|= MV_HP_ERRATA_60X1C0
;
3825 dev_printk(KERN_WARNING
, &pdev
->dev
,
3826 "Applying 60X1C0 workarounds to unknown rev\n");
3827 hp_flags
|= MV_HP_ERRATA_60X1C0
;
3832 if (soc_is_65n(hpriv
))
3833 hpriv
->ops
= &mv_soc_65n_ops
;
3835 hpriv
->ops
= &mv_soc_ops
;
3836 hp_flags
|= MV_HP_FLAG_SOC
| MV_HP_GEN_IIE
|
3837 MV_HP_ERRATA_60X1C0
;
3841 dev_printk(KERN_ERR
, host
->dev
,
3842 "BUG: invalid board index %u\n", board_idx
);
3846 hpriv
->hp_flags
= hp_flags
;
3847 if (hp_flags
& MV_HP_PCIE
) {
3848 hpriv
->irq_cause_offset
= PCIE_IRQ_CAUSE
;
3849 hpriv
->irq_mask_offset
= PCIE_IRQ_MASK
;
3850 hpriv
->unmask_all_irqs
= PCIE_UNMASK_ALL_IRQS
;
3852 hpriv
->irq_cause_offset
= PCI_IRQ_CAUSE
;
3853 hpriv
->irq_mask_offset
= PCI_IRQ_MASK
;
3854 hpriv
->unmask_all_irqs
= PCI_UNMASK_ALL_IRQS
;
3861 * mv_init_host - Perform some early initialization of the host.
3862 * @host: ATA host to initialize
3864 * If possible, do an early global reset of the host. Then do
3865 * our port init and clear/unmask all/relevant host interrupts.
3868 * Inherited from caller.
3870 static int mv_init_host(struct ata_host
*host
)
3872 int rc
= 0, n_hc
, port
, hc
;
3873 struct mv_host_priv
*hpriv
= host
->private_data
;
3874 void __iomem
*mmio
= hpriv
->base
;
3876 rc
= mv_chip_id(host
, hpriv
->board_idx
);
3880 if (IS_SOC(hpriv
)) {
3881 hpriv
->main_irq_cause_addr
= mmio
+ SOC_HC_MAIN_IRQ_CAUSE
;
3882 hpriv
->main_irq_mask_addr
= mmio
+ SOC_HC_MAIN_IRQ_MASK
;
3884 hpriv
->main_irq_cause_addr
= mmio
+ PCI_HC_MAIN_IRQ_CAUSE
;
3885 hpriv
->main_irq_mask_addr
= mmio
+ PCI_HC_MAIN_IRQ_MASK
;
3888 /* initialize shadow irq mask with register's value */
3889 hpriv
->main_irq_mask
= readl(hpriv
->main_irq_mask_addr
);
3891 /* global interrupt mask: 0 == mask everything */
3892 mv_set_main_irq_mask(host
, ~0, 0);
3894 n_hc
= mv_get_hc_count(host
->ports
[0]->flags
);
3896 for (port
= 0; port
< host
->n_ports
; port
++)
3897 if (hpriv
->ops
->read_preamp
)
3898 hpriv
->ops
->read_preamp(hpriv
, port
, mmio
);
3900 rc
= hpriv
->ops
->reset_hc(hpriv
, mmio
, n_hc
);
3904 hpriv
->ops
->reset_flash(hpriv
, mmio
);
3905 hpriv
->ops
->reset_bus(host
, mmio
);
3906 hpriv
->ops
->enable_leds(hpriv
, mmio
);
3908 for (port
= 0; port
< host
->n_ports
; port
++) {
3909 struct ata_port
*ap
= host
->ports
[port
];
3910 void __iomem
*port_mmio
= mv_port_base(mmio
, port
);
3912 mv_port_init(&ap
->ioaddr
, port_mmio
);
3915 for (hc
= 0; hc
< n_hc
; hc
++) {
3916 void __iomem
*hc_mmio
= mv_hc_base(mmio
, hc
);
3918 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3919 "(before clear)=0x%08x\n", hc
,
3920 readl(hc_mmio
+ HC_CFG
),
3921 readl(hc_mmio
+ HC_IRQ_CAUSE
));
3923 /* Clear any currently outstanding hc interrupt conditions */
3924 writelfl(0, hc_mmio
+ HC_IRQ_CAUSE
);
3927 if (!IS_SOC(hpriv
)) {
3928 /* Clear any currently outstanding host interrupt conditions */
3929 writelfl(0, mmio
+ hpriv
->irq_cause_offset
);
3931 /* and unmask interrupt generation for host regs */
3932 writelfl(hpriv
->unmask_all_irqs
, mmio
+ hpriv
->irq_mask_offset
);
3936 * enable only global host interrupts for now.
3937 * The per-port interrupts get done later as ports are set up.
3939 mv_set_main_irq_mask(host
, 0, PCI_ERR
);
3940 mv_set_irq_coalescing(host
, irq_coalescing_io_count
,
3941 irq_coalescing_usecs
);
3946 static int mv_create_dma_pools(struct mv_host_priv
*hpriv
, struct device
*dev
)
3948 hpriv
->crqb_pool
= dmam_pool_create("crqb_q", dev
, MV_CRQB_Q_SZ
,
3950 if (!hpriv
->crqb_pool
)
3953 hpriv
->crpb_pool
= dmam_pool_create("crpb_q", dev
, MV_CRPB_Q_SZ
,
3955 if (!hpriv
->crpb_pool
)
3958 hpriv
->sg_tbl_pool
= dmam_pool_create("sg_tbl", dev
, MV_SG_TBL_SZ
,
3960 if (!hpriv
->sg_tbl_pool
)
3966 static void mv_conf_mbus_windows(struct mv_host_priv
*hpriv
,
3967 struct mbus_dram_target_info
*dram
)
3971 for (i
= 0; i
< 4; i
++) {
3972 writel(0, hpriv
->base
+ WINDOW_CTRL(i
));
3973 writel(0, hpriv
->base
+ WINDOW_BASE(i
));
3976 for (i
= 0; i
< dram
->num_cs
; i
++) {
3977 struct mbus_dram_window
*cs
= dram
->cs
+ i
;
3979 writel(((cs
->size
- 1) & 0xffff0000) |
3980 (cs
->mbus_attr
<< 8) |
3981 (dram
->mbus_dram_target_id
<< 4) | 1,
3982 hpriv
->base
+ WINDOW_CTRL(i
));
3983 writel(cs
->base
, hpriv
->base
+ WINDOW_BASE(i
));
3988 * mv_platform_probe - handle a positive probe of an soc Marvell
3990 * @pdev: platform device found
3993 * Inherited from caller.
3995 static int mv_platform_probe(struct platform_device
*pdev
)
3997 static int printed_version
;
3998 const struct mv_sata_platform_data
*mv_platform_data
;
3999 const struct ata_port_info
*ppi
[] =
4000 { &mv_port_info
[chip_soc
], NULL
};
4001 struct ata_host
*host
;
4002 struct mv_host_priv
*hpriv
;
4003 struct resource
*res
;
4006 if (!printed_version
++)
4007 dev_printk(KERN_INFO
, &pdev
->dev
, "version " DRV_VERSION
"\n");
4010 * Simple resource validation ..
4012 if (unlikely(pdev
->num_resources
!= 2)) {
4013 dev_err(&pdev
->dev
, "invalid number of resources\n");
4018 * Get the register base first
4020 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
4025 mv_platform_data
= pdev
->dev
.platform_data
;
4026 n_ports
= mv_platform_data
->n_ports
;
4028 host
= ata_host_alloc_pinfo(&pdev
->dev
, ppi
, n_ports
);
4029 hpriv
= devm_kzalloc(&pdev
->dev
, sizeof(*hpriv
), GFP_KERNEL
);
4031 if (!host
|| !hpriv
)
4033 host
->private_data
= hpriv
;
4034 hpriv
->n_ports
= n_ports
;
4035 hpriv
->board_idx
= chip_soc
;
4038 hpriv
->base
= devm_ioremap(&pdev
->dev
, res
->start
,
4039 resource_size(res
));
4040 hpriv
->base
-= SATAHC0_REG_BASE
;
4042 #if defined(CONFIG_HAVE_CLK)
4043 hpriv
->clk
= clk_get(&pdev
->dev
, NULL
);
4044 if (IS_ERR(hpriv
->clk
))
4045 dev_notice(&pdev
->dev
, "cannot get clkdev\n");
4047 clk_enable(hpriv
->clk
);
4051 * (Re-)program MBUS remapping windows if we are asked to.
4053 if (mv_platform_data
->dram
!= NULL
)
4054 mv_conf_mbus_windows(hpriv
, mv_platform_data
->dram
);
4056 rc
= mv_create_dma_pools(hpriv
, &pdev
->dev
);
4060 /* initialize adapter */
4061 rc
= mv_init_host(host
);
4065 dev_printk(KERN_INFO
, &pdev
->dev
,
4066 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH
,
4069 return ata_host_activate(host
, platform_get_irq(pdev
, 0), mv_interrupt
,
4070 IRQF_SHARED
, &mv6_sht
);
4072 #if defined(CONFIG_HAVE_CLK)
4073 if (!IS_ERR(hpriv
->clk
)) {
4074 clk_disable(hpriv
->clk
);
4075 clk_put(hpriv
->clk
);
4084 * mv_platform_remove - unplug a platform interface
4085 * @pdev: platform device
4087 * A platform bus SATA device has been unplugged. Perform the needed
4088 * cleanup. Also called on module unload for any active devices.
4090 static int __devexit
mv_platform_remove(struct platform_device
*pdev
)
4092 struct device
*dev
= &pdev
->dev
;
4093 struct ata_host
*host
= dev_get_drvdata(dev
);
4094 #if defined(CONFIG_HAVE_CLK)
4095 struct mv_host_priv
*hpriv
= host
->private_data
;
4097 ata_host_detach(host
);
4099 #if defined(CONFIG_HAVE_CLK)
4100 if (!IS_ERR(hpriv
->clk
)) {
4101 clk_disable(hpriv
->clk
);
4102 clk_put(hpriv
->clk
);
4109 static int mv_platform_suspend(struct platform_device
*pdev
, pm_message_t state
)
4111 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
4113 return ata_host_suspend(host
, state
);
4118 static int mv_platform_resume(struct platform_device
*pdev
)
4120 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
4124 struct mv_host_priv
*hpriv
= host
->private_data
;
4125 const struct mv_sata_platform_data
*mv_platform_data
= \
4126 pdev
->dev
.platform_data
;
4128 * (Re-)program MBUS remapping windows if we are asked to.
4130 if (mv_platform_data
->dram
!= NULL
)
4131 mv_conf_mbus_windows(hpriv
, mv_platform_data
->dram
);
4133 /* initialize adapter */
4134 ret
= mv_init_host(host
);
4136 printk(KERN_ERR DRV_NAME
": Error during HW init\n");
4139 ata_host_resume(host
);
4145 #define mv_platform_suspend NULL
4146 #define mv_platform_resume NULL
4149 static struct platform_driver mv_platform_driver
= {
4150 .probe
= mv_platform_probe
,
4151 .remove
= __devexit_p(mv_platform_remove
),
4152 .suspend
= mv_platform_suspend
,
4153 .resume
= mv_platform_resume
,
4156 .owner
= THIS_MODULE
,
4162 static int mv_pci_init_one(struct pci_dev
*pdev
,
4163 const struct pci_device_id
*ent
);
4165 static int mv_pci_device_resume(struct pci_dev
*pdev
);
4169 static struct pci_driver mv_pci_driver
= {
4171 .id_table
= mv_pci_tbl
,
4172 .probe
= mv_pci_init_one
,
4173 .remove
= ata_pci_remove_one
,
4175 .suspend
= ata_pci_device_suspend
,
4176 .resume
= mv_pci_device_resume
,
4181 /* move to PCI layer or libata core? */
4182 static int pci_go_64(struct pci_dev
*pdev
)
4186 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(64))) {
4187 rc
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
4189 rc
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
4191 dev_printk(KERN_ERR
, &pdev
->dev
,
4192 "64-bit DMA enable failed\n");
4197 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
4199 dev_printk(KERN_ERR
, &pdev
->dev
,
4200 "32-bit DMA enable failed\n");
4203 rc
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
4205 dev_printk(KERN_ERR
, &pdev
->dev
,
4206 "32-bit consistent DMA enable failed\n");
4215 * mv_print_info - Dump key info to kernel log for perusal.
4216 * @host: ATA host to print info about
4218 * FIXME: complete this.
4221 * Inherited from caller.
4223 static void mv_print_info(struct ata_host
*host
)
4225 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
4226 struct mv_host_priv
*hpriv
= host
->private_data
;
4228 const char *scc_s
, *gen
;
4230 /* Use this to determine the HW stepping of the chip so we know
4231 * what errata to workaround
4233 pci_read_config_byte(pdev
, PCI_CLASS_DEVICE
, &scc
);
4236 else if (scc
== 0x01)
4241 if (IS_GEN_I(hpriv
))
4243 else if (IS_GEN_II(hpriv
))
4245 else if (IS_GEN_IIE(hpriv
))
4250 dev_printk(KERN_INFO
, &pdev
->dev
,
4251 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
4252 gen
, (unsigned)MV_MAX_Q_DEPTH
, host
->n_ports
,
4253 scc_s
, (MV_HP_FLAG_MSI
& hpriv
->hp_flags
) ? "MSI" : "INTx");
4257 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
4258 * @pdev: PCI device found
4259 * @ent: PCI device ID entry for the matched host
4262 * Inherited from caller.
4264 static int mv_pci_init_one(struct pci_dev
*pdev
,
4265 const struct pci_device_id
*ent
)
4267 static int printed_version
;
4268 unsigned int board_idx
= (unsigned int)ent
->driver_data
;
4269 const struct ata_port_info
*ppi
[] = { &mv_port_info
[board_idx
], NULL
};
4270 struct ata_host
*host
;
4271 struct mv_host_priv
*hpriv
;
4272 int n_ports
, port
, rc
;
4274 if (!printed_version
++)
4275 dev_printk(KERN_INFO
, &pdev
->dev
, "version " DRV_VERSION
"\n");
4278 n_ports
= mv_get_hc_count(ppi
[0]->flags
) * MV_PORTS_PER_HC
;
4280 host
= ata_host_alloc_pinfo(&pdev
->dev
, ppi
, n_ports
);
4281 hpriv
= devm_kzalloc(&pdev
->dev
, sizeof(*hpriv
), GFP_KERNEL
);
4282 if (!host
|| !hpriv
)
4284 host
->private_data
= hpriv
;
4285 hpriv
->n_ports
= n_ports
;
4286 hpriv
->board_idx
= board_idx
;
4288 /* acquire resources */
4289 rc
= pcim_enable_device(pdev
);
4293 rc
= pcim_iomap_regions(pdev
, 1 << MV_PRIMARY_BAR
, DRV_NAME
);
4295 pcim_pin_device(pdev
);
4298 host
->iomap
= pcim_iomap_table(pdev
);
4299 hpriv
->base
= host
->iomap
[MV_PRIMARY_BAR
];
4301 rc
= pci_go_64(pdev
);
4305 rc
= mv_create_dma_pools(hpriv
, &pdev
->dev
);
4309 for (port
= 0; port
< host
->n_ports
; port
++) {
4310 struct ata_port
*ap
= host
->ports
[port
];
4311 void __iomem
*port_mmio
= mv_port_base(hpriv
->base
, port
);
4312 unsigned int offset
= port_mmio
- hpriv
->base
;
4314 ata_port_pbar_desc(ap
, MV_PRIMARY_BAR
, -1, "mmio");
4315 ata_port_pbar_desc(ap
, MV_PRIMARY_BAR
, offset
, "port");
4318 /* initialize adapter */
4319 rc
= mv_init_host(host
);
4323 /* Enable message-switched interrupts, if requested */
4324 if (msi
&& pci_enable_msi(pdev
) == 0)
4325 hpriv
->hp_flags
|= MV_HP_FLAG_MSI
;
4327 mv_dump_pci_cfg(pdev
, 0x68);
4328 mv_print_info(host
);
4330 pci_set_master(pdev
);
4331 pci_try_set_mwi(pdev
);
4332 return ata_host_activate(host
, pdev
->irq
, mv_interrupt
, IRQF_SHARED
,
4333 IS_GEN_I(hpriv
) ? &mv5_sht
: &mv6_sht
);
4337 static int mv_pci_device_resume(struct pci_dev
*pdev
)
4339 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
4342 rc
= ata_pci_device_do_resume(pdev
);
4346 /* initialize adapter */
4347 rc
= mv_init_host(host
);
4351 ata_host_resume(host
);
4358 static int mv_platform_probe(struct platform_device
*pdev
);
4359 static int __devexit
mv_platform_remove(struct platform_device
*pdev
);
4361 static int __init
mv_init(void)
4365 rc
= pci_register_driver(&mv_pci_driver
);
4369 rc
= platform_driver_register(&mv_platform_driver
);
4373 pci_unregister_driver(&mv_pci_driver
);
4378 static void __exit
mv_exit(void)
4381 pci_unregister_driver(&mv_pci_driver
);
4383 platform_driver_unregister(&mv_platform_driver
);
4386 MODULE_AUTHOR("Brett Russ");
4387 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4388 MODULE_LICENSE("GPL");
4389 MODULE_DEVICE_TABLE(pci
, mv_pci_tbl
);
4390 MODULE_VERSION(DRV_VERSION
);
4391 MODULE_ALIAS("platform:" DRV_NAME
);
4393 module_init(mv_init
);
4394 module_exit(mv_exit
);