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mtd: m25p80: add support for Micron N25Q256A
[linux-2.6.git] / drivers / mtd / devices / m25p80.c
blob980cd6dac5d7bc0bf116346cb64d1418be67bf56
1 /*
2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
3 *
4 * Author: Mike Lavender, mike@steroidmicros.com
5 *
6 * Copyright (c) 2005, Intec Automation Inc.
7 *
8 * Some parts are based on lart.c by Abraham Van Der Merwe
9 *
10 * Cleaned up and generalized based on mtd_dataflash.c
11 *
12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18 #include <linux/init.h>
19 #include <linux/err.h>
20 #include <linux/errno.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/mutex.h>
25 #include <linux/math64.h>
26 #include <linux/slab.h>
27 #include <linux/sched.h>
28 #include <linux/mod_devicetable.h>
29
30 #include <linux/mtd/cfi.h>
31 #include <linux/mtd/mtd.h>
32 #include <linux/mtd/partitions.h>
33 #include <linux/of_platform.h>
34
35 #include <linux/spi/spi.h>
36 #include <linux/spi/flash.h>
37
38 /* Flash opcodes. */
39 #define OPCODE_WREN 0x06 /* Write enable */
40 #define OPCODE_RDSR 0x05 /* Read status register */
41 #define OPCODE_WRSR 0x01 /* Write status register 1 byte */
42 #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
43 #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
44 #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
45 #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
46 #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
47 #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
48 #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
49 #define OPCODE_RDID 0x9f /* Read JEDEC ID */
50
51 /* Used for SST flashes only. */
52 #define OPCODE_BP 0x02 /* Byte program */
53 #define OPCODE_WRDI 0x04 /* Write disable */
54 #define OPCODE_AAI_WP 0xad /* Auto address increment word program */
55
56 /* Used for Macronix flashes only. */
57 #define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
58 #define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
59
60 /* Used for Spansion flashes only. */
61 #define OPCODE_BRWR 0x17 /* Bank register write */
62
63 /* Status Register bits. */
64 #define SR_WIP 1 /* Write in progress */
65 #define SR_WEL 2 /* Write enable latch */
66 /* meaning of other SR_* bits may differ between vendors */
67 #define SR_BP0 4 /* Block protect 0 */
68 #define SR_BP1 8 /* Block protect 1 */
69 #define SR_BP2 0x10 /* Block protect 2 */
70 #define SR_SRWD 0x80 /* SR write protect */
71
72 /* Define max times to check status register before we give up. */
73 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
74 #define MAX_CMD_SIZE 5
75
76 #ifdef CONFIG_M25PXX_USE_FAST_READ
77 #define OPCODE_READ OPCODE_FAST_READ
78 #define FAST_READ_DUMMY_BYTE 1
79 #else
80 #define OPCODE_READ OPCODE_NORM_READ
81 #define FAST_READ_DUMMY_BYTE 0
82 #endif
83
84 #define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
85
86 /****************************************************************************/
87
88 struct m25p {
89 struct spi_device *spi;
90 struct mutex lock;
91 struct mtd_info mtd;
92 u16 page_size;
93 u16 addr_width;
94 u8 erase_opcode;
95 u8 *command;
96 };
97
98 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
99 {
100 return container_of(mtd, struct m25p, mtd);
101 }
102
103 /****************************************************************************/
104
105 /*
106 * Internal helper functions
107 */
108
109 /*
110 * Read the status register, returning its value in the location
111 * Return the status register value.
112 * Returns negative if error occurred.
113 */
114 static int read_sr(struct m25p *flash)
115 {
116 ssize_t retval;
117 u8 code = OPCODE_RDSR;
118 u8 val;
119
120 retval = spi_write_then_read(flash->spi, &code, 1, &val, 1);
121
122 if (retval < 0) {
123 dev_err(&flash->spi->dev, "error %d reading SR\n",
124 (int) retval);
125 return retval;
126 }
127
128 return val;
129 }
130
131 /*
132 * Write status register 1 byte
133 * Returns negative if error occurred.
134 */
135 static int write_sr(struct m25p *flash, u8 val)
136 {
137 flash->command[0] = OPCODE_WRSR;
138 flash->command[1] = val;
139
140 return spi_write(flash->spi, flash->command, 2);
141 }
142
143 /*
144 * Set write enable latch with Write Enable command.
145 * Returns negative if error occurred.
146 */
147 static inline int write_enable(struct m25p *flash)
148 {
149 u8 code = OPCODE_WREN;
150
151 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
152 }
153
154 /*
155 * Send write disble instruction to the chip.
156 */
157 static inline int write_disable(struct m25p *flash)
158 {
159 u8 code = OPCODE_WRDI;
160
161 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
162 }
163
164 /*
165 * Enable/disable 4-byte addressing mode.
166 */
167 static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
168 {
169 switch (JEDEC_MFR(jedec_id)) {
170 case CFI_MFR_MACRONIX:
171 flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
172 return spi_write(flash->spi, flash->command, 1);
173 default:
174 /* Spansion style */
175 flash->command[0] = OPCODE_BRWR;
176 flash->command[1] = enable << 7;
177 return spi_write(flash->spi, flash->command, 2);
178 }
179 }
180
181 /*
182 * Service routine to read status register until ready, or timeout occurs.
183 * Returns non-zero if error.
184 */
185 static int wait_till_ready(struct m25p *flash)
186 {
187 unsigned long deadline;
188 int sr;
189
190 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
191
192 do {
193 if ((sr = read_sr(flash)) < 0)
194 break;
195 else if (!(sr & SR_WIP))
196 return 0;
197
198 cond_resched();
199
200 } while (!time_after_eq(jiffies, deadline));
201
202 return 1;
203 }
204
205 /*
206 * Erase the whole flash memory
207 *
208 * Returns 0 if successful, non-zero otherwise.
209 */
210 static int erase_chip(struct m25p *flash)
211 {
212 pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__,
213 (long long)(flash->mtd.size >> 10));
214
215 /* Wait until finished previous write command. */
216 if (wait_till_ready(flash))
217 return 1;
218
219 /* Send write enable, then erase commands. */
220 write_enable(flash);
221
222 /* Set up command buffer. */
223 flash->command[0] = OPCODE_CHIP_ERASE;
224
225 spi_write(flash->spi, flash->command, 1);
226
227 return 0;
228 }
229
230 static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd)
231 {
232 /* opcode is in cmd[0] */
233 cmd[1] = addr >> (flash->addr_width * 8 - 8);
234 cmd[2] = addr >> (flash->addr_width * 8 - 16);
235 cmd[3] = addr >> (flash->addr_width * 8 - 24);
236 cmd[4] = addr >> (flash->addr_width * 8 - 32);
237 }
238
239 static int m25p_cmdsz(struct m25p *flash)
240 {
241 return 1 + flash->addr_width;
242 }
243
244 /*
245 * Erase one sector of flash memory at offset ``offset'' which is any
246 * address within the sector which should be erased.
247 *
248 * Returns 0 if successful, non-zero otherwise.
249 */
250 static int erase_sector(struct m25p *flash, u32 offset)
251 {
252 pr_debug("%s: %s %dKiB at 0x%08x\n", dev_name(&flash->spi->dev),
253 __func__, flash->mtd.erasesize / 1024, offset);
254
255 /* Wait until finished previous write command. */
256 if (wait_till_ready(flash))
257 return 1;
258
259 /* Send write enable, then erase commands. */
260 write_enable(flash);
261
262 /* Set up command buffer. */
263 flash->command[0] = flash->erase_opcode;
264 m25p_addr2cmd(flash, offset, flash->command);
265
266 spi_write(flash->spi, flash->command, m25p_cmdsz(flash));
267
268 return 0;
269 }
270
271 /****************************************************************************/
272
273 /*
274 * MTD implementation
275 */
276
277 /*
278 * Erase an address range on the flash chip. The address range may extend
279 * one or more erase sectors. Return an error is there is a problem erasing.
280 */
281 static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
282 {
283 struct m25p *flash = mtd_to_m25p(mtd);
284 u32 addr,len;
285 uint32_t rem;
286
287 pr_debug("%s: %s at 0x%llx, len %lld\n", dev_name(&flash->spi->dev),
288 __func__, (long long)instr->addr,
289 (long long)instr->len);
290
291 div_u64_rem(instr->len, mtd->erasesize, &rem);
292 if (rem)
293 return -EINVAL;
294
295 addr = instr->addr;
296 len = instr->len;
297
298 mutex_lock(&flash->lock);
299
300 /* whole-chip erase? */
301 if (len == flash->mtd.size) {
302 if (erase_chip(flash)) {
303 instr->state = MTD_ERASE_FAILED;
304 mutex_unlock(&flash->lock);
305 return -EIO;
306 }
307
308 /* REVISIT in some cases we could speed up erasing large regions
309 * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up
310 * to use "small sector erase", but that's not always optimal.
311 */
312
313 /* "sector"-at-a-time erase */
314 } else {
315 while (len) {
316 if (erase_sector(flash, addr)) {
317 instr->state = MTD_ERASE_FAILED;
318 mutex_unlock(&flash->lock);
319 return -EIO;
320 }
321
322 addr += mtd->erasesize;
323 len -= mtd->erasesize;
324 }
325 }
326
327 mutex_unlock(&flash->lock);
328
329 instr->state = MTD_ERASE_DONE;
330 mtd_erase_callback(instr);
331
332 return 0;
333 }
334
335 /*
336 * Read an address range from the flash chip. The address range
337 * may be any size provided it is within the physical boundaries.
338 */
339 static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
340 size_t *retlen, u_char *buf)
341 {
342 struct m25p *flash = mtd_to_m25p(mtd);
343 struct spi_transfer t[2];
344 struct spi_message m;
345
346 pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
347 __func__, (u32)from, len);
348
349 spi_message_init(&m);
350 memset(t, 0, (sizeof t));
351
352 /* NOTE:
353 * OPCODE_FAST_READ (if available) is faster.
354 * Should add 1 byte DUMMY_BYTE.
355 */
356 t[0].tx_buf = flash->command;
357 t[0].len = m25p_cmdsz(flash) + FAST_READ_DUMMY_BYTE;
358 spi_message_add_tail(&t[0], &m);
359
360 t[1].rx_buf = buf;
361 t[1].len = len;
362 spi_message_add_tail(&t[1], &m);
363
364 mutex_lock(&flash->lock);
365
366 /* Wait till previous write/erase is done. */
367 if (wait_till_ready(flash)) {
368 /* REVISIT status return?? */
369 mutex_unlock(&flash->lock);
370 return 1;
371 }
372
373 /* FIXME switch to OPCODE_FAST_READ. It's required for higher
374 * clocks; and at this writing, every chip this driver handles
375 * supports that opcode.
376 */
377
378 /* Set up the write data buffer. */
379 flash->command[0] = OPCODE_READ;
380 m25p_addr2cmd(flash, from, flash->command);
381
382 spi_sync(flash->spi, &m);
383
384 *retlen = m.actual_length - m25p_cmdsz(flash) - FAST_READ_DUMMY_BYTE;
385
386 mutex_unlock(&flash->lock);
387
388 return 0;
389 }
390
391 /*
392 * Write an address range to the flash chip. Data must be written in
393 * FLASH_PAGESIZE chunks. The address range may be any size provided
394 * it is within the physical boundaries.
395 */
396 static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
397 size_t *retlen, const u_char *buf)
398 {
399 struct m25p *flash = mtd_to_m25p(mtd);
400 u32 page_offset, page_size;
401 struct spi_transfer t[2];
402 struct spi_message m;
403
404 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
405 __func__, (u32)to, len);
406
407 spi_message_init(&m);
408 memset(t, 0, (sizeof t));
409
410 t[0].tx_buf = flash->command;
411 t[0].len = m25p_cmdsz(flash);
412 spi_message_add_tail(&t[0], &m);
413
414 t[1].tx_buf = buf;
415 spi_message_add_tail(&t[1], &m);
416
417 mutex_lock(&flash->lock);
418
419 /* Wait until finished previous write command. */
420 if (wait_till_ready(flash)) {
421 mutex_unlock(&flash->lock);
422 return 1;
423 }
424
425 write_enable(flash);
426
427 /* Set up the opcode in the write buffer. */
428 flash->command[0] = OPCODE_PP;
429 m25p_addr2cmd(flash, to, flash->command);
430
431 page_offset = to & (flash->page_size - 1);
432
433 /* do all the bytes fit onto one page? */
434 if (page_offset + len <= flash->page_size) {
435 t[1].len = len;
436
437 spi_sync(flash->spi, &m);
438
439 *retlen = m.actual_length - m25p_cmdsz(flash);
440 } else {
441 u32 i;
442
443 /* the size of data remaining on the first page */
444 page_size = flash->page_size - page_offset;
445
446 t[1].len = page_size;
447 spi_sync(flash->spi, &m);
448
449 *retlen = m.actual_length - m25p_cmdsz(flash);
450
451 /* write everything in flash->page_size chunks */
452 for (i = page_size; i < len; i += page_size) {
453 page_size = len - i;
454 if (page_size > flash->page_size)
455 page_size = flash->page_size;
456
457 /* write the next page to flash */
458 m25p_addr2cmd(flash, to + i, flash->command);
459
460 t[1].tx_buf = buf + i;
461 t[1].len = page_size;
462
463 wait_till_ready(flash);
464
465 write_enable(flash);
466
467 spi_sync(flash->spi, &m);
468
469 *retlen += m.actual_length - m25p_cmdsz(flash);
470 }
471 }
472
473 mutex_unlock(&flash->lock);
474
475 return 0;
476 }
477
478 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
479 size_t *retlen, const u_char *buf)
480 {
481 struct m25p *flash = mtd_to_m25p(mtd);
482 struct spi_transfer t[2];
483 struct spi_message m;
484 size_t actual;
485 int cmd_sz, ret;
486
487 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
488 __func__, (u32)to, len);
489
490 spi_message_init(&m);
491 memset(t, 0, (sizeof t));
492
493 t[0].tx_buf = flash->command;
494 t[0].len = m25p_cmdsz(flash);
495 spi_message_add_tail(&t[0], &m);
496
497 t[1].tx_buf = buf;
498 spi_message_add_tail(&t[1], &m);
499
500 mutex_lock(&flash->lock);
501
502 /* Wait until finished previous write command. */
503 ret = wait_till_ready(flash);
504 if (ret)
505 goto time_out;
506
507 write_enable(flash);
508
509 actual = to % 2;
510 /* Start write from odd address. */
511 if (actual) {
512 flash->command[0] = OPCODE_BP;
513 m25p_addr2cmd(flash, to, flash->command);
514
515 /* write one byte. */
516 t[1].len = 1;
517 spi_sync(flash->spi, &m);
518 ret = wait_till_ready(flash);
519 if (ret)
520 goto time_out;
521 *retlen += m.actual_length - m25p_cmdsz(flash);
522 }
523 to += actual;
524
525 flash->command[0] = OPCODE_AAI_WP;
526 m25p_addr2cmd(flash, to, flash->command);
527
528 /* Write out most of the data here. */
529 cmd_sz = m25p_cmdsz(flash);
530 for (; actual < len - 1; actual += 2) {
531 t[0].len = cmd_sz;
532 /* write two bytes. */
533 t[1].len = 2;
534 t[1].tx_buf = buf + actual;
535
536 spi_sync(flash->spi, &m);
537 ret = wait_till_ready(flash);
538 if (ret)
539 goto time_out;
540 *retlen += m.actual_length - cmd_sz;
541 cmd_sz = 1;
542 to += 2;
543 }
544 write_disable(flash);
545 ret = wait_till_ready(flash);
546 if (ret)
547 goto time_out;
548
549 /* Write out trailing byte if it exists. */
550 if (actual != len) {
551 write_enable(flash);
552 flash->command[0] = OPCODE_BP;
553 m25p_addr2cmd(flash, to, flash->command);
554 t[0].len = m25p_cmdsz(flash);
555 t[1].len = 1;
556 t[1].tx_buf = buf + actual;
557
558 spi_sync(flash->spi, &m);
559 ret = wait_till_ready(flash);
560 if (ret)
561 goto time_out;
562 *retlen += m.actual_length - m25p_cmdsz(flash);
563 write_disable(flash);
564 }
565
566 time_out:
567 mutex_unlock(&flash->lock);
568 return ret;
569 }
570
571 /****************************************************************************/
572
573 /*
574 * SPI device driver setup and teardown
575 */
576
577 struct flash_info {
578 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
579 * a high byte of zero plus three data bytes: the manufacturer id,
580 * then a two byte device id.
581 */
582 u32 jedec_id;
583 u16 ext_id;
584
585 /* The size listed here is what works with OPCODE_SE, which isn't
586 * necessarily called a "sector" by the vendor.
587 */
588 unsigned sector_size;
589 u16 n_sectors;
590
591 u16 page_size;
592 u16 addr_width;
593
594 u16 flags;
595 #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */
596 #define M25P_NO_ERASE 0x02 /* No erase command needed */
597 };
598
599 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
600 ((kernel_ulong_t)&(struct flash_info) { \
601 .jedec_id = (_jedec_id), \
602 .ext_id = (_ext_id), \
603 .sector_size = (_sector_size), \
604 .n_sectors = (_n_sectors), \
605 .page_size = 256, \
606 .flags = (_flags), \
607 })
608
609 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width) \
610 ((kernel_ulong_t)&(struct flash_info) { \
611 .sector_size = (_sector_size), \
612 .n_sectors = (_n_sectors), \
613 .page_size = (_page_size), \
614 .addr_width = (_addr_width), \
615 .flags = M25P_NO_ERASE, \
616 })
617
618 /* NOTE: double check command sets and memory organization when you add
619 * more flash chips. This current list focusses on newer chips, which
620 * have been converging on command sets which including JEDEC ID.
621 */
622 static const struct spi_device_id m25p_ids[] = {
623 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
624 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
625 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
626
627 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
628 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
629 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
630
631 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
632 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
633 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
634 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
635
636 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
637
638 /* EON -- en25xxx */
639 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
640 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
641 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
642 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
643
644 /* Everspin */
645 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2) },
646
647 /* Intel/Numonyx -- xxxs33b */
648 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
649 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
650 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
651 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
652
653 /* Macronix */
654 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
655 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
656 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
657 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
658 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
659 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
660 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
661 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
662 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
663 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
664
665 /* Micron */
666 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
667
668 /* Spansion -- single (large) sector size only, at least
669 * for the chips listed here (without boot sectors).
670 */
671 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SECT_4K) },
672 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SECT_4K) },
673 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
674 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, 0) },
675 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, 0) },
676 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
677 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
678 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
679 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
680 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
681 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
682 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
683 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
684 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
685 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
686 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
687 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
688
689 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
690 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K) },
691 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K) },
692 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K) },
693 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K) },
694 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K) },
695 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K) },
696 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K) },
697 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K) },
698
699 /* ST Microelectronics -- newer production may have feature updates */
700 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
701 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
702 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
703 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
704 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
705 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
706 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
707 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
708 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
709 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
710
711 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
712 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
713 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
714 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
715 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
716 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
717 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
718 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
719 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
720
721 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
722 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
723 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
724
725 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
726 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
727 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
728
729 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
730 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
731 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
732 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
733
734 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
735 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
736 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
737 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
738 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
739 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
740 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
741 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
742 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
743 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
744 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
745 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
746
747 /* Catalyst / On Semiconductor -- non-JEDEC */
748 { "cat25c11", CAT25_INFO( 16, 8, 16, 1) },
749 { "cat25c03", CAT25_INFO( 32, 8, 16, 2) },
750 { "cat25c09", CAT25_INFO( 128, 8, 32, 2) },
751 { "cat25c17", CAT25_INFO( 256, 8, 32, 2) },
752 { "cat25128", CAT25_INFO(2048, 8, 64, 2) },
753 { },
754 };
755 MODULE_DEVICE_TABLE(spi, m25p_ids);
756
757 static const struct spi_device_id *__devinit jedec_probe(struct spi_device *spi)
758 {
759 int tmp;
760 u8 code = OPCODE_RDID;
761 u8 id[5];
762 u32 jedec;
763 u16 ext_jedec;
764 struct flash_info *info;
765
766 /* JEDEC also defines an optional "extended device information"
767 * string for after vendor-specific data, after the three bytes
768 * we use here. Supporting some chips might require using it.
769 */
770 tmp = spi_write_then_read(spi, &code, 1, id, 5);
771 if (tmp < 0) {
772 pr_debug("%s: error %d reading JEDEC ID\n",
773 dev_name(&spi->dev), tmp);
774 return ERR_PTR(tmp);
775 }
776 jedec = id[0];
777 jedec = jedec << 8;
778 jedec |= id[1];
779 jedec = jedec << 8;
780 jedec |= id[2];
781
782 ext_jedec = id[3] << 8 | id[4];
783
784 for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) {
785 info = (void *)m25p_ids[tmp].driver_data;
786 if (info->jedec_id == jedec) {
787 if (info->ext_id != 0 && info->ext_id != ext_jedec)
788 continue;
789 return &m25p_ids[tmp];
790 }
791 }
792 dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec);
793 return ERR_PTR(-ENODEV);
794 }
795
796
797 /*
798 * board specific setup should have ensured the SPI clock used here
799 * matches what the READ command supports, at least until this driver
800 * understands FAST_READ (for clocks over 25 MHz).
801 */
802 static int __devinit m25p_probe(struct spi_device *spi)
803 {
804 const struct spi_device_id *id = spi_get_device_id(spi);
805 struct flash_platform_data *data;
806 struct m25p *flash;
807 struct flash_info *info;
808 unsigned i;
809 struct mtd_part_parser_data ppdata;
810
811 #ifdef CONFIG_MTD_OF_PARTS
812 if (!of_device_is_available(spi->dev.of_node))
813 return -ENODEV;
814 #endif
815
816 /* Platform data helps sort out which chip type we have, as
817 * well as how this board partitions it. If we don't have
818 * a chip ID, try the JEDEC id commands; they'll work for most
819 * newer chips, even if we don't recognize the particular chip.
820 */
821 data = spi->dev.platform_data;
822 if (data && data->type) {
823 const struct spi_device_id *plat_id;
824
825 for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) {
826 plat_id = &m25p_ids[i];
827 if (strcmp(data->type, plat_id->name))
828 continue;
829 break;
830 }
831
832 if (i < ARRAY_SIZE(m25p_ids) - 1)
833 id = plat_id;
834 else
835 dev_warn(&spi->dev, "unrecognized id %s\n", data->type);
836 }
837
838 info = (void *)id->driver_data;
839
840 if (info->jedec_id) {
841 const struct spi_device_id *jid;
842
843 jid = jedec_probe(spi);
844 if (IS_ERR(jid)) {
845 return PTR_ERR(jid);
846 } else if (jid != id) {
847 /*
848 * JEDEC knows better, so overwrite platform ID. We
849 * can't trust partitions any longer, but we'll let
850 * mtd apply them anyway, since some partitions may be
851 * marked read-only, and we don't want to lose that
852 * information, even if it's not 100% accurate.
853 */
854 dev_warn(&spi->dev, "found %s, expected %s\n",
855 jid->name, id->name);
856 id = jid;
857 info = (void *)jid->driver_data;
858 }
859 }
860
861 flash = kzalloc(sizeof *flash, GFP_KERNEL);
862 if (!flash)
863 return -ENOMEM;
864 flash->command = kmalloc(MAX_CMD_SIZE + FAST_READ_DUMMY_BYTE, GFP_KERNEL);
865 if (!flash->command) {
866 kfree(flash);
867 return -ENOMEM;
868 }
869
870 flash->spi = spi;
871 mutex_init(&flash->lock);
872 dev_set_drvdata(&spi->dev, flash);
873
874 /*
875 * Atmel, SST and Intel/Numonyx serial flash tend to power
876 * up with the software protection bits set
877 */
878
879 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
880 JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
881 JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
882 write_enable(flash);
883 write_sr(flash, 0);
884 }
885
886 if (data && data->name)
887 flash->mtd.name = data->name;
888 else
889 flash->mtd.name = dev_name(&spi->dev);
890
891 flash->mtd.type = MTD_NORFLASH;
892 flash->mtd.writesize = 1;
893 flash->mtd.flags = MTD_CAP_NORFLASH;
894 flash->mtd.size = info->sector_size * info->n_sectors;
895 flash->mtd._erase = m25p80_erase;
896 flash->mtd._read = m25p80_read;
897
898 /* sst flash chips use AAI word program */
899 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_SST)
900 flash->mtd._write = sst_write;
901 else
902 flash->mtd._write = m25p80_write;
903
904 /* prefer "small sector" erase if possible */
905 if (info->flags & SECT_4K) {
906 flash->erase_opcode = OPCODE_BE_4K;
907 flash->mtd.erasesize = 4096;
908 } else {
909 flash->erase_opcode = OPCODE_SE;
910 flash->mtd.erasesize = info->sector_size;
911 }
912
913 if (info->flags & M25P_NO_ERASE)
914 flash->mtd.flags |= MTD_NO_ERASE;
915
916 ppdata.of_node = spi->dev.of_node;
917 flash->mtd.dev.parent = &spi->dev;
918 flash->page_size = info->page_size;
919 flash->mtd.writebufsize = flash->page_size;
920
921 if (info->addr_width)
922 flash->addr_width = info->addr_width;
923 else {
924 /* enable 4-byte addressing if the device exceeds 16MiB */
925 if (flash->mtd.size > 0x1000000) {
926 flash->addr_width = 4;
927 set_4byte(flash, info->jedec_id, 1);
928 } else
929 flash->addr_width = 3;
930 }
931
932 dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
933 (long long)flash->mtd.size >> 10);
934
935 pr_debug("mtd .name = %s, .size = 0x%llx (%lldMiB) "
936 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
937 flash->mtd.name,
938 (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20),
939 flash->mtd.erasesize, flash->mtd.erasesize / 1024,
940 flash->mtd.numeraseregions);
941
942 if (flash->mtd.numeraseregions)
943 for (i = 0; i < flash->mtd.numeraseregions; i++)
944 pr_debug("mtd.eraseregions[%d] = { .offset = 0x%llx, "
945 ".erasesize = 0x%.8x (%uKiB), "
946 ".numblocks = %d }\n",
947 i, (long long)flash->mtd.eraseregions[i].offset,
948 flash->mtd.eraseregions[i].erasesize,
949 flash->mtd.eraseregions[i].erasesize / 1024,
950 flash->mtd.eraseregions[i].numblocks);
951
952
953 /* partitions should match sector boundaries; and it may be good to
954 * use readonly partitions for writeprotected sectors (BP2..BP0).
955 */
956 return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
957 data ? data->parts : NULL,
958 data ? data->nr_parts : 0);
959 }
960
961
962 static int __devexit m25p_remove(struct spi_device *spi)
963 {
964 struct m25p *flash = dev_get_drvdata(&spi->dev);
965 int status;
966
967 /* Clean up MTD stuff. */
968 status = mtd_device_unregister(&flash->mtd);
969 if (status == 0) {
970 kfree(flash->command);
971 kfree(flash);
972 }
973 return 0;
974 }
975
976
977 static struct spi_driver m25p80_driver = {
978 .driver = {
979 .name = "m25p80",
980 .owner = THIS_MODULE,
981 },
982 .id_table = m25p_ids,
983 .probe = m25p_probe,
984 .remove = __devexit_p(m25p_remove),
985
986 /* REVISIT: many of these chips have deep power-down modes, which
987 * should clearly be entered on suspend() to minimize power use.
988 * And also when they're otherwise idle...
989 */
990 };
991
992 module_spi_driver(m25p80_driver);
993
994 MODULE_LICENSE("GPL");
995 MODULE_AUTHOR("Mike Lavender");
996 MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");
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