drivers/infiniband/hw/cxgb4/iw_cxgb4.h

   1 /*
   2  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *      - Redistributions in binary form must reproduce the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer in the documentation and/or other materials
  20  *        provided with the distribution.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  23  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  24  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  25  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  26  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  27  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  28  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  29  * SOFTWARE.
  30  */
  31 #ifndef __IW_CXGB4_H__
  32 #define __IW_CXGB4_H__
  33
  34 #include <linux/mutex.h>
  35 #include <linux/list.h>
  36 #include <linux/spinlock.h>
  37 #include <linux/idr.h>
  38 #include <linux/completion.h>
  39 #include <linux/netdevice.h>
  40 #include <linux/sched.h>
  41 #include <linux/pci.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/inet.h>
  44 #include <linux/wait.h>
  45 #include <linux/kref.h>
  46 #include <linux/timer.h>
  47 #include <linux/io.h>
  48 #include <linux/kfifo.h>
  49
  50 #include <asm/byteorder.h>
  51
  52 #include <net/net_namespace.h>
  53
  54 #include <rdma/ib_verbs.h>
  55 #include <rdma/iw_cm.h>
  56
  57 #include "cxgb4.h"
  58 #include "cxgb4_uld.h"
  59 #include "l2t.h"
  60 #include "user.h"
  61
  62 #define DRV_NAME "iw_cxgb4"
  63 #define MOD DRV_NAME ":"
  64
  65 extern int c4iw_debug;
  66 #define PDBG(fmt, args...) \
  67 do { \
  68         if (c4iw_debug) \
  69                 printk(MOD fmt, ## args); \
  70 } while (0)
  71
  72 #include "t4.h"
  73
  74 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
  75 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
  76
  77 static inline void *cplhdr(struct sk_buff *skb)
  78 {
  79         return skb->data;
  80 }
  81
  82 struct c4iw_resource {
  83         struct kfifo tpt_fifo;
  84         spinlock_t tpt_fifo_lock;
  85         struct kfifo qid_fifo;
  86         spinlock_t qid_fifo_lock;
  87         struct kfifo pdid_fifo;
  88         spinlock_t pdid_fifo_lock;
  89 };
  90
  91 struct c4iw_qid_list {
  92         struct list_head entry;
  93         u32 qid;
  94 };
  95
  96 struct c4iw_dev_ucontext {
  97         struct list_head qpids;
  98         struct list_head cqids;
  99         struct mutex lock;
 100 };
 101
 102 enum c4iw_rdev_flags {
 103         T4_FATAL_ERROR = (1<<0),
 104 };
 105
 106 struct c4iw_stat {
 107         u64 total;
 108         u64 cur;
 109         u64 max;
 110 };
 111
 112 struct c4iw_stats {
 113         struct mutex lock;
 114         struct c4iw_stat qid;
 115         struct c4iw_stat pd;
 116         struct c4iw_stat stag;
 117         struct c4iw_stat pbl;
 118         struct c4iw_stat rqt;
 119         struct c4iw_stat ocqp;
 120 };
 121
 122 struct c4iw_rdev {
 123         struct c4iw_resource resource;
 124         unsigned long qpshift;
 125         u32 qpmask;
 126         unsigned long cqshift;
 127         u32 cqmask;
 128         struct c4iw_dev_ucontext uctx;
 129         struct gen_pool *pbl_pool;
 130         struct gen_pool *rqt_pool;
 131         struct gen_pool *ocqp_pool;
 132         u32 flags;
 133         struct cxgb4_lld_info lldi;
 134         unsigned long oc_mw_pa;
 135         void __iomem *oc_mw_kva;
 136         struct c4iw_stats stats;
 137 };
 138
 139 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
 140 {
 141         return rdev->flags & T4_FATAL_ERROR;
 142 }
 143
 144 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
 145 {
 146         return min((int)T4_MAX_NUM_STAG, (int)(rdev->lldi.vr->stag.size >> 5));
 147 }
 148
 149 #define C4IW_WR_TO (10*HZ)
 150
 151 struct c4iw_wr_wait {
 152         struct completion completion;
 153         int ret;
 154 };
 155
 156 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
 157 {
 158         wr_waitp->ret = 0;
 159         init_completion(&wr_waitp->completion);
 160 }
 161
 162 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
 163 {
 164         wr_waitp->ret = ret;
 165         complete(&wr_waitp->completion);
 166 }
 167
 168 static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
 169                                  struct c4iw_wr_wait *wr_waitp,
 170                                  u32 hwtid, u32 qpid,
 171                                  const char *func)
 172 {
 173         unsigned to = C4IW_WR_TO;
 174         int ret;
 175
 176         do {
 177                 ret = wait_for_completion_timeout(&wr_waitp->completion, to);
 178                 if (!ret) {
 179                         printk(KERN_ERR MOD "%s - Device %s not responding - "
 180                                "tid %u qpid %u\n", func,
 181                                pci_name(rdev->lldi.pdev), hwtid, qpid);
 182                         if (c4iw_fatal_error(rdev)) {
 183                                 wr_waitp->ret = -EIO;
 184                                 break;
 185                         }
 186                         to = to << 2;
 187                 }
 188         } while (!ret);
 189         if (wr_waitp->ret)
 190                 PDBG("%s: FW reply %d tid %u qpid %u\n",
 191                      pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid);
 192         return wr_waitp->ret;
 193 }
 194
 195 struct c4iw_dev {
 196         struct ib_device ibdev;
 197         struct c4iw_rdev rdev;
 198         u32 device_cap_flags;
 199         struct idr cqidr;
 200         struct idr qpidr;
 201         struct idr mmidr;
 202         spinlock_t lock;
 203         struct dentry *debugfs_root;
 204 };
 205
 206 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
 207 {
 208         return container_of(ibdev, struct c4iw_dev, ibdev);
 209 }
 210
 211 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
 212 {
 213         return container_of(rdev, struct c4iw_dev, rdev);
 214 }
 215
 216 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
 217 {
 218         return idr_find(&rhp->cqidr, cqid);
 219 }
 220
 221 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
 222 {
 223         return idr_find(&rhp->qpidr, qpid);
 224 }
 225
 226 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
 227 {
 228         return idr_find(&rhp->mmidr, mmid);
 229 }
 230
 231 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
 232                                 void *handle, u32 id)
 233 {
 234         int ret;
 235         int newid;
 236
 237         do {
 238                 if (!idr_pre_get(idr, GFP_KERNEL))
 239                         return -ENOMEM;
 240                 spin_lock_irq(&rhp->lock);
 241                 ret = idr_get_new_above(idr, handle, id, &newid);
 242                 BUG_ON(newid != id);
 243                 spin_unlock_irq(&rhp->lock);
 244         } while (ret == -EAGAIN);
 245
 246         return ret;
 247 }
 248
 249 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
 250 {
 251         spin_lock_irq(&rhp->lock);
 252         idr_remove(idr, id);
 253         spin_unlock_irq(&rhp->lock);
 254 }
 255
 256 struct c4iw_pd {
 257         struct ib_pd ibpd;
 258         u32 pdid;
 259         struct c4iw_dev *rhp;
 260 };
 261
 262 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
 263 {
 264         return container_of(ibpd, struct c4iw_pd, ibpd);
 265 }
 266
 267 struct tpt_attributes {
 268         u64 len;
 269         u64 va_fbo;
 270         enum fw_ri_mem_perms perms;
 271         u32 stag;
 272         u32 pdid;
 273         u32 qpid;
 274         u32 pbl_addr;
 275         u32 pbl_size;
 276         u32 state:1;
 277         u32 type:2;
 278         u32 rsvd:1;
 279         u32 remote_invaliate_disable:1;
 280         u32 zbva:1;
 281         u32 mw_bind_enable:1;
 282         u32 page_size:5;
 283 };
 284
 285 struct c4iw_mr {
 286         struct ib_mr ibmr;
 287         struct ib_umem *umem;
 288         struct c4iw_dev *rhp;
 289         u64 kva;
 290         struct tpt_attributes attr;
 291 };
 292
 293 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
 294 {
 295         return container_of(ibmr, struct c4iw_mr, ibmr);
 296 }
 297
 298 struct c4iw_mw {
 299         struct ib_mw ibmw;
 300         struct c4iw_dev *rhp;
 301         u64 kva;
 302         struct tpt_attributes attr;
 303 };
 304
 305 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
 306 {
 307         return container_of(ibmw, struct c4iw_mw, ibmw);
 308 }
 309
 310 struct c4iw_fr_page_list {
 311         struct ib_fast_reg_page_list ibpl;
 312         DEFINE_DMA_UNMAP_ADDR(mapping);
 313         dma_addr_t dma_addr;
 314         struct c4iw_dev *dev;
 315         int size;
 316 };
 317
 318 static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
 319                                         struct ib_fast_reg_page_list *ibpl)
 320 {
 321         return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
 322 }
 323
 324 struct c4iw_cq {
 325         struct ib_cq ibcq;
 326         struct c4iw_dev *rhp;
 327         struct t4_cq cq;
 328         spinlock_t lock;
 329         spinlock_t comp_handler_lock;
 330         atomic_t refcnt;
 331         wait_queue_head_t wait;
 332 };
 333
 334 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
 335 {
 336         return container_of(ibcq, struct c4iw_cq, ibcq);
 337 }
 338
 339 struct c4iw_mpa_attributes {
 340         u8 initiator;
 341         u8 recv_marker_enabled;
 342         u8 xmit_marker_enabled;
 343         u8 crc_enabled;
 344         u8 enhanced_rdma_conn;
 345         u8 version;
 346         u8 p2p_type;
 347 };
 348
 349 struct c4iw_qp_attributes {
 350         u32 scq;
 351         u32 rcq;
 352         u32 sq_num_entries;
 353         u32 rq_num_entries;
 354         u32 sq_max_sges;
 355         u32 sq_max_sges_rdma_write;
 356         u32 rq_max_sges;
 357         u32 state;
 358         u8 enable_rdma_read;
 359         u8 enable_rdma_write;
 360         u8 enable_bind;
 361         u8 enable_mmid0_fastreg;
 362         u32 max_ord;
 363         u32 max_ird;
 364         u32 pd;
 365         u32 next_state;
 366         char terminate_buffer[52];
 367         u32 terminate_msg_len;
 368         u8 is_terminate_local;
 369         struct c4iw_mpa_attributes mpa_attr;
 370         struct c4iw_ep *llp_stream_handle;
 371         u8 layer_etype;
 372         u8 ecode;
 373 };
 374
 375 struct c4iw_qp {
 376         struct ib_qp ibqp;
 377         struct c4iw_dev *rhp;
 378         struct c4iw_ep *ep;
 379         struct c4iw_qp_attributes attr;
 380         struct t4_wq wq;
 381         spinlock_t lock;
 382         struct mutex mutex;
 383         atomic_t refcnt;
 384         wait_queue_head_t wait;
 385         struct timer_list timer;
 386 };
 387
 388 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
 389 {
 390         return container_of(ibqp, struct c4iw_qp, ibqp);
 391 }
 392
 393 struct c4iw_ucontext {
 394         struct ib_ucontext ibucontext;
 395         struct c4iw_dev_ucontext uctx;
 396         u32 key;
 397         spinlock_t mmap_lock;
 398         struct list_head mmaps;
 399 };
 400
 401 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
 402 {
 403         return container_of(c, struct c4iw_ucontext, ibucontext);
 404 }
 405
 406 struct c4iw_mm_entry {
 407         struct list_head entry;
 408         u64 addr;
 409         u32 key;
 410         unsigned len;
 411 };
 412
 413 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
 414                                                 u32 key, unsigned len)
 415 {
 416         struct list_head *pos, *nxt;
 417         struct c4iw_mm_entry *mm;
 418
 419         spin_lock(&ucontext->mmap_lock);
 420         list_for_each_safe(pos, nxt, &ucontext->mmaps) {
 421
 422                 mm = list_entry(pos, struct c4iw_mm_entry, entry);
 423                 if (mm->key == key && mm->len == len) {
 424                         list_del_init(&mm->entry);
 425                         spin_unlock(&ucontext->mmap_lock);
 426                         PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
 427                              key, (unsigned long long) mm->addr, mm->len);
 428                         return mm;
 429                 }
 430         }
 431         spin_unlock(&ucontext->mmap_lock);
 432         return NULL;
 433 }
 434
 435 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
 436                                struct c4iw_mm_entry *mm)
 437 {
 438         spin_lock(&ucontext->mmap_lock);
 439         PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
 440              mm->key, (unsigned long long) mm->addr, mm->len);
 441         list_add_tail(&mm->entry, &ucontext->mmaps);
 442         spin_unlock(&ucontext->mmap_lock);
 443 }
 444
 445 enum c4iw_qp_attr_mask {
 446         C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
 447         C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
 448         C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
 449         C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
 450         C4IW_QP_ATTR_MAX_ORD = 1 << 11,
 451         C4IW_QP_ATTR_MAX_IRD = 1 << 12,
 452         C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
 453         C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
 454         C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
 455         C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
 456         C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
 457                                      C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
 458                                      C4IW_QP_ATTR_MAX_ORD |
 459                                      C4IW_QP_ATTR_MAX_IRD |
 460                                      C4IW_QP_ATTR_LLP_STREAM_HANDLE |
 461                                      C4IW_QP_ATTR_STREAM_MSG_BUFFER |
 462                                      C4IW_QP_ATTR_MPA_ATTR |
 463                                      C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
 464 };
 465
 466 int c4iw_modify_qp(struct c4iw_dev *rhp,
 467                                 struct c4iw_qp *qhp,
 468                                 enum c4iw_qp_attr_mask mask,
 469                                 struct c4iw_qp_attributes *attrs,
 470                                 int internal);
 471
 472 enum c4iw_qp_state {
 473         C4IW_QP_STATE_IDLE,
 474         C4IW_QP_STATE_RTS,
 475         C4IW_QP_STATE_ERROR,
 476         C4IW_QP_STATE_TERMINATE,
 477         C4IW_QP_STATE_CLOSING,
 478         C4IW_QP_STATE_TOT
 479 };
 480
 481 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
 482 {
 483         switch (ib_state) {
 484         case IB_QPS_RESET:
 485         case IB_QPS_INIT:
 486                 return C4IW_QP_STATE_IDLE;
 487         case IB_QPS_RTS:
 488                 return C4IW_QP_STATE_RTS;
 489         case IB_QPS_SQD:
 490                 return C4IW_QP_STATE_CLOSING;
 491         case IB_QPS_SQE:
 492                 return C4IW_QP_STATE_TERMINATE;
 493         case IB_QPS_ERR:
 494                 return C4IW_QP_STATE_ERROR;
 495         default:
 496                 return -1;
 497         }
 498 }
 499
 500 static inline u32 c4iw_ib_to_tpt_access(int a)
 501 {
 502         return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
 503                (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
 504                (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
 505                FW_RI_MEM_ACCESS_LOCAL_READ;
 506 }
 507
 508 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
 509 {
 510         return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
 511                (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
 512 }
 513
 514 enum c4iw_mmid_state {
 515         C4IW_STAG_STATE_VALID,
 516         C4IW_STAG_STATE_INVALID
 517 };
 518
 519 #define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
 520
 521 #define MPA_KEY_REQ "MPA ID Req Frame"
 522 #define MPA_KEY_REP "MPA ID Rep Frame"
 523
 524 #define MPA_MAX_PRIVATE_DATA    256
 525 #define MPA_ENHANCED_RDMA_CONN  0x10
 526 #define MPA_REJECT              0x20
 527 #define MPA_CRC                 0x40
 528 #define MPA_MARKERS             0x80
 529 #define MPA_FLAGS_MASK          0xE0
 530
 531 #define MPA_V2_PEER2PEER_MODEL          0x8000
 532 #define MPA_V2_ZERO_LEN_FPDU_RTR        0x4000
 533 #define MPA_V2_RDMA_WRITE_RTR           0x8000
 534 #define MPA_V2_RDMA_READ_RTR            0x4000
 535 #define MPA_V2_IRD_ORD_MASK             0x3FFF
 536
 537 #define c4iw_put_ep(ep) { \
 538         PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__,  \
 539              ep, atomic_read(&((ep)->kref.refcount))); \
 540         WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \
 541         kref_put(&((ep)->kref), _c4iw_free_ep); \
 542 }
 543
 544 #define c4iw_get_ep(ep) { \
 545         PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
 546              ep, atomic_read(&((ep)->kref.refcount))); \
 547         kref_get(&((ep)->kref));  \
 548 }
 549 void _c4iw_free_ep(struct kref *kref);
 550
 551 struct mpa_message {
 552         u8 key[16];
 553         u8 flags;
 554         u8 revision;
 555         __be16 private_data_size;
 556         u8 private_data[0];
 557 };
 558
 559 struct mpa_v2_conn_params {
 560         __be16 ird;
 561         __be16 ord;
 562 };
 563
 564 struct terminate_message {
 565         u8 layer_etype;
 566         u8 ecode;
 567         __be16 hdrct_rsvd;
 568         u8 len_hdrs[0];
 569 };
 570
 571 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
 572
 573 enum c4iw_layers_types {
 574         LAYER_RDMAP             = 0x00,
 575         LAYER_DDP               = 0x10,
 576         LAYER_MPA               = 0x20,
 577         RDMAP_LOCAL_CATA        = 0x00,
 578         RDMAP_REMOTE_PROT       = 0x01,
 579         RDMAP_REMOTE_OP         = 0x02,
 580         DDP_LOCAL_CATA          = 0x00,
 581         DDP_TAGGED_ERR          = 0x01,
 582         DDP_UNTAGGED_ERR        = 0x02,
 583         DDP_LLP                 = 0x03
 584 };
 585
 586 enum c4iw_rdma_ecodes {
 587         RDMAP_INV_STAG          = 0x00,
 588         RDMAP_BASE_BOUNDS       = 0x01,
 589         RDMAP_ACC_VIOL          = 0x02,
 590         RDMAP_STAG_NOT_ASSOC    = 0x03,
 591         RDMAP_TO_WRAP           = 0x04,
 592         RDMAP_INV_VERS          = 0x05,
 593         RDMAP_INV_OPCODE        = 0x06,
 594         RDMAP_STREAM_CATA       = 0x07,
 595         RDMAP_GLOBAL_CATA       = 0x08,
 596         RDMAP_CANT_INV_STAG     = 0x09,
 597         RDMAP_UNSPECIFIED       = 0xff
 598 };
 599
 600 enum c4iw_ddp_ecodes {
 601         DDPT_INV_STAG           = 0x00,
 602         DDPT_BASE_BOUNDS        = 0x01,
 603         DDPT_STAG_NOT_ASSOC     = 0x02,
 604         DDPT_TO_WRAP            = 0x03,
 605         DDPT_INV_VERS           = 0x04,
 606         DDPU_INV_QN             = 0x01,
 607         DDPU_INV_MSN_NOBUF      = 0x02,
 608         DDPU_INV_MSN_RANGE      = 0x03,
 609         DDPU_INV_MO             = 0x04,
 610         DDPU_MSG_TOOBIG         = 0x05,
 611         DDPU_INV_VERS           = 0x06
 612 };
 613
 614 enum c4iw_mpa_ecodes {
 615         MPA_CRC_ERR             = 0x02,
 616         MPA_MARKER_ERR          = 0x03,
 617         MPA_LOCAL_CATA          = 0x05,
 618         MPA_INSUFF_IRD          = 0x06,
 619         MPA_NOMATCH_RTR         = 0x07,
 620 };
 621
 622 enum c4iw_ep_state {
 623         IDLE = 0,
 624         LISTEN,
 625         CONNECTING,
 626         MPA_REQ_WAIT,
 627         MPA_REQ_SENT,
 628         MPA_REQ_RCVD,
 629         MPA_REP_SENT,
 630         FPDU_MODE,
 631         ABORTING,
 632         CLOSING,
 633         MORIBUND,
 634         DEAD,
 635 };
 636
 637 enum c4iw_ep_flags {
 638         PEER_ABORT_IN_PROGRESS  = 0,
 639         ABORT_REQ_IN_PROGRESS   = 1,
 640         RELEASE_RESOURCES       = 2,
 641         CLOSE_SENT              = 3,
 642 };
 643
 644 struct c4iw_ep_common {
 645         struct iw_cm_id *cm_id;
 646         struct c4iw_qp *qp;
 647         struct c4iw_dev *dev;
 648         enum c4iw_ep_state state;
 649         struct kref kref;
 650         struct mutex mutex;
 651         struct sockaddr_in local_addr;
 652         struct sockaddr_in remote_addr;
 653         struct c4iw_wr_wait wr_wait;
 654         unsigned long flags;
 655 };
 656
 657 struct c4iw_listen_ep {
 658         struct c4iw_ep_common com;
 659         unsigned int stid;
 660         int backlog;
 661 };
 662
 663 struct c4iw_ep {
 664         struct c4iw_ep_common com;
 665         struct c4iw_ep *parent_ep;
 666         struct timer_list timer;
 667         struct list_head entry;
 668         unsigned int atid;
 669         u32 hwtid;
 670         u32 snd_seq;
 671         u32 rcv_seq;
 672         struct l2t_entry *l2t;
 673         struct dst_entry *dst;
 674         struct sk_buff *mpa_skb;
 675         struct c4iw_mpa_attributes mpa_attr;
 676         u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
 677         unsigned int mpa_pkt_len;
 678         u32 ird;
 679         u32 ord;
 680         u32 smac_idx;
 681         u32 tx_chan;
 682         u32 mtu;
 683         u16 mss;
 684         u16 emss;
 685         u16 plen;
 686         u16 rss_qid;
 687         u16 txq_idx;
 688         u16 ctrlq_idx;
 689         u8 tos;
 690         u8 retry_with_mpa_v1;
 691         u8 tried_with_mpa_v1;
 692 };
 693
 694 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
 695 {
 696         return cm_id->provider_data;
 697 }
 698
 699 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
 700 {
 701         return cm_id->provider_data;
 702 }
 703
 704 static inline int compute_wscale(int win)
 705 {
 706         int wscale = 0;
 707
 708         while (wscale < 14 && (65535<<wscale) < win)
 709                 wscale++;
 710         return wscale;
 711 }
 712
 713 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);
 714
 715 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
 716                      struct l2t_entry *l2t);
 717 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
 718                    struct c4iw_dev_ucontext *uctx);
 719 u32 c4iw_get_resource(struct kfifo *fifo, spinlock_t *lock);
 720 void c4iw_put_resource(struct kfifo *fifo, u32 entry, spinlock_t *lock);
 721 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
 722 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
 723 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
 724 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
 725 int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev);
 726 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
 727 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
 728 void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev);
 729 void c4iw_destroy_resource(struct c4iw_resource *rscp);
 730 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
 731 int c4iw_register_device(struct c4iw_dev *dev);
 732 void c4iw_unregister_device(struct c4iw_dev *dev);
 733 int __init c4iw_cm_init(void);
 734 void __exit c4iw_cm_term(void);
 735 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
 736                                struct c4iw_dev_ucontext *uctx);
 737 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
 738                             struct c4iw_dev_ucontext *uctx);
 739 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
 740 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 741                       struct ib_send_wr **bad_wr);
 742 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 743                       struct ib_recv_wr **bad_wr);
 744 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
 745                  struct ib_mw_bind *mw_bind);
 746 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
 747 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
 748 int c4iw_destroy_listen(struct iw_cm_id *cm_id);
 749 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
 750 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
 751 void c4iw_qp_add_ref(struct ib_qp *qp);
 752 void c4iw_qp_rem_ref(struct ib_qp *qp);
 753 void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
 754 struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
 755                                         struct ib_device *device,
 756                                         int page_list_len);
 757 struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);
 758 int c4iw_dealloc_mw(struct ib_mw *mw);
 759 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd);
 760 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
 761                                            u64 length, u64 virt, int acc,
 762                                            struct ib_udata *udata);
 763 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
 764 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
 765                                         struct ib_phys_buf *buffer_list,
 766                                         int num_phys_buf,
 767                                         int acc,
 768                                         u64 *iova_start);
 769 int c4iw_reregister_phys_mem(struct ib_mr *mr,
 770                                      int mr_rereg_mask,
 771                                      struct ib_pd *pd,
 772                                      struct ib_phys_buf *buffer_list,
 773                                      int num_phys_buf,
 774                                      int acc, u64 *iova_start);
 775 int c4iw_dereg_mr(struct ib_mr *ib_mr);
 776 int c4iw_destroy_cq(struct ib_cq *ib_cq);
 777 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
 778                                         int vector,
 779                                         struct ib_ucontext *ib_context,
 780                                         struct ib_udata *udata);
 781 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
 782 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
 783 int c4iw_destroy_qp(struct ib_qp *ib_qp);
 784 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
 785                              struct ib_qp_init_attr *attrs,
 786                              struct ib_udata *udata);
 787 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
 788                                  int attr_mask, struct ib_udata *udata);
 789 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
 790 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
 791 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
 792 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
 793 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
 794 u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size);
 795 void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size);
 796 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
 797 void c4iw_flush_hw_cq(struct t4_cq *cq);
 798 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
 799 void c4iw_count_scqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
 800 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
 801 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
 802 int c4iw_flush_sq(struct t4_wq *wq, struct t4_cq *cq, int count);
 803 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
 804 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
 805 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
 806 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
 807 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
 808                 struct c4iw_dev_ucontext *uctx);
 809 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
 810 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
 811                 struct c4iw_dev_ucontext *uctx);
 812 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
 813
 814 extern struct cxgb4_client t4c_client;
 815 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
 816 extern int c4iw_max_read_depth;
 817
 818 #endif