?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
iwlwifi: refactor rx register initialization
[linux-2.6.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
blob7ca5627cc078bed3944190d36ab201c39b31c9e8
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/skbuff.h>
34 #include <linux/netdevice.h>
35 #include <linux/wireless.h>
36 #include <linux/firmware.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
39 #include <net/mac80211.h>
40
41 #include "iwl-3945-core.h"
42 #include "iwl-3945.h"
43 #include "iwl-helpers.h"
44 #include "iwl-3945-rs.h"
45
46 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
47 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
48 IWL_RATE_##r##M_IEEE, \
49 IWL_RATE_##ip##M_INDEX, \
50 IWL_RATE_##in##M_INDEX, \
51 IWL_RATE_##rp##M_INDEX, \
52 IWL_RATE_##rn##M_INDEX, \
53 IWL_RATE_##pp##M_INDEX, \
54 IWL_RATE_##np##M_INDEX, \
55 IWL_RATE_##r##M_INDEX_TABLE, \
56 IWL_RATE_##ip##M_INDEX_TABLE }
57
58 /*
59 * Parameter order:
60 * rate, prev rate, next rate, prev tgg rate, next tgg rate
61 *
62 * If there isn't a valid next or previous rate then INV is used which
63 * maps to IWL_RATE_INVALID
64 *
65 */
66 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT] = {
67 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
68 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
69 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
70 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
71 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
72 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
73 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
74 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
75 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
76 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
77 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
78 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
79 };
80
81 /* 1 = enable the iwl3945_disable_events() function */
82 #define IWL_EVT_DISABLE (0)
83 #define IWL_EVT_DISABLE_SIZE (1532/32)
84
85 /**
86 * iwl3945_disable_events - Disable selected events in uCode event log
87 *
88 * Disable an event by writing "1"s into "disable"
89 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
90 * Default values of 0 enable uCode events to be logged.
91 * Use for only special debugging. This function is just a placeholder as-is,
92 * you'll need to provide the special bits! ...
93 * ... and set IWL_EVT_DISABLE to 1. */
94 void iwl3945_disable_events(struct iwl3945_priv *priv)
95 {
96 int ret;
97 int i;
98 u32 base; /* SRAM address of event log header */
99 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
100 u32 array_size; /* # of u32 entries in array */
101 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
102 0x00000000, /* 31 - 0 Event id numbers */
103 0x00000000, /* 63 - 32 */
104 0x00000000, /* 95 - 64 */
105 0x00000000, /* 127 - 96 */
106 0x00000000, /* 159 - 128 */
107 0x00000000, /* 191 - 160 */
108 0x00000000, /* 223 - 192 */
109 0x00000000, /* 255 - 224 */
110 0x00000000, /* 287 - 256 */
111 0x00000000, /* 319 - 288 */
112 0x00000000, /* 351 - 320 */
113 0x00000000, /* 383 - 352 */
114 0x00000000, /* 415 - 384 */
115 0x00000000, /* 447 - 416 */
116 0x00000000, /* 479 - 448 */
117 0x00000000, /* 511 - 480 */
118 0x00000000, /* 543 - 512 */
119 0x00000000, /* 575 - 544 */
120 0x00000000, /* 607 - 576 */
121 0x00000000, /* 639 - 608 */
122 0x00000000, /* 671 - 640 */
123 0x00000000, /* 703 - 672 */
124 0x00000000, /* 735 - 704 */
125 0x00000000, /* 767 - 736 */
126 0x00000000, /* 799 - 768 */
127 0x00000000, /* 831 - 800 */
128 0x00000000, /* 863 - 832 */
129 0x00000000, /* 895 - 864 */
130 0x00000000, /* 927 - 896 */
131 0x00000000, /* 959 - 928 */
132 0x00000000, /* 991 - 960 */
133 0x00000000, /* 1023 - 992 */
134 0x00000000, /* 1055 - 1024 */
135 0x00000000, /* 1087 - 1056 */
136 0x00000000, /* 1119 - 1088 */
137 0x00000000, /* 1151 - 1120 */
138 0x00000000, /* 1183 - 1152 */
139 0x00000000, /* 1215 - 1184 */
140 0x00000000, /* 1247 - 1216 */
141 0x00000000, /* 1279 - 1248 */
142 0x00000000, /* 1311 - 1280 */
143 0x00000000, /* 1343 - 1312 */
144 0x00000000, /* 1375 - 1344 */
145 0x00000000, /* 1407 - 1376 */
146 0x00000000, /* 1439 - 1408 */
147 0x00000000, /* 1471 - 1440 */
148 0x00000000, /* 1503 - 1472 */
149 };
150
151 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
152 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
153 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
154 return;
155 }
156
157 ret = iwl3945_grab_nic_access(priv);
158 if (ret) {
159 IWL_WARNING("Can not read from adapter at this time.\n");
160 return;
161 }
162
163 disable_ptr = iwl3945_read_targ_mem(priv, base + (4 * sizeof(u32)));
164 array_size = iwl3945_read_targ_mem(priv, base + (5 * sizeof(u32)));
165 iwl3945_release_nic_access(priv);
166
167 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
168 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
169 disable_ptr);
170 ret = iwl3945_grab_nic_access(priv);
171 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
172 iwl3945_write_targ_mem(priv,
173 disable_ptr + (i * sizeof(u32)),
174 evt_disable[i]);
175
176 iwl3945_release_nic_access(priv);
177 } else {
178 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
179 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
180 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
181 disable_ptr, array_size);
182 }
183
184 }
185
186 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
187 {
188 int idx;
189
190 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
191 if (iwl3945_rates[idx].plcp == plcp)
192 return idx;
193 return -1;
194 }
195
196 /**
197 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
198 * @priv: eeprom and antenna fields are used to determine antenna flags
199 *
200 * priv->eeprom is used to determine if antenna AUX/MAIN are reversed
201 * priv->antenna specifies the antenna diversity mode:
202 *
203 * IWL_ANTENNA_DIVERISTY - NIC selects best antenna by itself
204 * IWL_ANTENNA_MAIN - Force MAIN antenna
205 * IWL_ANTENNA_AUX - Force AUX antenna
206 */
207 __le32 iwl3945_get_antenna_flags(const struct iwl3945_priv *priv)
208 {
209 switch (priv->antenna) {
210 case IWL_ANTENNA_DIVERSITY:
211 return 0;
212
213 case IWL_ANTENNA_MAIN:
214 if (priv->eeprom.antenna_switch_type)
215 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
216 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
217
218 case IWL_ANTENNA_AUX:
219 if (priv->eeprom.antenna_switch_type)
220 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
221 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
222 }
223
224 /* bad antenna selector value */
225 IWL_ERROR("Bad antenna selector value (0x%x)\n", priv->antenna);
226 return 0; /* "diversity" is default if error */
227 }
228
229 #ifdef CONFIG_IWL3945_DEBUG
230 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
231
232 static const char *iwl3945_get_tx_fail_reason(u32 status)
233 {
234 switch (status & TX_STATUS_MSK) {
235 case TX_STATUS_SUCCESS:
236 return "SUCCESS";
237 TX_STATUS_ENTRY(SHORT_LIMIT);
238 TX_STATUS_ENTRY(LONG_LIMIT);
239 TX_STATUS_ENTRY(FIFO_UNDERRUN);
240 TX_STATUS_ENTRY(MGMNT_ABORT);
241 TX_STATUS_ENTRY(NEXT_FRAG);
242 TX_STATUS_ENTRY(LIFE_EXPIRE);
243 TX_STATUS_ENTRY(DEST_PS);
244 TX_STATUS_ENTRY(ABORTED);
245 TX_STATUS_ENTRY(BT_RETRY);
246 TX_STATUS_ENTRY(STA_INVALID);
247 TX_STATUS_ENTRY(FRAG_DROPPED);
248 TX_STATUS_ENTRY(TID_DISABLE);
249 TX_STATUS_ENTRY(FRAME_FLUSHED);
250 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
251 TX_STATUS_ENTRY(TX_LOCKED);
252 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
253 }
254
255 return "UNKNOWN";
256 }
257 #else
258 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
259 {
260 return "";
261 }
262 #endif
263
264
265 /**
266 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
267 *
268 * When FW advances 'R' index, all entries between old and new 'R' index
269 * need to be reclaimed. As result, some free space forms. If there is
270 * enough free space (> low mark), wake the stack that feeds us.
271 */
272 static void iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv,
273 int txq_id, int index)
274 {
275 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
276 struct iwl3945_queue *q = &txq->q;
277 struct iwl3945_tx_info *tx_info;
278
279 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
280
281 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
282 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
283
284 tx_info = &txq->txb[txq->q.read_ptr];
285 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
286 tx_info->skb[0] = NULL;
287 iwl3945_hw_txq_free_tfd(priv, txq);
288 }
289
290 if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) &&
291 (txq_id != IWL_CMD_QUEUE_NUM) &&
292 priv->mac80211_registered)
293 ieee80211_wake_queue(priv->hw, txq_id);
294 }
295
296 /**
297 * iwl3945_rx_reply_tx - Handle Tx response
298 */
299 static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
300 struct iwl3945_rx_mem_buffer *rxb)
301 {
302 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
303 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
304 int txq_id = SEQ_TO_QUEUE(sequence);
305 int index = SEQ_TO_INDEX(sequence);
306 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
307 struct ieee80211_tx_info *info;
308 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
309 u32 status = le32_to_cpu(tx_resp->status);
310 int rate_idx;
311
312 if ((index >= txq->q.n_bd) || (iwl3945_x2_queue_used(&txq->q, index) == 0)) {
313 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
314 "is out of range [0-%d] %d %d\n", txq_id,
315 index, txq->q.n_bd, txq->q.write_ptr,
316 txq->q.read_ptr);
317 return;
318 }
319
320 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
321 memset(&info->status, 0, sizeof(info->status));
322
323 info->status.retry_count = tx_resp->failure_frame;
324 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
325 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
326 IEEE80211_TX_STAT_ACK : 0;
327
328 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
329 txq_id, iwl3945_get_tx_fail_reason(status), status,
330 tx_resp->rate, tx_resp->failure_frame);
331
332 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
333 if (info->band == IEEE80211_BAND_5GHZ)
334 rate_idx -= IWL_FIRST_OFDM_RATE;
335 info->tx_rate_idx = rate_idx;
336 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
337 iwl3945_tx_queue_reclaim(priv, txq_id, index);
338
339 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
340 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
341 }
342
343
344
345 /*****************************************************************************
346 *
347 * Intel PRO/Wireless 3945ABG/BG Network Connection
348 *
349 * RX handler implementations
350 *
351 *****************************************************************************/
352
353 void iwl3945_hw_rx_statistics(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
354 {
355 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
356 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
357 (int)sizeof(struct iwl3945_notif_statistics),
358 le32_to_cpu(pkt->len));
359
360 memcpy(&priv->statistics, pkt->u.raw, sizeof(priv->statistics));
361
362 iwl3945_led_background(priv);
363
364 priv->last_statistics_time = jiffies;
365 }
366
367 /******************************************************************************
368 *
369 * Misc. internal state and helper functions
370 *
371 ******************************************************************************/
372 #ifdef CONFIG_IWL3945_DEBUG
373
374 /**
375 * iwl3945_report_frame - dump frame to syslog during debug sessions
376 *
377 * You may hack this function to show different aspects of received frames,
378 * including selective frame dumps.
379 * group100 parameter selects whether to show 1 out of 100 good frames.
380 */
381 static void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
382 struct iwl3945_rx_packet *pkt,
383 struct ieee80211_hdr *header, int group100)
384 {
385 u32 to_us;
386 u32 print_summary = 0;
387 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
388 u32 hundred = 0;
389 u32 dataframe = 0;
390 __le16 fc;
391 u16 seq_ctl;
392 u16 channel;
393 u16 phy_flags;
394 u16 length;
395 u16 status;
396 u16 bcn_tmr;
397 u32 tsf_low;
398 u64 tsf;
399 u8 rssi;
400 u8 agc;
401 u16 sig_avg;
402 u16 noise_diff;
403 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
404 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
405 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
406 u8 *data = IWL_RX_DATA(pkt);
407
408 /* MAC header */
409 fc = header->frame_control;
410 seq_ctl = le16_to_cpu(header->seq_ctrl);
411
412 /* metadata */
413 channel = le16_to_cpu(rx_hdr->channel);
414 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
415 length = le16_to_cpu(rx_hdr->len);
416
417 /* end-of-frame status and timestamp */
418 status = le32_to_cpu(rx_end->status);
419 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
420 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
421 tsf = le64_to_cpu(rx_end->timestamp);
422
423 /* signal statistics */
424 rssi = rx_stats->rssi;
425 agc = rx_stats->agc;
426 sig_avg = le16_to_cpu(rx_stats->sig_avg);
427 noise_diff = le16_to_cpu(rx_stats->noise_diff);
428
429 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
430
431 /* if data frame is to us and all is good,
432 * (optionally) print summary for only 1 out of every 100 */
433 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
434 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
435 dataframe = 1;
436 if (!group100)
437 print_summary = 1; /* print each frame */
438 else if (priv->framecnt_to_us < 100) {
439 priv->framecnt_to_us++;
440 print_summary = 0;
441 } else {
442 priv->framecnt_to_us = 0;
443 print_summary = 1;
444 hundred = 1;
445 }
446 } else {
447 /* print summary for all other frames */
448 print_summary = 1;
449 }
450
451 if (print_summary) {
452 char *title;
453 int rate;
454
455 if (hundred)
456 title = "100Frames";
457 else if (ieee80211_has_retry(fc))
458 title = "Retry";
459 else if (ieee80211_is_assoc_resp(fc))
460 title = "AscRsp";
461 else if (ieee80211_is_reassoc_resp(fc))
462 title = "RasRsp";
463 else if (ieee80211_is_probe_resp(fc)) {
464 title = "PrbRsp";
465 print_dump = 1; /* dump frame contents */
466 } else if (ieee80211_is_beacon(fc)) {
467 title = "Beacon";
468 print_dump = 1; /* dump frame contents */
469 } else if (ieee80211_is_atim(fc))
470 title = "ATIM";
471 else if (ieee80211_is_auth(fc))
472 title = "Auth";
473 else if (ieee80211_is_deauth(fc))
474 title = "DeAuth";
475 else if (ieee80211_is_disassoc(fc))
476 title = "DisAssoc";
477 else
478 title = "Frame";
479
480 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
481 if (rate == -1)
482 rate = 0;
483 else
484 rate = iwl3945_rates[rate].ieee / 2;
485
486 /* print frame summary.
487 * MAC addresses show just the last byte (for brevity),
488 * but you can hack it to show more, if you'd like to. */
489 if (dataframe)
490 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
491 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
492 title, le16_to_cpu(fc), header->addr1[5],
493 length, rssi, channel, rate);
494 else {
495 /* src/dst addresses assume managed mode */
496 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
497 "src=0x%02x, rssi=%u, tim=%lu usec, "
498 "phy=0x%02x, chnl=%d\n",
499 title, le16_to_cpu(fc), header->addr1[5],
500 header->addr3[5], rssi,
501 tsf_low - priv->scan_start_tsf,
502 phy_flags, channel);
503 }
504 }
505 if (print_dump)
506 iwl3945_print_hex_dump(IWL_DL_RX, data, length);
507 }
508 #else
509 static inline void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
510 struct iwl3945_rx_packet *pkt,
511 struct ieee80211_hdr *header, int group100)
512 {
513 }
514 #endif
515
516 /* This is necessary only for a number of statistics, see the caller. */
517 static int iwl3945_is_network_packet(struct iwl3945_priv *priv,
518 struct ieee80211_hdr *header)
519 {
520 /* Filter incoming packets to determine if they are targeted toward
521 * this network, discarding packets coming from ourselves */
522 switch (priv->iw_mode) {
523 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
524 /* packets to our IBSS update information */
525 return !compare_ether_addr(header->addr3, priv->bssid);
526 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
527 /* packets to our IBSS update information */
528 return !compare_ether_addr(header->addr2, priv->bssid);
529 default:
530 return 1;
531 }
532 }
533
534 static void iwl3945_pass_packet_to_mac80211(struct iwl3945_priv *priv,
535 struct iwl3945_rx_mem_buffer *rxb,
536 struct ieee80211_rx_status *stats)
537 {
538 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
539 #ifdef CONFIG_IWL3945_LEDS
540 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
541 #endif
542 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
543 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
544 short len = le16_to_cpu(rx_hdr->len);
545
546 /* We received data from the HW, so stop the watchdog */
547 if (unlikely((len + IWL_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
548 IWL_DEBUG_DROP("Corruption detected!\n");
549 return;
550 }
551
552 /* We only process data packets if the interface is open */
553 if (unlikely(!priv->is_open)) {
554 IWL_DEBUG_DROP_LIMIT
555 ("Dropping packet while interface is not open.\n");
556 return;
557 }
558
559 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
560 /* Set the size of the skb to the size of the frame */
561 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
562
563 if (iwl3945_param_hwcrypto)
564 iwl3945_set_decrypted_flag(priv, rxb->skb,
565 le32_to_cpu(rx_end->status), stats);
566
567 #ifdef CONFIG_IWL3945_LEDS
568 if (ieee80211_is_data(hdr->frame_control))
569 priv->rxtxpackets += len;
570 #endif
571 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
572 rxb->skb = NULL;
573 }
574
575 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
576
577 static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv,
578 struct iwl3945_rx_mem_buffer *rxb)
579 {
580 struct ieee80211_hdr *header;
581 struct ieee80211_rx_status rx_status;
582 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
583 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
584 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
585 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
586 int snr;
587 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
588 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
589 u8 network_packet;
590
591 rx_status.flag = 0;
592 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
593 rx_status.freq =
594 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
595 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
596 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
597
598 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
599 if (rx_status.band == IEEE80211_BAND_5GHZ)
600 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
601
602 rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
603 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
604
605 /* set the preamble flag if appropriate */
606 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
607 rx_status.flag |= RX_FLAG_SHORTPRE;
608
609 if ((unlikely(rx_stats->phy_count > 20))) {
610 IWL_DEBUG_DROP
611 ("dsp size out of range [0,20]: "
612 "%d/n", rx_stats->phy_count);
613 return;
614 }
615
616 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
617 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
618 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
619 return;
620 }
621
622
623
624 /* Convert 3945's rssi indicator to dBm */
625 rx_status.signal = rx_stats->rssi - IWL_RSSI_OFFSET;
626
627 /* Set default noise value to -127 */
628 if (priv->last_rx_noise == 0)
629 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
630
631 /* 3945 provides noise info for OFDM frames only.
632 * sig_avg and noise_diff are measured by the 3945's digital signal
633 * processor (DSP), and indicate linear levels of signal level and
634 * distortion/noise within the packet preamble after
635 * automatic gain control (AGC). sig_avg should stay fairly
636 * constant if the radio's AGC is working well.
637 * Since these values are linear (not dB or dBm), linear
638 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
639 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
640 * to obtain noise level in dBm.
641 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
642 if (rx_stats_noise_diff) {
643 snr = rx_stats_sig_avg / rx_stats_noise_diff;
644 rx_status.noise = rx_status.signal -
645 iwl3945_calc_db_from_ratio(snr);
646 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
647 rx_status.noise);
648
649 /* If noise info not available, calculate signal quality indicator (%)
650 * using just the dBm signal level. */
651 } else {
652 rx_status.noise = priv->last_rx_noise;
653 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
654 }
655
656
657 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
658 rx_status.signal, rx_status.noise, rx_status.qual,
659 rx_stats_sig_avg, rx_stats_noise_diff);
660
661 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
662
663 network_packet = iwl3945_is_network_packet(priv, header);
664
665 IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
666 network_packet ? '*' : ' ',
667 le16_to_cpu(rx_hdr->channel),
668 rx_status.signal, rx_status.signal,
669 rx_status.noise, rx_status.rate_idx);
670
671 #ifdef CONFIG_IWL3945_DEBUG
672 if (iwl3945_debug_level & (IWL_DL_RX))
673 /* Set "1" to report good data frames in groups of 100 */
674 iwl3945_dbg_report_frame(priv, pkt, header, 1);
675 #endif
676
677 if (network_packet) {
678 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
679 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
680 priv->last_rx_rssi = rx_status.signal;
681 priv->last_rx_noise = rx_status.noise;
682 }
683
684 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
685 }
686
687 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl3945_priv *priv, void *ptr,
688 dma_addr_t addr, u16 len)
689 {
690 int count;
691 u32 pad;
692 struct iwl3945_tfd_frame *tfd = (struct iwl3945_tfd_frame *)ptr;
693
694 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
695 pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
696
697 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
698 IWL_ERROR("Error can not send more than %d chunks\n",
699 NUM_TFD_CHUNKS);
700 return -EINVAL;
701 }
702
703 tfd->pa[count].addr = cpu_to_le32(addr);
704 tfd->pa[count].len = cpu_to_le32(len);
705
706 count++;
707
708 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
709 TFD_CTL_PAD_SET(pad));
710
711 return 0;
712 }
713
714 /**
715 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
716 *
717 * Does NOT advance any indexes
718 */
719 int iwl3945_hw_txq_free_tfd(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
720 {
721 struct iwl3945_tfd_frame *bd_tmp = (struct iwl3945_tfd_frame *)&txq->bd[0];
722 struct iwl3945_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
723 struct pci_dev *dev = priv->pci_dev;
724 int i;
725 int counter;
726
727 /* classify bd */
728 if (txq->q.id == IWL_CMD_QUEUE_NUM)
729 /* nothing to cleanup after for host commands */
730 return 0;
731
732 /* sanity check */
733 counter = TFD_CTL_COUNT_GET(le32_to_cpu(bd->control_flags));
734 if (counter > NUM_TFD_CHUNKS) {
735 IWL_ERROR("Too many chunks: %i\n", counter);
736 /* @todo issue fatal error, it is quite serious situation */
737 return 0;
738 }
739
740 /* unmap chunks if any */
741
742 for (i = 1; i < counter; i++) {
743 pci_unmap_single(dev, le32_to_cpu(bd->pa[i].addr),
744 le32_to_cpu(bd->pa[i].len), PCI_DMA_TODEVICE);
745 if (txq->txb[txq->q.read_ptr].skb[0]) {
746 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
747 if (txq->txb[txq->q.read_ptr].skb[0]) {
748 /* Can be called from interrupt context */
749 dev_kfree_skb_any(skb);
750 txq->txb[txq->q.read_ptr].skb[0] = NULL;
751 }
752 }
753 }
754 return 0;
755 }
756
757 u8 iwl3945_hw_find_station(struct iwl3945_priv *priv, const u8 *addr)
758 {
759 int i;
760 int ret = IWL_INVALID_STATION;
761 unsigned long flags;
762 DECLARE_MAC_BUF(mac);
763
764 spin_lock_irqsave(&priv->sta_lock, flags);
765 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
766 if ((priv->stations[i].used) &&
767 (!compare_ether_addr
768 (priv->stations[i].sta.sta.addr, addr))) {
769 ret = i;
770 goto out;
771 }
772
773 IWL_DEBUG_INFO("can not find STA %s (total %d)\n",
774 print_mac(mac, addr), priv->num_stations);
775 out:
776 spin_unlock_irqrestore(&priv->sta_lock, flags);
777 return ret;
778 }
779
780 /**
781 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
782 *
783 */
784 void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv,
785 struct iwl3945_cmd *cmd,
786 struct ieee80211_tx_info *info,
787 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
788 {
789 unsigned long flags;
790 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
791 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
792 u16 rate_mask;
793 int rate;
794 u8 rts_retry_limit;
795 u8 data_retry_limit;
796 __le32 tx_flags;
797 __le16 fc = hdr->frame_control;
798
799 rate = iwl3945_rates[rate_index].plcp;
800 tx_flags = cmd->cmd.tx.tx_flags;
801
802 /* We need to figure out how to get the sta->supp_rates while
803 * in this running context */
804 rate_mask = IWL_RATES_MASK;
805
806 spin_lock_irqsave(&priv->sta_lock, flags);
807
808 priv->stations[sta_id].current_rate.rate_n_flags = rate;
809
810 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
811 (sta_id != priv->hw_setting.bcast_sta_id) &&
812 (sta_id != IWL_MULTICAST_ID))
813 priv->stations[IWL_STA_ID].current_rate.rate_n_flags = rate;
814
815 spin_unlock_irqrestore(&priv->sta_lock, flags);
816
817 if (tx_id >= IWL_CMD_QUEUE_NUM)
818 rts_retry_limit = 3;
819 else
820 rts_retry_limit = 7;
821
822 if (ieee80211_is_probe_resp(fc)) {
823 data_retry_limit = 3;
824 if (data_retry_limit < rts_retry_limit)
825 rts_retry_limit = data_retry_limit;
826 } else
827 data_retry_limit = IWL_DEFAULT_TX_RETRY;
828
829 if (priv->data_retry_limit != -1)
830 data_retry_limit = priv->data_retry_limit;
831
832 if (ieee80211_is_mgmt(fc)) {
833 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
834 case cpu_to_le16(IEEE80211_STYPE_AUTH):
835 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
836 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
837 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
838 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
839 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
840 tx_flags |= TX_CMD_FLG_CTS_MSK;
841 }
842 break;
843 default:
844 break;
845 }
846 }
847
848 cmd->cmd.tx.rts_retry_limit = rts_retry_limit;
849 cmd->cmd.tx.data_retry_limit = data_retry_limit;
850 cmd->cmd.tx.rate = rate;
851 cmd->cmd.tx.tx_flags = tx_flags;
852
853 /* OFDM */
854 cmd->cmd.tx.supp_rates[0] =
855 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
856
857 /* CCK */
858 cmd->cmd.tx.supp_rates[1] = (rate_mask & 0xF);
859
860 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
861 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
862 cmd->cmd.tx.rate, le32_to_cpu(cmd->cmd.tx.tx_flags),
863 cmd->cmd.tx.supp_rates[1], cmd->cmd.tx.supp_rates[0]);
864 }
865
866 u8 iwl3945_sync_sta(struct iwl3945_priv *priv, int sta_id, u16 tx_rate, u8 flags)
867 {
868 unsigned long flags_spin;
869 struct iwl3945_station_entry *station;
870
871 if (sta_id == IWL_INVALID_STATION)
872 return IWL_INVALID_STATION;
873
874 spin_lock_irqsave(&priv->sta_lock, flags_spin);
875 station = &priv->stations[sta_id];
876
877 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
878 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
879 station->current_rate.rate_n_flags = tx_rate;
880 station->sta.mode = STA_CONTROL_MODIFY_MSK;
881
882 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
883
884 iwl3945_send_add_station(priv, &station->sta, flags);
885 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
886 sta_id, tx_rate);
887 return sta_id;
888 }
889
890 static int iwl3945_nic_set_pwr_src(struct iwl3945_priv *priv, int pwr_max)
891 {
892 int rc;
893 unsigned long flags;
894
895 spin_lock_irqsave(&priv->lock, flags);
896 rc = iwl3945_grab_nic_access(priv);
897 if (rc) {
898 spin_unlock_irqrestore(&priv->lock, flags);
899 return rc;
900 }
901
902 if (!pwr_max) {
903 u32 val;
904
905 rc = pci_read_config_dword(priv->pci_dev,
906 PCI_POWER_SOURCE, &val);
907 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
908 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
909 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
910 ~APMG_PS_CTRL_MSK_PWR_SRC);
911 iwl3945_release_nic_access(priv);
912
913 iwl3945_poll_bit(priv, CSR_GPIO_IN,
914 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
915 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
916 } else
917 iwl3945_release_nic_access(priv);
918 } else {
919 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
920 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
921 ~APMG_PS_CTRL_MSK_PWR_SRC);
922
923 iwl3945_release_nic_access(priv);
924 iwl3945_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
925 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
926 }
927 spin_unlock_irqrestore(&priv->lock, flags);
928
929 return rc;
930 }
931
932 static int iwl3945_rx_init(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
933 {
934 int rc;
935 unsigned long flags;
936
937 spin_lock_irqsave(&priv->lock, flags);
938 rc = iwl3945_grab_nic_access(priv);
939 if (rc) {
940 spin_unlock_irqrestore(&priv->lock, flags);
941 return rc;
942 }
943
944 iwl3945_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr);
945 iwl3945_write_direct32(priv, FH_RCSR_RPTR_ADDR(0),
946 priv->hw_setting.shared_phys +
947 offsetof(struct iwl3945_shared, rx_read_ptr[0]));
948 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), 0);
949 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0),
950 ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
951 ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
952 ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
953 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
954 (RX_QUEUE_SIZE_LOG << ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
955 ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
956 (1 << ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
957 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
958
959 /* fake read to flush all prev I/O */
960 iwl3945_read_direct32(priv, FH_RSSR_CTRL);
961
962 iwl3945_release_nic_access(priv);
963 spin_unlock_irqrestore(&priv->lock, flags);
964
965 return 0;
966 }
967
968 static int iwl3945_tx_reset(struct iwl3945_priv *priv)
969 {
970 int rc;
971 unsigned long flags;
972
973 spin_lock_irqsave(&priv->lock, flags);
974 rc = iwl3945_grab_nic_access(priv);
975 if (rc) {
976 spin_unlock_irqrestore(&priv->lock, flags);
977 return rc;
978 }
979
980 /* bypass mode */
981 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
982
983 /* RA 0 is active */
984 iwl3945_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
985
986 /* all 6 fifo are active */
987 iwl3945_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
988
989 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
990 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
991 iwl3945_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
992 iwl3945_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
993
994 iwl3945_write_direct32(priv, FH_TSSR_CBB_BASE,
995 priv->hw_setting.shared_phys);
996
997 iwl3945_write_direct32(priv, FH_TSSR_MSG_CONFIG,
998 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
999 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1000 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1001 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1002 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1003 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1004 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
1005
1006 iwl3945_release_nic_access(priv);
1007 spin_unlock_irqrestore(&priv->lock, flags);
1008
1009 return 0;
1010 }
1011
1012 /**
1013 * iwl3945_txq_ctx_reset - Reset TX queue context
1014 *
1015 * Destroys all DMA structures and initialize them again
1016 */
1017 static int iwl3945_txq_ctx_reset(struct iwl3945_priv *priv)
1018 {
1019 int rc;
1020 int txq_id, slots_num;
1021
1022 iwl3945_hw_txq_ctx_free(priv);
1023
1024 /* Tx CMD queue */
1025 rc = iwl3945_tx_reset(priv);
1026 if (rc)
1027 goto error;
1028
1029 /* Tx queue(s) */
1030 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1031 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1032 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1033 rc = iwl3945_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1034 txq_id);
1035 if (rc) {
1036 IWL_ERROR("Tx %d queue init failed\n", txq_id);
1037 goto error;
1038 }
1039 }
1040
1041 return rc;
1042
1043 error:
1044 iwl3945_hw_txq_ctx_free(priv);
1045 return rc;
1046 }
1047
1048 int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
1049 {
1050 u8 rev_id;
1051 int rc;
1052 unsigned long flags;
1053 struct iwl3945_rx_queue *rxq = &priv->rxq;
1054
1055 iwl3945_power_init_handle(priv);
1056
1057 spin_lock_irqsave(&priv->lock, flags);
1058 iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
1059 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1060 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1061
1062 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1063 rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
1064 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1065 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1066 if (rc < 0) {
1067 spin_unlock_irqrestore(&priv->lock, flags);
1068 IWL_DEBUG_INFO("Failed to init the card\n");
1069 return rc;
1070 }
1071
1072 rc = iwl3945_grab_nic_access(priv);
1073 if (rc) {
1074 spin_unlock_irqrestore(&priv->lock, flags);
1075 return rc;
1076 }
1077 iwl3945_write_prph(priv, APMG_CLK_EN_REG,
1078 APMG_CLK_VAL_DMA_CLK_RQT |
1079 APMG_CLK_VAL_BSM_CLK_RQT);
1080 udelay(20);
1081 iwl3945_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1082 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1083 iwl3945_release_nic_access(priv);
1084 spin_unlock_irqrestore(&priv->lock, flags);
1085
1086 /* Determine HW type */
1087 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1088 if (rc)
1089 return rc;
1090 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1091
1092 iwl3945_nic_set_pwr_src(priv, 1);
1093 spin_lock_irqsave(&priv->lock, flags);
1094
1095 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1096 IWL_DEBUG_INFO("RTP type \n");
1097 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1098 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
1099 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1100 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1101 } else {
1102 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
1103 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1104 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1105 }
1106
1107 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom.sku_cap) {
1108 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
1109 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1110 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1111 } else
1112 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1113
1114 if ((priv->eeprom.board_revision & 0xF0) == 0xD0) {
1115 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1116 priv->eeprom.board_revision);
1117 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1118 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1119 } else {
1120 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1121 priv->eeprom.board_revision);
1122 iwl3945_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1123 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1124 }
1125
1126 if (priv->eeprom.almgor_m_version <= 1) {
1127 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1128 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1129 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
1130 priv->eeprom.almgor_m_version);
1131 } else {
1132 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
1133 priv->eeprom.almgor_m_version);
1134 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1135 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1136 }
1137 spin_unlock_irqrestore(&priv->lock, flags);
1138
1139 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1140 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1141
1142 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1143 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
1144
1145 /* Allocate the RX queue, or reset if it is already allocated */
1146 if (!rxq->bd) {
1147 rc = iwl3945_rx_queue_alloc(priv);
1148 if (rc) {
1149 IWL_ERROR("Unable to initialize Rx queue\n");
1150 return -ENOMEM;
1151 }
1152 } else
1153 iwl3945_rx_queue_reset(priv, rxq);
1154
1155 iwl3945_rx_replenish(priv);
1156
1157 iwl3945_rx_init(priv, rxq);
1158
1159 spin_lock_irqsave(&priv->lock, flags);
1160
1161 /* Look at using this instead:
1162 rxq->need_update = 1;
1163 iwl3945_rx_queue_update_write_ptr(priv, rxq);
1164 */
1165
1166 rc = iwl3945_grab_nic_access(priv);
1167 if (rc) {
1168 spin_unlock_irqrestore(&priv->lock, flags);
1169 return rc;
1170 }
1171 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7);
1172 iwl3945_release_nic_access(priv);
1173
1174 spin_unlock_irqrestore(&priv->lock, flags);
1175
1176 rc = iwl3945_txq_ctx_reset(priv);
1177 if (rc)
1178 return rc;
1179
1180 set_bit(STATUS_INIT, &priv->status);
1181
1182 return 0;
1183 }
1184
1185 /**
1186 * iwl3945_hw_txq_ctx_free - Free TXQ Context
1187 *
1188 * Destroy all TX DMA queues and structures
1189 */
1190 void iwl3945_hw_txq_ctx_free(struct iwl3945_priv *priv)
1191 {
1192 int txq_id;
1193
1194 /* Tx queues */
1195 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
1196 iwl3945_tx_queue_free(priv, &priv->txq[txq_id]);
1197 }
1198
1199 void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv)
1200 {
1201 int queue;
1202 unsigned long flags;
1203
1204 spin_lock_irqsave(&priv->lock, flags);
1205 if (iwl3945_grab_nic_access(priv)) {
1206 spin_unlock_irqrestore(&priv->lock, flags);
1207 iwl3945_hw_txq_ctx_free(priv);
1208 return;
1209 }
1210
1211 /* stop SCD */
1212 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0);
1213
1214 /* reset TFD queues */
1215 for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
1216 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0);
1217 iwl3945_poll_direct_bit(priv, FH_TSSR_TX_STATUS,
1218 ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue),
1219 1000);
1220 }
1221
1222 iwl3945_release_nic_access(priv);
1223 spin_unlock_irqrestore(&priv->lock, flags);
1224
1225 iwl3945_hw_txq_ctx_free(priv);
1226 }
1227
1228 int iwl3945_hw_nic_stop_master(struct iwl3945_priv *priv)
1229 {
1230 int rc = 0;
1231 u32 reg_val;
1232 unsigned long flags;
1233
1234 spin_lock_irqsave(&priv->lock, flags);
1235
1236 /* set stop master bit */
1237 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1238
1239 reg_val = iwl3945_read32(priv, CSR_GP_CNTRL);
1240
1241 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
1242 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
1243 IWL_DEBUG_INFO("Card in power save, master is already "
1244 "stopped\n");
1245 else {
1246 rc = iwl3945_poll_bit(priv, CSR_RESET,
1247 CSR_RESET_REG_FLAG_MASTER_DISABLED,
1248 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1249 if (rc < 0) {
1250 spin_unlock_irqrestore(&priv->lock, flags);
1251 return rc;
1252 }
1253 }
1254
1255 spin_unlock_irqrestore(&priv->lock, flags);
1256 IWL_DEBUG_INFO("stop master\n");
1257
1258 return rc;
1259 }
1260
1261 int iwl3945_hw_nic_reset(struct iwl3945_priv *priv)
1262 {
1263 int rc;
1264 unsigned long flags;
1265
1266 iwl3945_hw_nic_stop_master(priv);
1267
1268 spin_lock_irqsave(&priv->lock, flags);
1269
1270 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1271
1272 rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
1273 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1274 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1275
1276 rc = iwl3945_grab_nic_access(priv);
1277 if (!rc) {
1278 iwl3945_write_prph(priv, APMG_CLK_CTRL_REG,
1279 APMG_CLK_VAL_BSM_CLK_RQT);
1280
1281 udelay(10);
1282
1283 iwl3945_set_bit(priv, CSR_GP_CNTRL,
1284 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1285
1286 iwl3945_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1287 iwl3945_write_prph(priv, APMG_RTC_INT_STT_REG,
1288 0xFFFFFFFF);
1289
1290 /* enable DMA */
1291 iwl3945_write_prph(priv, APMG_CLK_EN_REG,
1292 APMG_CLK_VAL_DMA_CLK_RQT |
1293 APMG_CLK_VAL_BSM_CLK_RQT);
1294 udelay(10);
1295
1296 iwl3945_set_bits_prph(priv, APMG_PS_CTRL_REG,
1297 APMG_PS_CTRL_VAL_RESET_REQ);
1298 udelay(5);
1299 iwl3945_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1300 APMG_PS_CTRL_VAL_RESET_REQ);
1301 iwl3945_release_nic_access(priv);
1302 }
1303
1304 /* Clear the 'host command active' bit... */
1305 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1306
1307 wake_up_interruptible(&priv->wait_command_queue);
1308 spin_unlock_irqrestore(&priv->lock, flags);
1309
1310 return rc;
1311 }
1312
1313 /**
1314 * iwl3945_hw_reg_adjust_power_by_temp
1315 * return index delta into power gain settings table
1316 */
1317 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1318 {
1319 return (new_reading - old_reading) * (-11) / 100;
1320 }
1321
1322 /**
1323 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1324 */
1325 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1326 {
1327 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1328 }
1329
1330 int iwl3945_hw_get_temperature(struct iwl3945_priv *priv)
1331 {
1332 return iwl3945_read32(priv, CSR_UCODE_DRV_GP2);
1333 }
1334
1335 /**
1336 * iwl3945_hw_reg_txpower_get_temperature
1337 * get the current temperature by reading from NIC
1338 */
1339 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl3945_priv *priv)
1340 {
1341 int temperature;
1342
1343 temperature = iwl3945_hw_get_temperature(priv);
1344
1345 /* driver's okay range is -260 to +25.
1346 * human readable okay range is 0 to +285 */
1347 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1348
1349 /* handle insane temp reading */
1350 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1351 IWL_ERROR("Error bad temperature value %d\n", temperature);
1352
1353 /* if really really hot(?),
1354 * substitute the 3rd band/group's temp measured at factory */
1355 if (priv->last_temperature > 100)
1356 temperature = priv->eeprom.groups[2].temperature;
1357 else /* else use most recent "sane" value from driver */
1358 temperature = priv->last_temperature;
1359 }
1360
1361 return temperature; /* raw, not "human readable" */
1362 }
1363
1364 /* Adjust Txpower only if temperature variance is greater than threshold.
1365 *
1366 * Both are lower than older versions' 9 degrees */
1367 #define IWL_TEMPERATURE_LIMIT_TIMER 6
1368
1369 /**
1370 * is_temp_calib_needed - determines if new calibration is needed
1371 *
1372 * records new temperature in tx_mgr->temperature.
1373 * replaces tx_mgr->last_temperature *only* if calib needed
1374 * (assumes caller will actually do the calibration!). */
1375 static int is_temp_calib_needed(struct iwl3945_priv *priv)
1376 {
1377 int temp_diff;
1378
1379 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1380 temp_diff = priv->temperature - priv->last_temperature;
1381
1382 /* get absolute value */
1383 if (temp_diff < 0) {
1384 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1385 temp_diff = -temp_diff;
1386 } else if (temp_diff == 0)
1387 IWL_DEBUG_POWER("Same temp,\n");
1388 else
1389 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1390
1391 /* if we don't need calibration, *don't* update last_temperature */
1392 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1393 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1394 return 0;
1395 }
1396
1397 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1398
1399 /* assume that caller will actually do calib ...
1400 * update the "last temperature" value */
1401 priv->last_temperature = priv->temperature;
1402 return 1;
1403 }
1404
1405 #define IWL_MAX_GAIN_ENTRIES 78
1406 #define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1407 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1408
1409 /* radio and DSP power table, each step is 1/2 dB.
1410 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1411 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1412 {
1413 {251, 127}, /* 2.4 GHz, highest power */
1414 {251, 127},
1415 {251, 127},
1416 {251, 127},
1417 {251, 125},
1418 {251, 110},
1419 {251, 105},
1420 {251, 98},
1421 {187, 125},
1422 {187, 115},
1423 {187, 108},
1424 {187, 99},
1425 {243, 119},
1426 {243, 111},
1427 {243, 105},
1428 {243, 97},
1429 {243, 92},
1430 {211, 106},
1431 {211, 100},
1432 {179, 120},
1433 {179, 113},
1434 {179, 107},
1435 {147, 125},
1436 {147, 119},
1437 {147, 112},
1438 {147, 106},
1439 {147, 101},
1440 {147, 97},
1441 {147, 91},
1442 {115, 107},
1443 {235, 121},
1444 {235, 115},
1445 {235, 109},
1446 {203, 127},
1447 {203, 121},
1448 {203, 115},
1449 {203, 108},
1450 {203, 102},
1451 {203, 96},
1452 {203, 92},
1453 {171, 110},
1454 {171, 104},
1455 {171, 98},
1456 {139, 116},
1457 {227, 125},
1458 {227, 119},
1459 {227, 113},
1460 {227, 107},
1461 {227, 101},
1462 {227, 96},
1463 {195, 113},
1464 {195, 106},
1465 {195, 102},
1466 {195, 95},
1467 {163, 113},
1468 {163, 106},
1469 {163, 102},
1470 {163, 95},
1471 {131, 113},
1472 {131, 106},
1473 {131, 102},
1474 {131, 95},
1475 {99, 113},
1476 {99, 106},
1477 {99, 102},
1478 {99, 95},
1479 {67, 113},
1480 {67, 106},
1481 {67, 102},
1482 {67, 95},
1483 {35, 113},
1484 {35, 106},
1485 {35, 102},
1486 {35, 95},
1487 {3, 113},
1488 {3, 106},
1489 {3, 102},
1490 {3, 95} }, /* 2.4 GHz, lowest power */
1491 {
1492 {251, 127}, /* 5.x GHz, highest power */
1493 {251, 120},
1494 {251, 114},
1495 {219, 119},
1496 {219, 101},
1497 {187, 113},
1498 {187, 102},
1499 {155, 114},
1500 {155, 103},
1501 {123, 117},
1502 {123, 107},
1503 {123, 99},
1504 {123, 92},
1505 {91, 108},
1506 {59, 125},
1507 {59, 118},
1508 {59, 109},
1509 {59, 102},
1510 {59, 96},
1511 {59, 90},
1512 {27, 104},
1513 {27, 98},
1514 {27, 92},
1515 {115, 118},
1516 {115, 111},
1517 {115, 104},
1518 {83, 126},
1519 {83, 121},
1520 {83, 113},
1521 {83, 105},
1522 {83, 99},
1523 {51, 118},
1524 {51, 111},
1525 {51, 104},
1526 {51, 98},
1527 {19, 116},
1528 {19, 109},
1529 {19, 102},
1530 {19, 98},
1531 {19, 93},
1532 {171, 113},
1533 {171, 107},
1534 {171, 99},
1535 {139, 120},
1536 {139, 113},
1537 {139, 107},
1538 {139, 99},
1539 {107, 120},
1540 {107, 113},
1541 {107, 107},
1542 {107, 99},
1543 {75, 120},
1544 {75, 113},
1545 {75, 107},
1546 {75, 99},
1547 {43, 120},
1548 {43, 113},
1549 {43, 107},
1550 {43, 99},
1551 {11, 120},
1552 {11, 113},
1553 {11, 107},
1554 {11, 99},
1555 {131, 107},
1556 {131, 99},
1557 {99, 120},
1558 {99, 113},
1559 {99, 107},
1560 {99, 99},
1561 {67, 120},
1562 {67, 113},
1563 {67, 107},
1564 {67, 99},
1565 {35, 120},
1566 {35, 113},
1567 {35, 107},
1568 {35, 99},
1569 {3, 120} } /* 5.x GHz, lowest power */
1570 };
1571
1572 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1573 {
1574 if (index < 0)
1575 return 0;
1576 if (index >= IWL_MAX_GAIN_ENTRIES)
1577 return IWL_MAX_GAIN_ENTRIES - 1;
1578 return (u8) index;
1579 }
1580
1581 /* Kick off thermal recalibration check every 60 seconds */
1582 #define REG_RECALIB_PERIOD (60)
1583
1584 /**
1585 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1586 *
1587 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1588 * or 6 Mbit (OFDM) rates.
1589 */
1590 static void iwl3945_hw_reg_set_scan_power(struct iwl3945_priv *priv, u32 scan_tbl_index,
1591 s32 rate_index, const s8 *clip_pwrs,
1592 struct iwl3945_channel_info *ch_info,
1593 int band_index)
1594 {
1595 struct iwl3945_scan_power_info *scan_power_info;
1596 s8 power;
1597 u8 power_index;
1598
1599 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1600
1601 /* use this channel group's 6Mbit clipping/saturation pwr,
1602 * but cap at regulatory scan power restriction (set during init
1603 * based on eeprom channel data) for this channel. */
1604 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1605
1606 /* further limit to user's max power preference.
1607 * FIXME: Other spectrum management power limitations do not
1608 * seem to apply?? */
1609 power = min(power, priv->user_txpower_limit);
1610 scan_power_info->requested_power = power;
1611
1612 /* find difference between new scan *power* and current "normal"
1613 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1614 * current "normal" temperature-compensated Tx power *index* for
1615 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1616 * *index*. */
1617 power_index = ch_info->power_info[rate_index].power_table_index
1618 - (power - ch_info->power_info
1619 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1620
1621 /* store reference index that we use when adjusting *all* scan
1622 * powers. So we can accommodate user (all channel) or spectrum
1623 * management (single channel) power changes "between" temperature
1624 * feedback compensation procedures.
1625 * don't force fit this reference index into gain table; it may be a
1626 * negative number. This will help avoid errors when we're at
1627 * the lower bounds (highest gains, for warmest temperatures)
1628 * of the table. */
1629
1630 /* don't exceed table bounds for "real" setting */
1631 power_index = iwl3945_hw_reg_fix_power_index(power_index);
1632
1633 scan_power_info->power_table_index = power_index;
1634 scan_power_info->tpc.tx_gain =
1635 power_gain_table[band_index][power_index].tx_gain;
1636 scan_power_info->tpc.dsp_atten =
1637 power_gain_table[band_index][power_index].dsp_atten;
1638 }
1639
1640 /**
1641 * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings
1642 *
1643 * Configures power settings for all rates for the current channel,
1644 * using values from channel info struct, and send to NIC
1645 */
1646 int iwl3945_hw_reg_send_txpower(struct iwl3945_priv *priv)
1647 {
1648 int rate_idx, i;
1649 const struct iwl3945_channel_info *ch_info = NULL;
1650 struct iwl3945_txpowertable_cmd txpower = {
1651 .channel = priv->active_rxon.channel,
1652 };
1653
1654 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1655 ch_info = iwl3945_get_channel_info(priv,
1656 priv->band,
1657 le16_to_cpu(priv->active_rxon.channel));
1658 if (!ch_info) {
1659 IWL_ERROR
1660 ("Failed to get channel info for channel %d [%d]\n",
1661 le16_to_cpu(priv->active_rxon.channel), priv->band);
1662 return -EINVAL;
1663 }
1664
1665 if (!is_channel_valid(ch_info)) {
1666 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1667 "non-Tx channel.\n");
1668 return 0;
1669 }
1670
1671 /* fill cmd with power settings for all rates for current channel */
1672 /* Fill OFDM rate */
1673 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1674 rate_idx <= IWL_LAST_OFDM_RATE; rate_idx++, i++) {
1675
1676 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1677 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1678
1679 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1680 le16_to_cpu(txpower.channel),
1681 txpower.band,
1682 txpower.power[i].tpc.tx_gain,
1683 txpower.power[i].tpc.dsp_atten,
1684 txpower.power[i].rate);
1685 }
1686 /* Fill CCK rates */
1687 for (rate_idx = IWL_FIRST_CCK_RATE;
1688 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1689 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1690 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1691
1692 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1693 le16_to_cpu(txpower.channel),
1694 txpower.band,
1695 txpower.power[i].tpc.tx_gain,
1696 txpower.power[i].tpc.dsp_atten,
1697 txpower.power[i].rate);
1698 }
1699
1700 return iwl3945_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1701 sizeof(struct iwl3945_txpowertable_cmd), &txpower);
1702
1703 }
1704
1705 /**
1706 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1707 * @ch_info: Channel to update. Uses power_info.requested_power.
1708 *
1709 * Replace requested_power and base_power_index ch_info fields for
1710 * one channel.
1711 *
1712 * Called if user or spectrum management changes power preferences.
1713 * Takes into account h/w and modulation limitations (clip power).
1714 *
1715 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1716 *
1717 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1718 * properly fill out the scan powers, and actual h/w gain settings,
1719 * and send changes to NIC
1720 */
1721 static int iwl3945_hw_reg_set_new_power(struct iwl3945_priv *priv,
1722 struct iwl3945_channel_info *ch_info)
1723 {
1724 struct iwl3945_channel_power_info *power_info;
1725 int power_changed = 0;
1726 int i;
1727 const s8 *clip_pwrs;
1728 int power;
1729
1730 /* Get this chnlgrp's rate-to-max/clip-powers table */
1731 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1732
1733 /* Get this channel's rate-to-current-power settings table */
1734 power_info = ch_info->power_info;
1735
1736 /* update OFDM Txpower settings */
1737 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1738 i++, ++power_info) {
1739 int delta_idx;
1740
1741 /* limit new power to be no more than h/w capability */
1742 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1743 if (power == power_info->requested_power)
1744 continue;
1745
1746 /* find difference between old and new requested powers,
1747 * update base (non-temp-compensated) power index */
1748 delta_idx = (power - power_info->requested_power) * 2;
1749 power_info->base_power_index -= delta_idx;
1750
1751 /* save new requested power value */
1752 power_info->requested_power = power;
1753
1754 power_changed = 1;
1755 }
1756
1757 /* update CCK Txpower settings, based on OFDM 12M setting ...
1758 * ... all CCK power settings for a given channel are the *same*. */
1759 if (power_changed) {
1760 power =
1761 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1762 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1763
1764 /* do all CCK rates' iwl3945_channel_power_info structures */
1765 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1766 power_info->requested_power = power;
1767 power_info->base_power_index =
1768 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1769 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1770 ++power_info;
1771 }
1772 }
1773
1774 return 0;
1775 }
1776
1777 /**
1778 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1779 *
1780 * NOTE: Returned power limit may be less (but not more) than requested,
1781 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1782 * (no consideration for h/w clipping limitations).
1783 */
1784 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl3945_channel_info *ch_info)
1785 {
1786 s8 max_power;
1787
1788 #if 0
1789 /* if we're using TGd limits, use lower of TGd or EEPROM */
1790 if (ch_info->tgd_data.max_power != 0)
1791 max_power = min(ch_info->tgd_data.max_power,
1792 ch_info->eeprom.max_power_avg);
1793
1794 /* else just use EEPROM limits */
1795 else
1796 #endif
1797 max_power = ch_info->eeprom.max_power_avg;
1798
1799 return min(max_power, ch_info->max_power_avg);
1800 }
1801
1802 /**
1803 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1804 *
1805 * Compensate txpower settings of *all* channels for temperature.
1806 * This only accounts for the difference between current temperature
1807 * and the factory calibration temperatures, and bases the new settings
1808 * on the channel's base_power_index.
1809 *
1810 * If RxOn is "associated", this sends the new Txpower to NIC!
1811 */
1812 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl3945_priv *priv)
1813 {
1814 struct iwl3945_channel_info *ch_info = NULL;
1815 int delta_index;
1816 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1817 u8 a_band;
1818 u8 rate_index;
1819 u8 scan_tbl_index;
1820 u8 i;
1821 int ref_temp;
1822 int temperature = priv->temperature;
1823
1824 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1825 for (i = 0; i < priv->channel_count; i++) {
1826 ch_info = &priv->channel_info[i];
1827 a_band = is_channel_a_band(ch_info);
1828
1829 /* Get this chnlgrp's factory calibration temperature */
1830 ref_temp = (s16)priv->eeprom.groups[ch_info->group_index].
1831 temperature;
1832
1833 /* get power index adjustment based on curr and factory
1834 * temps */
1835 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1836 ref_temp);
1837
1838 /* set tx power value for all rates, OFDM and CCK */
1839 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1840 rate_index++) {
1841 int power_idx =
1842 ch_info->power_info[rate_index].base_power_index;
1843
1844 /* temperature compensate */
1845 power_idx += delta_index;
1846
1847 /* stay within table range */
1848 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1849 ch_info->power_info[rate_index].
1850 power_table_index = (u8) power_idx;
1851 ch_info->power_info[rate_index].tpc =
1852 power_gain_table[a_band][power_idx];
1853 }
1854
1855 /* Get this chnlgrp's rate-to-max/clip-powers table */
1856 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1857
1858 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1859 for (scan_tbl_index = 0;
1860 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1861 s32 actual_index = (scan_tbl_index == 0) ?
1862 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1863 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1864 actual_index, clip_pwrs,
1865 ch_info, a_band);
1866 }
1867 }
1868
1869 /* send Txpower command for current channel to ucode */
1870 return iwl3945_hw_reg_send_txpower(priv);
1871 }
1872
1873 int iwl3945_hw_reg_set_txpower(struct iwl3945_priv *priv, s8 power)
1874 {
1875 struct iwl3945_channel_info *ch_info;
1876 s8 max_power;
1877 u8 a_band;
1878 u8 i;
1879
1880 if (priv->user_txpower_limit == power) {
1881 IWL_DEBUG_POWER("Requested Tx power same as current "
1882 "limit: %ddBm.\n", power);
1883 return 0;
1884 }
1885
1886 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1887 priv->user_txpower_limit = power;
1888
1889 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1890
1891 for (i = 0; i < priv->channel_count; i++) {
1892 ch_info = &priv->channel_info[i];
1893 a_band = is_channel_a_band(ch_info);
1894
1895 /* find minimum power of all user and regulatory constraints
1896 * (does not consider h/w clipping limitations) */
1897 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1898 max_power = min(power, max_power);
1899 if (max_power != ch_info->curr_txpow) {
1900 ch_info->curr_txpow = max_power;
1901
1902 /* this considers the h/w clipping limitations */
1903 iwl3945_hw_reg_set_new_power(priv, ch_info);
1904 }
1905 }
1906
1907 /* update txpower settings for all channels,
1908 * send to NIC if associated. */
1909 is_temp_calib_needed(priv);
1910 iwl3945_hw_reg_comp_txpower_temp(priv);
1911
1912 return 0;
1913 }
1914
1915 /* will add 3945 channel switch cmd handling later */
1916 int iwl3945_hw_channel_switch(struct iwl3945_priv *priv, u16 channel)
1917 {
1918 return 0;
1919 }
1920
1921 /**
1922 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1923 *
1924 * -- reset periodic timer
1925 * -- see if temp has changed enough to warrant re-calibration ... if so:
1926 * -- correct coeffs for temp (can reset temp timer)
1927 * -- save this temp as "last",
1928 * -- send new set of gain settings to NIC
1929 * NOTE: This should continue working, even when we're not associated,
1930 * so we can keep our internal table of scan powers current. */
1931 void iwl3945_reg_txpower_periodic(struct iwl3945_priv *priv)
1932 {
1933 /* This will kick in the "brute force"
1934 * iwl3945_hw_reg_comp_txpower_temp() below */
1935 if (!is_temp_calib_needed(priv))
1936 goto reschedule;
1937
1938 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1939 * This is based *only* on current temperature,
1940 * ignoring any previous power measurements */
1941 iwl3945_hw_reg_comp_txpower_temp(priv);
1942
1943 reschedule:
1944 queue_delayed_work(priv->workqueue,
1945 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
1946 }
1947
1948 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1949 {
1950 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv,
1951 thermal_periodic.work);
1952
1953 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1954 return;
1955
1956 mutex_lock(&priv->mutex);
1957 iwl3945_reg_txpower_periodic(priv);
1958 mutex_unlock(&priv->mutex);
1959 }
1960
1961 /**
1962 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
1963 * for the channel.
1964 *
1965 * This function is used when initializing channel-info structs.
1966 *
1967 * NOTE: These channel groups do *NOT* match the bands above!
1968 * These channel groups are based on factory-tested channels;
1969 * on A-band, EEPROM's "group frequency" entries represent the top
1970 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1971 */
1972 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl3945_priv *priv,
1973 const struct iwl3945_channel_info *ch_info)
1974 {
1975 struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom.groups[0];
1976 u8 group;
1977 u16 group_index = 0; /* based on factory calib frequencies */
1978 u8 grp_channel;
1979
1980 /* Find the group index for the channel ... don't use index 1(?) */
1981 if (is_channel_a_band(ch_info)) {
1982 for (group = 1; group < 5; group++) {
1983 grp_channel = ch_grp[group].group_channel;
1984 if (ch_info->channel <= grp_channel) {
1985 group_index = group;
1986 break;
1987 }
1988 }
1989 /* group 4 has a few channels *above* its factory cal freq */
1990 if (group == 5)
1991 group_index = 4;
1992 } else
1993 group_index = 0; /* 2.4 GHz, group 0 */
1994
1995 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
1996 group_index);
1997 return group_index;
1998 }
1999
2000 /**
2001 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2002 *
2003 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2004 * into radio/DSP gain settings table for requested power.
2005 */
2006 static int iwl3945_hw_reg_get_matched_power_index(struct iwl3945_priv *priv,
2007 s8 requested_power,
2008 s32 setting_index, s32 *new_index)
2009 {
2010 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2011 s32 index0, index1;
2012 s32 power = 2 * requested_power;
2013 s32 i;
2014 const struct iwl3945_eeprom_txpower_sample *samples;
2015 s32 gains0, gains1;
2016 s32 res;
2017 s32 denominator;
2018
2019 chnl_grp = &priv->eeprom.groups[setting_index];
2020 samples = chnl_grp->samples;
2021 for (i = 0; i < 5; i++) {
2022 if (power == samples[i].power) {
2023 *new_index = samples[i].gain_index;
2024 return 0;
2025 }
2026 }
2027
2028 if (power > samples[1].power) {
2029 index0 = 0;
2030 index1 = 1;
2031 } else if (power > samples[2].power) {
2032 index0 = 1;
2033 index1 = 2;
2034 } else if (power > samples[3].power) {
2035 index0 = 2;
2036 index1 = 3;
2037 } else {
2038 index0 = 3;
2039 index1 = 4;
2040 }
2041
2042 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2043 if (denominator == 0)
2044 return -EINVAL;
2045 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2046 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2047 res = gains0 + (gains1 - gains0) *
2048 ((s32) power - (s32) samples[index0].power) / denominator +
2049 (1 << 18);
2050 *new_index = res >> 19;
2051 return 0;
2052 }
2053
2054 static void iwl3945_hw_reg_init_channel_groups(struct iwl3945_priv *priv)
2055 {
2056 u32 i;
2057 s32 rate_index;
2058 const struct iwl3945_eeprom_txpower_group *group;
2059
2060 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
2061
2062 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2063 s8 *clip_pwrs; /* table of power levels for each rate */
2064 s8 satur_pwr; /* saturation power for each chnl group */
2065 group = &priv->eeprom.groups[i];
2066
2067 /* sanity check on factory saturation power value */
2068 if (group->saturation_power < 40) {
2069 IWL_WARNING("Error: saturation power is %d, "
2070 "less than minimum expected 40\n",
2071 group->saturation_power);
2072 return;
2073 }
2074
2075 /*
2076 * Derive requested power levels for each rate, based on
2077 * hardware capabilities (saturation power for band).
2078 * Basic value is 3dB down from saturation, with further
2079 * power reductions for highest 3 data rates. These
2080 * backoffs provide headroom for high rate modulation
2081 * power peaks, without too much distortion (clipping).
2082 */
2083 /* we'll fill in this array with h/w max power levels */
2084 clip_pwrs = (s8 *) priv->clip_groups[i].clip_powers;
2085
2086 /* divide factory saturation power by 2 to find -3dB level */
2087 satur_pwr = (s8) (group->saturation_power >> 1);
2088
2089 /* fill in channel group's nominal powers for each rate */
2090 for (rate_index = 0;
2091 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2092 switch (rate_index) {
2093 case IWL_RATE_36M_INDEX_TABLE:
2094 if (i == 0) /* B/G */
2095 *clip_pwrs = satur_pwr;
2096 else /* A */
2097 *clip_pwrs = satur_pwr - 5;
2098 break;
2099 case IWL_RATE_48M_INDEX_TABLE:
2100 if (i == 0)
2101 *clip_pwrs = satur_pwr - 7;
2102 else
2103 *clip_pwrs = satur_pwr - 10;
2104 break;
2105 case IWL_RATE_54M_INDEX_TABLE:
2106 if (i == 0)
2107 *clip_pwrs = satur_pwr - 9;
2108 else
2109 *clip_pwrs = satur_pwr - 12;
2110 break;
2111 default:
2112 *clip_pwrs = satur_pwr;
2113 break;
2114 }
2115 }
2116 }
2117 }
2118
2119 /**
2120 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2121 *
2122 * Second pass (during init) to set up priv->channel_info
2123 *
2124 * Set up Tx-power settings in our channel info database for each VALID
2125 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2126 * and current temperature.
2127 *
2128 * Since this is based on current temperature (at init time), these values may
2129 * not be valid for very long, but it gives us a starting/default point,
2130 * and allows us to active (i.e. using Tx) scan.
2131 *
2132 * This does *not* write values to NIC, just sets up our internal table.
2133 */
2134 int iwl3945_txpower_set_from_eeprom(struct iwl3945_priv *priv)
2135 {
2136 struct iwl3945_channel_info *ch_info = NULL;
2137 struct iwl3945_channel_power_info *pwr_info;
2138 int delta_index;
2139 u8 rate_index;
2140 u8 scan_tbl_index;
2141 const s8 *clip_pwrs; /* array of power levels for each rate */
2142 u8 gain, dsp_atten;
2143 s8 power;
2144 u8 pwr_index, base_pwr_index, a_band;
2145 u8 i;
2146 int temperature;
2147
2148 /* save temperature reference,
2149 * so we can determine next time to calibrate */
2150 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2151 priv->last_temperature = temperature;
2152
2153 iwl3945_hw_reg_init_channel_groups(priv);
2154
2155 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2156 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2157 i++, ch_info++) {
2158 a_band = is_channel_a_band(ch_info);
2159 if (!is_channel_valid(ch_info))
2160 continue;
2161
2162 /* find this channel's channel group (*not* "band") index */
2163 ch_info->group_index =
2164 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2165
2166 /* Get this chnlgrp's rate->max/clip-powers table */
2167 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
2168
2169 /* calculate power index *adjustment* value according to
2170 * diff between current temperature and factory temperature */
2171 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2172 priv->eeprom.groups[ch_info->group_index].
2173 temperature);
2174
2175 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2176 ch_info->channel, delta_index, temperature +
2177 IWL_TEMP_CONVERT);
2178
2179 /* set tx power value for all OFDM rates */
2180 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2181 rate_index++) {
2182 s32 power_idx;
2183 int rc;
2184
2185 /* use channel group's clip-power table,
2186 * but don't exceed channel's max power */
2187 s8 pwr = min(ch_info->max_power_avg,
2188 clip_pwrs[rate_index]);
2189
2190 pwr_info = &ch_info->power_info[rate_index];
2191
2192 /* get base (i.e. at factory-measured temperature)
2193 * power table index for this rate's power */
2194 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2195 ch_info->group_index,
2196 &power_idx);
2197 if (rc) {
2198 IWL_ERROR("Invalid power index\n");
2199 return rc;
2200 }
2201 pwr_info->base_power_index = (u8) power_idx;
2202
2203 /* temperature compensate */
2204 power_idx += delta_index;
2205
2206 /* stay within range of gain table */
2207 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2208
2209 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2210 pwr_info->requested_power = pwr;
2211 pwr_info->power_table_index = (u8) power_idx;
2212 pwr_info->tpc.tx_gain =
2213 power_gain_table[a_band][power_idx].tx_gain;
2214 pwr_info->tpc.dsp_atten =
2215 power_gain_table[a_band][power_idx].dsp_atten;
2216 }
2217
2218 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2219 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2220 power = pwr_info->requested_power +
2221 IWL_CCK_FROM_OFDM_POWER_DIFF;
2222 pwr_index = pwr_info->power_table_index +
2223 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2224 base_pwr_index = pwr_info->base_power_index +
2225 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2226
2227 /* stay within table range */
2228 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2229 gain = power_gain_table[a_band][pwr_index].tx_gain;
2230 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2231
2232 /* fill each CCK rate's iwl3945_channel_power_info structure
2233 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2234 * NOTE: CCK rates start at end of OFDM rates! */
2235 for (rate_index = 0;
2236 rate_index < IWL_CCK_RATES; rate_index++) {
2237 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2238 pwr_info->requested_power = power;
2239 pwr_info->power_table_index = pwr_index;
2240 pwr_info->base_power_index = base_pwr_index;
2241 pwr_info->tpc.tx_gain = gain;
2242 pwr_info->tpc.dsp_atten = dsp_atten;
2243 }
2244
2245 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2246 for (scan_tbl_index = 0;
2247 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2248 s32 actual_index = (scan_tbl_index == 0) ?
2249 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2250 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2251 actual_index, clip_pwrs, ch_info, a_band);
2252 }
2253 }
2254
2255 return 0;
2256 }
2257
2258 int iwl3945_hw_rxq_stop(struct iwl3945_priv *priv)
2259 {
2260 int rc;
2261 unsigned long flags;
2262
2263 spin_lock_irqsave(&priv->lock, flags);
2264 rc = iwl3945_grab_nic_access(priv);
2265 if (rc) {
2266 spin_unlock_irqrestore(&priv->lock, flags);
2267 return rc;
2268 }
2269
2270 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0), 0);
2271 rc = iwl3945_poll_direct_bit(priv, FH_RSSR_STATUS, (1 << 24), 1000);
2272 if (rc < 0)
2273 IWL_ERROR("Can't stop Rx DMA.\n");
2274
2275 iwl3945_release_nic_access(priv);
2276 spin_unlock_irqrestore(&priv->lock, flags);
2277
2278 return 0;
2279 }
2280
2281 int iwl3945_hw_tx_queue_init(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
2282 {
2283 int rc;
2284 unsigned long flags;
2285 int txq_id = txq->q.id;
2286
2287 struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
2288
2289 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2290
2291 spin_lock_irqsave(&priv->lock, flags);
2292 rc = iwl3945_grab_nic_access(priv);
2293 if (rc) {
2294 spin_unlock_irqrestore(&priv->lock, flags);
2295 return rc;
2296 }
2297 iwl3945_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0);
2298 iwl3945_write_direct32(priv, FH_CBCC_BASE(txq_id), 0);
2299
2300 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(txq_id),
2301 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2302 ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2303 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2304 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2305 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2306 iwl3945_release_nic_access(priv);
2307
2308 /* fake read to flush all prev. writes */
2309 iwl3945_read32(priv, FH_TSSR_CBB_BASE);
2310 spin_unlock_irqrestore(&priv->lock, flags);
2311
2312 return 0;
2313 }
2314
2315 int iwl3945_hw_get_rx_read(struct iwl3945_priv *priv)
2316 {
2317 struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
2318
2319 return le32_to_cpu(shared_data->rx_read_ptr[0]);
2320 }
2321
2322 /**
2323 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2324 */
2325 int iwl3945_init_hw_rate_table(struct iwl3945_priv *priv)
2326 {
2327 int rc, i, index, prev_index;
2328 struct iwl3945_rate_scaling_cmd rate_cmd = {
2329 .reserved = {0, 0, 0},
2330 };
2331 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2332
2333 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2334 index = iwl3945_rates[i].table_rs_index;
2335
2336 table[index].rate_n_flags =
2337 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2338 table[index].try_cnt = priv->retry_rate;
2339 prev_index = iwl3945_get_prev_ieee_rate(i);
2340 table[index].next_rate_index = iwl3945_rates[prev_index].table_rs_index;
2341 }
2342
2343 switch (priv->band) {
2344 case IEEE80211_BAND_5GHZ:
2345 IWL_DEBUG_RATE("Select A mode rate scale\n");
2346 /* If one of the following CCK rates is used,
2347 * have it fall back to the 6M OFDM rate */
2348 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++)
2349 table[i].next_rate_index = iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2350
2351 /* Don't fall back to CCK rates */
2352 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index = IWL_RATE_9M_INDEX_TABLE;
2353
2354 /* Don't drop out of OFDM rates */
2355 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2356 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2357 break;
2358
2359 case IEEE80211_BAND_2GHZ:
2360 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
2361 /* If an OFDM rate is used, have it fall back to the
2362 * 1M CCK rates */
2363 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE; i++)
2364 table[i].next_rate_index = iwl3945_rates[IWL_FIRST_CCK_RATE].table_rs_index;
2365
2366 /* CCK shouldn't fall back to OFDM... */
2367 table[IWL_RATE_11M_INDEX_TABLE].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2368 break;
2369
2370 default:
2371 WARN_ON(1);
2372 break;
2373 }
2374
2375 /* Update the rate scaling for control frame Tx */
2376 rate_cmd.table_id = 0;
2377 rc = iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2378 &rate_cmd);
2379 if (rc)
2380 return rc;
2381
2382 /* Update the rate scaling for data frame Tx */
2383 rate_cmd.table_id = 1;
2384 return iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2385 &rate_cmd);
2386 }
2387
2388 /* Called when initializing driver */
2389 int iwl3945_hw_set_hw_setting(struct iwl3945_priv *priv)
2390 {
2391 memset((void *)&priv->hw_setting, 0,
2392 sizeof(struct iwl3945_driver_hw_info));
2393
2394 priv->hw_setting.shared_virt =
2395 pci_alloc_consistent(priv->pci_dev,
2396 sizeof(struct iwl3945_shared),
2397 &priv->hw_setting.shared_phys);
2398
2399 if (!priv->hw_setting.shared_virt) {
2400 IWL_ERROR("failed to allocate pci memory\n");
2401 mutex_unlock(&priv->mutex);
2402 return -ENOMEM;
2403 }
2404
2405 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE;
2406 priv->hw_setting.max_pkt_size = 2342;
2407 priv->hw_setting.tx_cmd_len = sizeof(struct iwl3945_tx_cmd);
2408 priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
2409 priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
2410 priv->hw_setting.max_stations = IWL3945_STATION_COUNT;
2411 priv->hw_setting.bcast_sta_id = IWL3945_BROADCAST_ID;
2412
2413 priv->hw_setting.tx_ant_num = 2;
2414 return 0;
2415 }
2416
2417 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl3945_priv *priv,
2418 struct iwl3945_frame *frame, u8 rate)
2419 {
2420 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2421 unsigned int frame_size;
2422
2423 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2424 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2425
2426 tx_beacon_cmd->tx.sta_id = priv->hw_setting.bcast_sta_id;
2427 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2428
2429 frame_size = iwl3945_fill_beacon_frame(priv,
2430 tx_beacon_cmd->frame,
2431 iwl3945_broadcast_addr,
2432 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2433
2434 BUG_ON(frame_size > MAX_MPDU_SIZE);
2435 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2436
2437 tx_beacon_cmd->tx.rate = rate;
2438 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2439 TX_CMD_FLG_TSF_MSK);
2440
2441 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2442 tx_beacon_cmd->tx.supp_rates[0] =
2443 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2444
2445 tx_beacon_cmd->tx.supp_rates[1] =
2446 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2447
2448 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2449 }
2450
2451 void iwl3945_hw_rx_handler_setup(struct iwl3945_priv *priv)
2452 {
2453 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2454 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2455 }
2456
2457 void iwl3945_hw_setup_deferred_work(struct iwl3945_priv *priv)
2458 {
2459 INIT_DELAYED_WORK(&priv->thermal_periodic,
2460 iwl3945_bg_reg_txpower_periodic);
2461 }
2462
2463 void iwl3945_hw_cancel_deferred_work(struct iwl3945_priv *priv)
2464 {
2465 cancel_delayed_work(&priv->thermal_periodic);
2466 }
2467
2468 static struct iwl_3945_cfg iwl3945_bg_cfg = {
2469 .name = "3945BG",
2470 .fw_name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode",
2471 .sku = IWL_SKU_G,
2472 };
2473
2474 static struct iwl_3945_cfg iwl3945_abg_cfg = {
2475 .name = "3945ABG",
2476 .fw_name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode",
2477 .sku = IWL_SKU_A|IWL_SKU_G,
2478 };
2479
2480 struct pci_device_id iwl3945_hw_card_ids[] = {
2481 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2482 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2483 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2484 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2485 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2486 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2487 {0}
2488 };
2489
2490 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
Linus' kernel tree