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mmc: spi: Move SSP register definitions into separate file
[linux-2.6.git] / drivers / mmc / host / mxs-mmc.c
blob26c95dc87cb211fd5cd7223aafa508bcd352e2f3
1 /*
2 * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
3 * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
4 *
5 * Copyright 2008 Embedded Alley Solutions, Inc.
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 */
22
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/of_gpio.h>
29 #include <linux/platform_device.h>
30 #include <linux/delay.h>
31 #include <linux/interrupt.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/dmaengine.h>
34 #include <linux/highmem.h>
35 #include <linux/clk.h>
36 #include <linux/err.h>
37 #include <linux/completion.h>
38 #include <linux/mmc/host.h>
39 #include <linux/mmc/mmc.h>
40 #include <linux/mmc/sdio.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/module.h>
44 #include <linux/fsl/mxs-dma.h>
45 #include <linux/pinctrl/consumer.h>
46 #include <linux/stmp_device.h>
47 #include <linux/mmc/mxs-mmc.h>
48 #include <linux/spi/mxs-spi.h>
49
50 #define DRIVER_NAME "mxs-mmc"
51
52 #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \
53 BM_SSP_CTRL1_RESP_ERR_IRQ | \
54 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \
55 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \
56 BM_SSP_CTRL1_DATA_CRC_IRQ | \
57 BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \
58 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \
59 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
60
61 /* card detect polling timeout */
62 #define MXS_MMC_DETECT_TIMEOUT (HZ/2)
63
64 struct mxs_mmc_host {
65 struct mmc_host *mmc;
66 struct mmc_request *mrq;
67 struct mmc_command *cmd;
68 struct mmc_data *data;
69
70 void __iomem *base;
71 int dma_channel;
72 struct clk *clk;
73 unsigned int clk_rate;
74
75 struct dma_chan *dmach;
76 struct mxs_dma_data dma_data;
77 unsigned int dma_dir;
78 enum dma_transfer_direction slave_dirn;
79 u32 ssp_pio_words[SSP_PIO_NUM];
80
81 enum mxs_mmc_id devid;
82 unsigned char bus_width;
83 spinlock_t lock;
84 int sdio_irq_en;
85 int wp_gpio;
86 bool wp_inverted;
87 };
88
89 static int mxs_mmc_get_ro(struct mmc_host *mmc)
90 {
91 struct mxs_mmc_host *host = mmc_priv(mmc);
92 int ret;
93
94 if (!gpio_is_valid(host->wp_gpio))
95 return -EINVAL;
96
97 ret = gpio_get_value(host->wp_gpio);
98
99 if (host->wp_inverted)
100 ret = !ret;
101
102 return ret;
103 }
104
105 static int mxs_mmc_get_cd(struct mmc_host *mmc)
106 {
107 struct mxs_mmc_host *host = mmc_priv(mmc);
108
109 return !(readl(host->base + HW_SSP_STATUS(host)) &
110 BM_SSP_STATUS_CARD_DETECT);
111 }
112
113 static void mxs_mmc_reset(struct mxs_mmc_host *host)
114 {
115 u32 ctrl0, ctrl1;
116
117 stmp_reset_block(host->base);
118
119 ctrl0 = BM_SSP_CTRL0_IGNORE_CRC;
120 ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) |
121 BF_SSP(0x7, CTRL1_WORD_LENGTH) |
122 BM_SSP_CTRL1_DMA_ENABLE |
123 BM_SSP_CTRL1_POLARITY |
124 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
125 BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
126 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
127 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
128 BM_SSP_CTRL1_RESP_ERR_IRQ_EN;
129
130 writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
131 BF_SSP(2, TIMING_CLOCK_DIVIDE) |
132 BF_SSP(0, TIMING_CLOCK_RATE),
133 host->base + HW_SSP_TIMING(host));
134
135 if (host->sdio_irq_en) {
136 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
137 ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
138 }
139
140 writel(ctrl0, host->base + HW_SSP_CTRL0);
141 writel(ctrl1, host->base + HW_SSP_CTRL1(host));
142 }
143
144 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
145 struct mmc_command *cmd);
146
147 static void mxs_mmc_request_done(struct mxs_mmc_host *host)
148 {
149 struct mmc_command *cmd = host->cmd;
150 struct mmc_data *data = host->data;
151 struct mmc_request *mrq = host->mrq;
152
153 if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
154 if (mmc_resp_type(cmd) & MMC_RSP_136) {
155 cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0(host));
156 cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1(host));
157 cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2(host));
158 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3(host));
159 } else {
160 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0(host));
161 }
162 }
163
164 if (data) {
165 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
166 data->sg_len, host->dma_dir);
167 /*
168 * If there was an error on any block, we mark all
169 * data blocks as being in error.
170 */
171 if (!data->error)
172 data->bytes_xfered = data->blocks * data->blksz;
173 else
174 data->bytes_xfered = 0;
175
176 host->data = NULL;
177 if (mrq->stop) {
178 mxs_mmc_start_cmd(host, mrq->stop);
179 return;
180 }
181 }
182
183 host->mrq = NULL;
184 mmc_request_done(host->mmc, mrq);
185 }
186
187 static void mxs_mmc_dma_irq_callback(void *param)
188 {
189 struct mxs_mmc_host *host = param;
190
191 mxs_mmc_request_done(host);
192 }
193
194 static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
195 {
196 struct mxs_mmc_host *host = dev_id;
197 struct mmc_command *cmd = host->cmd;
198 struct mmc_data *data = host->data;
199 u32 stat;
200
201 spin_lock(&host->lock);
202
203 stat = readl(host->base + HW_SSP_CTRL1(host));
204 writel(stat & MXS_MMC_IRQ_BITS,
205 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR);
206
207 if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
208 mmc_signal_sdio_irq(host->mmc);
209
210 spin_unlock(&host->lock);
211
212 if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
213 cmd->error = -ETIMEDOUT;
214 else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)
215 cmd->error = -EIO;
216
217 if (data) {
218 if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ |
219 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ))
220 data->error = -ETIMEDOUT;
221 else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ)
222 data->error = -EILSEQ;
223 else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ |
224 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ))
225 data->error = -EIO;
226 }
227
228 return IRQ_HANDLED;
229 }
230
231 static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
232 struct mxs_mmc_host *host, unsigned long flags)
233 {
234 struct dma_async_tx_descriptor *desc;
235 struct mmc_data *data = host->data;
236 struct scatterlist * sgl;
237 unsigned int sg_len;
238
239 if (data) {
240 /* data */
241 dma_map_sg(mmc_dev(host->mmc), data->sg,
242 data->sg_len, host->dma_dir);
243 sgl = data->sg;
244 sg_len = data->sg_len;
245 } else {
246 /* pio */
247 sgl = (struct scatterlist *) host->ssp_pio_words;
248 sg_len = SSP_PIO_NUM;
249 }
250
251 desc = dmaengine_prep_slave_sg(host->dmach,
252 sgl, sg_len, host->slave_dirn, flags);
253 if (desc) {
254 desc->callback = mxs_mmc_dma_irq_callback;
255 desc->callback_param = host;
256 } else {
257 if (data)
258 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
259 data->sg_len, host->dma_dir);
260 }
261
262 return desc;
263 }
264
265 static void mxs_mmc_bc(struct mxs_mmc_host *host)
266 {
267 struct mmc_command *cmd = host->cmd;
268 struct dma_async_tx_descriptor *desc;
269 u32 ctrl0, cmd0, cmd1;
270
271 ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC;
272 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC;
273 cmd1 = cmd->arg;
274
275 if (host->sdio_irq_en) {
276 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
277 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
278 }
279
280 host->ssp_pio_words[0] = ctrl0;
281 host->ssp_pio_words[1] = cmd0;
282 host->ssp_pio_words[2] = cmd1;
283 host->dma_dir = DMA_NONE;
284 host->slave_dirn = DMA_TRANS_NONE;
285 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
286 if (!desc)
287 goto out;
288
289 dmaengine_submit(desc);
290 dma_async_issue_pending(host->dmach);
291 return;
292
293 out:
294 dev_warn(mmc_dev(host->mmc),
295 "%s: failed to prep dma\n", __func__);
296 }
297
298 static void mxs_mmc_ac(struct mxs_mmc_host *host)
299 {
300 struct mmc_command *cmd = host->cmd;
301 struct dma_async_tx_descriptor *desc;
302 u32 ignore_crc, get_resp, long_resp;
303 u32 ctrl0, cmd0, cmd1;
304
305 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
306 0 : BM_SSP_CTRL0_IGNORE_CRC;
307 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
308 BM_SSP_CTRL0_GET_RESP : 0;
309 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
310 BM_SSP_CTRL0_LONG_RESP : 0;
311
312 ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp;
313 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
314 cmd1 = cmd->arg;
315
316 if (host->sdio_irq_en) {
317 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
318 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
319 }
320
321 host->ssp_pio_words[0] = ctrl0;
322 host->ssp_pio_words[1] = cmd0;
323 host->ssp_pio_words[2] = cmd1;
324 host->dma_dir = DMA_NONE;
325 host->slave_dirn = DMA_TRANS_NONE;
326 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
327 if (!desc)
328 goto out;
329
330 dmaengine_submit(desc);
331 dma_async_issue_pending(host->dmach);
332 return;
333
334 out:
335 dev_warn(mmc_dev(host->mmc),
336 "%s: failed to prep dma\n", __func__);
337 }
338
339 static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
340 {
341 const unsigned int ssp_timeout_mul = 4096;
342 /*
343 * Calculate ticks in ms since ns are large numbers
344 * and might overflow
345 */
346 const unsigned int clock_per_ms = clock_rate / 1000;
347 const unsigned int ms = ns / 1000;
348 const unsigned int ticks = ms * clock_per_ms;
349 const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
350
351 WARN_ON(ssp_ticks == 0);
352 return ssp_ticks;
353 }
354
355 static void mxs_mmc_adtc(struct mxs_mmc_host *host)
356 {
357 struct mmc_command *cmd = host->cmd;
358 struct mmc_data *data = cmd->data;
359 struct dma_async_tx_descriptor *desc;
360 struct scatterlist *sgl = data->sg, *sg;
361 unsigned int sg_len = data->sg_len;
362 int i;
363
364 unsigned short dma_data_dir, timeout;
365 enum dma_transfer_direction slave_dirn;
366 unsigned int data_size = 0, log2_blksz;
367 unsigned int blocks = data->blocks;
368
369 u32 ignore_crc, get_resp, long_resp, read;
370 u32 ctrl0, cmd0, cmd1, val;
371
372 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
373 0 : BM_SSP_CTRL0_IGNORE_CRC;
374 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
375 BM_SSP_CTRL0_GET_RESP : 0;
376 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
377 BM_SSP_CTRL0_LONG_RESP : 0;
378
379 if (data->flags & MMC_DATA_WRITE) {
380 dma_data_dir = DMA_TO_DEVICE;
381 slave_dirn = DMA_MEM_TO_DEV;
382 read = 0;
383 } else {
384 dma_data_dir = DMA_FROM_DEVICE;
385 slave_dirn = DMA_DEV_TO_MEM;
386 read = BM_SSP_CTRL0_READ;
387 }
388
389 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) |
390 ignore_crc | get_resp | long_resp |
391 BM_SSP_CTRL0_DATA_XFER | read |
392 BM_SSP_CTRL0_WAIT_FOR_IRQ |
393 BM_SSP_CTRL0_ENABLE;
394
395 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
396
397 /* get logarithm to base 2 of block size for setting register */
398 log2_blksz = ilog2(data->blksz);
399
400 /*
401 * take special care of the case that data size from data->sg
402 * is not equal to blocks x blksz
403 */
404 for_each_sg(sgl, sg, sg_len, i)
405 data_size += sg->length;
406
407 if (data_size != data->blocks * data->blksz)
408 blocks = 1;
409
410 /* xfer count, block size and count need to be set differently */
411 if (ssp_is_old(host)) {
412 ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT);
413 cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) |
414 BF_SSP(blocks - 1, CMD0_BLOCK_COUNT);
415 } else {
416 writel(data_size, host->base + HW_SSP_XFER_SIZE);
417 writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
418 BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT),
419 host->base + HW_SSP_BLOCK_SIZE);
420 }
421
422 if ((cmd->opcode == MMC_STOP_TRANSMISSION) ||
423 (cmd->opcode == SD_IO_RW_EXTENDED))
424 cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
425
426 cmd1 = cmd->arg;
427
428 if (host->sdio_irq_en) {
429 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
430 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
431 }
432
433 /* set the timeout count */
434 timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns);
435 val = readl(host->base + HW_SSP_TIMING(host));
436 val &= ~(BM_SSP_TIMING_TIMEOUT);
437 val |= BF_SSP(timeout, TIMING_TIMEOUT);
438 writel(val, host->base + HW_SSP_TIMING(host));
439
440 /* pio */
441 host->ssp_pio_words[0] = ctrl0;
442 host->ssp_pio_words[1] = cmd0;
443 host->ssp_pio_words[2] = cmd1;
444 host->dma_dir = DMA_NONE;
445 host->slave_dirn = DMA_TRANS_NONE;
446 desc = mxs_mmc_prep_dma(host, 0);
447 if (!desc)
448 goto out;
449
450 /* append data sg */
451 WARN_ON(host->data != NULL);
452 host->data = data;
453 host->dma_dir = dma_data_dir;
454 host->slave_dirn = slave_dirn;
455 desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
456 if (!desc)
457 goto out;
458
459 dmaengine_submit(desc);
460 dma_async_issue_pending(host->dmach);
461 return;
462 out:
463 dev_warn(mmc_dev(host->mmc),
464 "%s: failed to prep dma\n", __func__);
465 }
466
467 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
468 struct mmc_command *cmd)
469 {
470 host->cmd = cmd;
471
472 switch (mmc_cmd_type(cmd)) {
473 case MMC_CMD_BC:
474 mxs_mmc_bc(host);
475 break;
476 case MMC_CMD_BCR:
477 mxs_mmc_ac(host);
478 break;
479 case MMC_CMD_AC:
480 mxs_mmc_ac(host);
481 break;
482 case MMC_CMD_ADTC:
483 mxs_mmc_adtc(host);
484 break;
485 default:
486 dev_warn(mmc_dev(host->mmc),
487 "%s: unknown MMC command\n", __func__);
488 break;
489 }
490 }
491
492 static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
493 {
494 struct mxs_mmc_host *host = mmc_priv(mmc);
495
496 WARN_ON(host->mrq != NULL);
497 host->mrq = mrq;
498 mxs_mmc_start_cmd(host, mrq->cmd);
499 }
500
501 static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate)
502 {
503 unsigned int ssp_clk, ssp_sck;
504 u32 clock_divide, clock_rate;
505 u32 val;
506
507 ssp_clk = clk_get_rate(host->clk);
508
509 for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
510 clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
511 clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
512 if (clock_rate <= 255)
513 break;
514 }
515
516 if (clock_divide > 254) {
517 dev_err(mmc_dev(host->mmc),
518 "%s: cannot set clock to %d\n", __func__, rate);
519 return;
520 }
521
522 ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
523
524 val = readl(host->base + HW_SSP_TIMING(host));
525 val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
526 val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
527 val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
528 writel(val, host->base + HW_SSP_TIMING(host));
529
530 host->clk_rate = ssp_sck;
531
532 dev_dbg(mmc_dev(host->mmc),
533 "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
534 __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
535 }
536
537 static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
538 {
539 struct mxs_mmc_host *host = mmc_priv(mmc);
540
541 if (ios->bus_width == MMC_BUS_WIDTH_8)
542 host->bus_width = 2;
543 else if (ios->bus_width == MMC_BUS_WIDTH_4)
544 host->bus_width = 1;
545 else
546 host->bus_width = 0;
547
548 if (ios->clock)
549 mxs_mmc_set_clk_rate(host, ios->clock);
550 }
551
552 static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
553 {
554 struct mxs_mmc_host *host = mmc_priv(mmc);
555 unsigned long flags;
556
557 spin_lock_irqsave(&host->lock, flags);
558
559 host->sdio_irq_en = enable;
560
561 if (enable) {
562 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
563 host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
564 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
565 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_SET);
566
567 if (readl(host->base + HW_SSP_STATUS(host)) &
568 BM_SSP_STATUS_SDIO_IRQ)
569 mmc_signal_sdio_irq(host->mmc);
570
571 } else {
572 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
573 host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
574 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
575 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR);
576 }
577
578 spin_unlock_irqrestore(&host->lock, flags);
579 }
580
581 static const struct mmc_host_ops mxs_mmc_ops = {
582 .request = mxs_mmc_request,
583 .get_ro = mxs_mmc_get_ro,
584 .get_cd = mxs_mmc_get_cd,
585 .set_ios = mxs_mmc_set_ios,
586 .enable_sdio_irq = mxs_mmc_enable_sdio_irq,
587 };
588
589 static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
590 {
591 struct mxs_mmc_host *host = param;
592
593 if (!mxs_dma_is_apbh(chan))
594 return false;
595
596 if (chan->chan_id != host->dma_channel)
597 return false;
598
599 chan->private = &host->dma_data;
600
601 return true;
602 }
603
604 static struct platform_device_id mxs_mmc_ids[] = {
605 {
606 .name = "imx23-mmc",
607 .driver_data = IMX23_MMC,
608 }, {
609 .name = "imx28-mmc",
610 .driver_data = IMX28_MMC,
611 }, {
612 /* sentinel */
613 }
614 };
615 MODULE_DEVICE_TABLE(platform, mxs_mmc_ids);
616
617 static const struct of_device_id mxs_mmc_dt_ids[] = {
618 { .compatible = "fsl,imx23-mmc", .data = (void *) IMX23_MMC, },
619 { .compatible = "fsl,imx28-mmc", .data = (void *) IMX28_MMC, },
620 { /* sentinel */ }
621 };
622 MODULE_DEVICE_TABLE(of, mxs_mmc_dt_ids);
623
624 static int mxs_mmc_probe(struct platform_device *pdev)
625 {
626 const struct of_device_id *of_id =
627 of_match_device(mxs_mmc_dt_ids, &pdev->dev);
628 struct device_node *np = pdev->dev.of_node;
629 struct mxs_mmc_host *host;
630 struct mmc_host *mmc;
631 struct resource *iores, *dmares;
632 struct mxs_mmc_platform_data *pdata;
633 struct pinctrl *pinctrl;
634 int ret = 0, irq_err, irq_dma;
635 dma_cap_mask_t mask;
636 struct regulator *reg_vmmc;
637 enum of_gpio_flags flags;
638
639 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
640 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
641 irq_err = platform_get_irq(pdev, 0);
642 irq_dma = platform_get_irq(pdev, 1);
643 if (!iores || irq_err < 0 || irq_dma < 0)
644 return -EINVAL;
645
646 mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev);
647 if (!mmc)
648 return -ENOMEM;
649
650 host = mmc_priv(mmc);
651 host->base = devm_request_and_ioremap(&pdev->dev, iores);
652 if (!host->base) {
653 ret = -EADDRNOTAVAIL;
654 goto out_mmc_free;
655 }
656
657 if (np) {
658 host->devid = (enum mxs_mmc_id) of_id->data;
659 /*
660 * TODO: This is a temporary solution and should be changed
661 * to use generic DMA binding later when the helpers get in.
662 */
663 ret = of_property_read_u32(np, "fsl,ssp-dma-channel",
664 &host->dma_channel);
665 if (ret) {
666 dev_err(mmc_dev(host->mmc),
667 "failed to get dma channel\n");
668 goto out_mmc_free;
669 }
670 } else {
671 host->devid = pdev->id_entry->driver_data;
672 host->dma_channel = dmares->start;
673 }
674
675 host->mmc = mmc;
676 host->sdio_irq_en = 0;
677
678 reg_vmmc = devm_regulator_get(&pdev->dev, "vmmc");
679 if (!IS_ERR(reg_vmmc)) {
680 ret = regulator_enable(reg_vmmc);
681 if (ret) {
682 dev_err(&pdev->dev,
683 "Failed to enable vmmc regulator: %d\n", ret);
684 goto out_mmc_free;
685 }
686 }
687
688 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
689 if (IS_ERR(pinctrl)) {
690 ret = PTR_ERR(pinctrl);
691 goto out_mmc_free;
692 }
693
694 host->clk = clk_get(&pdev->dev, NULL);
695 if (IS_ERR(host->clk)) {
696 ret = PTR_ERR(host->clk);
697 goto out_mmc_free;
698 }
699 clk_prepare_enable(host->clk);
700
701 mxs_mmc_reset(host);
702
703 dma_cap_zero(mask);
704 dma_cap_set(DMA_SLAVE, mask);
705 host->dma_data.chan_irq = irq_dma;
706 host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host);
707 if (!host->dmach) {
708 dev_err(mmc_dev(host->mmc),
709 "%s: failed to request dma\n", __func__);
710 goto out_clk_put;
711 }
712
713 /* set mmc core parameters */
714 mmc->ops = &mxs_mmc_ops;
715 mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
716 MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL;
717
718 pdata = mmc_dev(host->mmc)->platform_data;
719 if (!pdata) {
720 u32 bus_width = 0;
721 of_property_read_u32(np, "bus-width", &bus_width);
722 if (bus_width == 4)
723 mmc->caps |= MMC_CAP_4_BIT_DATA;
724 else if (bus_width == 8)
725 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
726 host->wp_gpio = of_get_named_gpio_flags(np, "wp-gpios", 0,
727 &flags);
728 if (flags & OF_GPIO_ACTIVE_LOW)
729 host->wp_inverted = 1;
730 } else {
731 if (pdata->flags & SLOTF_8_BIT_CAPABLE)
732 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
733 if (pdata->flags & SLOTF_4_BIT_CAPABLE)
734 mmc->caps |= MMC_CAP_4_BIT_DATA;
735 host->wp_gpio = pdata->wp_gpio;
736 }
737
738 mmc->f_min = 400000;
739 mmc->f_max = 288000000;
740 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
741
742 mmc->max_segs = 52;
743 mmc->max_blk_size = 1 << 0xf;
744 mmc->max_blk_count = (ssp_is_old(host)) ? 0xff : 0xffffff;
745 mmc->max_req_size = (ssp_is_old(host)) ? 0xffff : 0xffffffff;
746 mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev);
747
748 platform_set_drvdata(pdev, mmc);
749
750 ret = devm_request_irq(&pdev->dev, irq_err, mxs_mmc_irq_handler, 0,
751 DRIVER_NAME, host);
752 if (ret)
753 goto out_free_dma;
754
755 spin_lock_init(&host->lock);
756
757 ret = mmc_add_host(mmc);
758 if (ret)
759 goto out_free_dma;
760
761 dev_info(mmc_dev(host->mmc), "initialized\n");
762
763 return 0;
764
765 out_free_dma:
766 if (host->dmach)
767 dma_release_channel(host->dmach);
768 out_clk_put:
769 clk_disable_unprepare(host->clk);
770 clk_put(host->clk);
771 out_mmc_free:
772 mmc_free_host(mmc);
773 return ret;
774 }
775
776 static int mxs_mmc_remove(struct platform_device *pdev)
777 {
778 struct mmc_host *mmc = platform_get_drvdata(pdev);
779 struct mxs_mmc_host *host = mmc_priv(mmc);
780
781 mmc_remove_host(mmc);
782
783 platform_set_drvdata(pdev, NULL);
784
785 if (host->dmach)
786 dma_release_channel(host->dmach);
787
788 clk_disable_unprepare(host->clk);
789 clk_put(host->clk);
790
791 mmc_free_host(mmc);
792
793 return 0;
794 }
795
796 #ifdef CONFIG_PM
797 static int mxs_mmc_suspend(struct device *dev)
798 {
799 struct mmc_host *mmc = dev_get_drvdata(dev);
800 struct mxs_mmc_host *host = mmc_priv(mmc);
801 int ret = 0;
802
803 ret = mmc_suspend_host(mmc);
804
805 clk_disable_unprepare(host->clk);
806
807 return ret;
808 }
809
810 static int mxs_mmc_resume(struct device *dev)
811 {
812 struct mmc_host *mmc = dev_get_drvdata(dev);
813 struct mxs_mmc_host *host = mmc_priv(mmc);
814 int ret = 0;
815
816 clk_prepare_enable(host->clk);
817
818 ret = mmc_resume_host(mmc);
819
820 return ret;
821 }
822
823 static const struct dev_pm_ops mxs_mmc_pm_ops = {
824 .suspend = mxs_mmc_suspend,
825 .resume = mxs_mmc_resume,
826 };
827 #endif
828
829 static struct platform_driver mxs_mmc_driver = {
830 .probe = mxs_mmc_probe,
831 .remove = mxs_mmc_remove,
832 .id_table = mxs_mmc_ids,
833 .driver = {
834 .name = DRIVER_NAME,
835 .owner = THIS_MODULE,
836 #ifdef CONFIG_PM
837 .pm = &mxs_mmc_pm_ops,
838 #endif
839 .of_match_table = mxs_mmc_dt_ids,
840 },
841 };
842
843 module_platform_driver(mxs_mmc_driver);
844
845 MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral");
846 MODULE_AUTHOR("Freescale Semiconductor");
847 MODULE_LICENSE("GPL");
Linus' kernel tree