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[ARM] 4370/3: AT91: Support for Atmel AT91SAM9RL processors.
[linux-2.6.git] / arch / arm / mach-at91 / at91sam9rl_devices.c
blobe775aa65bb63544d2dcf8d17e927901fdafca1da
1 /*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive for
6 * more details.
7 */
8
9 #include <asm/mach/arch.h>
10 #include <asm/mach/map.h>
11
12 #include <linux/platform_device.h>
13 #include <linux/fb.h>
14
15 #include <video/atmel_lcdc.h>
16
17 #include <asm/arch/board.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/at91sam9rl.h>
20 #include <asm/arch/at91sam9rl_matrix.h>
21 #include <asm/arch/at91sam926x_mc.h>
22
23 #include "generic.h"
24
25 #define SZ_512 0x00000200
26 #define SZ_256 0x00000100
27 #define SZ_16 0x00000010
28
29
30 /* --------------------------------------------------------------------
31 * MMC / SD
32 * -------------------------------------------------------------------- */
33
34 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
35 static u64 mmc_dmamask = 0xffffffffUL;
36 static struct at91_mmc_data mmc_data;
37
38 static struct resource mmc_resources[] = {
39 [0] = {
40 .start = AT91SAM9RL_BASE_MCI,
41 .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
42 .flags = IORESOURCE_MEM,
43 },
44 [1] = {
45 .start = AT91SAM9RL_ID_MCI,
46 .end = AT91SAM9RL_ID_MCI,
47 .flags = IORESOURCE_IRQ,
48 },
49 };
50
51 static struct platform_device at91sam9rl_mmc_device = {
52 .name = "at91_mci",
53 .id = -1,
54 .dev = {
55 .dma_mask = &mmc_dmamask,
56 .coherent_dma_mask = 0xffffffff,
57 .platform_data = &mmc_data,
58 },
59 .resource = mmc_resources,
60 .num_resources = ARRAY_SIZE(mmc_resources),
61 };
62
63 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
64 {
65 if (!data)
66 return;
67
68 /* input/irq */
69 if (data->det_pin) {
70 at91_set_gpio_input(data->det_pin, 1);
71 at91_set_deglitch(data->det_pin, 1);
72 }
73 if (data->wp_pin)
74 at91_set_gpio_input(data->wp_pin, 1);
75 if (data->vcc_pin)
76 at91_set_gpio_output(data->vcc_pin, 0);
77
78 /* CLK */
79 at91_set_A_periph(AT91_PIN_PA2, 0);
80
81 /* CMD */
82 at91_set_A_periph(AT91_PIN_PA1, 1);
83
84 /* DAT0, maybe DAT1..DAT3 */
85 at91_set_A_periph(AT91_PIN_PA0, 1);
86 if (data->wire4) {
87 at91_set_A_periph(AT91_PIN_PA3, 1);
88 at91_set_A_periph(AT91_PIN_PA4, 1);
89 at91_set_A_periph(AT91_PIN_PA5, 1);
90 }
91
92 mmc_data = *data;
93 platform_device_register(&at91sam9rl_mmc_device);
94 }
95 #else
96 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
97 #endif
98
99
100 /* --------------------------------------------------------------------
101 * NAND / SmartMedia
102 * -------------------------------------------------------------------- */
103
104 #if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
105 static struct at91_nand_data nand_data;
106
107 #define NAND_BASE AT91_CHIPSELECT_3
108
109 static struct resource nand_resources[] = {
110 {
111 .start = NAND_BASE,
112 .end = NAND_BASE + SZ_256M - 1,
113 .flags = IORESOURCE_MEM,
114 }
115 };
116
117 static struct platform_device at91_nand_device = {
118 .name = "at91_nand",
119 .id = -1,
120 .dev = {
121 .platform_data = &nand_data,
122 },
123 .resource = nand_resources,
124 .num_resources = ARRAY_SIZE(nand_resources),
125 };
126
127 void __init at91_add_device_nand(struct at91_nand_data *data)
128 {
129 unsigned long csa;
130
131 if (!data)
132 return;
133
134 csa = at91_sys_read(AT91_MATRIX_EBICSA);
135 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
136
137 /* set the bus interface characteristics */
138 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
139 | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
140
141 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
142 | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
143
144 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
145
146 at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
147
148 /* enable pin */
149 if (data->enable_pin)
150 at91_set_gpio_output(data->enable_pin, 1);
151
152 /* ready/busy pin */
153 if (data->rdy_pin)
154 at91_set_gpio_input(data->rdy_pin, 1);
155
156 /* card detect pin */
157 if (data->det_pin)
158 at91_set_gpio_input(data->det_pin, 1);
159
160 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
161 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
162
163 nand_data = *data;
164 platform_device_register(&at91_nand_device);
165 }
166
167 #else
168 void __init at91_add_device_nand(struct at91_nand_data *data) {}
169 #endif
170
171
172 /* --------------------------------------------------------------------
173 * TWI (i2c)
174 * -------------------------------------------------------------------- */
175
176 #if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
177
178 static struct resource twi_resources[] = {
179 [0] = {
180 .start = AT91SAM9RL_BASE_TWI0,
181 .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
182 .flags = IORESOURCE_MEM,
183 },
184 [1] = {
185 .start = AT91SAM9RL_ID_TWI0,
186 .end = AT91SAM9RL_ID_TWI0,
187 .flags = IORESOURCE_IRQ,
188 },
189 };
190
191 static struct platform_device at91sam9rl_twi_device = {
192 .name = "at91_i2c",
193 .id = -1,
194 .resource = twi_resources,
195 .num_resources = ARRAY_SIZE(twi_resources),
196 };
197
198 void __init at91_add_device_i2c(void)
199 {
200 /* pins used for TWI interface */
201 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
202 at91_set_multi_drive(AT91_PIN_PA23, 1);
203
204 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
205 at91_set_multi_drive(AT91_PIN_PA24, 1);
206
207 platform_device_register(&at91sam9rl_twi_device);
208 }
209 #else
210 void __init at91_add_device_i2c(void) {}
211 #endif
212
213
214 /* --------------------------------------------------------------------
215 * SPI
216 * -------------------------------------------------------------------- */
217
218 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
219 static u64 spi_dmamask = 0xffffffffUL;
220
221 static struct resource spi_resources[] = {
222 [0] = {
223 .start = AT91SAM9RL_BASE_SPI,
224 .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
225 .flags = IORESOURCE_MEM,
226 },
227 [1] = {
228 .start = AT91SAM9RL_ID_SPI,
229 .end = AT91SAM9RL_ID_SPI,
230 .flags = IORESOURCE_IRQ,
231 },
232 };
233
234 static struct platform_device at91sam9rl_spi_device = {
235 .name = "atmel_spi",
236 .id = 0,
237 .dev = {
238 .dma_mask = &spi_dmamask,
239 .coherent_dma_mask = 0xffffffff,
240 },
241 .resource = spi_resources,
242 .num_resources = ARRAY_SIZE(spi_resources),
243 };
244
245 static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
246
247
248 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
249 {
250 int i;
251 unsigned long cs_pin;
252
253 at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */
254 at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */
255 at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */
256
257 /* Enable SPI chip-selects */
258 for (i = 0; i < nr_devices; i++) {
259 if (devices[i].controller_data)
260 cs_pin = (unsigned long) devices[i].controller_data;
261 else
262 cs_pin = spi_standard_cs[devices[i].chip_select];
263
264 /* enable chip-select pin */
265 at91_set_gpio_output(cs_pin, 1);
266
267 /* pass chip-select pin to driver */
268 devices[i].controller_data = (void *) cs_pin;
269 }
270
271 spi_register_board_info(devices, nr_devices);
272 platform_device_register(&at91sam9rl_spi_device);
273 }
274 #else
275 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
276 #endif
277
278
279 /* --------------------------------------------------------------------
280 * LCD Controller
281 * -------------------------------------------------------------------- */
282
283 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
284 static u64 lcdc_dmamask = 0xffffffffUL;
285 static struct atmel_lcdfb_info lcdc_data;
286
287 static struct resource lcdc_resources[] = {
288 [0] = {
289 .start = AT91SAM9RL_LCDC_BASE,
290 .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
291 .flags = IORESOURCE_MEM,
292 },
293 [1] = {
294 .start = AT91SAM9RL_ID_LCDC,
295 .end = AT91SAM9RL_ID_LCDC,
296 .flags = IORESOURCE_IRQ,
297 },
298 #if defined(CONFIG_FB_INTSRAM)
299 [2] = {
300 .start = AT91SAM9RL_SRAM_BASE,
301 .end = AT91SAM9RL_SRAM_BASE + AT91SAM9RL_SRAM_SIZE - 1,
302 .flags = IORESOURCE_MEM,
303 },
304 #endif
305 };
306
307 static struct platform_device at91_lcdc_device = {
308 .name = "atmel_lcdfb",
309 .id = 0,
310 .dev = {
311 .dma_mask = &lcdc_dmamask,
312 .coherent_dma_mask = 0xffffffff,
313 .platform_data = &lcdc_data,
314 },
315 .resource = lcdc_resources,
316 .num_resources = ARRAY_SIZE(lcdc_resources),
317 };
318
319 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
320 {
321 if (!data) {
322 return;
323 }
324
325 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
326 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
327 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
328 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
329 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
330 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
331 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
332 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
333 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
334 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
335 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
336 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
337 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
338 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
339 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
340 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
341 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
342 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
343 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
344 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
345 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
346
347 lcdc_data = *data;
348 platform_device_register(&at91_lcdc_device);
349 }
350 #else
351 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
352 #endif
353
354
355 /* --------------------------------------------------------------------
356 * LEDs
357 * -------------------------------------------------------------------- */
358
359 #if defined(CONFIG_LEDS)
360 u8 at91_leds_cpu;
361 u8 at91_leds_timer;
362
363 void __init at91_init_leds(u8 cpu_led, u8 timer_led)
364 {
365 /* Enable GPIO to access the LEDs */
366 at91_set_gpio_output(cpu_led, 1);
367 at91_set_gpio_output(timer_led, 1);
368
369 at91_leds_cpu = cpu_led;
370 at91_leds_timer = timer_led;
371 }
372 #else
373 void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
374 #endif
375
376
377 /* --------------------------------------------------------------------
378 * UART
379 * -------------------------------------------------------------------- */
380
381 #if defined(CONFIG_SERIAL_ATMEL)
382 static struct resource dbgu_resources[] = {
383 [0] = {
384 .start = AT91_VA_BASE_SYS + AT91_DBGU,
385 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
386 .flags = IORESOURCE_MEM,
387 },
388 [1] = {
389 .start = AT91_ID_SYS,
390 .end = AT91_ID_SYS,
391 .flags = IORESOURCE_IRQ,
392 },
393 };
394
395 static struct atmel_uart_data dbgu_data = {
396 .use_dma_tx = 0,
397 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
398 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
399 };
400
401 static struct platform_device at91sam9rl_dbgu_device = {
402 .name = "atmel_usart",
403 .id = 0,
404 .dev = {
405 .platform_data = &dbgu_data,
406 .coherent_dma_mask = 0xffffffff,
407 },
408 .resource = dbgu_resources,
409 .num_resources = ARRAY_SIZE(dbgu_resources),
410 };
411
412 static inline void configure_dbgu_pins(void)
413 {
414 at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
415 at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
416 }
417
418 static struct resource uart0_resources[] = {
419 [0] = {
420 .start = AT91SAM9RL_BASE_US0,
421 .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
422 .flags = IORESOURCE_MEM,
423 },
424 [1] = {
425 .start = AT91SAM9RL_ID_US0,
426 .end = AT91SAM9RL_ID_US0,
427 .flags = IORESOURCE_IRQ,
428 },
429 };
430
431 static struct atmel_uart_data uart0_data = {
432 .use_dma_tx = 1,
433 .use_dma_rx = 1,
434 };
435
436 static struct platform_device at91sam9rl_uart0_device = {
437 .name = "atmel_usart",
438 .id = 1,
439 .dev = {
440 .platform_data = &uart0_data,
441 .coherent_dma_mask = 0xffffffff,
442 },
443 .resource = uart0_resources,
444 .num_resources = ARRAY_SIZE(uart0_resources),
445 };
446
447 static inline void configure_usart0_pins(void)
448 {
449 at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
450 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
451 at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */
452 at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */
453 }
454
455 static struct resource uart1_resources[] = {
456 [0] = {
457 .start = AT91SAM9RL_BASE_US1,
458 .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
459 .flags = IORESOURCE_MEM,
460 },
461 [1] = {
462 .start = AT91SAM9RL_ID_US1,
463 .end = AT91SAM9RL_ID_US1,
464 .flags = IORESOURCE_IRQ,
465 },
466 };
467
468 static struct atmel_uart_data uart1_data = {
469 .use_dma_tx = 1,
470 .use_dma_rx = 1,
471 };
472
473 static struct platform_device at91sam9rl_uart1_device = {
474 .name = "atmel_usart",
475 .id = 2,
476 .dev = {
477 .platform_data = &uart1_data,
478 .coherent_dma_mask = 0xffffffff,
479 },
480 .resource = uart1_resources,
481 .num_resources = ARRAY_SIZE(uart1_resources),
482 };
483
484 static inline void configure_usart1_pins(void)
485 {
486 at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
487 at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
488 }
489
490 static struct resource uart2_resources[] = {
491 [0] = {
492 .start = AT91SAM9RL_BASE_US2,
493 .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
494 .flags = IORESOURCE_MEM,
495 },
496 [1] = {
497 .start = AT91SAM9RL_ID_US2,
498 .end = AT91SAM9RL_ID_US2,
499 .flags = IORESOURCE_IRQ,
500 },
501 };
502
503 static struct atmel_uart_data uart2_data = {
504 .use_dma_tx = 1,
505 .use_dma_rx = 1,
506 };
507
508 static struct platform_device at91sam9rl_uart2_device = {
509 .name = "atmel_usart",
510 .id = 3,
511 .dev = {
512 .platform_data = &uart2_data,
513 .coherent_dma_mask = 0xffffffff,
514 },
515 .resource = uart2_resources,
516 .num_resources = ARRAY_SIZE(uart2_resources),
517 };
518
519 static inline void configure_usart2_pins(void)
520 {
521 at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
522 at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
523 }
524
525 static struct resource uart3_resources[] = {
526 [0] = {
527 .start = AT91SAM9RL_BASE_US3,
528 .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
529 .flags = IORESOURCE_MEM,
530 },
531 [1] = {
532 .start = AT91SAM9RL_ID_US3,
533 .end = AT91SAM9RL_ID_US3,
534 .flags = IORESOURCE_IRQ,
535 },
536 };
537
538 static struct atmel_uart_data uart3_data = {
539 .use_dma_tx = 1,
540 .use_dma_rx = 1,
541 };
542
543 static struct platform_device at91sam9rl_uart3_device = {
544 .name = "atmel_usart",
545 .id = 4,
546 .dev = {
547 .platform_data = &uart3_data,
548 .coherent_dma_mask = 0xffffffff,
549 },
550 .resource = uart3_resources,
551 .num_resources = ARRAY_SIZE(uart3_resources),
552 };
553
554 static inline void configure_usart3_pins(void)
555 {
556 at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */
557 at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */
558 }
559
560 struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
561 struct platform_device *atmel_default_console_device; /* the serial console device */
562
563 void __init at91_init_serial(struct at91_uart_config *config)
564 {
565 int i;
566
567 /* Fill in list of supported UARTs */
568 for (i = 0; i < config->nr_tty; i++) {
569 switch (config->tty_map[i]) {
570 case 0:
571 configure_usart0_pins();
572 at91_uarts[i] = &at91sam9rl_uart0_device;
573 at91_clock_associate("usart0_clk", &at91sam9rl_uart0_device.dev, "usart");
574 break;
575 case 1:
576 configure_usart1_pins();
577 at91_uarts[i] = &at91sam9rl_uart1_device;
578 at91_clock_associate("usart1_clk", &at91sam9rl_uart1_device.dev, "usart");
579 break;
580 case 2:
581 configure_usart2_pins();
582 at91_uarts[i] = &at91sam9rl_uart2_device;
583 at91_clock_associate("usart2_clk", &at91sam9rl_uart2_device.dev, "usart");
584 break;
585 case 3:
586 configure_usart3_pins();
587 at91_uarts[i] = &at91sam9rl_uart3_device;
588 at91_clock_associate("usart3_clk", &at91sam9rl_uart3_device.dev, "usart");
589 break;
590 case 4:
591 configure_dbgu_pins();
592 at91_uarts[i] = &at91sam9rl_dbgu_device;
593 at91_clock_associate("mck", &at91sam9rl_dbgu_device.dev, "usart");
594 break;
595 default:
596 continue;
597 }
598 at91_uarts[i]->id = i; /* update ID number to mapped ID */
599 }
600
601 /* Set serial console device */
602 if (config->console_tty < ATMEL_MAX_UART)
603 atmel_default_console_device = at91_uarts[config->console_tty];
604 if (!atmel_default_console_device)
605 printk(KERN_INFO "AT91: No default serial console defined.\n");
606 }
607
608 void __init at91_add_device_serial(void)
609 {
610 int i;
611
612 for (i = 0; i < ATMEL_MAX_UART; i++) {
613 if (at91_uarts[i])
614 platform_device_register(at91_uarts[i]);
615 }
616 }
617 #else
618 void __init at91_init_serial(struct at91_uart_config *config) {}
619 void __init at91_add_device_serial(void) {}
620 #endif
621
622
623 /* -------------------------------------------------------------------- */
624
625 /*
626 * These devices are always present and don't need any board-specific
627 * setup.
628 */
629 static int __init at91_add_standard_devices(void)
630 {
631 return 0;
632 }
633
634 arch_initcall(at91_add_standard_devices);
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