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spi: davinci: let DMA operation be specified on per-device basis
[linux-2.6.git] / arch / arm / mach-davinci / da850.c
blob63916b90276042f01750bf5a41f79d7b64c2fd3a
1 /*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14 #include <linux/init.h>
15 #include <linux/clk.h>
16 #include <linux/platform_device.h>
17 #include <linux/cpufreq.h>
18 #include <linux/regulator/consumer.h>
19
20 #include <asm/mach/map.h>
21
22 #include <mach/psc.h>
23 #include <mach/irqs.h>
24 #include <mach/cputype.h>
25 #include <mach/common.h>
26 #include <mach/time.h>
27 #include <mach/da8xx.h>
28 #include <mach/cpufreq.h>
29 #include <mach/pm.h>
30 #include <mach/gpio.h>
31
32 #include "clock.h"
33 #include "mux.h"
34
35 /* SoC specific clock flags */
36 #define DA850_CLK_ASYNC3 BIT(16)
37
38 #define DA850_PLL1_BASE 0x01e1a000
39 #define DA850_TIMER64P2_BASE 0x01f0c000
40 #define DA850_TIMER64P3_BASE 0x01f0d000
41
42 #define DA850_REF_FREQ 24000000
43
44 #define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
45 #define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
46 #define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
47
48 static int da850_set_armrate(struct clk *clk, unsigned long rate);
49 static int da850_round_armrate(struct clk *clk, unsigned long rate);
50 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
51
52 static struct pll_data pll0_data = {
53 .num = 1,
54 .phys_base = DA8XX_PLL0_BASE,
55 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
56 };
57
58 static struct clk ref_clk = {
59 .name = "ref_clk",
60 .rate = DA850_REF_FREQ,
61 };
62
63 static struct clk pll0_clk = {
64 .name = "pll0",
65 .parent = &ref_clk,
66 .pll_data = &pll0_data,
67 .flags = CLK_PLL,
68 .set_rate = da850_set_pll0rate,
69 };
70
71 static struct clk pll0_aux_clk = {
72 .name = "pll0_aux_clk",
73 .parent = &pll0_clk,
74 .flags = CLK_PLL | PRE_PLL,
75 };
76
77 static struct clk pll0_sysclk2 = {
78 .name = "pll0_sysclk2",
79 .parent = &pll0_clk,
80 .flags = CLK_PLL,
81 .div_reg = PLLDIV2,
82 };
83
84 static struct clk pll0_sysclk3 = {
85 .name = "pll0_sysclk3",
86 .parent = &pll0_clk,
87 .flags = CLK_PLL,
88 .div_reg = PLLDIV3,
89 .set_rate = davinci_set_sysclk_rate,
90 .maxrate = 100000000,
91 };
92
93 static struct clk pll0_sysclk4 = {
94 .name = "pll0_sysclk4",
95 .parent = &pll0_clk,
96 .flags = CLK_PLL,
97 .div_reg = PLLDIV4,
98 };
99
100 static struct clk pll0_sysclk5 = {
101 .name = "pll0_sysclk5",
102 .parent = &pll0_clk,
103 .flags = CLK_PLL,
104 .div_reg = PLLDIV5,
105 };
106
107 static struct clk pll0_sysclk6 = {
108 .name = "pll0_sysclk6",
109 .parent = &pll0_clk,
110 .flags = CLK_PLL,
111 .div_reg = PLLDIV6,
112 };
113
114 static struct clk pll0_sysclk7 = {
115 .name = "pll0_sysclk7",
116 .parent = &pll0_clk,
117 .flags = CLK_PLL,
118 .div_reg = PLLDIV7,
119 };
120
121 static struct pll_data pll1_data = {
122 .num = 2,
123 .phys_base = DA850_PLL1_BASE,
124 .flags = PLL_HAS_POSTDIV,
125 };
126
127 static struct clk pll1_clk = {
128 .name = "pll1",
129 .parent = &ref_clk,
130 .pll_data = &pll1_data,
131 .flags = CLK_PLL,
132 };
133
134 static struct clk pll1_aux_clk = {
135 .name = "pll1_aux_clk",
136 .parent = &pll1_clk,
137 .flags = CLK_PLL | PRE_PLL,
138 };
139
140 static struct clk pll1_sysclk2 = {
141 .name = "pll1_sysclk2",
142 .parent = &pll1_clk,
143 .flags = CLK_PLL,
144 .div_reg = PLLDIV2,
145 };
146
147 static struct clk pll1_sysclk3 = {
148 .name = "pll1_sysclk3",
149 .parent = &pll1_clk,
150 .flags = CLK_PLL,
151 .div_reg = PLLDIV3,
152 };
153
154 static struct clk pll1_sysclk4 = {
155 .name = "pll1_sysclk4",
156 .parent = &pll1_clk,
157 .flags = CLK_PLL,
158 .div_reg = PLLDIV4,
159 };
160
161 static struct clk pll1_sysclk5 = {
162 .name = "pll1_sysclk5",
163 .parent = &pll1_clk,
164 .flags = CLK_PLL,
165 .div_reg = PLLDIV5,
166 };
167
168 static struct clk pll1_sysclk6 = {
169 .name = "pll0_sysclk6",
170 .parent = &pll0_clk,
171 .flags = CLK_PLL,
172 .div_reg = PLLDIV6,
173 };
174
175 static struct clk pll1_sysclk7 = {
176 .name = "pll1_sysclk7",
177 .parent = &pll1_clk,
178 .flags = CLK_PLL,
179 .div_reg = PLLDIV7,
180 };
181
182 static struct clk i2c0_clk = {
183 .name = "i2c0",
184 .parent = &pll0_aux_clk,
185 };
186
187 static struct clk timerp64_0_clk = {
188 .name = "timer0",
189 .parent = &pll0_aux_clk,
190 };
191
192 static struct clk timerp64_1_clk = {
193 .name = "timer1",
194 .parent = &pll0_aux_clk,
195 };
196
197 static struct clk arm_rom_clk = {
198 .name = "arm_rom",
199 .parent = &pll0_sysclk2,
200 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
201 .flags = ALWAYS_ENABLED,
202 };
203
204 static struct clk tpcc0_clk = {
205 .name = "tpcc0",
206 .parent = &pll0_sysclk2,
207 .lpsc = DA8XX_LPSC0_TPCC,
208 .flags = ALWAYS_ENABLED | CLK_PSC,
209 };
210
211 static struct clk tptc0_clk = {
212 .name = "tptc0",
213 .parent = &pll0_sysclk2,
214 .lpsc = DA8XX_LPSC0_TPTC0,
215 .flags = ALWAYS_ENABLED,
216 };
217
218 static struct clk tptc1_clk = {
219 .name = "tptc1",
220 .parent = &pll0_sysclk2,
221 .lpsc = DA8XX_LPSC0_TPTC1,
222 .flags = ALWAYS_ENABLED,
223 };
224
225 static struct clk tpcc1_clk = {
226 .name = "tpcc1",
227 .parent = &pll0_sysclk2,
228 .lpsc = DA850_LPSC1_TPCC1,
229 .gpsc = 1,
230 .flags = CLK_PSC | ALWAYS_ENABLED,
231 };
232
233 static struct clk tptc2_clk = {
234 .name = "tptc2",
235 .parent = &pll0_sysclk2,
236 .lpsc = DA850_LPSC1_TPTC2,
237 .gpsc = 1,
238 .flags = ALWAYS_ENABLED,
239 };
240
241 static struct clk uart0_clk = {
242 .name = "uart0",
243 .parent = &pll0_sysclk2,
244 .lpsc = DA8XX_LPSC0_UART0,
245 };
246
247 static struct clk uart1_clk = {
248 .name = "uart1",
249 .parent = &pll0_sysclk2,
250 .lpsc = DA8XX_LPSC1_UART1,
251 .gpsc = 1,
252 .flags = DA850_CLK_ASYNC3,
253 };
254
255 static struct clk uart2_clk = {
256 .name = "uart2",
257 .parent = &pll0_sysclk2,
258 .lpsc = DA8XX_LPSC1_UART2,
259 .gpsc = 1,
260 .flags = DA850_CLK_ASYNC3,
261 };
262
263 static struct clk aintc_clk = {
264 .name = "aintc",
265 .parent = &pll0_sysclk4,
266 .lpsc = DA8XX_LPSC0_AINTC,
267 .flags = ALWAYS_ENABLED,
268 };
269
270 static struct clk gpio_clk = {
271 .name = "gpio",
272 .parent = &pll0_sysclk4,
273 .lpsc = DA8XX_LPSC1_GPIO,
274 .gpsc = 1,
275 };
276
277 static struct clk i2c1_clk = {
278 .name = "i2c1",
279 .parent = &pll0_sysclk4,
280 .lpsc = DA8XX_LPSC1_I2C,
281 .gpsc = 1,
282 };
283
284 static struct clk emif3_clk = {
285 .name = "emif3",
286 .parent = &pll0_sysclk5,
287 .lpsc = DA8XX_LPSC1_EMIF3C,
288 .gpsc = 1,
289 .flags = ALWAYS_ENABLED,
290 };
291
292 static struct clk arm_clk = {
293 .name = "arm",
294 .parent = &pll0_sysclk6,
295 .lpsc = DA8XX_LPSC0_ARM,
296 .flags = ALWAYS_ENABLED,
297 .set_rate = da850_set_armrate,
298 .round_rate = da850_round_armrate,
299 };
300
301 static struct clk rmii_clk = {
302 .name = "rmii",
303 .parent = &pll0_sysclk7,
304 };
305
306 static struct clk emac_clk = {
307 .name = "emac",
308 .parent = &pll0_sysclk4,
309 .lpsc = DA8XX_LPSC1_CPGMAC,
310 .gpsc = 1,
311 };
312
313 static struct clk mcasp_clk = {
314 .name = "mcasp",
315 .parent = &pll0_sysclk2,
316 .lpsc = DA8XX_LPSC1_McASP0,
317 .gpsc = 1,
318 .flags = DA850_CLK_ASYNC3,
319 };
320
321 static struct clk lcdc_clk = {
322 .name = "lcdc",
323 .parent = &pll0_sysclk2,
324 .lpsc = DA8XX_LPSC1_LCDC,
325 .gpsc = 1,
326 };
327
328 static struct clk mmcsd0_clk = {
329 .name = "mmcsd0",
330 .parent = &pll0_sysclk2,
331 .lpsc = DA8XX_LPSC0_MMC_SD,
332 };
333
334 static struct clk mmcsd1_clk = {
335 .name = "mmcsd1",
336 .parent = &pll0_sysclk2,
337 .lpsc = DA850_LPSC1_MMC_SD1,
338 .gpsc = 1,
339 };
340
341 static struct clk aemif_clk = {
342 .name = "aemif",
343 .parent = &pll0_sysclk3,
344 .lpsc = DA8XX_LPSC0_EMIF25,
345 .flags = ALWAYS_ENABLED,
346 };
347
348 static struct clk_lookup da850_clks[] = {
349 CLK(NULL, "ref", &ref_clk),
350 CLK(NULL, "pll0", &pll0_clk),
351 CLK(NULL, "pll0_aux", &pll0_aux_clk),
352 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
353 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
354 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
355 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
356 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
357 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
358 CLK(NULL, "pll1", &pll1_clk),
359 CLK(NULL, "pll1_aux", &pll1_aux_clk),
360 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
361 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
362 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
363 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
364 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
365 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
366 CLK("i2c_davinci.1", NULL, &i2c0_clk),
367 CLK(NULL, "timer0", &timerp64_0_clk),
368 CLK("watchdog", NULL, &timerp64_1_clk),
369 CLK(NULL, "arm_rom", &arm_rom_clk),
370 CLK(NULL, "tpcc0", &tpcc0_clk),
371 CLK(NULL, "tptc0", &tptc0_clk),
372 CLK(NULL, "tptc1", &tptc1_clk),
373 CLK(NULL, "tpcc1", &tpcc1_clk),
374 CLK(NULL, "tptc2", &tptc2_clk),
375 CLK(NULL, "uart0", &uart0_clk),
376 CLK(NULL, "uart1", &uart1_clk),
377 CLK(NULL, "uart2", &uart2_clk),
378 CLK(NULL, "aintc", &aintc_clk),
379 CLK(NULL, "gpio", &gpio_clk),
380 CLK("i2c_davinci.2", NULL, &i2c1_clk),
381 CLK(NULL, "emif3", &emif3_clk),
382 CLK(NULL, "arm", &arm_clk),
383 CLK(NULL, "rmii", &rmii_clk),
384 CLK("davinci_emac.1", NULL, &emac_clk),
385 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
386 CLK("da8xx_lcdc.0", NULL, &lcdc_clk),
387 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
388 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
389 CLK(NULL, "aemif", &aemif_clk),
390 CLK(NULL, NULL, NULL),
391 };
392
393 /*
394 * Device specific mux setup
395 *
396 * soc description mux mode mode mux dbg
397 * reg offset mask mode
398 */
399 static const struct mux_config da850_pins[] = {
400 #ifdef CONFIG_DAVINCI_MUX
401 /* UART0 function */
402 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
403 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
404 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
405 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
406 /* UART1 function */
407 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
408 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
409 /* UART2 function */
410 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
411 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
412 /* I2C1 function */
413 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
414 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
415 /* I2C0 function */
416 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
417 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
418 /* EMAC function */
419 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
420 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
421 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
422 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
423 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
424 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
425 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
426 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
427 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
428 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
429 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
430 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
431 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
432 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
433 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
434 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
435 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
436 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
437 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
438 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
439 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
440 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
441 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
442 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
443 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
444 /* McASP function */
445 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
446 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
447 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
448 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
449 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
450 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
451 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
452 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
453 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
454 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
455 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
456 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
457 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
458 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
459 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
460 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
461 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
462 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
463 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
464 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
465 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
466 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
467 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
468 /* LCD function */
469 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
470 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
471 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
472 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
473 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
474 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
475 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
476 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
477 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
478 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
479 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
480 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
481 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
482 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
483 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
484 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
485 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
486 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
487 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
488 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
489 /* MMC/SD0 function */
490 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
491 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
492 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
493 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
494 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
495 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
496 /* EMIF2.5/EMIFA function */
497 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
498 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
499 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
500 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
501 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
502 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
503 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
504 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
505 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
506 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
507 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
508 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
509 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
510 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
511 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
512 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
513 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
514 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
515 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
516 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
517 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
518 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
519 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
520 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
521 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
522 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
523 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
524 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
525 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
526 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
527 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
528 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
529 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
530 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
531 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
532 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
533 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
534 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
535 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
536 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
537 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
538 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
539 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
540 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
541 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
542 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
543 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
544 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
545 /* GPIO function */
546 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
547 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
548 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
549 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
550 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
551 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
552 #endif
553 };
554
555 const short da850_uart0_pins[] __initdata = {
556 DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
557 -1
558 };
559
560 const short da850_uart1_pins[] __initdata = {
561 DA850_UART1_RXD, DA850_UART1_TXD,
562 -1
563 };
564
565 const short da850_uart2_pins[] __initdata = {
566 DA850_UART2_RXD, DA850_UART2_TXD,
567 -1
568 };
569
570 const short da850_i2c0_pins[] __initdata = {
571 DA850_I2C0_SDA, DA850_I2C0_SCL,
572 -1
573 };
574
575 const short da850_i2c1_pins[] __initdata = {
576 DA850_I2C1_SCL, DA850_I2C1_SDA,
577 -1
578 };
579
580 const short da850_cpgmac_pins[] __initdata = {
581 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
582 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
583 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
584 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
585 DA850_MDIO_D, DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
586 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, DA850_RMII_RXER,
587 DA850_RMII_MHZ_50_CLK,
588 -1
589 };
590
591 const short da850_mcasp_pins[] __initdata = {
592 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
593 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
594 DA850_AXR_11, DA850_AXR_12,
595 -1
596 };
597
598 const short da850_lcdcntl_pins[] __initdata = {
599 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
600 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
601 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
602 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
603 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
604 -1
605 };
606
607 const short da850_mmcsd0_pins[] __initdata = {
608 DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
609 DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
610 DA850_GPIO4_0, DA850_GPIO4_1,
611 -1
612 };
613
614 const short da850_emif25_pins[] __initdata = {
615 DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
616 DA850_NEMA_CS_3, DA850_NEMA_CS_4, DA850_NEMA_WE, DA850_NEMA_OE,
617 DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3,
618 DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7,
619 DA850_EMA_D_8, DA850_EMA_D_9, DA850_EMA_D_10, DA850_EMA_D_11,
620 DA850_EMA_D_12, DA850_EMA_D_13, DA850_EMA_D_14, DA850_EMA_D_15,
621 DA850_EMA_A_0, DA850_EMA_A_1, DA850_EMA_A_2, DA850_EMA_A_3,
622 DA850_EMA_A_4, DA850_EMA_A_5, DA850_EMA_A_6, DA850_EMA_A_7,
623 DA850_EMA_A_8, DA850_EMA_A_9, DA850_EMA_A_10, DA850_EMA_A_11,
624 DA850_EMA_A_12, DA850_EMA_A_13, DA850_EMA_A_14, DA850_EMA_A_15,
625 DA850_EMA_A_16, DA850_EMA_A_17, DA850_EMA_A_18, DA850_EMA_A_19,
626 DA850_EMA_A_20, DA850_EMA_A_21, DA850_EMA_A_22, DA850_EMA_A_23,
627 -1
628 };
629
630 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
631 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
632 [IRQ_DA8XX_COMMTX] = 7,
633 [IRQ_DA8XX_COMMRX] = 7,
634 [IRQ_DA8XX_NINT] = 7,
635 [IRQ_DA8XX_EVTOUT0] = 7,
636 [IRQ_DA8XX_EVTOUT1] = 7,
637 [IRQ_DA8XX_EVTOUT2] = 7,
638 [IRQ_DA8XX_EVTOUT3] = 7,
639 [IRQ_DA8XX_EVTOUT4] = 7,
640 [IRQ_DA8XX_EVTOUT5] = 7,
641 [IRQ_DA8XX_EVTOUT6] = 7,
642 [IRQ_DA8XX_EVTOUT7] = 7,
643 [IRQ_DA8XX_CCINT0] = 7,
644 [IRQ_DA8XX_CCERRINT] = 7,
645 [IRQ_DA8XX_TCERRINT0] = 7,
646 [IRQ_DA8XX_AEMIFINT] = 7,
647 [IRQ_DA8XX_I2CINT0] = 7,
648 [IRQ_DA8XX_MMCSDINT0] = 7,
649 [IRQ_DA8XX_MMCSDINT1] = 7,
650 [IRQ_DA8XX_ALLINT0] = 7,
651 [IRQ_DA8XX_RTC] = 7,
652 [IRQ_DA8XX_SPINT0] = 7,
653 [IRQ_DA8XX_TINT12_0] = 7,
654 [IRQ_DA8XX_TINT34_0] = 7,
655 [IRQ_DA8XX_TINT12_1] = 7,
656 [IRQ_DA8XX_TINT34_1] = 7,
657 [IRQ_DA8XX_UARTINT0] = 7,
658 [IRQ_DA8XX_KEYMGRINT] = 7,
659 [IRQ_DA850_MPUADDRERR0] = 7,
660 [IRQ_DA8XX_CHIPINT0] = 7,
661 [IRQ_DA8XX_CHIPINT1] = 7,
662 [IRQ_DA8XX_CHIPINT2] = 7,
663 [IRQ_DA8XX_CHIPINT3] = 7,
664 [IRQ_DA8XX_TCERRINT1] = 7,
665 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
666 [IRQ_DA8XX_C0_RX_PULSE] = 7,
667 [IRQ_DA8XX_C0_TX_PULSE] = 7,
668 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
669 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
670 [IRQ_DA8XX_C1_RX_PULSE] = 7,
671 [IRQ_DA8XX_C1_TX_PULSE] = 7,
672 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
673 [IRQ_DA8XX_MEMERR] = 7,
674 [IRQ_DA8XX_GPIO0] = 7,
675 [IRQ_DA8XX_GPIO1] = 7,
676 [IRQ_DA8XX_GPIO2] = 7,
677 [IRQ_DA8XX_GPIO3] = 7,
678 [IRQ_DA8XX_GPIO4] = 7,
679 [IRQ_DA8XX_GPIO5] = 7,
680 [IRQ_DA8XX_GPIO6] = 7,
681 [IRQ_DA8XX_GPIO7] = 7,
682 [IRQ_DA8XX_GPIO8] = 7,
683 [IRQ_DA8XX_I2CINT1] = 7,
684 [IRQ_DA8XX_LCDINT] = 7,
685 [IRQ_DA8XX_UARTINT1] = 7,
686 [IRQ_DA8XX_MCASPINT] = 7,
687 [IRQ_DA8XX_ALLINT1] = 7,
688 [IRQ_DA8XX_SPINT1] = 7,
689 [IRQ_DA8XX_UHPI_INT1] = 7,
690 [IRQ_DA8XX_USB_INT] = 7,
691 [IRQ_DA8XX_IRQN] = 7,
692 [IRQ_DA8XX_RWAKEUP] = 7,
693 [IRQ_DA8XX_UARTINT2] = 7,
694 [IRQ_DA8XX_DFTSSINT] = 7,
695 [IRQ_DA8XX_EHRPWM0] = 7,
696 [IRQ_DA8XX_EHRPWM0TZ] = 7,
697 [IRQ_DA8XX_EHRPWM1] = 7,
698 [IRQ_DA8XX_EHRPWM1TZ] = 7,
699 [IRQ_DA850_SATAINT] = 7,
700 [IRQ_DA850_TINTALL_2] = 7,
701 [IRQ_DA8XX_ECAP0] = 7,
702 [IRQ_DA8XX_ECAP1] = 7,
703 [IRQ_DA8XX_ECAP2] = 7,
704 [IRQ_DA850_MMCSDINT0_1] = 7,
705 [IRQ_DA850_MMCSDINT1_1] = 7,
706 [IRQ_DA850_T12CMPINT0_2] = 7,
707 [IRQ_DA850_T12CMPINT1_2] = 7,
708 [IRQ_DA850_T12CMPINT2_2] = 7,
709 [IRQ_DA850_T12CMPINT3_2] = 7,
710 [IRQ_DA850_T12CMPINT4_2] = 7,
711 [IRQ_DA850_T12CMPINT5_2] = 7,
712 [IRQ_DA850_T12CMPINT6_2] = 7,
713 [IRQ_DA850_T12CMPINT7_2] = 7,
714 [IRQ_DA850_T12CMPINT0_3] = 7,
715 [IRQ_DA850_T12CMPINT1_3] = 7,
716 [IRQ_DA850_T12CMPINT2_3] = 7,
717 [IRQ_DA850_T12CMPINT3_3] = 7,
718 [IRQ_DA850_T12CMPINT4_3] = 7,
719 [IRQ_DA850_T12CMPINT5_3] = 7,
720 [IRQ_DA850_T12CMPINT6_3] = 7,
721 [IRQ_DA850_T12CMPINT7_3] = 7,
722 [IRQ_DA850_RPIINT] = 7,
723 [IRQ_DA850_VPIFINT] = 7,
724 [IRQ_DA850_CCINT1] = 7,
725 [IRQ_DA850_CCERRINT1] = 7,
726 [IRQ_DA850_TCERRINT2] = 7,
727 [IRQ_DA850_TINTALL_3] = 7,
728 [IRQ_DA850_MCBSP0RINT] = 7,
729 [IRQ_DA850_MCBSP0XINT] = 7,
730 [IRQ_DA850_MCBSP1RINT] = 7,
731 [IRQ_DA850_MCBSP1XINT] = 7,
732 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
733 };
734
735 static struct map_desc da850_io_desc[] = {
736 {
737 .virtual = IO_VIRT,
738 .pfn = __phys_to_pfn(IO_PHYS),
739 .length = IO_SIZE,
740 .type = MT_DEVICE
741 },
742 {
743 .virtual = DA8XX_CP_INTC_VIRT,
744 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
745 .length = DA8XX_CP_INTC_SIZE,
746 .type = MT_DEVICE
747 },
748 {
749 .virtual = SRAM_VIRT,
750 .pfn = __phys_to_pfn(DA8XX_ARM_RAM_BASE),
751 .length = SZ_8K,
752 .type = MT_DEVICE
753 },
754 };
755
756 static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
757
758 /* Contents of JTAG ID register used to identify exact cpu type */
759 static struct davinci_id da850_ids[] = {
760 {
761 .variant = 0x0,
762 .part_no = 0xb7d1,
763 .manufacturer = 0x017, /* 0x02f >> 1 */
764 .cpu_id = DAVINCI_CPU_ID_DA850,
765 .name = "da850/omap-l138",
766 },
767 };
768
769 static struct davinci_timer_instance da850_timer_instance[4] = {
770 {
771 .base = DA8XX_TIMER64P0_BASE,
772 .bottom_irq = IRQ_DA8XX_TINT12_0,
773 .top_irq = IRQ_DA8XX_TINT34_0,
774 },
775 {
776 .base = DA8XX_TIMER64P1_BASE,
777 .bottom_irq = IRQ_DA8XX_TINT12_1,
778 .top_irq = IRQ_DA8XX_TINT34_1,
779 },
780 {
781 .base = DA850_TIMER64P2_BASE,
782 .bottom_irq = IRQ_DA850_TINT12_2,
783 .top_irq = IRQ_DA850_TINT34_2,
784 },
785 {
786 .base = DA850_TIMER64P3_BASE,
787 .bottom_irq = IRQ_DA850_TINT12_3,
788 .top_irq = IRQ_DA850_TINT34_3,
789 },
790 };
791
792 /*
793 * T0_BOT: Timer 0, bottom : Used for clock_event
794 * T0_TOP: Timer 0, top : Used for clocksource
795 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
796 */
797 static struct davinci_timer_info da850_timer_info = {
798 .timers = da850_timer_instance,
799 .clockevent_id = T0_BOT,
800 .clocksource_id = T0_TOP,
801 };
802
803 static void da850_set_async3_src(int pllnum)
804 {
805 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
806 struct clk_lookup *c;
807 unsigned int v;
808 int ret;
809
810 for (c = da850_clks; c->clk; c++) {
811 clk = c->clk;
812 if (clk->flags & DA850_CLK_ASYNC3) {
813 ret = clk_set_parent(clk, newparent);
814 WARN(ret, "DA850: unable to re-parent clock %s",
815 clk->name);
816 }
817 }
818
819 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
820 if (pllnum)
821 v |= CFGCHIP3_ASYNC3_CLKSRC;
822 else
823 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
824 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
825 }
826
827 #ifdef CONFIG_CPU_FREQ
828 /*
829 * Notes:
830 * According to the TRM, minimum PLLM results in maximum power savings.
831 * The OPP definitions below should keep the PLLM as low as possible.
832 *
833 * The output of the PLLM must be between 400 to 600 MHz.
834 * This rules out prediv of anything but divide-by-one for 24Mhz OSC input.
835 */
836 struct da850_opp {
837 unsigned int freq; /* in KHz */
838 unsigned int prediv;
839 unsigned int mult;
840 unsigned int postdiv;
841 unsigned int cvdd_min; /* in uV */
842 unsigned int cvdd_max; /* in uV */
843 };
844
845 static const struct da850_opp da850_opp_300 = {
846 .freq = 300000,
847 .prediv = 1,
848 .mult = 25,
849 .postdiv = 2,
850 .cvdd_min = 1200000,
851 .cvdd_max = 1320000,
852 };
853
854 static const struct da850_opp da850_opp_200 = {
855 .freq = 200000,
856 .prediv = 1,
857 .mult = 25,
858 .postdiv = 3,
859 .cvdd_min = 1100000,
860 .cvdd_max = 1160000,
861 };
862
863 static const struct da850_opp da850_opp_96 = {
864 .freq = 96000,
865 .prediv = 1,
866 .mult = 20,
867 .postdiv = 5,
868 .cvdd_min = 1000000,
869 .cvdd_max = 1050000,
870 };
871
872 #define OPP(freq) \
873 { \
874 .index = (unsigned int) &da850_opp_##freq, \
875 .frequency = freq * 1000, \
876 }
877
878 static struct cpufreq_frequency_table da850_freq_table[] = {
879 OPP(300),
880 OPP(200),
881 OPP(96),
882 {
883 .index = 0,
884 .frequency = CPUFREQ_TABLE_END,
885 },
886 };
887
888 #ifdef CONFIG_REGULATOR
889 static struct regulator *cvdd;
890
891 static int da850_set_voltage(unsigned int index)
892 {
893 struct da850_opp *opp;
894
895 if (!cvdd)
896 return -ENODEV;
897
898 opp = (struct da850_opp *) da850_freq_table[index].index;
899
900 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
901 }
902
903 static int da850_regulator_init(void)
904 {
905 cvdd = regulator_get(NULL, "cvdd");
906 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
907 " voltage scaling unsupported\n")) {
908 return PTR_ERR(cvdd);
909 }
910
911 return 0;
912 }
913 #endif
914
915 static struct davinci_cpufreq_config cpufreq_info = {
916 .freq_table = &da850_freq_table[0],
917 #ifdef CONFIG_REGULATOR
918 .init = da850_regulator_init,
919 .set_voltage = da850_set_voltage,
920 #endif
921 };
922
923 static struct platform_device da850_cpufreq_device = {
924 .name = "cpufreq-davinci",
925 .dev = {
926 .platform_data = &cpufreq_info,
927 },
928 .id = -1,
929 };
930
931 int __init da850_register_cpufreq(char *async_clk)
932 {
933 /* cpufreq driver can help keep an "async" clock constant */
934 if (async_clk)
935 clk_add_alias("async", da850_cpufreq_device.name,
936 async_clk, NULL);
937
938 return platform_device_register(&da850_cpufreq_device);
939 }
940
941 static int da850_round_armrate(struct clk *clk, unsigned long rate)
942 {
943 int i, ret = 0, diff;
944 unsigned int best = (unsigned int) -1;
945
946 rate /= 1000; /* convert to kHz */
947
948 for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
949 diff = da850_freq_table[i].frequency - rate;
950 if (diff < 0)
951 diff = -diff;
952
953 if (diff < best) {
954 best = diff;
955 ret = da850_freq_table[i].frequency;
956 }
957 }
958
959 return ret * 1000;
960 }
961
962 static int da850_set_armrate(struct clk *clk, unsigned long index)
963 {
964 struct clk *pllclk = &pll0_clk;
965
966 return clk_set_rate(pllclk, index);
967 }
968
969 static int da850_set_pll0rate(struct clk *clk, unsigned long index)
970 {
971 unsigned int prediv, mult, postdiv;
972 struct da850_opp *opp;
973 struct pll_data *pll = clk->pll_data;
974 int ret;
975
976 opp = (struct da850_opp *) da850_freq_table[index].index;
977 prediv = opp->prediv;
978 mult = opp->mult;
979 postdiv = opp->postdiv;
980
981 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
982 if (WARN_ON(ret))
983 return ret;
984
985 return 0;
986 }
987 #else
988 int __init da850_register_cpufreq(char *async_clk)
989 {
990 return 0;
991 }
992
993 static int da850_set_armrate(struct clk *clk, unsigned long rate)
994 {
995 return -EINVAL;
996 }
997
998 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
999 {
1000 return -EINVAL;
1001 }
1002
1003 static int da850_round_armrate(struct clk *clk, unsigned long rate)
1004 {
1005 return clk->rate;
1006 }
1007 #endif
1008
1009 int da850_register_pm(struct platform_device *pdev)
1010 {
1011 int ret;
1012 struct davinci_pm_config *pdata = pdev->dev.platform_data;
1013
1014 ret = davinci_cfg_reg(DA850_RTC_ALARM);
1015 if (ret)
1016 return ret;
1017
1018 pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
1019 pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
1020 pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
1021
1022 pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
1023 if (!pdata->cpupll_reg_base)
1024 return -ENOMEM;
1025
1026 pdata->ddrpll_reg_base = ioremap(DA8XX_PLL1_BASE, SZ_4K);
1027 if (!pdata->ddrpll_reg_base) {
1028 ret = -ENOMEM;
1029 goto no_ddrpll_mem;
1030 }
1031
1032 pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
1033 if (!pdata->ddrpsc_reg_base) {
1034 ret = -ENOMEM;
1035 goto no_ddrpsc_mem;
1036 }
1037
1038 return platform_device_register(pdev);
1039
1040 no_ddrpsc_mem:
1041 iounmap(pdata->ddrpll_reg_base);
1042 no_ddrpll_mem:
1043 iounmap(pdata->cpupll_reg_base);
1044 return ret;
1045 }
1046
1047 static struct davinci_soc_info davinci_soc_info_da850 = {
1048 .io_desc = da850_io_desc,
1049 .io_desc_num = ARRAY_SIZE(da850_io_desc),
1050 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
1051 .ids = da850_ids,
1052 .ids_num = ARRAY_SIZE(da850_ids),
1053 .cpu_clks = da850_clks,
1054 .psc_bases = da850_psc_bases,
1055 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
1056 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
1057 .pinmux_pins = da850_pins,
1058 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
1059 .intc_base = DA8XX_CP_INTC_BASE,
1060 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
1061 .intc_irq_prios = da850_default_priorities,
1062 .intc_irq_num = DA850_N_CP_INTC_IRQ,
1063 .timer_info = &da850_timer_info,
1064 .gpio_type = GPIO_TYPE_DAVINCI,
1065 .gpio_base = DA8XX_GPIO_BASE,
1066 .gpio_num = 144,
1067 .gpio_irq = IRQ_DA8XX_GPIO0,
1068 .serial_dev = &da8xx_serial_device,
1069 .emac_pdata = &da8xx_emac_pdata,
1070 .sram_dma = DA8XX_ARM_RAM_BASE,
1071 .sram_len = SZ_8K,
1072 .reset_device = &da8xx_wdt_device,
1073 };
1074
1075 void __init da850_init(void)
1076 {
1077 unsigned int v;
1078
1079 davinci_common_init(&davinci_soc_info_da850);
1080
1081 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1082 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1083 return;
1084
1085 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
1086 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
1087 return;
1088
1089 /*
1090 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
1091 * This helps keeping the peripherals on this domain insulated
1092 * from CPU frequency changes caused by DVFS. The firmware sets
1093 * both PLL0 and PLL1 to the same frequency so, there should not
1094 * be any noticible change even in non-DVFS use cases.
1095 */
1096 da850_set_async3_src(1);
1097
1098 /* Unlock writing to PLL0 registers */
1099 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1100 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1101 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1102
1103 /* Unlock writing to PLL1 registers */
1104 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1105 v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
1106 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1107 }
Linus' kernel tree