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drivers/staging: Remove unnecessary semicolons
[linux-2.6.git] / drivers / staging / rtl8192e / r819xE_phy.c
blob50cd0e52b9213ace1ab4fe30b98f0aa57c201670
1 #include "r8192E.h"
2 #include "r8192E_hw.h"
3 #include "r819xE_phyreg.h"
4 #include "r8190_rtl8256.h"
5 #include "r819xE_phy.h"
6 #include "r8192E_dm.h"
7 #ifdef ENABLE_DOT11D
8 #include "ieee80211/dot11d.h"
9 #endif
10 static const u32 RF_CHANNEL_TABLE_ZEBRA[] = {
11 0,
12 0x085c, //2412 1
13 0x08dc, //2417 2
14 0x095c, //2422 3
15 0x09dc, //2427 4
16 0x0a5c, //2432 5
17 0x0adc, //2437 6
18 0x0b5c, //2442 7
19 0x0bdc, //2447 8
20 0x0c5c, //2452 9
21 0x0cdc, //2457 10
22 0x0d5c, //2462 11
23 0x0ddc, //2467 12
24 0x0e5c, //2472 13
25 0x0f72, //2484
26 };
27 #ifdef RTL8190P
28 u32 Rtl8190PciMACPHY_Array[] = {
29 0x03c,0xffff0000,0x00000f0f,
30 0x340,0xffffffff,0x161a1a1a,
31 0x344,0xffffffff,0x12121416,
32 0x348,0x0000ffff,0x00001818,
33 0x12c,0xffffffff,0x04000802,
34 0x318,0x00000fff,0x00000800,
35 };
36 u32 Rtl8190PciMACPHY_Array_PG[] = {
37 0x03c,0xffff0000,0x00000f0f,
38 0x340,0xffffffff,0x0a0c0d0f,
39 0x344,0xffffffff,0x06070809,
40 0x344,0xffffffff,0x06070809,
41 0x348,0x0000ffff,0x00000000,
42 0x12c,0xffffffff,0x04000802,
43 0x318,0x00000fff,0x00000800,
44 };
45
46 u32 Rtl8190PciAGCTAB_Array[AGCTAB_ArrayLength] = {
47 0xc78,0x7d000001,
48 0xc78,0x7d010001,
49 0xc78,0x7d020001,
50 0xc78,0x7d030001,
51 0xc78,0x7c040001,
52 0xc78,0x7b050001,
53 0xc78,0x7a060001,
54 0xc78,0x79070001,
55 0xc78,0x78080001,
56 0xc78,0x77090001,
57 0xc78,0x760a0001,
58 0xc78,0x750b0001,
59 0xc78,0x740c0001,
60 0xc78,0x730d0001,
61 0xc78,0x720e0001,
62 0xc78,0x710f0001,
63 0xc78,0x70100001,
64 0xc78,0x6f110001,
65 0xc78,0x6e120001,
66 0xc78,0x6d130001,
67 0xc78,0x6c140001,
68 0xc78,0x6b150001,
69 0xc78,0x6a160001,
70 0xc78,0x69170001,
71 0xc78,0x68180001,
72 0xc78,0x67190001,
73 0xc78,0x661a0001,
74 0xc78,0x651b0001,
75 0xc78,0x641c0001,
76 0xc78,0x491d0001,
77 0xc78,0x481e0001,
78 0xc78,0x471f0001,
79 0xc78,0x46200001,
80 0xc78,0x45210001,
81 0xc78,0x44220001,
82 0xc78,0x43230001,
83 0xc78,0x28240001,
84 0xc78,0x27250001,
85 0xc78,0x26260001,
86 0xc78,0x25270001,
87 0xc78,0x24280001,
88 0xc78,0x23290001,
89 0xc78,0x222a0001,
90 0xc78,0x212b0001,
91 0xc78,0x202c0001,
92 0xc78,0x0a2d0001,
93 0xc78,0x082e0001,
94 0xc78,0x062f0001,
95 0xc78,0x05300001,
96 0xc78,0x04310001,
97 0xc78,0x03320001,
98 0xc78,0x02330001,
99 0xc78,0x01340001,
100 0xc78,0x00350001,
101 0xc78,0x00360001,
102 0xc78,0x00370001,
103 0xc78,0x00380001,
104 0xc78,0x00390001,
105 0xc78,0x003a0001,
106 0xc78,0x003b0001,
107 0xc78,0x003c0001,
108 0xc78,0x003d0001,
109 0xc78,0x003e0001,
110 0xc78,0x003f0001,
111 0xc78,0x7d400001,
112 0xc78,0x7d410001,
113 0xc78,0x7d420001,
114 0xc78,0x7d430001,
115 0xc78,0x7c440001,
116 0xc78,0x7b450001,
117 0xc78,0x7a460001,
118 0xc78,0x79470001,
119 0xc78,0x78480001,
120 0xc78,0x77490001,
121 0xc78,0x764a0001,
122 0xc78,0x754b0001,
123 0xc78,0x744c0001,
124 0xc78,0x734d0001,
125 0xc78,0x724e0001,
126 0xc78,0x714f0001,
127 0xc78,0x70500001,
128 0xc78,0x6f510001,
129 0xc78,0x6e520001,
130 0xc78,0x6d530001,
131 0xc78,0x6c540001,
132 0xc78,0x6b550001,
133 0xc78,0x6a560001,
134 0xc78,0x69570001,
135 0xc78,0x68580001,
136 0xc78,0x67590001,
137 0xc78,0x665a0001,
138 0xc78,0x655b0001,
139 0xc78,0x645c0001,
140 0xc78,0x495d0001,
141 0xc78,0x485e0001,
142 0xc78,0x475f0001,
143 0xc78,0x46600001,
144 0xc78,0x45610001,
145 0xc78,0x44620001,
146 0xc78,0x43630001,
147 0xc78,0x28640001,
148 0xc78,0x27650001,
149 0xc78,0x26660001,
150 0xc78,0x25670001,
151 0xc78,0x24680001,
152 0xc78,0x23690001,
153 0xc78,0x226a0001,
154 0xc78,0x216b0001,
155 0xc78,0x206c0001,
156 0xc78,0x0a6d0001,
157 0xc78,0x086e0001,
158 0xc78,0x066f0001,
159 0xc78,0x05700001,
160 0xc78,0x04710001,
161 0xc78,0x03720001,
162 0xc78,0x02730001,
163 0xc78,0x01740001,
164 0xc78,0x00750001,
165 0xc78,0x00760001,
166 0xc78,0x00770001,
167 0xc78,0x00780001,
168 0xc78,0x00790001,
169 0xc78,0x007a0001,
170 0xc78,0x007b0001,
171 0xc78,0x007c0001,
172 0xc78,0x007d0001,
173 0xc78,0x007e0001,
174 0xc78,0x007f0001,
175 0xc78,0x3600001e,
176 0xc78,0x3601001e,
177 0xc78,0x3602001e,
178 0xc78,0x3603001e,
179 0xc78,0x3604001e,
180 0xc78,0x3605001e,
181 0xc78,0x3a06001e,
182 0xc78,0x3c07001e,
183 0xc78,0x3e08001e,
184 0xc78,0x4209001e,
185 0xc78,0x430a001e,
186 0xc78,0x450b001e,
187 0xc78,0x470c001e,
188 0xc78,0x480d001e,
189 0xc78,0x490e001e,
190 0xc78,0x4b0f001e,
191 0xc78,0x4c10001e,
192 0xc78,0x4d11001e,
193 0xc78,0x4d12001e,
194 0xc78,0x4e13001e,
195 0xc78,0x4f14001e,
196 0xc78,0x5015001e,
197 0xc78,0x5116001e,
198 0xc78,0x5117001e,
199 0xc78,0x5218001e,
200 0xc78,0x5219001e,
201 0xc78,0x531a001e,
202 0xc78,0x541b001e,
203 0xc78,0x541c001e,
204 0xc78,0x551d001e,
205 0xc78,0x561e001e,
206 0xc78,0x561f001e,
207 0xc78,0x5720001e,
208 0xc78,0x5821001e,
209 0xc78,0x5822001e,
210 0xc78,0x5923001e,
211 0xc78,0x5924001e,
212 0xc78,0x5a25001e,
213 0xc78,0x5b26001e,
214 0xc78,0x5b27001e,
215 0xc78,0x5c28001e,
216 0xc78,0x5c29001e,
217 0xc78,0x5d2a001e,
218 0xc78,0x5d2b001e,
219 0xc78,0x5e2c001e,
220 0xc78,0x5e2d001e,
221 0xc78,0x5f2e001e,
222 0xc78,0x602f001e,
223 0xc78,0x6030001e,
224 0xc78,0x6131001e,
225 0xc78,0x6132001e,
226 0xc78,0x6233001e,
227 0xc78,0x6234001e,
228 0xc78,0x6335001e,
229 0xc78,0x6336001e,
230 0xc78,0x6437001e,
231 0xc78,0x6538001e,
232 0xc78,0x6639001e,
233 0xc78,0x663a001e,
234 0xc78,0x673b001e,
235 0xc78,0x683c001e,
236 0xc78,0x693d001e,
237 0xc78,0x6a3e001e,
238 0xc78,0x6b3f001e,
239 };
240
241 u32 Rtl8190PciPHY_REGArray[PHY_REGArrayLength] = {
242 0x800,0x00050060,
243 0x804,0x00000005,
244 0x808,0x0000fc00,
245 0x80c,0x0000001c,
246 0x810,0x801010aa,
247 0x814,0x000908c0,
248 0x818,0x00000000,
249 0x81c,0x00000000,
250 0x820,0x00000004,
251 0x824,0x00690000,
252 0x828,0x00000004,
253 0x82c,0x00e90000,
254 0x830,0x00000004,
255 0x834,0x00690000,
256 0x838,0x00000004,
257 0x83c,0x00e90000,
258 0x840,0x00000000,
259 0x844,0x00000000,
260 0x848,0x00000000,
261 0x84c,0x00000000,
262 0x850,0x00000000,
263 0x854,0x00000000,
264 0x858,0x65a965a9,
265 0x85c,0x65a965a9,
266 0x860,0x001f0010,
267 0x864,0x007f0010,
268 0x868,0x001f0010,
269 0x86c,0x007f0010,
270 0x870,0x0f100f70,
271 0x874,0x0f100f70,
272 0x878,0x00000000,
273 0x87c,0x00000000,
274 0x880,0x5c385eb8,
275 0x884,0x6357060d,
276 0x888,0x0460c341,
277 0x88c,0x0000ff00,
278 0x890,0x00000000,
279 0x894,0xfffffffe,
280 0x898,0x4c42382f,
281 0x89c,0x00656056,
282 0x8b0,0x00000000,
283 0x8e0,0x00000000,
284 0x8e4,0x00000000,
285 0x900,0x00000000,
286 0x904,0x00000023,
287 0x908,0x00000000,
288 0x90c,0x35541545,
289 0xa00,0x00d0c7d8,
290 0xa04,0xab1f0008,
291 0xa08,0x80cd8300,
292 0xa0c,0x2e62740f,
293 0xa10,0x95009b78,
294 0xa14,0x11145008,
295 0xa18,0x00881117,
296 0xa1c,0x89140fa0,
297 0xa20,0x1a1b0000,
298 0xa24,0x090e1317,
299 0xa28,0x00000204,
300 0xa2c,0x00000000,
301 0xc00,0x00000040,
302 0xc04,0x0000500f,
303 0xc08,0x000000e4,
304 0xc0c,0x6c6c6c6c,
305 0xc10,0x08000000,
306 0xc14,0x40000100,
307 0xc18,0x08000000,
308 0xc1c,0x40000100,
309 0xc20,0x08000000,
310 0xc24,0x40000100,
311 0xc28,0x08000000,
312 0xc2c,0x40000100,
313 0xc30,0x6de9ac44,
314 0xc34,0x164052cd,
315 0xc38,0x00070a14,
316 0xc3c,0x0a969764,
317 0xc40,0x1f7c403f,
318 0xc44,0x000100b7,
319 0xc48,0xec020000,
320 0xc4c,0x00000300,
321 0xc50,0x69543420,
322 0xc54,0x433c0094,
323 0xc58,0x69543420,
324 0xc5c,0x433c0094,
325 0xc60,0x69543420,
326 0xc64,0x433c0094,
327 0xc68,0x69543420,
328 0xc6c,0x433c0094,
329 0xc70,0x2c7f000d,
330 0xc74,0x0186175b,
331 0xc78,0x0000001f,
332 0xc7c,0x00b91612,
333 0xc80,0x40000100,
334 0xc84,0x00000000,
335 0xc88,0x40000100,
336 0xc8c,0x08000000,
337 0xc90,0x40000100,
338 0xc94,0x00000000,
339 0xc98,0x40000100,
340 0xc9c,0x00000000,
341 0xca0,0x00492492,
342 0xca4,0x00000000,
343 0xca8,0x00000000,
344 0xcac,0x00000000,
345 0xcb0,0x00000000,
346 0xcb4,0x00000000,
347 0xcb8,0x00000000,
348 0xcbc,0x00492492,
349 0xcc0,0x00000000,
350 0xcc4,0x00000000,
351 0xcc8,0x00000000,
352 0xccc,0x00000000,
353 0xcd0,0x00000000,
354 0xcd4,0x00000000,
355 0xcd8,0x64b22427,
356 0xcdc,0x00766932,
357 0xce0,0x00222222,
358 0xd00,0x00000740,
359 0xd04,0x0000040f,
360 0xd08,0x0000803f,
361 0xd0c,0x00000001,
362 0xd10,0xa0633333,
363 0xd14,0x33333c63,
364 0xd18,0x6a8f5b6b,
365 0xd1c,0x00000000,
366 0xd20,0x00000000,
367 0xd24,0x00000000,
368 0xd28,0x00000000,
369 0xd2c,0xcc979975,
370 0xd30,0x00000000,
371 0xd34,0x00000000,
372 0xd38,0x00000000,
373 0xd3c,0x00027293,
374 0xd40,0x00000000,
375 0xd44,0x00000000,
376 0xd48,0x00000000,
377 0xd4c,0x00000000,
378 0xd50,0x6437140a,
379 0xd54,0x024dbd02,
380 0xd58,0x00000000,
381 0xd5c,0x14032064,
382 };
383 u32 Rtl8190PciPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = {
384 0x800,0x00050060,
385 0x804,0x00000004,
386 0x808,0x0000fc00,
387 0x80c,0x0000001c,
388 0x810,0x801010aa,
389 0x814,0x000908c0,
390 0x818,0x00000000,
391 0x81c,0x00000000,
392 0x820,0x00000004,
393 0x824,0x00690000,
394 0x828,0x00000004,
395 0x82c,0x00e90000,
396 0x830,0x00000004,
397 0x834,0x00690000,
398 0x838,0x00000004,
399 0x83c,0x00e90000,
400 0x840,0x00000000,
401 0x844,0x00000000,
402 0x848,0x00000000,
403 0x84c,0x00000000,
404 0x850,0x00000000,
405 0x854,0x00000000,
406 0x858,0x65a965a9,
407 0x85c,0x65a965a9,
408 0x860,0x001f0000,
409 0x864,0x007f0000,
410 0x868,0x001f0010,
411 0x86c,0x007f0010,
412 0x870,0x0f100f70,
413 0x874,0x0f100f70,
414 0x878,0x00000000,
415 0x87c,0x00000000,
416 0x880,0x5c385898,
417 0x884,0x6357060d,
418 0x888,0x0460c341,
419 0x88c,0x0000fc00,
420 0x890,0x00000000,
421 0x894,0xfffffffe,
422 0x898,0x4c42382f,
423 0x89c,0x00656056,
424 0x8b0,0x00000000,
425 0x8e0,0x00000000,
426 0x8e4,0x00000000,
427 0x900,0x00000000,
428 0x904,0x00000023,
429 0x908,0x00000000,
430 0x90c,0x34441444,
431 0xa00,0x00d0c7d8,
432 0xa04,0x2b1f0008,
433 0xa08,0x80cd8300,
434 0xa0c,0x2e62740f,
435 0xa10,0x95009b78,
436 0xa14,0x11145008,
437 0xa18,0x00881117,
438 0xa1c,0x89140fa0,
439 0xa20,0x1a1b0000,
440 0xa24,0x090e1317,
441 0xa28,0x00000204,
442 0xa2c,0x00000000,
443 0xc00,0x00000040,
444 0xc04,0x0000500c,
445 0xc08,0x000000e4,
446 0xc0c,0x6c6c6c6c,
447 0xc10,0x08000000,
448 0xc14,0x40000100,
449 0xc18,0x08000000,
450 0xc1c,0x40000100,
451 0xc20,0x08000000,
452 0xc24,0x40000100,
453 0xc28,0x08000000,
454 0xc2c,0x40000100,
455 0xc30,0x6de9ac44,
456 0xc34,0x164052cd,
457 0xc38,0x00070a14,
458 0xc3c,0x0a969764,
459 0xc40,0x1f7c403f,
460 0xc44,0x000100b7,
461 0xc48,0xec020000,
462 0xc4c,0x00000300,
463 0xc50,0x69543420,
464 0xc54,0x433c0094,
465 0xc58,0x69543420,
466 0xc5c,0x433c0094,
467 0xc60,0x69543420,
468 0xc64,0x433c0094,
469 0xc68,0x69543420,
470 0xc6c,0x433c0094,
471 0xc70,0x2c7f000d,
472 0xc74,0x0186175b,
473 0xc78,0x0000001f,
474 0xc7c,0x00b91612,
475 0xc80,0x40000100,
476 0xc84,0x00000000,
477 0xc88,0x40000100,
478 0xc8c,0x08000000,
479 0xc90,0x40000100,
480 0xc94,0x00000000,
481 0xc98,0x40000100,
482 0xc9c,0x00000000,
483 0xca0,0x00492492,
484 0xca4,0x00000000,
485 0xca8,0x00000000,
486 0xcac,0x00000000,
487 0xcb0,0x00000000,
488 0xcb4,0x00000000,
489 0xcb8,0x00000000,
490 0xcbc,0x00492492,
491 0xcc0,0x00000000,
492 0xcc4,0x00000000,
493 0xcc8,0x00000000,
494 0xccc,0x00000000,
495 0xcd0,0x00000000,
496 0xcd4,0x00000000,
497 0xcd8,0x64b22427,
498 0xcdc,0x00766932,
499 0xce0,0x00222222,
500 0xd00,0x00000740,
501 0xd04,0x0000040c,
502 0xd08,0x0000803f,
503 0xd0c,0x00000001,
504 0xd10,0xa0633333,
505 0xd14,0x33333c63,
506 0xd18,0x6a8f5b6b,
507 0xd1c,0x00000000,
508 0xd20,0x00000000,
509 0xd24,0x00000000,
510 0xd28,0x00000000,
511 0xd2c,0xcc979975,
512 0xd30,0x00000000,
513 0xd34,0x00000000,
514 0xd38,0x00000000,
515 0xd3c,0x00027293,
516 0xd40,0x00000000,
517 0xd44,0x00000000,
518 0xd48,0x00000000,
519 0xd4c,0x00000000,
520 0xd50,0x6437140a,
521 0xd54,0x024dbd02,
522 0xd58,0x00000000,
523 0xd5c,0x14032064,
524 };
525
526 u32 Rtl8190PciRadioA_Array[RadioA_ArrayLength] = {
527 0x019,0x00000003,
528 0x000,0x000000bf,
529 0x001,0x00000ee0,
530 0x002,0x0000004c,
531 0x003,0x000007f1,
532 0x004,0x00000975,
533 0x005,0x00000c58,
534 0x006,0x00000ae6,
535 0x007,0x000000ca,
536 0x008,0x00000e1c,
537 0x009,0x000007f0,
538 0x00a,0x000009d0,
539 0x00b,0x000001ba,
540 0x00c,0x00000240,
541 0x00e,0x00000020,
542 0x00f,0x00000990,
543 0x012,0x00000806,
544 0x014,0x000005ab,
545 0x015,0x00000f80,
546 0x016,0x00000020,
547 0x017,0x00000597,
548 0x018,0x0000050a,
549 0x01a,0x00000f80,
550 0x01b,0x00000f5e,
551 0x01c,0x00000008,
552 0x01d,0x00000607,
553 0x01e,0x000006cc,
554 0x01f,0x00000000,
555 0x020,0x000001a5,
556 0x01f,0x00000001,
557 0x020,0x00000165,
558 0x01f,0x00000002,
559 0x020,0x000000c6,
560 0x01f,0x00000003,
561 0x020,0x00000086,
562 0x01f,0x00000004,
563 0x020,0x00000046,
564 0x01f,0x00000005,
565 0x020,0x000001e6,
566 0x01f,0x00000006,
567 0x020,0x000001a6,
568 0x01f,0x00000007,
569 0x020,0x00000166,
570 0x01f,0x00000008,
571 0x020,0x000000c7,
572 0x01f,0x00000009,
573 0x020,0x00000087,
574 0x01f,0x0000000a,
575 0x020,0x000000f7,
576 0x01f,0x0000000b,
577 0x020,0x000000d7,
578 0x01f,0x0000000c,
579 0x020,0x000000b7,
580 0x01f,0x0000000d,
581 0x020,0x00000097,
582 0x01f,0x0000000e,
583 0x020,0x00000077,
584 0x01f,0x0000000f,
585 0x020,0x00000057,
586 0x01f,0x00000010,
587 0x020,0x00000037,
588 0x01f,0x00000011,
589 0x020,0x000000fb,
590 0x01f,0x00000012,
591 0x020,0x000000db,
592 0x01f,0x00000013,
593 0x020,0x000000bb,
594 0x01f,0x00000014,
595 0x020,0x000000ff,
596 0x01f,0x00000015,
597 0x020,0x000000e3,
598 0x01f,0x00000016,
599 0x020,0x000000c3,
600 0x01f,0x00000017,
601 0x020,0x000000a3,
602 0x01f,0x00000018,
603 0x020,0x00000083,
604 0x01f,0x00000019,
605 0x020,0x00000063,
606 0x01f,0x0000001a,
607 0x020,0x00000043,
608 0x01f,0x0000001b,
609 0x020,0x00000023,
610 0x01f,0x0000001c,
611 0x020,0x00000003,
612 0x01f,0x0000001d,
613 0x020,0x000001e3,
614 0x01f,0x0000001e,
615 0x020,0x000001c3,
616 0x01f,0x0000001f,
617 0x020,0x000001a3,
618 0x01f,0x00000020,
619 0x020,0x00000183,
620 0x01f,0x00000021,
621 0x020,0x00000163,
622 0x01f,0x00000022,
623 0x020,0x00000143,
624 0x01f,0x00000023,
625 0x020,0x00000123,
626 0x01f,0x00000024,
627 0x020,0x00000103,
628 0x023,0x00000203,
629 0x024,0x00000200,
630 0x00b,0x000001ba,
631 0x02c,0x000003d7,
632 0x02d,0x00000ff0,
633 0x000,0x00000037,
634 0x004,0x00000160,
635 0x007,0x00000080,
636 0x002,0x0000088d,
637 0x0fe,0x00000000,
638 0x0fe,0x00000000,
639 0x016,0x00000200,
640 0x016,0x00000380,
641 0x016,0x00000020,
642 0x016,0x000001a0,
643 0x000,0x000000bf,
644 0x00d,0x0000001f,
645 0x00d,0x00000c9f,
646 0x002,0x0000004d,
647 0x000,0x00000cbf,
648 0x004,0x00000975,
649 0x007,0x00000700,
650 };
651 u32 Rtl8190PciRadioB_Array[RadioB_ArrayLength] = {
652 0x019,0x00000003,
653 0x000,0x000000bf,
654 0x001,0x000006e0,
655 0x002,0x0000004c,
656 0x003,0x000007f1,
657 0x004,0x00000975,
658 0x005,0x00000c58,
659 0x006,0x00000ae6,
660 0x007,0x000000ca,
661 0x008,0x00000e1c,
662 0x000,0x000000b7,
663 0x00a,0x00000850,
664 0x000,0x000000bf,
665 0x00b,0x000001ba,
666 0x00c,0x00000240,
667 0x00e,0x00000020,
668 0x015,0x00000f80,
669 0x016,0x00000020,
670 0x017,0x00000597,
671 0x018,0x0000050a,
672 0x01a,0x00000e00,
673 0x01b,0x00000f5e,
674 0x01d,0x00000607,
675 0x01e,0x000006cc,
676 0x00b,0x000001ba,
677 0x023,0x00000203,
678 0x024,0x00000200,
679 0x000,0x00000037,
680 0x004,0x00000160,
681 0x016,0x00000200,
682 0x016,0x00000380,
683 0x016,0x00000020,
684 0x016,0x000001a0,
685 0x00d,0x00000ccc,
686 0x000,0x000000bf,
687 0x002,0x0000004d,
688 0x000,0x00000cbf,
689 0x004,0x00000975,
690 0x007,0x00000700,
691 };
692 u32 Rtl8190PciRadioC_Array[RadioC_ArrayLength] = {
693 0x019,0x00000003,
694 0x000,0x000000bf,
695 0x001,0x00000ee0,
696 0x002,0x0000004c,
697 0x003,0x000007f1,
698 0x004,0x00000975,
699 0x005,0x00000c58,
700 0x006,0x00000ae6,
701 0x007,0x000000ca,
702 0x008,0x00000e1c,
703 0x009,0x000007f0,
704 0x00a,0x000009d0,
705 0x00b,0x000001ba,
706 0x00c,0x00000240,
707 0x00e,0x00000020,
708 0x00f,0x00000990,
709 0x012,0x00000806,
710 0x014,0x000005ab,
711 0x015,0x00000f80,
712 0x016,0x00000020,
713 0x017,0x00000597,
714 0x018,0x0000050a,
715 0x01a,0x00000f80,
716 0x01b,0x00000f5e,
717 0x01c,0x00000008,
718 0x01d,0x00000607,
719 0x01e,0x000006cc,
720 0x01f,0x00000000,
721 0x020,0x000001a5,
722 0x01f,0x00000001,
723 0x020,0x00000165,
724 0x01f,0x00000002,
725 0x020,0x000000c6,
726 0x01f,0x00000003,
727 0x020,0x00000086,
728 0x01f,0x00000004,
729 0x020,0x00000046,
730 0x01f,0x00000005,
731 0x020,0x000001e6,
732 0x01f,0x00000006,
733 0x020,0x000001a6,
734 0x01f,0x00000007,
735 0x020,0x00000166,
736 0x01f,0x00000008,
737 0x020,0x000000c7,
738 0x01f,0x00000009,
739 0x020,0x00000087,
740 0x01f,0x0000000a,
741 0x020,0x000000f7,
742 0x01f,0x0000000b,
743 0x020,0x000000d7,
744 0x01f,0x0000000c,
745 0x020,0x000000b7,
746 0x01f,0x0000000d,
747 0x020,0x00000097,
748 0x01f,0x0000000e,
749 0x020,0x00000077,
750 0x01f,0x0000000f,
751 0x020,0x00000057,
752 0x01f,0x00000010,
753 0x020,0x00000037,
754 0x01f,0x00000011,
755 0x020,0x000000fb,
756 0x01f,0x00000012,
757 0x020,0x000000db,
758 0x01f,0x00000013,
759 0x020,0x000000bb,
760 0x01f,0x00000014,
761 0x020,0x000000ff,
762 0x01f,0x00000015,
763 0x020,0x000000e3,
764 0x01f,0x00000016,
765 0x020,0x000000c3,
766 0x01f,0x00000017,
767 0x020,0x000000a3,
768 0x01f,0x00000018,
769 0x020,0x00000083,
770 0x01f,0x00000019,
771 0x020,0x00000063,
772 0x01f,0x0000001a,
773 0x020,0x00000043,
774 0x01f,0x0000001b,
775 0x020,0x00000023,
776 0x01f,0x0000001c,
777 0x020,0x00000003,
778 0x01f,0x0000001d,
779 0x020,0x000001e3,
780 0x01f,0x0000001e,
781 0x020,0x000001c3,
782 0x01f,0x0000001f,
783 0x020,0x000001a3,
784 0x01f,0x00000020,
785 0x020,0x00000183,
786 0x01f,0x00000021,
787 0x020,0x00000163,
788 0x01f,0x00000022,
789 0x020,0x00000143,
790 0x01f,0x00000023,
791 0x020,0x00000123,
792 0x01f,0x00000024,
793 0x020,0x00000103,
794 0x023,0x00000203,
795 0x024,0x00000200,
796 0x00b,0x000001ba,
797 0x02c,0x000003d7,
798 0x02d,0x00000ff0,
799 0x000,0x00000037,
800 0x004,0x00000160,
801 0x007,0x00000080,
802 0x002,0x0000088d,
803 0x0fe,0x00000000,
804 0x0fe,0x00000000,
805 0x016,0x00000200,
806 0x016,0x00000380,
807 0x016,0x00000020,
808 0x016,0x000001a0,
809 0x000,0x000000bf,
810 0x00d,0x0000001f,
811 0x00d,0x00000c9f,
812 0x002,0x0000004d,
813 0x000,0x00000cbf,
814 0x004,0x00000975,
815 0x007,0x00000700,
816 };
817 u32 Rtl8190PciRadioD_Array[RadioD_ArrayLength] = {
818 0x019,0x00000003,
819 0x000,0x000000bf,
820 0x001,0x000006e0,
821 0x002,0x0000004c,
822 0x003,0x000007f1,
823 0x004,0x00000975,
824 0x005,0x00000c58,
825 0x006,0x00000ae6,
826 0x007,0x000000ca,
827 0x008,0x00000e1c,
828 0x000,0x000000b7,
829 0x00a,0x00000850,
830 0x000,0x000000bf,
831 0x00b,0x000001ba,
832 0x00c,0x00000240,
833 0x00e,0x00000020,
834 0x015,0x00000f80,
835 0x016,0x00000020,
836 0x017,0x00000597,
837 0x018,0x0000050a,
838 0x01a,0x00000e00,
839 0x01b,0x00000f5e,
840 0x01d,0x00000607,
841 0x01e,0x000006cc,
842 0x00b,0x000001ba,
843 0x023,0x00000203,
844 0x024,0x00000200,
845 0x000,0x00000037,
846 0x004,0x00000160,
847 0x016,0x00000200,
848 0x016,0x00000380,
849 0x016,0x00000020,
850 0x016,0x000001a0,
851 0x00d,0x00000ccc,
852 0x000,0x000000bf,
853 0x002,0x0000004d,
854 0x000,0x00000cbf,
855 0x004,0x00000975,
856 0x007,0x00000700,
857 };
858 #endif
859 #ifdef RTL8192E
860 static u32 Rtl8192PciEMACPHY_Array[] = {
861 0x03c,0xffff0000,0x00000f0f,
862 0x340,0xffffffff,0x161a1a1a,
863 0x344,0xffffffff,0x12121416,
864 0x348,0x0000ffff,0x00001818,
865 0x12c,0xffffffff,0x04000802,
866 0x318,0x00000fff,0x00000100,
867 };
868 static u32 Rtl8192PciEMACPHY_Array_PG[] = {
869 0x03c,0xffff0000,0x00000f0f,
870 0xe00,0xffffffff,0x06090909,
871 0xe04,0xffffffff,0x00030306,
872 0xe08,0x0000ff00,0x00000000,
873 0xe10,0xffffffff,0x0a0c0d0f,
874 0xe14,0xffffffff,0x06070809,
875 0xe18,0xffffffff,0x0a0c0d0f,
876 0xe1c,0xffffffff,0x06070809,
877 0x12c,0xffffffff,0x04000802,
878 0x318,0x00000fff,0x00000800,
879 };
880 static u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLength] = {
881 0xc78,0x7d000001,
882 0xc78,0x7d010001,
883 0xc78,0x7d020001,
884 0xc78,0x7d030001,
885 0xc78,0x7d040001,
886 0xc78,0x7d050001,
887 0xc78,0x7c060001,
888 0xc78,0x7b070001,
889 0xc78,0x7a080001,
890 0xc78,0x79090001,
891 0xc78,0x780a0001,
892 0xc78,0x770b0001,
893 0xc78,0x760c0001,
894 0xc78,0x750d0001,
895 0xc78,0x740e0001,
896 0xc78,0x730f0001,
897 0xc78,0x72100001,
898 0xc78,0x71110001,
899 0xc78,0x70120001,
900 0xc78,0x6f130001,
901 0xc78,0x6e140001,
902 0xc78,0x6d150001,
903 0xc78,0x6c160001,
904 0xc78,0x6b170001,
905 0xc78,0x6a180001,
906 0xc78,0x69190001,
907 0xc78,0x681a0001,
908 0xc78,0x671b0001,
909 0xc78,0x661c0001,
910 0xc78,0x651d0001,
911 0xc78,0x641e0001,
912 0xc78,0x491f0001,
913 0xc78,0x48200001,
914 0xc78,0x47210001,
915 0xc78,0x46220001,
916 0xc78,0x45230001,
917 0xc78,0x44240001,
918 0xc78,0x43250001,
919 0xc78,0x28260001,
920 0xc78,0x27270001,
921 0xc78,0x26280001,
922 0xc78,0x25290001,
923 0xc78,0x242a0001,
924 0xc78,0x232b0001,
925 0xc78,0x222c0001,
926 0xc78,0x212d0001,
927 0xc78,0x202e0001,
928 0xc78,0x0a2f0001,
929 0xc78,0x08300001,
930 0xc78,0x06310001,
931 0xc78,0x05320001,
932 0xc78,0x04330001,
933 0xc78,0x03340001,
934 0xc78,0x02350001,
935 0xc78,0x01360001,
936 0xc78,0x00370001,
937 0xc78,0x00380001,
938 0xc78,0x00390001,
939 0xc78,0x003a0001,
940 0xc78,0x003b0001,
941 0xc78,0x003c0001,
942 0xc78,0x003d0001,
943 0xc78,0x003e0001,
944 0xc78,0x003f0001,
945 0xc78,0x7d400001,
946 0xc78,0x7d410001,
947 0xc78,0x7d420001,
948 0xc78,0x7d430001,
949 0xc78,0x7d440001,
950 0xc78,0x7d450001,
951 0xc78,0x7c460001,
952 0xc78,0x7b470001,
953 0xc78,0x7a480001,
954 0xc78,0x79490001,
955 0xc78,0x784a0001,
956 0xc78,0x774b0001,
957 0xc78,0x764c0001,
958 0xc78,0x754d0001,
959 0xc78,0x744e0001,
960 0xc78,0x734f0001,
961 0xc78,0x72500001,
962 0xc78,0x71510001,
963 0xc78,0x70520001,
964 0xc78,0x6f530001,
965 0xc78,0x6e540001,
966 0xc78,0x6d550001,
967 0xc78,0x6c560001,
968 0xc78,0x6b570001,
969 0xc78,0x6a580001,
970 0xc78,0x69590001,
971 0xc78,0x685a0001,
972 0xc78,0x675b0001,
973 0xc78,0x665c0001,
974 0xc78,0x655d0001,
975 0xc78,0x645e0001,
976 0xc78,0x495f0001,
977 0xc78,0x48600001,
978 0xc78,0x47610001,
979 0xc78,0x46620001,
980 0xc78,0x45630001,
981 0xc78,0x44640001,
982 0xc78,0x43650001,
983 0xc78,0x28660001,
984 0xc78,0x27670001,
985 0xc78,0x26680001,
986 0xc78,0x25690001,
987 0xc78,0x246a0001,
988 0xc78,0x236b0001,
989 0xc78,0x226c0001,
990 0xc78,0x216d0001,
991 0xc78,0x206e0001,
992 0xc78,0x0a6f0001,
993 0xc78,0x08700001,
994 0xc78,0x06710001,
995 0xc78,0x05720001,
996 0xc78,0x04730001,
997 0xc78,0x03740001,
998 0xc78,0x02750001,
999 0xc78,0x01760001,
1000 0xc78,0x00770001,
1001 0xc78,0x00780001,
1002 0xc78,0x00790001,
1003 0xc78,0x007a0001,
1004 0xc78,0x007b0001,
1005 0xc78,0x007c0001,
1006 0xc78,0x007d0001,
1007 0xc78,0x007e0001,
1008 0xc78,0x007f0001,
1009 0xc78,0x2e00001e,
1010 0xc78,0x2e01001e,
1011 0xc78,0x2e02001e,
1012 0xc78,0x2e03001e,
1013 0xc78,0x2e04001e,
1014 0xc78,0x2e05001e,
1015 0xc78,0x3006001e,
1016 0xc78,0x3407001e,
1017 0xc78,0x3908001e,
1018 0xc78,0x3c09001e,
1019 0xc78,0x3f0a001e,
1020 0xc78,0x420b001e,
1021 0xc78,0x440c001e,
1022 0xc78,0x450d001e,
1023 0xc78,0x460e001e,
1024 0xc78,0x460f001e,
1025 0xc78,0x4710001e,
1026 0xc78,0x4811001e,
1027 0xc78,0x4912001e,
1028 0xc78,0x4a13001e,
1029 0xc78,0x4b14001e,
1030 0xc78,0x4b15001e,
1031 0xc78,0x4c16001e,
1032 0xc78,0x4d17001e,
1033 0xc78,0x4e18001e,
1034 0xc78,0x4f19001e,
1035 0xc78,0x4f1a001e,
1036 0xc78,0x501b001e,
1037 0xc78,0x511c001e,
1038 0xc78,0x521d001e,
1039 0xc78,0x521e001e,
1040 0xc78,0x531f001e,
1041 0xc78,0x5320001e,
1042 0xc78,0x5421001e,
1043 0xc78,0x5522001e,
1044 0xc78,0x5523001e,
1045 0xc78,0x5624001e,
1046 0xc78,0x5725001e,
1047 0xc78,0x5726001e,
1048 0xc78,0x5827001e,
1049 0xc78,0x5828001e,
1050 0xc78,0x5929001e,
1051 0xc78,0x592a001e,
1052 0xc78,0x5a2b001e,
1053 0xc78,0x5b2c001e,
1054 0xc78,0x5c2d001e,
1055 0xc78,0x5c2e001e,
1056 0xc78,0x5d2f001e,
1057 0xc78,0x5e30001e,
1058 0xc78,0x5f31001e,
1059 0xc78,0x6032001e,
1060 0xc78,0x6033001e,
1061 0xc78,0x6134001e,
1062 0xc78,0x6235001e,
1063 0xc78,0x6336001e,
1064 0xc78,0x6437001e,
1065 0xc78,0x6438001e,
1066 0xc78,0x6539001e,
1067 0xc78,0x663a001e,
1068 0xc78,0x673b001e,
1069 0xc78,0x673c001e,
1070 0xc78,0x683d001e,
1071 0xc78,0x693e001e,
1072 0xc78,0x6a3f001e,
1073 };
1074 static u32 Rtl8192PciEPHY_REGArray[PHY_REGArrayLength] = {
1075 0x0, };
1076 static u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = {
1077 0x800,0x00000000,
1078 0x804,0x00000001,
1079 0x808,0x0000fc00,
1080 0x80c,0x0000001c,
1081 0x810,0x801010aa,
1082 0x814,0x008514d0,
1083 0x818,0x00000040,
1084 0x81c,0x00000000,
1085 0x820,0x00000004,
1086 0x824,0x00690000,
1087 0x828,0x00000004,
1088 0x82c,0x00e90000,
1089 0x830,0x00000004,
1090 0x834,0x00690000,
1091 0x838,0x00000004,
1092 0x83c,0x00e90000,
1093 0x840,0x00000000,
1094 0x844,0x00000000,
1095 0x848,0x00000000,
1096 0x84c,0x00000000,
1097 0x850,0x00000000,
1098 0x854,0x00000000,
1099 0x858,0x65a965a9,
1100 0x85c,0x65a965a9,
1101 0x860,0x001f0010,
1102 0x864,0x007f0010,
1103 0x868,0x001f0010,
1104 0x86c,0x007f0010,
1105 0x870,0x0f100f70,
1106 0x874,0x0f100f70,
1107 0x878,0x00000000,
1108 0x87c,0x00000000,
1109 0x880,0x6870e36c,
1110 0x884,0xe3573600,
1111 0x888,0x4260c340,
1112 0x88c,0x0000ff00,
1113 0x890,0x00000000,
1114 0x894,0xfffffffe,
1115 0x898,0x4c42382f,
1116 0x89c,0x00656056,
1117 0x8b0,0x00000000,
1118 0x8e0,0x00000000,
1119 0x8e4,0x00000000,
1120 0x900,0x00000000,
1121 0x904,0x00000023,
1122 0x908,0x00000000,
1123 0x90c,0x31121311,
1124 0xa00,0x00d0c7d8,
1125 0xa04,0x811f0008,
1126 0xa08,0x80cd8300,
1127 0xa0c,0x2e62740f,
1128 0xa10,0x95009b78,
1129 0xa14,0x11145008,
1130 0xa18,0x00881117,
1131 0xa1c,0x89140fa0,
1132 0xa20,0x1a1b0000,
1133 0xa24,0x090e1317,
1134 0xa28,0x00000204,
1135 0xa2c,0x00000000,
1136 0xc00,0x00000040,
1137 0xc04,0x00005433,
1138 0xc08,0x000000e4,
1139 0xc0c,0x6c6c6c6c,
1140 0xc10,0x08800000,
1141 0xc14,0x40000100,
1142 0xc18,0x08000000,
1143 0xc1c,0x40000100,
1144 0xc20,0x08000000,
1145 0xc24,0x40000100,
1146 0xc28,0x08000000,
1147 0xc2c,0x40000100,
1148 0xc30,0x6de9ac44,
1149 0xc34,0x465c52cd,
1150 0xc38,0x497f5994,
1151 0xc3c,0x0a969764,
1152 0xc40,0x1f7c403f,
1153 0xc44,0x000100b7,
1154 0xc48,0xec020000,
1155 0xc4c,0x00000300,
1156 0xc50,0x69543420,
1157 0xc54,0x433c0094,
1158 0xc58,0x69543420,
1159 0xc5c,0x433c0094,
1160 0xc60,0x69543420,
1161 0xc64,0x433c0094,
1162 0xc68,0x69543420,
1163 0xc6c,0x433c0094,
1164 0xc70,0x2c7f000d,
1165 0xc74,0x0186175b,
1166 0xc78,0x0000001f,
1167 0xc7c,0x00b91612,
1168 0xc80,0x40000100,
1169 0xc84,0x20000000,
1170 0xc88,0x40000100,
1171 0xc8c,0x20200000,
1172 0xc90,0x40000100,
1173 0xc94,0x00000000,
1174 0xc98,0x40000100,
1175 0xc9c,0x00000000,
1176 0xca0,0x00492492,
1177 0xca4,0x00000000,
1178 0xca8,0x00000000,
1179 0xcac,0x00000000,
1180 0xcb0,0x00000000,
1181 0xcb4,0x00000000,
1182 0xcb8,0x00000000,
1183 0xcbc,0x00492492,
1184 0xcc0,0x00000000,
1185 0xcc4,0x00000000,
1186 0xcc8,0x00000000,
1187 0xccc,0x00000000,
1188 0xcd0,0x00000000,
1189 0xcd4,0x00000000,
1190 0xcd8,0x64b22427,
1191 0xcdc,0x00766932,
1192 0xce0,0x00222222,
1193 0xd00,0x00000750,
1194 0xd04,0x00000403,
1195 0xd08,0x0000907f,
1196 0xd0c,0x00000001,
1197 0xd10,0xa0633333,
1198 0xd14,0x33333c63,
1199 0xd18,0x6a8f5b6b,
1200 0xd1c,0x00000000,
1201 0xd20,0x00000000,
1202 0xd24,0x00000000,
1203 0xd28,0x00000000,
1204 0xd2c,0xcc979975,
1205 0xd30,0x00000000,
1206 0xd34,0x00000000,
1207 0xd38,0x00000000,
1208 0xd3c,0x00027293,
1209 0xd40,0x00000000,
1210 0xd44,0x00000000,
1211 0xd48,0x00000000,
1212 0xd4c,0x00000000,
1213 0xd50,0x6437140a,
1214 0xd54,0x024dbd02,
1215 0xd58,0x00000000,
1216 0xd5c,0x04032064,
1217 0xe00,0x161a1a1a,
1218 0xe04,0x12121416,
1219 0xe08,0x00001800,
1220 0xe0c,0x00000000,
1221 0xe10,0x161a1a1a,
1222 0xe14,0x12121416,
1223 0xe18,0x161a1a1a,
1224 0xe1c,0x12121416,
1225 };
1226 static u32 Rtl8192PciERadioA_Array[RadioA_ArrayLength] = {
1227 0x019,0x00000003,
1228 0x000,0x000000bf,
1229 0x001,0x00000ee0,
1230 0x002,0x0000004c,
1231 0x003,0x000007f1,
1232 0x004,0x00000975,
1233 0x005,0x00000c58,
1234 0x006,0x00000ae6,
1235 0x007,0x000000ca,
1236 0x008,0x00000e1c,
1237 0x009,0x000007f0,
1238 0x00a,0x000009d0,
1239 0x00b,0x000001ba,
1240 0x00c,0x00000240,
1241 0x00e,0x00000020,
1242 0x00f,0x00000990,
1243 0x012,0x00000806,
1244 0x014,0x000005ab,
1245 0x015,0x00000f80,
1246 0x016,0x00000020,
1247 0x017,0x00000597,
1248 0x018,0x0000050a,
1249 0x01a,0x00000f80,
1250 0x01b,0x00000f5e,
1251 0x01c,0x00000008,
1252 0x01d,0x00000607,
1253 0x01e,0x000006cc,
1254 0x01f,0x00000000,
1255 0x020,0x000001a5,
1256 0x01f,0x00000001,
1257 0x020,0x00000165,
1258 0x01f,0x00000002,
1259 0x020,0x000000c6,
1260 0x01f,0x00000003,
1261 0x020,0x00000086,
1262 0x01f,0x00000004,
1263 0x020,0x00000046,
1264 0x01f,0x00000005,
1265 0x020,0x000001e6,
1266 0x01f,0x00000006,
1267 0x020,0x000001a6,
1268 0x01f,0x00000007,
1269 0x020,0x00000166,
1270 0x01f,0x00000008,
1271 0x020,0x000000c7,
1272 0x01f,0x00000009,
1273 0x020,0x00000087,
1274 0x01f,0x0000000a,
1275 0x020,0x000000f7,
1276 0x01f,0x0000000b,
1277 0x020,0x000000d7,
1278 0x01f,0x0000000c,
1279 0x020,0x000000b7,
1280 0x01f,0x0000000d,
1281 0x020,0x00000097,
1282 0x01f,0x0000000e,
1283 0x020,0x00000077,
1284 0x01f,0x0000000f,
1285 0x020,0x00000057,
1286 0x01f,0x00000010,
1287 0x020,0x00000037,
1288 0x01f,0x00000011,
1289 0x020,0x000000fb,
1290 0x01f,0x00000012,
1291 0x020,0x000000db,
1292 0x01f,0x00000013,
1293 0x020,0x000000bb,
1294 0x01f,0x00000014,
1295 0x020,0x000000ff,
1296 0x01f,0x00000015,
1297 0x020,0x000000e3,
1298 0x01f,0x00000016,
1299 0x020,0x000000c3,
1300 0x01f,0x00000017,
1301 0x020,0x000000a3,
1302 0x01f,0x00000018,
1303 0x020,0x00000083,
1304 0x01f,0x00000019,
1305 0x020,0x00000063,
1306 0x01f,0x0000001a,
1307 0x020,0x00000043,
1308 0x01f,0x0000001b,
1309 0x020,0x00000023,
1310 0x01f,0x0000001c,
1311 0x020,0x00000003,
1312 0x01f,0x0000001d,
1313 0x020,0x000001e3,
1314 0x01f,0x0000001e,
1315 0x020,0x000001c3,
1316 0x01f,0x0000001f,
1317 0x020,0x000001a3,
1318 0x01f,0x00000020,
1319 0x020,0x00000183,
1320 0x01f,0x00000021,
1321 0x020,0x00000163,
1322 0x01f,0x00000022,
1323 0x020,0x00000143,
1324 0x01f,0x00000023,
1325 0x020,0x00000123,
1326 0x01f,0x00000024,
1327 0x020,0x00000103,
1328 0x023,0x00000203,
1329 0x024,0x00000100,
1330 0x00b,0x000001ba,
1331 0x02c,0x000003d7,
1332 0x02d,0x00000ff0,
1333 0x000,0x00000037,
1334 0x004,0x00000160,
1335 0x007,0x00000080,
1336 0x002,0x0000088d,
1337 0x0fe,0x00000000,
1338 0x0fe,0x00000000,
1339 0x016,0x00000200,
1340 0x016,0x00000380,
1341 0x016,0x00000020,
1342 0x016,0x000001a0,
1343 0x000,0x000000bf,
1344 0x00d,0x0000001f,
1345 0x00d,0x00000c9f,
1346 0x002,0x0000004d,
1347 0x000,0x00000cbf,
1348 0x004,0x00000975,
1349 0x007,0x00000700,
1350 };
1351 static u32 Rtl8192PciERadioB_Array[RadioB_ArrayLength] = {
1352 0x019,0x00000003,
1353 0x000,0x000000bf,
1354 0x001,0x000006e0,
1355 0x002,0x0000004c,
1356 0x003,0x000007f1,
1357 0x004,0x00000975,
1358 0x005,0x00000c58,
1359 0x006,0x00000ae6,
1360 0x007,0x000000ca,
1361 0x008,0x00000e1c,
1362 0x000,0x000000b7,
1363 0x00a,0x00000850,
1364 0x000,0x000000bf,
1365 0x00b,0x000001ba,
1366 0x00c,0x00000240,
1367 0x00e,0x00000020,
1368 0x015,0x00000f80,
1369 0x016,0x00000020,
1370 0x017,0x00000597,
1371 0x018,0x0000050a,
1372 0x01a,0x00000e00,
1373 0x01b,0x00000f5e,
1374 0x01d,0x00000607,
1375 0x01e,0x000006cc,
1376 0x00b,0x000001ba,
1377 0x023,0x00000203,
1378 0x024,0x00000100,
1379 0x000,0x00000037,
1380 0x004,0x00000160,
1381 0x016,0x00000200,
1382 0x016,0x00000380,
1383 0x016,0x00000020,
1384 0x016,0x000001a0,
1385 0x00d,0x00000ccc,
1386 0x000,0x000000bf,
1387 0x002,0x0000004d,
1388 0x000,0x00000cbf,
1389 0x004,0x00000975,
1390 0x007,0x00000700,
1391 };
1392 static u32 Rtl8192PciERadioC_Array[RadioC_ArrayLength] = {
1393 0x0, };
1394 static u32 Rtl8192PciERadioD_Array[RadioD_ArrayLength] = {
1395 0x0, };
1396 #endif
1397
1398 /*************************Define local function prototype**********************/
1399
1400 static u32 phy_FwRFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset);
1401 static void phy_FwRFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32 Data);
1402 /*************************Define local function prototype**********************/
1403 /******************************************************************************
1404 *function: This function read BB parameters from Header file we gen,
1405 * and do register read/write
1406 * input: u32 dwBitMask //taget bit pos in the addr to be modified
1407 * output: none
1408 * return: u32 return the shift bit bit position of the mask
1409 * ****************************************************************************/
1410 static u32 rtl8192_CalculateBitShift(u32 dwBitMask)
1411 {
1412 u32 i;
1413 for (i=0; i<=31; i++)
1414 {
1415 if (((dwBitMask>>i)&0x1) == 1)
1416 break;
1417 }
1418 return i;
1419 }
1420 /******************************************************************************
1421 *function: This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false.
1422 * input: none
1423 * output: none
1424 * return: 0(illegal, false), 1(legal,true)
1425 * ***************************************************************************/
1426 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
1427 {
1428 u8 ret = 1;
1429 struct r8192_priv *priv = ieee80211_priv(dev);
1430 #ifdef RTL8190P
1431 if(priv->rf_type == RF_2T4R)
1432 {
1433 ret= 1;
1434 }
1435 else if (priv->rf_type == RF_1T2R)
1436 {
1437 if(eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
1438 ret = 0;
1439 else if(eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
1440 ret = 1;
1441 }
1442 #else
1443 #ifdef RTL8192E
1444 if (priv->rf_type == RF_2T4R)
1445 ret = 0;
1446 else if (priv->rf_type == RF_1T2R)
1447 {
1448 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
1449 ret = 1;
1450 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
1451 ret = 0;
1452 }
1453 #endif
1454 #endif
1455 return ret;
1456 }
1457 /******************************************************************************
1458 *function: This function set specific bits to BB register
1459 * input: net_device dev
1460 * u32 dwRegAddr //target addr to be modified
1461 * u32 dwBitMask //taget bit pos in the addr to be modified
1462 * u32 dwData //value to be write
1463 * output: none
1464 * return: none
1465 * notice:
1466 * ****************************************************************************/
1467 void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
1468 {
1469
1470 u32 OriginalValue, BitShift, NewValue;
1471
1472 if(dwBitMask!= bMaskDWord)
1473 {//if not "double word" write
1474 OriginalValue = read_nic_dword(dev, dwRegAddr);
1475 BitShift = rtl8192_CalculateBitShift(dwBitMask);
1476 NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
1477 write_nic_dword(dev, dwRegAddr, NewValue);
1478 }else
1479 write_nic_dword(dev, dwRegAddr, dwData);
1480 }
1481 /******************************************************************************
1482 *function: This function reads specific bits from BB register
1483 * input: net_device dev
1484 * u32 dwRegAddr //target addr to be readback
1485 * u32 dwBitMask //taget bit pos in the addr to be readback
1486 * output: none
1487 * return: u32 Data //the readback register value
1488 * notice:
1489 * ****************************************************************************/
1490 u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask)
1491 {
1492 u32 OriginalValue, BitShift;
1493
1494 OriginalValue = read_nic_dword(dev, dwRegAddr);
1495 BitShift = rtl8192_CalculateBitShift(dwBitMask);
1496 return (OriginalValue & dwBitMask) >> BitShift;
1497 }
1498 /******************************************************************************
1499 *function: This function read register from RF chip
1500 * input: net_device dev
1501 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
1502 * u32 Offset //target address to be read
1503 * output: none
1504 * return: u32 readback value
1505 * notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information.
1506 * ****************************************************************************/
1507 static u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset)
1508 {
1509 struct r8192_priv *priv = ieee80211_priv(dev);
1510 u32 ret = 0;
1511 u32 NewOffset = 0;
1512 BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath];
1513 //rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
1514 //make sure RF register offset is correct
1515 Offset &= 0x3f;
1516
1517 //switch page for 8256 RF IC
1518 if (priv->rf_chip == RF_8256)
1519 {
1520 #ifdef RTL8190P
1521 //analog to digital off, for protection
1522 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1523 #else
1524 #ifdef RTL8192E
1525 //analog to digital off, for protection
1526 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1527 #endif
1528 #endif
1529 if (Offset >= 31)
1530 {
1531 priv->RfReg0Value[eRFPath] |= 0x140;
1532 //Switch to Reg_Mode2 for Reg 31-45
1533 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
1534 //modify offset
1535 NewOffset = Offset -30;
1536 }
1537 else if (Offset >= 16)
1538 {
1539 priv->RfReg0Value[eRFPath] |= 0x100;
1540 priv->RfReg0Value[eRFPath] &= (~0x40);
1541 //Switch to Reg_Mode 1 for Reg16-30
1542 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
1543
1544 NewOffset = Offset - 15;
1545 }
1546 else
1547 NewOffset = Offset;
1548 }
1549 else
1550 {
1551 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
1552 NewOffset = Offset;
1553 }
1554 //put desired read addr to LSSI control Register
1555 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
1556 //Issue a posedge trigger
1557 //
1558 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
1559 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
1560
1561
1562 // TODO: we should not delay such a long time. Ask help from SD3
1563 msleep(1);
1564
1565 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
1566
1567
1568 // Switch back to Reg_Mode0;
1569 if(priv->rf_chip == RF_8256)
1570 {
1571 priv->RfReg0Value[eRFPath] &= 0xebf;
1572
1573 rtl8192_setBBreg(
1574 dev,
1575 pPhyReg->rf3wireOffset,
1576 bMaskDWord,
1577 (priv->RfReg0Value[eRFPath] << 16));
1578
1579 #ifdef RTL8190P
1580 if(priv->rf_type == RF_2T4R)
1581 {
1582 //analog to digital on
1583 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
1584 }
1585 else if(priv->rf_type == RF_1T2R)
1586 {
1587 //analog to digital on
1588 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10]
1589 }
1590 #else
1591 #ifdef RTL8192E
1592 //analog to digital on
1593 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
1594 #endif
1595 #endif
1596 }
1597
1598
1599 return ret;
1600
1601 }
1602
1603 /******************************************************************************
1604 *function: This function write data to RF register
1605 * input: net_device dev
1606 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
1607 * u32 Offset //target address to be written
1608 * u32 Data //The new register data to be written
1609 * output: none
1610 * return: none
1611 * notice: For RF8256 only.
1612 ===========================================================
1613 *Reg Mode RegCTL[1] RegCTL[0] Note
1614 * (Reg00[12]) (Reg00[10])
1615 *===========================================================
1616 *Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
1617 *------------------------------------------------------------------
1618 *Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
1619 *------------------------------------------------------------------
1620 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
1621 *------------------------------------------------------------------
1622 * ****************************************************************************/
1623 static void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data)
1624 {
1625 struct r8192_priv *priv = ieee80211_priv(dev);
1626 u32 DataAndAddr = 0, NewOffset = 0;
1627 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
1628
1629 Offset &= 0x3f;
1630 if (priv->rf_chip == RF_8256)
1631 {
1632
1633 #ifdef RTL8190P
1634 //analog to digital off, for protection
1635 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1636 #else
1637 #ifdef RTL8192E
1638 //analog to digital off, for protection
1639 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1640 #endif
1641 #endif
1642
1643 if (Offset >= 31)
1644 {
1645 priv->RfReg0Value[eRFPath] |= 0x140;
1646 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16));
1647 NewOffset = Offset - 30;
1648 }
1649 else if (Offset >= 16)
1650 {
1651 priv->RfReg0Value[eRFPath] |= 0x100;
1652 priv->RfReg0Value[eRFPath] &= (~0x40);
1653 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
1654 NewOffset = Offset - 15;
1655 }
1656 else
1657 NewOffset = Offset;
1658 }
1659 else
1660 {
1661 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
1662 NewOffset = Offset;
1663 }
1664
1665 // Put write addr in [5:0] and write data in [31:16]
1666 DataAndAddr = (Data<<16) | (NewOffset&0x3f);
1667
1668 // Write Operation
1669 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
1670
1671
1672 if(Offset==0x0)
1673 priv->RfReg0Value[eRFPath] = Data;
1674
1675 // Switch back to Reg_Mode0;
1676 if(priv->rf_chip == RF_8256)
1677 {
1678 if(Offset != 0)
1679 {
1680 priv->RfReg0Value[eRFPath] &= 0xebf;
1681 rtl8192_setBBreg(
1682 dev,
1683 pPhyReg->rf3wireOffset,
1684 bMaskDWord,
1685 (priv->RfReg0Value[eRFPath] << 16));
1686 }
1687 #ifdef RTL8190P
1688 if(priv->rf_type == RF_2T4R)
1689 {
1690 //analog to digital on
1691 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
1692 }
1693 else if(priv->rf_type == RF_1T2R)
1694 {
1695 //analog to digital on
1696 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10]
1697 }
1698 #else
1699 #ifdef RTL8192E
1700 //analog to digital on
1701 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
1702 #endif
1703 #endif
1704 }
1705 }
1706
1707 /******************************************************************************
1708 *function: This function set specific bits to RF register
1709 * input: net_device dev
1710 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
1711 * u32 RegAddr //target addr to be modified
1712 * u32 BitMask //taget bit pos in the addr to be modified
1713 * u32 Data //value to be write
1714 * output: none
1715 * return: none
1716 * notice:
1717 * ****************************************************************************/
1718 void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
1719 {
1720 struct r8192_priv *priv = ieee80211_priv(dev);
1721 u32 Original_Value, BitShift, New_Value;
1722 // u8 time = 0;
1723
1724 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1725 return;
1726 #ifdef RTL8192E
1727 if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter)
1728 return;
1729 #endif
1730 //spin_lock_irqsave(&priv->rf_lock, flags);
1731 //down(&priv->rf_sem);
1732
1733 RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
1734 if (priv->Rf_Mode == RF_OP_By_FW)
1735 {
1736 if (BitMask != bMask12Bits) // RF data is 12 bits only
1737 {
1738 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
1739 BitShift = rtl8192_CalculateBitShift(BitMask);
1740 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
1741
1742 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
1743 }else
1744 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
1745 udelay(200);
1746
1747 }
1748 else
1749 {
1750 if (BitMask != bMask12Bits) // RF data is 12 bits only
1751 {
1752 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
1753 BitShift = rtl8192_CalculateBitShift(BitMask);
1754 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
1755
1756 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
1757 }else
1758 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
1759 }
1760 //spin_unlock_irqrestore(&priv->rf_lock, flags);
1761 //up(&priv->rf_sem);
1762 }
1763
1764 /******************************************************************************
1765 *function: This function reads specific bits from RF register
1766 * input: net_device dev
1767 * u32 RegAddr //target addr to be readback
1768 * u32 BitMask //taget bit pos in the addr to be readback
1769 * output: none
1770 * return: u32 Data //the readback register value
1771 * notice:
1772 * ****************************************************************************/
1773 u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
1774 {
1775 u32 Original_Value, Readback_Value, BitShift;
1776 struct r8192_priv *priv = ieee80211_priv(dev);
1777 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1778 return 0;
1779 #ifdef RTL8192E
1780 if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter)
1781 return 0;
1782 #endif
1783 down(&priv->rf_sem);
1784 if (priv->Rf_Mode == RF_OP_By_FW)
1785 {
1786 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
1787 udelay(200);
1788 }
1789 else
1790 {
1791 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
1792
1793 }
1794 BitShift = rtl8192_CalculateBitShift(BitMask);
1795 Readback_Value = (Original_Value & BitMask) >> BitShift;
1796 up(&priv->rf_sem);
1797 // udelay(200);
1798 return Readback_Value;
1799 }
1800
1801 /******************************************************************************
1802 *function: We support firmware to execute RF-R/W.
1803 * input: dev
1804 * output: none
1805 * return: none
1806 * notice:
1807 * ***************************************************************************/
1808 static u32 phy_FwRFSerialRead(
1809 struct net_device* dev,
1810 RF90_RADIO_PATH_E eRFPath,
1811 u32 Offset )
1812 {
1813 u32 Data = 0;
1814 u8 time = 0;
1815 //DbgPrint("FW RF CTRL\n\r");
1816 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
1817 not execute the scheme in the initial step. Otherwise, RF-R/W will waste
1818 much time. This is only for site survey. */
1819 // 1. Read operation need not insert data. bit 0-11
1820 //Data &= bMask12Bits;
1821 // 2. Write RF register address. Bit 12-19
1822 Data |= ((Offset&0xFF)<<12);
1823 // 3. Write RF path. bit 20-21
1824 Data |= ((eRFPath&0x3)<<20);
1825 // 4. Set RF read indicator. bit 22=0
1826 //Data |= 0x00000;
1827 // 5. Trigger Fw to operate the command. bit 31
1828 Data |= 0x80000000;
1829 // 6. We can not execute read operation if bit 31 is 1.
1830 while (read_nic_dword(dev, QPNR)&0x80000000)
1831 {
1832 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
1833 if (time++ < 100)
1834 {
1835 //DbgPrint("FW not finish RF-R Time=%d\n\r", time);
1836 udelay(10);
1837 }
1838 else
1839 break;
1840 }
1841 // 7. Execute read operation.
1842 write_nic_dword(dev, QPNR, Data);
1843 // 8. Check if firmawre send back RF content.
1844 while (read_nic_dword(dev, QPNR)&0x80000000)
1845 {
1846 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
1847 if (time++ < 100)
1848 {
1849 //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
1850 udelay(10);
1851 }
1852 else
1853 return 0;
1854 }
1855 return read_nic_dword(dev, RF_DATA);
1856 }
1857
1858 /******************************************************************************
1859 *function: We support firmware to execute RF-R/W.
1860 * input: dev
1861 * output: none
1862 * return: none
1863 * notice:
1864 * ***************************************************************************/
1865 static void
1866 phy_FwRFSerialWrite(
1867 struct net_device* dev,
1868 RF90_RADIO_PATH_E eRFPath,
1869 u32 Offset,
1870 u32 Data )
1871 {
1872 u8 time = 0;
1873
1874 //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
1875 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
1876 not execute the scheme in the initial step. Otherwise, RF-R/W will waste
1877 much time. This is only for site survey. */
1878
1879 // 1. Set driver write bit and 12 bit data. bit 0-11
1880 //Data &= bMask12Bits; // Done by uper layer.
1881 // 2. Write RF register address. bit 12-19
1882 Data |= ((Offset&0xFF)<<12);
1883 // 3. Write RF path. bit 20-21
1884 Data |= ((eRFPath&0x3)<<20);
1885 // 4. Set RF write indicator. bit 22=1
1886 Data |= 0x400000;
1887 // 5. Trigger Fw to operate the command. bit 31=1
1888 Data |= 0x80000000;
1889
1890 // 6. Write operation. We can not write if bit 31 is 1.
1891 while (read_nic_dword(dev, QPNR)&0x80000000)
1892 {
1893 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
1894 if (time++ < 100)
1895 {
1896 //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
1897 udelay(10);
1898 }
1899 else
1900 break;
1901 }
1902 // 7. No matter check bit. We always force the write. Because FW will
1903 // not accept the command.
1904 write_nic_dword(dev, QPNR, Data);
1905 /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
1906 to finish RF write operation. */
1907 /* 2008/01/17 MH We support delay in firmware side now. */
1908 //delay_us(20);
1909
1910 }
1911
1912
1913 /******************************************************************************
1914 *function: This function read BB parameters from Header file we gen,
1915 * and do register read/write
1916 * input: dev
1917 * output: none
1918 * return: none
1919 * notice: BB parameters may change all the time, so please make
1920 * sure it has been synced with the newest.
1921 * ***************************************************************************/
1922 void rtl8192_phy_configmac(struct net_device* dev)
1923 {
1924 u32 dwArrayLen = 0, i = 0;
1925 u32* pdwArray = NULL;
1926 struct r8192_priv *priv = ieee80211_priv(dev);
1927 #ifdef TO_DO_LIST
1928 if(Adapter->bInHctTest)
1929 {
1930 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_ArrayDTM\n");
1931 dwArrayLen = MACPHY_ArrayLengthDTM;
1932 pdwArray = Rtl819XMACPHY_ArrayDTM;
1933 }
1934 else if(priv->bTXPowerDataReadFromEEPORM)
1935 #endif
1936 if(priv->bTXPowerDataReadFromEEPORM)
1937 {
1938 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
1939 dwArrayLen = MACPHY_Array_PGLength;
1940 pdwArray = Rtl819XMACPHY_Array_PG;
1941
1942 }
1943 else
1944 {
1945 RT_TRACE(COMP_PHY,"Read rtl819XMACPHY_Array\n");
1946 dwArrayLen = MACPHY_ArrayLength;
1947 pdwArray = Rtl819XMACPHY_Array;
1948 }
1949 for(i = 0; i<dwArrayLen; i=i+3){
1950 RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
1951 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
1952 if(pdwArray[i] == 0x318)
1953 {
1954 pdwArray[i+2] = 0x00000800;
1955 //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
1956 // ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
1957 }
1958 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
1959 }
1960 }
1961
1962 /******************************************************************************
1963 *function: This function do dirty work
1964 * input: dev
1965 * output: none
1966 * return: none
1967 * notice: BB parameters may change all the time, so please make
1968 * sure it has been synced with the newest.
1969 * ***************************************************************************/
1970
1971 void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType)
1972 {
1973 int i;
1974 //u8 ArrayLength;
1975 u32* Rtl819XPHY_REGArray_Table = NULL;
1976 u32* Rtl819XAGCTAB_Array_Table = NULL;
1977 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
1978 struct r8192_priv *priv = ieee80211_priv(dev);
1979 #ifdef TO_DO_LIST
1980 u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
1981 if(Adapter->bInHctTest)
1982 {
1983 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
1984 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
1985
1986 if(priv->RF_Type == RF_2T4R)
1987 {
1988 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
1989 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
1990 }
1991 else if (priv->RF_Type == RF_1T2R)
1992 {
1993 PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
1994 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
1995 }
1996 }
1997 else
1998 #endif
1999 {
2000 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
2001 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
2002 if(priv->rf_type == RF_2T4R)
2003 {
2004 PHY_REGArrayLen = PHY_REGArrayLength;
2005 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
2006 }
2007 else if (priv->rf_type == RF_1T2R)
2008 {
2009 PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
2010 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
2011 }
2012 }
2013
2014 if (ConfigType == BaseBand_Config_PHY_REG)
2015 {
2016 for (i=0; i<PHY_REGArrayLen; i+=2)
2017 {
2018 rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
2019 RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]);
2020 }
2021 }
2022 else if (ConfigType == BaseBand_Config_AGC_TAB)
2023 {
2024 for (i=0; i<AGCTAB_ArrayLen; i+=2)
2025 {
2026 rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
2027 RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]);
2028 }
2029 }
2030 }
2031 /******************************************************************************
2032 *function: This function initialize Register definition offset for Radio Path
2033 * A/B/C/D
2034 * input: net_device dev
2035 * output: none
2036 * return: none
2037 * notice: Initialization value here is constant and it should never be changed
2038 * ***************************************************************************/
2039 static void rtl8192_InitBBRFRegDef(struct net_device* dev)
2040 {
2041 struct r8192_priv *priv = ieee80211_priv(dev);
2042 // RF Interface Sowrtware Control
2043 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
2044 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
2045 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
2046 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
2047
2048 // RF Interface Readback Value
2049 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
2050 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
2051 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
2052 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
2053
2054 // RF Interface Output (and Enable)
2055 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
2056 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
2057 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
2058 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
2059
2060 // RF Interface (Output and) Enable
2061 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
2062 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
2063 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
2064 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
2065
2066 //Addr of LSSI. Wirte RF register by driver
2067 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
2068 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
2069 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
2070 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
2071
2072 // RF parameter
2073 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select
2074 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
2075 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
2076 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
2077
2078 // Tx AGC Gain Stage (same for all path. Should we remove this?)
2079 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2080 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2081 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2082 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2083
2084 // Tranceiver A~D HSSI Parameter-1
2085 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1
2086 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1
2087 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1
2088 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1
2089
2090 // Tranceiver A~D HSSI Parameter-2
2091 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2
2092 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2
2093 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2
2094 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1
2095
2096 // RF switch Control
2097 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
2098 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
2099 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
2100 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
2101
2102 // AGC control 1
2103 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
2104 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
2105 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
2106 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
2107
2108 // AGC control 2
2109 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
2110 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
2111 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
2112 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
2113
2114 // RX AFE control 1
2115 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
2116 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
2117 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
2118 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
2119
2120 // RX AFE control 1
2121 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
2122 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
2123 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
2124 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
2125
2126 // Tx AFE control 1
2127 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
2128 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
2129 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
2130 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
2131
2132 // Tx AFE control 2
2133 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
2134 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
2135 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
2136 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
2137
2138 // Tranceiver LSSI Readback
2139 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
2140 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
2141 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
2142 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
2143
2144 }
2145 /******************************************************************************
2146 *function: This function is to write register and then readback to make sure whether BB and RF is OK
2147 * input: net_device dev
2148 * HW90_BLOCK_E CheckBlock
2149 * RF90_RADIO_PATH_E eRFPath //only used when checkblock is HW90_BLOCK_RF
2150 * output: none
2151 * return: return whether BB and RF is ok(0:OK; 1:Fail)
2152 * notice: This function may be removed in the ASIC
2153 * ***************************************************************************/
2154 RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath)
2155 {
2156 //struct r8192_priv *priv = ieee80211_priv(dev);
2157 // BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
2158 RT_STATUS ret = RT_STATUS_SUCCESS;
2159 u32 i, CheckTimes = 4, dwRegRead = 0;
2160 u32 WriteAddr[4];
2161 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
2162 // Initialize register address offset to be checked
2163 WriteAddr[HW90_BLOCK_MAC] = 0x100;
2164 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
2165 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
2166 WriteAddr[HW90_BLOCK_RF] = 0x3;
2167 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock);
2168 for(i=0 ; i < CheckTimes ; i++)
2169 {
2170
2171 //
2172 // Write Data to register and readback
2173 //
2174 switch(CheckBlock)
2175 {
2176 case HW90_BLOCK_MAC:
2177 RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!");
2178 break;
2179
2180 case HW90_BLOCK_PHY0:
2181 case HW90_BLOCK_PHY1:
2182 write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
2183 dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
2184 break;
2185
2186 case HW90_BLOCK_RF:
2187 WriteData[i] &= 0xfff;
2188 rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]);
2189 // TODO: we should not delay for such a long time. Ask SD3
2190 mdelay(10);
2191 dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
2192 mdelay(10);
2193 break;
2194
2195 default:
2196 ret = RT_STATUS_FAILURE;
2197 break;
2198 }
2199
2200
2201 //
2202 // Check whether readback data is correct
2203 //
2204 if(dwRegRead != WriteData[i])
2205 {
2206 RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]);
2207 ret = RT_STATUS_FAILURE;
2208 break;
2209 }
2210 }
2211
2212 return ret;
2213 }
2214
2215
2216 /******************************************************************************
2217 *function: This function initialize BB&RF
2218 * input: net_device dev
2219 * output: none
2220 * return: none
2221 * notice: Initialization value may change all the time, so please make
2222 * sure it has been synced with the newest.
2223 * ***************************************************************************/
2224 static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev)
2225 {
2226 struct r8192_priv *priv = ieee80211_priv(dev);
2227 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
2228 u8 bRegValue = 0, eCheckItem = 0;
2229 u32 dwRegValue = 0;
2230 /**************************************
2231 //<1>Initialize BaseBand
2232 **************************************/
2233
2234 /*--set BB Global Reset--*/
2235 bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET);
2236 write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
2237
2238 /*---set BB reset Active---*/
2239 dwRegValue = read_nic_dword(dev, CPU_GEN);
2240 write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
2241
2242 /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
2243 // TODO: this function should be removed on ASIC , Emily 2007.2.2
2244 for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++)
2245 {
2246 rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path
2247 if(rtStatus != RT_STATUS_SUCCESS)
2248 {
2249 RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1);
2250 return rtStatus;
2251 }
2252 }
2253 /*---- Set CCK and OFDM Block "OFF"----*/
2254 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
2255 /*----BB Register Initilazation----*/
2256 //==m==>Set PHY REG From Header<==m==
2257 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
2258
2259 /*----Set BB reset de-Active----*/
2260 dwRegValue = read_nic_dword(dev, CPU_GEN);
2261 write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
2262
2263 /*----BB AGC table Initialization----*/
2264 //==m==>Set PHY REG From Header<==m==
2265 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
2266
2267 if (priv->card_8192_version > VERSION_8190_BD)
2268 {
2269 if(priv->rf_type == RF_2T4R)
2270 {
2271 // Antenna gain offset from B/C/D to A
2272 dwRegValue = ( priv->AntennaTxPwDiff[2]<<8 |
2273 priv->AntennaTxPwDiff[1]<<4 |
2274 priv->AntennaTxPwDiff[0]);
2275 }
2276 else
2277 dwRegValue = 0x0; //Antenna gain offset doesn't make sense in RF 1T2R.
2278 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
2279 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
2280
2281
2282 //XSTALLCap
2283 #ifdef RTL8190P
2284 dwRegValue = priv->CrystalCap & 0x3; // bit0~1 of crystal cap
2285 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap01, dwRegValue);
2286 dwRegValue = ((priv->CrystalCap & 0xc)>>2); // bit2~3 of crystal cap
2287 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, bXtalCap23, dwRegValue);
2288 #else
2289 #ifdef RTL8192E
2290 dwRegValue = priv->CrystalCap;
2291 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue);
2292 #endif
2293 #endif
2294
2295 }
2296
2297 // Check if the CCK HighPower is turned ON.
2298 // This is used to calculate PWDB.
2299 // priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
2300 return rtStatus;
2301 }
2302 /******************************************************************************
2303 *function: This function initialize BB&RF
2304 * input: net_device dev
2305 * output: none
2306 * return: none
2307 * notice: Initialization value may change all the time, so please make
2308 * sure it has been synced with the newest.
2309 * ***************************************************************************/
2310 RT_STATUS rtl8192_BBConfig(struct net_device* dev)
2311 {
2312 rtl8192_InitBBRFRegDef(dev);
2313 //config BB&RF. As hardCode based initialization has not been well
2314 //implemented, so use file first.FIXME:should implement it for hardcode?
2315 return rtl8192_BB_Config_ParaFile(dev);
2316 }
2317
2318 /******************************************************************************
2319 *function: This function obtains the initialization value of Tx power Level offset
2320 * input: net_device dev
2321 * output: none
2322 * return: none
2323 * ***************************************************************************/
2324 void rtl8192_phy_getTxPower(struct net_device* dev)
2325 {
2326 struct r8192_priv *priv = ieee80211_priv(dev);
2327 #ifdef RTL8190P
2328 priv->MCSTxPowerLevelOriginalOffset[0] =
2329 read_nic_dword(dev, MCS_TXAGC);
2330 priv->MCSTxPowerLevelOriginalOffset[1] =
2331 read_nic_dword(dev, (MCS_TXAGC+4));
2332 priv->CCKTxPowerLevelOriginalOffset =
2333 read_nic_dword(dev, CCK_TXAGC);
2334 #else
2335 #ifdef RTL8192E
2336 priv->MCSTxPowerLevelOriginalOffset[0] =
2337 read_nic_dword(dev, rTxAGC_Rate18_06);
2338 priv->MCSTxPowerLevelOriginalOffset[1] =
2339 read_nic_dword(dev, rTxAGC_Rate54_24);
2340 priv->MCSTxPowerLevelOriginalOffset[2] =
2341 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00);
2342 priv->MCSTxPowerLevelOriginalOffset[3] =
2343 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04);
2344 priv->MCSTxPowerLevelOriginalOffset[4] =
2345 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08);
2346 priv->MCSTxPowerLevelOriginalOffset[5] =
2347 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12);
2348 #endif
2349 #endif
2350
2351 // read rx initial gain
2352 priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1);
2353 priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
2354 priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1);
2355 priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
2356 RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
2357 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
2358 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
2359
2360 // read framesync
2361 priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3);
2362 priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2);
2363 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
2364 rOFDM0_RxDetector3, priv->framesync);
2365 // read SIFS (save the value read fome MACPHY_REG.txt)
2366 priv->SifsTime = read_nic_word(dev, SIFS);
2367 }
2368
2369 /******************************************************************************
2370 *function: This function obtains the initialization value of Tx power Level offset
2371 * input: net_device dev
2372 * output: none
2373 * return: none
2374 * ***************************************************************************/
2375 void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)
2376 {
2377 struct r8192_priv *priv = ieee80211_priv(dev);
2378 u8 powerlevel = 0,powerlevelOFDM24G = 0;
2379 char ant_pwr_diff;
2380 u32 u4RegValue;
2381
2382 if(priv->epromtype == EPROM_93c46)
2383 {
2384 powerlevel = priv->TxPowerLevelCCK[channel-1];
2385 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
2386 }
2387 else if(priv->epromtype == EPROM_93c56)
2388 {
2389 if(priv->rf_type == RF_1T2R)
2390 {
2391 powerlevel = priv->TxPowerLevelCCK_C[channel-1];
2392 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
2393 }
2394 else if(priv->rf_type == RF_2T4R)
2395 {
2396 // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-C Tx
2397 // Power must be calculated by the antenna diff.
2398 // So we have to rewrite Antenna gain offset register here.
2399 powerlevel = priv->TxPowerLevelCCK_A[channel-1];
2400 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
2401
2402 ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
2403 -priv->TxPowerLevelOFDM24G_A[channel-1];
2404 ant_pwr_diff &= 0xf;
2405 //DbgPrint(" ant_pwr_diff = 0x%x", (u8)(ant_pwr_diff));
2406 priv->RF_C_TxPwDiff = ant_pwr_diff;
2407
2408 priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care
2409 priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);// RF-C
2410 priv->AntennaTxPwDiff[0] = 0;// RF-B, don't care
2411
2412 // Antenna gain offset from B/C/D to A
2413 u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 |
2414 priv->AntennaTxPwDiff[1]<<4 |
2415 priv->AntennaTxPwDiff[0]);
2416
2417 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
2418 (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
2419 }
2420 }
2421 #ifdef TODO
2422 //
2423 // CCX 2 S31, AP control of client transmit power:
2424 // 1. We shall not exceed Cell Power Limit as possible as we can.
2425 // 2. Tolerance is +/- 5dB.
2426 // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
2427 //
2428 // TODO:
2429 // 1. 802.11h power contraint
2430 //
2431 // 071011, by rcnjko.
2432 //
2433 if( pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
2434 pMgntInfo->bWithCcxCellPwr &&
2435 channel == pMgntInfo->dot11CurrentChannelNumber)
2436 {
2437 u8 CckCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pMgntInfo->CcxCellPwr);
2438 u8 LegacyOfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pMgntInfo->CcxCellPwr);
2439 u8 OfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pMgntInfo->CcxCellPwr);
2440
2441 RT_TRACE(COMP_TXAGC, DBG_LOUD,
2442 ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2443 pMgntInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
2444 RT_TRACE(COMP_TXAGC, DBG_LOUD,
2445 ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2446 channel, powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2447
2448 // CCK
2449 if(powerlevel > CckCellPwrIdx)
2450 powerlevel = CckCellPwrIdx;
2451 // Legacy OFDM, HT OFDM
2452 if(powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff > OfdmCellPwrIdx)
2453 {
2454 if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0)
2455 {
2456 powerlevelOFDM24G = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff;
2457 }
2458 else
2459 {
2460 LegacyOfdmCellPwrIdx = 0;
2461 }
2462 }
2463
2464 RT_TRACE(COMP_TXAGC, DBG_LOUD,
2465 ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
2466 powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2467 }
2468
2469 pHalData->CurrentCckTxPwrIdx = powerlevel;
2470 pHalData->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
2471 #endif
2472 switch(priv->rf_chip)
2473 {
2474 case RF_8225:
2475 // PHY_SetRF8225CckTxPower(Adapter, powerlevel);
2476 // PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
2477 break;
2478 case RF_8256:
2479 PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement
2480 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
2481 break;
2482 case RF_8258:
2483 break;
2484 default:
2485 RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n", __FUNCTION__);
2486 break;
2487 }
2488 }
2489
2490 /******************************************************************************
2491 *function: This function check Rf chip to do RF config
2492 * input: net_device dev
2493 * output: none
2494 * return: only 8256 is supported
2495 * ***************************************************************************/
2496 RT_STATUS rtl8192_phy_RFConfig(struct net_device* dev)
2497 {
2498 struct r8192_priv *priv = ieee80211_priv(dev);
2499 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
2500 switch(priv->rf_chip)
2501 {
2502 case RF_8225:
2503 // rtStatus = PHY_RF8225_Config(Adapter);
2504 break;
2505 case RF_8256:
2506 rtStatus = PHY_RF8256_Config(dev);
2507 break;
2508
2509 case RF_8258:
2510 break;
2511 case RF_PSEUDO_11N:
2512 //rtStatus = PHY_RF8225_Config(Adapter);
2513 break;
2514
2515 default:
2516 RT_TRACE(COMP_ERR, "error chip id\n");
2517 break;
2518 }
2519 return rtStatus;
2520 }
2521
2522 /******************************************************************************
2523 *function: This function update Initial gain
2524 * input: net_device dev
2525 * output: none
2526 * return: As Windows has not implemented this, wait for complement
2527 * ***************************************************************************/
2528 void rtl8192_phy_updateInitGain(struct net_device* dev)
2529 {
2530 }
2531
2532 /******************************************************************************
2533 *function: This function read RF parameters from general head file, and do RF 3-wire
2534 * input: net_device dev
2535 * output: none
2536 * return: return code show if RF configuration is successful(0:pass, 1:fail)
2537 * Note: Delay may be required for RF configuration
2538 * ***************************************************************************/
2539 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
2540 {
2541
2542 int i;
2543 //u32* pRFArray;
2544 u8 ret = 0;
2545
2546 switch(eRFPath){
2547 case RF90_PATH_A:
2548 for(i = 0;i<RadioA_ArrayLength; i=i+2){
2549
2550 if(Rtl819XRadioA_Array[i] == 0xfe){
2551 msleep(100);
2552 continue;
2553 }
2554 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array[i], bMask12Bits, Rtl819XRadioA_Array[i+1]);
2555 //msleep(1);
2556
2557 }
2558 break;
2559 case RF90_PATH_B:
2560 for(i = 0;i<RadioB_ArrayLength; i=i+2){
2561
2562 if(Rtl819XRadioB_Array[i] == 0xfe){
2563 msleep(100);
2564 continue;
2565 }
2566 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array[i], bMask12Bits, Rtl819XRadioB_Array[i+1]);
2567 //msleep(1);
2568
2569 }
2570 break;
2571 case RF90_PATH_C:
2572 for(i = 0;i<RadioC_ArrayLength; i=i+2){
2573
2574 if(Rtl819XRadioC_Array[i] == 0xfe){
2575 msleep(100);
2576 continue;
2577 }
2578 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioC_Array[i], bMask12Bits, Rtl819XRadioC_Array[i+1]);
2579 //msleep(1);
2580
2581 }
2582 break;
2583 case RF90_PATH_D:
2584 for(i = 0;i<RadioD_ArrayLength; i=i+2){
2585
2586 if(Rtl819XRadioD_Array[i] == 0xfe){
2587 msleep(100);
2588 continue;
2589 }
2590 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioD_Array[i], bMask12Bits, Rtl819XRadioD_Array[i+1]);
2591 //msleep(1);
2592
2593 }
2594 break;
2595 default:
2596 break;
2597 }
2598
2599 return ret;
2600
2601 }
2602 /******************************************************************************
2603 *function: This function set Tx Power of the channel
2604 * input: struct net_device *dev
2605 * u8 channel
2606 * output: none
2607 * return: none
2608 * Note:
2609 * ***************************************************************************/
2610 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
2611 {
2612 struct r8192_priv *priv = ieee80211_priv(dev);
2613 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
2614 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
2615
2616 switch(priv->rf_chip)
2617 {
2618 case RF_8225:
2619 #ifdef TO_DO_LIST
2620 PHY_SetRF8225CckTxPower(Adapter, powerlevel);
2621 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
2622 #endif
2623 break;
2624
2625 case RF_8256:
2626 PHY_SetRF8256CCKTxPower(dev, powerlevel);
2627 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
2628 break;
2629
2630 case RF_8258:
2631 break;
2632 default:
2633 RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n");
2634 break;
2635 }
2636 }
2637 /****************************************************************************************
2638 *function: This function set command table variable(struct SwChnlCmd).
2639 * input: SwChnlCmd* CmdTable //table to be set.
2640 * u32 CmdTableIdx //variable index in table to be set
2641 * u32 CmdTableSz //table size.
2642 * SwChnlCmdID CmdID //command ID to set.
2643 * u32 Para1
2644 * u32 Para2
2645 * u32 msDelay
2646 * output:
2647 * return: true if finished, false otherwise
2648 * Note:
2649 * ************************************************************************************/
2650 static u8 rtl8192_phy_SetSwChnlCmdArray(
2651 SwChnlCmd* CmdTable,
2652 u32 CmdTableIdx,
2653 u32 CmdTableSz,
2654 SwChnlCmdID CmdID,
2655 u32 Para1,
2656 u32 Para2,
2657 u32 msDelay
2658 )
2659 {
2660 SwChnlCmd* pCmd;
2661
2662 if(CmdTable == NULL)
2663 {
2664 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n");
2665 return false;
2666 }
2667 if(CmdTableIdx >= CmdTableSz)
2668 {
2669 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
2670 CmdTableIdx, CmdTableSz);
2671 return false;
2672 }
2673
2674 pCmd = CmdTable + CmdTableIdx;
2675 pCmd->CmdID = CmdID;
2676 pCmd->Para1 = Para1;
2677 pCmd->Para2 = Para2;
2678 pCmd->msDelay = msDelay;
2679
2680 return true;
2681 }
2682 /******************************************************************************
2683 *function: This function set channel step by step
2684 * input: struct net_device *dev
2685 * u8 channel
2686 * u8* stage //3 stages
2687 * u8* step //
2688 * u32* delay //whether need to delay
2689 * output: store new stage, step and delay for next step(combine with function above)
2690 * return: true if finished, false otherwise
2691 * Note: Wait for simpler function to replace it //wb
2692 * ***************************************************************************/
2693 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay)
2694 {
2695 struct r8192_priv *priv = ieee80211_priv(dev);
2696 // PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
2697 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
2698 u32 PreCommonCmdCnt;
2699 SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
2700 u32 PostCommonCmdCnt;
2701 SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
2702 u32 RfDependCmdCnt;
2703 SwChnlCmd *CurrentCmd = NULL;
2704 //RF90_RADIO_PATH_E eRFPath;
2705 u8 eRFPath;
2706 // u32 RfRetVal;
2707 // u8 RetryCnt;
2708
2709 RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel);
2710 // RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
2711
2712 #ifdef ENABLE_DOT11D
2713 if (!IsLegalChannel(priv->ieee80211, channel))
2714 {
2715 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
2716 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
2717 }
2718 #endif
2719
2720 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
2721 //for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++)
2722 {
2723 //if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
2724 // return false;
2725 // <1> Fill up pre common command.
2726 PreCommonCmdCnt = 0;
2727 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
2728 CmdID_SetTxPowerLevel, 0, 0, 0);
2729 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
2730 CmdID_End, 0, 0, 0);
2731
2732 // <2> Fill up post common command.
2733 PostCommonCmdCnt = 0;
2734
2735 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
2736 CmdID_End, 0, 0, 0);
2737
2738 // <3> Fill up RF dependent command.
2739 RfDependCmdCnt = 0;
2740 switch( priv->rf_chip )
2741 {
2742 case RF_8225:
2743 if (!(channel >= 1 && channel <= 14))
2744 {
2745 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel);
2746 return false;
2747 }
2748 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2749 CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10);
2750 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2751 CmdID_End, 0, 0, 0);
2752 break;
2753
2754 case RF_8256:
2755 // TEST!! This is not the table for 8256!!
2756 if (!(channel >= 1 && channel <= 14))
2757 {
2758 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel);
2759 return false;
2760 }
2761 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2762 CmdID_RF_WriteReg, rZebra1_Channel, channel, 10);
2763 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2764 CmdID_End, 0, 0, 0);
2765 break;
2766
2767 case RF_8258:
2768 break;
2769
2770 default:
2771 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
2772 return false;
2773 break;
2774 }
2775
2776
2777 do{
2778 switch(*stage)
2779 {
2780 case 0:
2781 CurrentCmd=&PreCommonCmd[*step];
2782 break;
2783 case 1:
2784 CurrentCmd=&RfDependCmd[*step];
2785 break;
2786 case 2:
2787 CurrentCmd=&PostCommonCmd[*step];
2788 break;
2789 }
2790
2791 if(CurrentCmd->CmdID==CmdID_End)
2792 {
2793 if((*stage)==2)
2794 {
2795 return true;
2796 }
2797 else
2798 {
2799 (*stage)++;
2800 (*step)=0;
2801 continue;
2802 }
2803 }
2804
2805 switch(CurrentCmd->CmdID)
2806 {
2807 case CmdID_SetTxPowerLevel:
2808 if(priv->card_8192_version > (u8)VERSION_8190_BD) //xiong: consider it later!
2809 rtl8192_SetTxPowerLevel(dev,channel);
2810 break;
2811 case CmdID_WritePortUlong:
2812 write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
2813 break;
2814 case CmdID_WritePortUshort:
2815 write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
2816 break;
2817 case CmdID_WritePortUchar:
2818 write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
2819 break;
2820 case CmdID_RF_WriteReg:
2821 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
2822 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7);
2823 break;
2824 default:
2825 break;
2826 }
2827
2828 break;
2829 }while(true);
2830 }/*for(Number of RF paths)*/
2831
2832 (*delay)=CurrentCmd->msDelay;
2833 (*step)++;
2834 return false;
2835 }
2836
2837 /******************************************************************************
2838 *function: This function does acturally set channel work
2839 * input: struct net_device *dev
2840 * u8 channel
2841 * output: none
2842 * return: noin
2843 * Note: We should not call this function directly
2844 * ***************************************************************************/
2845 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
2846 {
2847 struct r8192_priv *priv = ieee80211_priv(dev);
2848 u32 delay = 0;
2849
2850 while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
2851 {
2852 if(delay>0)
2853 msleep(delay);//or mdelay? need further consideration
2854 if(!priv->up)
2855 break;
2856 }
2857 }
2858 /******************************************************************************
2859 *function: Callback routine of the work item for switch channel.
2860 * input:
2861 *
2862 * output: none
2863 * return: noin
2864 * ***************************************************************************/
2865 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
2866 {
2867
2868 struct r8192_priv *priv = ieee80211_priv(dev);
2869
2870 RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
2871
2872 RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __FUNCTION__, priv->chan, priv);
2873
2874 rtl8192_phy_FinishSwChnlNow(dev , priv->chan);
2875
2876 RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
2877 }
2878
2879 /******************************************************************************
2880 *function: This function scheduled actural workitem to set channel
2881 * input: net_device dev
2882 * u8 channel //channel to set
2883 * output: none
2884 * return: return code show if workitem is scheduled(1:pass, 0:fail)
2885 * Note: Delay may be required for RF configuration
2886 * ***************************************************************************/
2887 u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
2888 {
2889 struct r8192_priv *priv = ieee80211_priv(dev);
2890 RT_TRACE(COMP_PHY, "=====>%s()\n", __FUNCTION__);
2891 if(!priv->up)
2892 return false;
2893 if(priv->SwChnlInProgress)
2894 return false;
2895
2896 // if(pHalData->SetBWModeInProgress)
2897 // return;
2898
2899 //--------------------------------------------
2900 switch(priv->ieee80211->mode)
2901 {
2902 case WIRELESS_MODE_A:
2903 case WIRELESS_MODE_N_5G:
2904 if (channel<=14){
2905 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
2906 return false;
2907 }
2908 break;
2909 case WIRELESS_MODE_B:
2910 if (channel>14){
2911 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
2912 return false;
2913 }
2914 break;
2915 case WIRELESS_MODE_G:
2916 case WIRELESS_MODE_N_24G:
2917 if (channel>14){
2918 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
2919 return false;
2920 }
2921 break;
2922 }
2923 //--------------------------------------------
2924
2925 priv->SwChnlInProgress = true;
2926 if(channel == 0)
2927 channel = 1;
2928
2929 priv->chan=channel;
2930
2931 priv->SwChnlStage=0;
2932 priv->SwChnlStep=0;
2933 // schedule_work(&(priv->SwChnlWorkItem));
2934 // rtl8192_SwChnl_WorkItem(dev);
2935 if(priv->up) {
2936 // queue_work(priv->priv_wq,&(priv->SwChnlWorkItem));
2937 rtl8192_SwChnl_WorkItem(dev);
2938 }
2939 priv->SwChnlInProgress = false;
2940 return true;
2941 }
2942
2943 static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev )
2944 {
2945 struct r8192_priv *priv = ieee80211_priv(dev);
2946
2947 switch(priv->CurrentChannelBW)
2948 {
2949 /* 20 MHz channel*/
2950 case HT_CHANNEL_WIDTH_20:
2951 //added by vivi, cck,tx power track, 20080703
2952 priv->CCKPresentAttentuation =
2953 priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference;
2954
2955 if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
2956 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
2957 if(priv->CCKPresentAttentuation < 0)
2958 priv->CCKPresentAttentuation = 0;
2959
2960 RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
2961
2962 if(priv->ieee80211->current_network.channel== 14 && !priv->bcck_in_ch14)
2963 {
2964 priv->bcck_in_ch14 = TRUE;
2965 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2966 }
2967 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
2968 {
2969 priv->bcck_in_ch14 = FALSE;
2970 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2971 }
2972 else
2973 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2974 break;
2975
2976 /* 40 MHz channel*/
2977 case HT_CHANNEL_WIDTH_20_40:
2978 //added by vivi, cck,tx power track, 20080703
2979 priv->CCKPresentAttentuation =
2980 priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference;
2981
2982 RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
2983 if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
2984 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
2985 if(priv->CCKPresentAttentuation < 0)
2986 priv->CCKPresentAttentuation = 0;
2987
2988 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
2989 {
2990 priv->bcck_in_ch14 = TRUE;
2991 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2992 }
2993 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
2994 {
2995 priv->bcck_in_ch14 = FALSE;
2996 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2997 }
2998 else
2999 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
3000 break;
3001 }
3002 }
3003
3004 #ifndef RTL8190P
3005 static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
3006 {
3007 struct r8192_priv *priv = ieee80211_priv(dev);
3008
3009 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
3010 priv->bcck_in_ch14 = TRUE;
3011 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
3012 priv->bcck_in_ch14 = FALSE;
3013
3014 //write to default index and tx power track will be done in dm.
3015 switch(priv->CurrentChannelBW)
3016 {
3017 /* 20 MHz channel*/
3018 case HT_CHANNEL_WIDTH_20:
3019 if(priv->Record_CCK_20Mindex == 0)
3020 priv->Record_CCK_20Mindex = 6; //set default value.
3021 priv->CCK_index = priv->Record_CCK_20Mindex;//6;
3022 RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(),CCK_index = %d\n", priv->CCK_index);
3023 break;
3024
3025 /* 40 MHz channel*/
3026 case HT_CHANNEL_WIDTH_20_40:
3027 priv->CCK_index = priv->Record_CCK_40Mindex;//0;
3028 RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n", priv->CCK_index);
3029 break;
3030 }
3031 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
3032 }
3033 #endif
3034
3035 static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
3036 {
3037 #ifdef RTL8192E
3038 struct r8192_priv *priv = ieee80211_priv(dev);
3039 #endif
3040
3041 #ifdef RTL8190P
3042 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
3043 #else
3044 //if(pHalData->bDcut == TRUE)
3045 if(priv->IC_Cut >= IC_VersionCut_D)
3046 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
3047 else
3048 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev);
3049 #endif
3050 }
3051
3052
3053 //
3054 /******************************************************************************
3055 *function: Callback routine of the work item for set bandwidth mode.
3056 * input: struct net_device *dev
3057 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
3058 * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
3059 * output: none
3060 * return: none
3061 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
3062 * test whether current work in the queue or not.//do I?
3063 * ***************************************************************************/
3064 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
3065 {
3066
3067 struct r8192_priv *priv = ieee80211_priv(dev);
3068 u8 regBwOpMode;
3069
3070 RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n",
3071 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")
3072
3073
3074 if(priv->rf_chip== RF_PSEUDO_11N)
3075 {
3076 priv->SetBWModeInProgress= false;
3077 return;
3078 }
3079 if(!priv->up)
3080 {
3081 priv->SetBWModeInProgress= false;
3082 return;
3083 }
3084 //<1>Set MAC register
3085 regBwOpMode = read_nic_byte(dev, BW_OPMODE);
3086
3087 switch(priv->CurrentChannelBW)
3088 {
3089 case HT_CHANNEL_WIDTH_20:
3090 regBwOpMode |= BW_OPMODE_20MHZ;
3091 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3092 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3093 break;
3094
3095 case HT_CHANNEL_WIDTH_20_40:
3096 regBwOpMode &= ~BW_OPMODE_20MHZ;
3097 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3098 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3099 break;
3100
3101 default:
3102 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
3103 break;
3104 }
3105
3106 //<2>Set PHY related register
3107 switch(priv->CurrentChannelBW)
3108 {
3109 case HT_CHANNEL_WIDTH_20:
3110 // Add by Vivi 20071119
3111 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
3112 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
3113 // rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
3114
3115 // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
3116 // write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
3117 // write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
3118 // write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
3119 if(!priv->btxpower_tracking)
3120 {
3121 write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
3122 write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
3123 write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
3124 }
3125 else
3126 CCK_Tx_Power_Track_BW_Switch(dev);
3127
3128 #ifdef RTL8190P
3129 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1);
3130 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x44); // 0xc30 is for 8190 only, Emily
3131 #else
3132 #ifdef RTL8192E
3133 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
3134 #endif
3135 #endif
3136
3137 break;
3138 case HT_CHANNEL_WIDTH_20_40:
3139 // Add by Vivi 20071119
3140 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
3141 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
3142 //rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3143 //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
3144 //rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3145
3146 // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
3147 //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
3148 //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
3149 //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
3150 if(!priv->btxpower_tracking)
3151 {
3152 write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
3153 write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
3154 write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
3155 }
3156 else
3157 CCK_Tx_Power_Track_BW_Switch(dev);
3158
3159 // Set Control channel to upper or lower. These settings are required only for 40MHz
3160 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3161 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3162
3163
3164 #ifdef RTL8190P
3165 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0);
3166 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x42); // 0xc30 is for 8190 only, Emily
3167
3168 // Set whether CCK should be sent in upper or lower channel. Suggest by YN. 20071207
3169 // It is set in Tx descriptor for 8192x series
3170 if(priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
3171 {
3172 rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x01);
3173 }else if(priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
3174 {
3175 rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x02);
3176 }
3177
3178 #else
3179 #ifdef RTL8192E
3180 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
3181 #endif
3182 #endif
3183 break;
3184 default:
3185 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW);
3186 break;
3187
3188 }
3189 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
3190
3191 #if 1
3192 //<3>Set RF related register
3193 switch( priv->rf_chip )
3194 {
3195 case RF_8225:
3196 #ifdef TO_DO_LIST
3197 PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
3198 #endif
3199 break;
3200
3201 case RF_8256:
3202 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
3203 break;
3204
3205 case RF_8258:
3206 // PHY_SetRF8258Bandwidth();
3207 break;
3208
3209 case RF_PSEUDO_11N:
3210 // Do Nothing
3211 break;
3212
3213 default:
3214 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
3215 break;
3216 }
3217 #endif
3218 atomic_dec(&(priv->ieee80211->atm_swbw));
3219 priv->SetBWModeInProgress= false;
3220
3221 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()");
3222 }
3223
3224 /******************************************************************************
3225 *function: This function schedules bandwith switch work.
3226 * input: struct net_device *dev
3227 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
3228 * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
3229 * output: none
3230 * return: none
3231 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
3232 * test whether current work in the queue or not.//do I?
3233 * ***************************************************************************/
3234 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
3235 {
3236 struct r8192_priv *priv = ieee80211_priv(dev);
3237
3238
3239 if(priv->SetBWModeInProgress)
3240 return;
3241
3242 atomic_inc(&(priv->ieee80211->atm_swbw));
3243 priv->SetBWModeInProgress= true;
3244
3245 priv->CurrentChannelBW = Bandwidth;
3246
3247 if(Offset==HT_EXTCHNL_OFFSET_LOWER)
3248 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
3249 else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
3250 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
3251 else
3252 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
3253
3254 //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem));
3255 // schedule_work(&(priv->SetBWModeWorkItem));
3256 rtl8192_SetBWModeWorkItem(dev);
3257
3258 }
3259
3260
3261 void InitialGain819xPci(struct net_device *dev, u8 Operation)
3262 {
3263 #define SCAN_RX_INITIAL_GAIN 0x17
3264 #define POWER_DETECTION_TH 0x08
3265 struct r8192_priv *priv = ieee80211_priv(dev);
3266 u32 BitMask;
3267 u8 initial_gain;
3268
3269 if(priv->up)
3270 {
3271 switch(Operation)
3272 {
3273 case IG_Backup:
3274 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
3275 initial_gain = SCAN_RX_INITIAL_GAIN;//pHalData->DefaultInitialGain[0];//
3276 BitMask = bMaskByte0;
3277 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3278 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3279 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
3280 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
3281 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
3282 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
3283 BitMask = bMaskByte2;
3284 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
3285
3286 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
3287 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
3288 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
3289 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
3290 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
3291
3292 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
3293 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
3294 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
3295 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
3296 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
3297 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
3298 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
3299 break;
3300 case IG_Restore:
3301 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
3302 BitMask = 0x7f; //Bit0~ Bit6
3303 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3304 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3305
3306 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
3307 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
3308 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
3309 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
3310 BitMask = bMaskByte2;
3311 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
3312
3313 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
3314 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
3315 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
3316 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
3317 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
3318
3319 rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);
3320
3321
3322 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3323 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON
3324 break;
3325 default:
3326 RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
3327 break;
3328 }
3329 }
3330 }
3331
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