?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[SCSI] mvsas: misc improvements
[linux-2.6.git] / drivers / scsi / mvsas / mv_94xx.c
blob1276e494b868bb0d6202e0aa3490c98c6a495270
1 /*
2 * Marvell 88SE94xx hardware specific
3 *
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
7 *
8 * This file is licensed under GPLv2.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; version 2 of the
13 * License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
23 * USA
24 */
25
26 #include "mv_sas.h"
27 #include "mv_94xx.h"
28 #include "mv_chips.h"
29
30 static void mvs_94xx_detect_porttype(struct mvs_info *mvi, int i)
31 {
32 u32 reg;
33 struct mvs_phy *phy = &mvi->phy[i];
34 u32 phy_status;
35
36 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE3);
37 reg = mvs_read_port_vsr_data(mvi, i);
38 phy_status = ((reg & 0x3f0000) >> 16) & 0xff;
39 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
40 switch (phy_status) {
41 case 0x10:
42 phy->phy_type |= PORT_TYPE_SAS;
43 break;
44 case 0x1d:
45 default:
46 phy->phy_type |= PORT_TYPE_SATA;
47 break;
48 }
49 }
50
51 void set_phy_tuning(struct mvs_info *mvi, int phy_id,
52 struct phy_tuning phy_tuning)
53 {
54 u32 tmp, setting_0 = 0, setting_1 = 0;
55 u8 i;
56
57 /* Remap information for B0 chip:
58 *
59 * R0Ch -> R118h[15:0] (Adapted DFE F3 - F5 coefficient)
60 * R0Dh -> R118h[31:16] (Generation 1 Setting 0)
61 * R0Eh -> R11Ch[15:0] (Generation 1 Setting 1)
62 * R0Fh -> R11Ch[31:16] (Generation 2 Setting 0)
63 * R10h -> R120h[15:0] (Generation 2 Setting 1)
64 * R11h -> R120h[31:16] (Generation 3 Setting 0)
65 * R12h -> R124h[15:0] (Generation 3 Setting 1)
66 * R13h -> R124h[31:16] (Generation 4 Setting 0 (Reserved))
67 */
68
69 /* A0 has a different set of registers */
70 if (mvi->pdev->revision == VANIR_A0_REV)
71 return;
72
73 for (i = 0; i < 3; i++) {
74 /* loop 3 times, set Gen 1, Gen 2, Gen 3 */
75 switch (i) {
76 case 0:
77 setting_0 = GENERATION_1_SETTING;
78 setting_1 = GENERATION_1_2_SETTING;
79 break;
80 case 1:
81 setting_0 = GENERATION_1_2_SETTING;
82 setting_1 = GENERATION_2_3_SETTING;
83 break;
84 case 2:
85 setting_0 = GENERATION_2_3_SETTING;
86 setting_1 = GENERATION_3_4_SETTING;
87 break;
88 }
89
90 /* Set:
91 *
92 * Transmitter Emphasis Enable
93 * Transmitter Emphasis Amplitude
94 * Transmitter Amplitude
95 */
96 mvs_write_port_vsr_addr(mvi, phy_id, setting_0);
97 tmp = mvs_read_port_vsr_data(mvi, phy_id);
98 tmp &= ~(0xFBE << 16);
99 tmp |= (((phy_tuning.trans_emp_en << 11) |
100 (phy_tuning.trans_emp_amp << 7) |
101 (phy_tuning.trans_amp << 1)) << 16);
102 mvs_write_port_vsr_data(mvi, phy_id, tmp);
103
104 /* Set Transmitter Amplitude Adjust */
105 mvs_write_port_vsr_addr(mvi, phy_id, setting_1);
106 tmp = mvs_read_port_vsr_data(mvi, phy_id);
107 tmp &= ~(0xC000);
108 tmp |= (phy_tuning.trans_amp_adj << 14);
109 mvs_write_port_vsr_data(mvi, phy_id, tmp);
110 }
111 }
112
113 void set_phy_ffe_tuning(struct mvs_info *mvi, int phy_id,
114 struct ffe_control ffe)
115 {
116 u32 tmp;
117
118 /* Don't run this if A0/B0 */
119 if ((mvi->pdev->revision == VANIR_A0_REV)
120 || (mvi->pdev->revision == VANIR_B0_REV))
121 return;
122
123 /* FFE Resistor and Capacitor */
124 /* R10Ch DFE Resolution Control/Squelch and FFE Setting
125 *
126 * FFE_FORCE [7]
127 * FFE_RES_SEL [6:4]
128 * FFE_CAP_SEL [3:0]
129 */
130 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_FFE_CONTROL);
131 tmp = mvs_read_port_vsr_data(mvi, phy_id);
132 tmp &= ~0xFF;
133
134 /* Read from HBA_Info_Page */
135 tmp |= ((0x1 << 7) |
136 (ffe.ffe_rss_sel << 4) |
137 (ffe.ffe_cap_sel << 0));
138
139 mvs_write_port_vsr_data(mvi, phy_id, tmp);
140
141 /* R064h PHY Mode Register 1
142 *
143 * DFE_DIS 18
144 */
145 mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL);
146 tmp = mvs_read_port_vsr_data(mvi, phy_id);
147 tmp &= ~0x40001;
148 /* Hard coding */
149 /* No defines in HBA_Info_Page */
150 tmp |= (0 << 18);
151 mvs_write_port_vsr_data(mvi, phy_id, tmp);
152
153 /* R110h DFE F0-F1 Coefficient Control/DFE Update Control
154 *
155 * DFE_UPDATE_EN [11:6]
156 * DFE_FX_FORCE [5:0]
157 */
158 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_DFE_UPDATE_CRTL);
159 tmp = mvs_read_port_vsr_data(mvi, phy_id);
160 tmp &= ~0xFFF;
161 /* Hard coding */
162 /* No defines in HBA_Info_Page */
163 tmp |= ((0x3F << 6) | (0x0 << 0));
164 mvs_write_port_vsr_data(mvi, phy_id, tmp);
165
166 /* R1A0h Interface and Digital Reference Clock Control/Reserved_50h
167 *
168 * FFE_TRAIN_EN 3
169 */
170 mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL);
171 tmp = mvs_read_port_vsr_data(mvi, phy_id);
172 tmp &= ~0x8;
173 /* Hard coding */
174 /* No defines in HBA_Info_Page */
175 tmp |= (0 << 3);
176 mvs_write_port_vsr_data(mvi, phy_id, tmp);
177 }
178
179 /*Notice: this function must be called when phy is disabled*/
180 void set_phy_rate(struct mvs_info *mvi, int phy_id, u8 rate)
181 {
182 union reg_phy_cfg phy_cfg, phy_cfg_tmp;
183 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
184 phy_cfg_tmp.v = mvs_read_port_vsr_data(mvi, phy_id);
185 phy_cfg.v = 0;
186 phy_cfg.u.disable_phy = phy_cfg_tmp.u.disable_phy;
187 phy_cfg.u.sas_support = 1;
188 phy_cfg.u.sata_support = 1;
189 phy_cfg.u.sata_host_mode = 1;
190
191 switch (rate) {
192 case 0x0:
193 /* support 1.5 Gbps */
194 phy_cfg.u.speed_support = 1;
195 phy_cfg.u.snw_3_support = 0;
196 phy_cfg.u.tx_lnk_parity = 1;
197 phy_cfg.u.tx_spt_phs_lnk_rate = 0x30;
198 break;
199 case 0x1:
200
201 /* support 1.5, 3.0 Gbps */
202 phy_cfg.u.speed_support = 3;
203 phy_cfg.u.tx_spt_phs_lnk_rate = 0x3c;
204 phy_cfg.u.tx_lgcl_lnk_rate = 0x08;
205 break;
206 case 0x2:
207 default:
208 /* support 1.5, 3.0, 6.0 Gbps */
209 phy_cfg.u.speed_support = 7;
210 phy_cfg.u.snw_3_support = 1;
211 phy_cfg.u.tx_lnk_parity = 1;
212 phy_cfg.u.tx_spt_phs_lnk_rate = 0x3f;
213 phy_cfg.u.tx_lgcl_lnk_rate = 0x09;
214 break;
215 }
216 mvs_write_port_vsr_data(mvi, phy_id, phy_cfg.v);
217 }
218
219 static void __devinit
220 mvs_94xx_config_reg_from_hba(struct mvs_info *mvi, int phy_id)
221 {
222 u32 temp;
223 temp = (u32)(*(u32 *)&mvi->hba_info_param.phy_tuning[phy_id]);
224 if (temp == 0xFFFFFFFFL) {
225 mvi->hba_info_param.phy_tuning[phy_id].trans_emp_amp = 0x6;
226 mvi->hba_info_param.phy_tuning[phy_id].trans_amp = 0x1A;
227 mvi->hba_info_param.phy_tuning[phy_id].trans_amp_adj = 0x3;
228 }
229
230 temp = (u8)(*(u8 *)&mvi->hba_info_param.ffe_ctl[phy_id]);
231 if (temp == 0xFFL) {
232 switch (mvi->pdev->revision) {
233 case VANIR_A0_REV:
234 case VANIR_B0_REV:
235 mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7;
236 mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0x7;
237 break;
238 case VANIR_C0_REV:
239 case VANIR_C1_REV:
240 case VANIR_C2_REV:
241 default:
242 mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7;
243 mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0xC;
244 break;
245 }
246 }
247
248 temp = (u8)(*(u8 *)&mvi->hba_info_param.phy_rate[phy_id]);
249 if (temp == 0xFFL)
250 /*set default phy_rate = 6Gbps*/
251 mvi->hba_info_param.phy_rate[phy_id] = 0x2;
252
253 set_phy_tuning(mvi, phy_id,
254 mvi->hba_info_param.phy_tuning[phy_id]);
255 set_phy_ffe_tuning(mvi, phy_id,
256 mvi->hba_info_param.ffe_ctl[phy_id]);
257 set_phy_rate(mvi, phy_id,
258 mvi->hba_info_param.phy_rate[phy_id]);
259 }
260
261 static void __devinit mvs_94xx_enable_xmt(struct mvs_info *mvi, int phy_id)
262 {
263 void __iomem *regs = mvi->regs;
264 u32 tmp;
265
266 tmp = mr32(MVS_PCS);
267 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2);
268 mw32(MVS_PCS, tmp);
269 }
270
271 static void mvs_94xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard)
272 {
273 u32 tmp;
274 u32 delay = 5000;
275 if (hard == MVS_PHY_TUNE) {
276 mvs_write_port_cfg_addr(mvi, phy_id, PHYR_SATA_CTL);
277 tmp = mvs_read_port_cfg_data(mvi, phy_id);
278 mvs_write_port_cfg_data(mvi, phy_id, tmp|0x20000000);
279 mvs_write_port_cfg_data(mvi, phy_id, tmp|0x100000);
280 return;
281 }
282 tmp = mvs_read_port_irq_stat(mvi, phy_id);
283 tmp &= ~PHYEV_RDY_CH;
284 mvs_write_port_irq_stat(mvi, phy_id, tmp);
285 if (hard) {
286 tmp = mvs_read_phy_ctl(mvi, phy_id);
287 tmp |= PHY_RST_HARD;
288 mvs_write_phy_ctl(mvi, phy_id, tmp);
289 do {
290 tmp = mvs_read_phy_ctl(mvi, phy_id);
291 udelay(10);
292 delay--;
293 } while ((tmp & PHY_RST_HARD) && delay);
294 if (!delay)
295 mv_dprintk("phy hard reset failed.\n");
296 } else {
297 tmp = mvs_read_phy_ctl(mvi, phy_id);
298 tmp |= PHY_RST;
299 mvs_write_phy_ctl(mvi, phy_id, tmp);
300 }
301 }
302
303 static void mvs_94xx_phy_disable(struct mvs_info *mvi, u32 phy_id)
304 {
305 u32 tmp;
306 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
307 tmp = mvs_read_port_vsr_data(mvi, phy_id);
308 mvs_write_port_vsr_data(mvi, phy_id, tmp | 0x00800000);
309 }
310
311 static void mvs_94xx_phy_enable(struct mvs_info *mvi, u32 phy_id)
312 {
313 u32 tmp;
314 u8 revision = 0;
315
316 revision = mvi->pdev->revision;
317 if (revision == VANIR_A0_REV) {
318 mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA);
319 mvs_write_port_vsr_data(mvi, phy_id, 0x8300ffc1);
320 }
321 if (revision == VANIR_B0_REV) {
322 mvs_write_port_vsr_addr(mvi, phy_id, CMD_APP_MEM_CTL);
323 mvs_write_port_vsr_data(mvi, phy_id, 0x08001006);
324 mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA);
325 mvs_write_port_vsr_data(mvi, phy_id, 0x0000705f);
326 }
327
328 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
329 tmp = mvs_read_port_vsr_data(mvi, phy_id);
330 tmp |= bit(0);
331 mvs_write_port_vsr_data(mvi, phy_id, tmp & 0xfd7fffff);
332 }
333
334 static int __devinit mvs_94xx_init(struct mvs_info *mvi)
335 {
336 void __iomem *regs = mvi->regs;
337 int i;
338 u32 tmp, cctl;
339 u8 revision;
340
341 revision = mvi->pdev->revision;
342 mvs_show_pcie_usage(mvi);
343 if (mvi->flags & MVF_FLAG_SOC) {
344 tmp = mr32(MVS_PHY_CTL);
345 tmp &= ~PCTL_PWR_OFF;
346 tmp |= PCTL_PHY_DSBL;
347 mw32(MVS_PHY_CTL, tmp);
348 }
349
350 /* Init Chip */
351 /* make sure RST is set; HBA_RST /should/ have done that for us */
352 cctl = mr32(MVS_CTL) & 0xFFFF;
353 if (cctl & CCTL_RST)
354 cctl &= ~CCTL_RST;
355 else
356 mw32_f(MVS_CTL, cctl | CCTL_RST);
357
358 if (mvi->flags & MVF_FLAG_SOC) {
359 tmp = mr32(MVS_PHY_CTL);
360 tmp &= ~PCTL_PWR_OFF;
361 tmp |= PCTL_COM_ON;
362 tmp &= ~PCTL_PHY_DSBL;
363 tmp |= PCTL_LINK_RST;
364 mw32(MVS_PHY_CTL, tmp);
365 msleep(100);
366 tmp &= ~PCTL_LINK_RST;
367 mw32(MVS_PHY_CTL, tmp);
368 msleep(100);
369 }
370
371 /* disable Multiplexing, enable phy implemented */
372 mw32(MVS_PORTS_IMP, 0xFF);
373
374 if (revision == VANIR_A0_REV) {
375 mw32(MVS_PA_VSR_ADDR, CMD_CMWK_OOB_DET);
376 mw32(MVS_PA_VSR_PORT, 0x00018080);
377 }
378 mw32(MVS_PA_VSR_ADDR, VSR_PHY_MODE2);
379 if (revision == VANIR_A0_REV || revision == VANIR_B0_REV)
380 /* set 6G/3G/1.5G, multiplexing, without SSC */
381 mw32(MVS_PA_VSR_PORT, 0x0084d4fe);
382 else
383 /* set 6G/3G/1.5G, multiplexing, with and without SSC */
384 mw32(MVS_PA_VSR_PORT, 0x0084fffe);
385
386 if (revision == VANIR_B0_REV) {
387 mw32(MVS_PA_VSR_ADDR, CMD_APP_MEM_CTL);
388 mw32(MVS_PA_VSR_PORT, 0x08001006);
389 mw32(MVS_PA_VSR_ADDR, CMD_HOST_RD_DATA);
390 mw32(MVS_PA_VSR_PORT, 0x0000705f);
391 }
392
393 /* reset control */
394 mw32(MVS_PCS, 0); /* MVS_PCS */
395 mw32(MVS_STP_REG_SET_0, 0);
396 mw32(MVS_STP_REG_SET_1, 0);
397
398 /* init phys */
399 mvs_phy_hacks(mvi);
400
401 /* set LED blink when IO*/
402 mw32(MVS_PA_VSR_ADDR, VSR_PHY_ACT_LED);
403 tmp = mr32(MVS_PA_VSR_PORT);
404 tmp &= 0xFFFF00FF;
405 tmp |= 0x00003300;
406 mw32(MVS_PA_VSR_PORT, tmp);
407
408 mw32(MVS_CMD_LIST_LO, mvi->slot_dma);
409 mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);
410
411 mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);
412 mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);
413
414 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ);
415 mw32(MVS_TX_LO, mvi->tx_dma);
416 mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);
417
418 mw32(MVS_RX_CFG, MVS_RX_RING_SZ);
419 mw32(MVS_RX_LO, mvi->rx_dma);
420 mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);
421
422 for (i = 0; i < mvi->chip->n_phy; i++) {
423 mvs_94xx_phy_disable(mvi, i);
424 /* set phy local SAS address */
425 mvs_set_sas_addr(mvi, i, CONFIG_ID_FRAME3, CONFIG_ID_FRAME4,
426 cpu_to_le64(mvi->phy[i].dev_sas_addr));
427
428 mvs_94xx_enable_xmt(mvi, i);
429 mvs_94xx_config_reg_from_hba(mvi, i);
430 mvs_94xx_phy_enable(mvi, i);
431
432 mvs_94xx_phy_reset(mvi, i, PHY_RST_HARD);
433 msleep(500);
434 mvs_94xx_detect_porttype(mvi, i);
435 }
436
437 if (mvi->flags & MVF_FLAG_SOC) {
438 /* set select registers */
439 writel(0x0E008000, regs + 0x000);
440 writel(0x59000008, regs + 0x004);
441 writel(0x20, regs + 0x008);
442 writel(0x20, regs + 0x00c);
443 writel(0x20, regs + 0x010);
444 writel(0x20, regs + 0x014);
445 writel(0x20, regs + 0x018);
446 writel(0x20, regs + 0x01c);
447 }
448 for (i = 0; i < mvi->chip->n_phy; i++) {
449 /* clear phy int status */
450 tmp = mvs_read_port_irq_stat(mvi, i);
451 tmp &= ~PHYEV_SIG_FIS;
452 mvs_write_port_irq_stat(mvi, i, tmp);
453
454 /* set phy int mask */
455 tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH |
456 PHYEV_ID_DONE | PHYEV_DCDR_ERR | PHYEV_CRC_ERR ;
457 mvs_write_port_irq_mask(mvi, i, tmp);
458
459 msleep(100);
460 mvs_update_phyinfo(mvi, i, 1);
461 }
462
463 /* FIXME: update wide port bitmaps */
464
465 /* little endian for open address and command table, etc. */
466 /*
467 * it seems that ( from the spec ) turning on big-endian won't
468 * do us any good on big-endian machines, need further confirmation
469 */
470 cctl = mr32(MVS_CTL);
471 cctl |= CCTL_ENDIAN_CMD;
472 cctl &= ~CCTL_ENDIAN_OPEN;
473 cctl |= CCTL_ENDIAN_RSP;
474 mw32_f(MVS_CTL, cctl);
475
476 /* reset CMD queue */
477 tmp = mr32(MVS_PCS);
478 tmp |= PCS_CMD_RST;
479 tmp &= ~PCS_SELF_CLEAR;
480 mw32(MVS_PCS, tmp);
481 /* interrupt coalescing may cause missing HW interrput in some case,
482 * and the max count is 0x1ff, while our max slot is 0x200,
483 * it will make count 0.
484 */
485 tmp = 0;
486 if (MVS_CHIP_SLOT_SZ > 0x1ff)
487 mw32(MVS_INT_COAL, 0x1ff | COAL_EN);
488 else
489 mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ | COAL_EN);
490
491 tmp = 0x10000 | interrupt_coalescing;
492 mw32(MVS_INT_COAL_TMOUT, tmp);
493
494 /* ladies and gentlemen, start your engines */
495 mw32(MVS_TX_CFG, 0);
496 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN);
497 mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN);
498 /* enable CMD/CMPL_Q/RESP mode */
499 mw32(MVS_PCS, PCS_SATA_RETRY_2 | PCS_FIS_RX_EN |
500 PCS_CMD_EN | PCS_CMD_STOP_ERR);
501
502 /* enable completion queue interrupt */
503 tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP |
504 CINT_DMA_PCIE | CINT_NON_SPEC_NCQ_ERROR);
505 tmp |= CINT_PHY_MASK;
506 mw32(MVS_INT_MASK, tmp);
507
508 /* Enable SRS interrupt */
509 mw32(MVS_INT_MASK_SRS_0, 0xFFFF);
510
511 return 0;
512 }
513
514 static int mvs_94xx_ioremap(struct mvs_info *mvi)
515 {
516 if (!mvs_ioremap(mvi, 2, -1)) {
517 mvi->regs_ex = mvi->regs + 0x10200;
518 mvi->regs += 0x20000;
519 if (mvi->id == 1)
520 mvi->regs += 0x4000;
521 return 0;
522 }
523 return -1;
524 }
525
526 static void mvs_94xx_iounmap(struct mvs_info *mvi)
527 {
528 if (mvi->regs) {
529 mvi->regs -= 0x20000;
530 if (mvi->id == 1)
531 mvi->regs -= 0x4000;
532 mvs_iounmap(mvi->regs);
533 }
534 }
535
536 static void mvs_94xx_interrupt_enable(struct mvs_info *mvi)
537 {
538 void __iomem *regs = mvi->regs_ex;
539 u32 tmp;
540
541 tmp = mr32(MVS_GBL_CTL);
542 tmp |= (IRQ_SAS_A | IRQ_SAS_B);
543 mw32(MVS_GBL_INT_STAT, tmp);
544 writel(tmp, regs + 0x0C);
545 writel(tmp, regs + 0x10);
546 writel(tmp, regs + 0x14);
547 writel(tmp, regs + 0x18);
548 mw32(MVS_GBL_CTL, tmp);
549 }
550
551 static void mvs_94xx_interrupt_disable(struct mvs_info *mvi)
552 {
553 void __iomem *regs = mvi->regs_ex;
554 u32 tmp;
555
556 tmp = mr32(MVS_GBL_CTL);
557
558 tmp &= ~(IRQ_SAS_A | IRQ_SAS_B);
559 mw32(MVS_GBL_INT_STAT, tmp);
560 writel(tmp, regs + 0x0C);
561 writel(tmp, regs + 0x10);
562 writel(tmp, regs + 0x14);
563 writel(tmp, regs + 0x18);
564 mw32(MVS_GBL_CTL, tmp);
565 }
566
567 static u32 mvs_94xx_isr_status(struct mvs_info *mvi, int irq)
568 {
569 void __iomem *regs = mvi->regs_ex;
570 u32 stat = 0;
571 if (!(mvi->flags & MVF_FLAG_SOC)) {
572 stat = mr32(MVS_GBL_INT_STAT);
573
574 if (!(stat & (IRQ_SAS_A | IRQ_SAS_B)))
575 return 0;
576 }
577 return stat;
578 }
579
580 static irqreturn_t mvs_94xx_isr(struct mvs_info *mvi, int irq, u32 stat)
581 {
582 void __iomem *regs = mvi->regs;
583
584 if (((stat & IRQ_SAS_A) && mvi->id == 0) ||
585 ((stat & IRQ_SAS_B) && mvi->id == 1)) {
586 mw32_f(MVS_INT_STAT, CINT_DONE);
587 #ifndef MVS_USE_TASKLET
588 spin_lock(&mvi->lock);
589 #endif
590 mvs_int_full(mvi);
591 #ifndef MVS_USE_TASKLET
592 spin_unlock(&mvi->lock);
593 #endif
594 }
595 return IRQ_HANDLED;
596 }
597
598 static void mvs_94xx_command_active(struct mvs_info *mvi, u32 slot_idx)
599 {
600 u32 tmp;
601 tmp = mvs_cr32(mvi, MVS_COMMAND_ACTIVE+(slot_idx >> 3));
602 if (tmp && 1 << (slot_idx % 32)) {
603 mv_printk("command active %08X, slot [%x].\n", tmp, slot_idx);
604 mvs_cw32(mvi, MVS_COMMAND_ACTIVE + (slot_idx >> 3),
605 1 << (slot_idx % 32));
606 do {
607 tmp = mvs_cr32(mvi,
608 MVS_COMMAND_ACTIVE + (slot_idx >> 3));
609 } while (tmp & 1 << (slot_idx % 32));
610 }
611 }
612
613 void mvs_94xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all)
614 {
615 void __iomem *regs = mvi->regs;
616 u32 tmp;
617
618 if (clear_all) {
619 tmp = mr32(MVS_INT_STAT_SRS_0);
620 if (tmp) {
621 mv_dprintk("check SRS 0 %08X.\n", tmp);
622 mw32(MVS_INT_STAT_SRS_0, tmp);
623 }
624 tmp = mr32(MVS_INT_STAT_SRS_1);
625 if (tmp) {
626 mv_dprintk("check SRS 1 %08X.\n", tmp);
627 mw32(MVS_INT_STAT_SRS_1, tmp);
628 }
629 } else {
630 if (reg_set > 31)
631 tmp = mr32(MVS_INT_STAT_SRS_1);
632 else
633 tmp = mr32(MVS_INT_STAT_SRS_0);
634
635 if (tmp & (1 << (reg_set % 32))) {
636 mv_dprintk("register set 0x%x was stopped.\n", reg_set);
637 if (reg_set > 31)
638 mw32(MVS_INT_STAT_SRS_1, 1 << (reg_set % 32));
639 else
640 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32));
641 }
642 }
643 }
644
645 static void mvs_94xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type,
646 u32 tfs)
647 {
648 void __iomem *regs = mvi->regs;
649 u32 tmp;
650 mvs_94xx_clear_srs_irq(mvi, 0, 1);
651
652 tmp = mr32(MVS_INT_STAT);
653 mw32(MVS_INT_STAT, tmp | CINT_CI_STOP);
654 tmp = mr32(MVS_PCS) | 0xFF00;
655 mw32(MVS_PCS, tmp);
656 }
657
658 static void mvs_94xx_non_spec_ncq_error(struct mvs_info *mvi)
659 {
660 void __iomem *regs = mvi->regs;
661 u32 err_0, err_1;
662 u8 i;
663 struct mvs_device *device;
664
665 err_0 = mr32(MVS_NON_NCQ_ERR_0);
666 err_1 = mr32(MVS_NON_NCQ_ERR_1);
667
668 mv_dprintk("non specific ncq error err_0:%x,err_1:%x.\n",
669 err_0, err_1);
670 for (i = 0; i < 32; i++) {
671 if (err_0 & bit(i)) {
672 device = mvs_find_dev_by_reg_set(mvi, i);
673 if (device)
674 mvs_release_task(mvi, device->sas_device);
675 }
676 if (err_1 & bit(i)) {
677 device = mvs_find_dev_by_reg_set(mvi, i+32);
678 if (device)
679 mvs_release_task(mvi, device->sas_device);
680 }
681 }
682
683 mw32(MVS_NON_NCQ_ERR_0, err_0);
684 mw32(MVS_NON_NCQ_ERR_1, err_1);
685 }
686
687 static void mvs_94xx_free_reg_set(struct mvs_info *mvi, u8 *tfs)
688 {
689 void __iomem *regs = mvi->regs;
690 u8 reg_set = *tfs;
691
692 if (*tfs == MVS_ID_NOT_MAPPED)
693 return;
694
695 mvi->sata_reg_set &= ~bit(reg_set);
696 if (reg_set < 32)
697 w_reg_set_enable(reg_set, (u32)mvi->sata_reg_set);
698 else
699 w_reg_set_enable(reg_set, (u32)(mvi->sata_reg_set >> 32));
700
701 *tfs = MVS_ID_NOT_MAPPED;
702
703 return;
704 }
705
706 static u8 mvs_94xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs)
707 {
708 int i;
709 void __iomem *regs = mvi->regs;
710
711 if (*tfs != MVS_ID_NOT_MAPPED)
712 return 0;
713
714 i = mv_ffc64(mvi->sata_reg_set);
715 if (i >= 32) {
716 mvi->sata_reg_set |= bit(i);
717 w_reg_set_enable(i, (u32)(mvi->sata_reg_set >> 32));
718 *tfs = i;
719 return 0;
720 } else if (i >= 0) {
721 mvi->sata_reg_set |= bit(i);
722 w_reg_set_enable(i, (u32)mvi->sata_reg_set);
723 *tfs = i;
724 return 0;
725 }
726 return MVS_ID_NOT_MAPPED;
727 }
728
729 static void mvs_94xx_make_prd(struct scatterlist *scatter, int nr, void *prd)
730 {
731 int i;
732 struct scatterlist *sg;
733 struct mvs_prd *buf_prd = prd;
734 struct mvs_prd_imt im_len;
735 *(u32 *)&im_len = 0;
736 for_each_sg(scatter, sg, nr, i) {
737 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
738 im_len.len = sg_dma_len(sg);
739 buf_prd->im_len = cpu_to_le32(*(u32 *)&im_len);
740 buf_prd++;
741 }
742 }
743
744 static int mvs_94xx_oob_done(struct mvs_info *mvi, int i)
745 {
746 u32 phy_st;
747 phy_st = mvs_read_phy_ctl(mvi, i);
748 if (phy_st & PHY_READY_MASK) /* phy ready */
749 return 1;
750 return 0;
751 }
752
753 static void mvs_94xx_get_dev_identify_frame(struct mvs_info *mvi, int port_id,
754 struct sas_identify_frame *id)
755 {
756 int i;
757 u32 id_frame[7];
758
759 for (i = 0; i < 7; i++) {
760 mvs_write_port_cfg_addr(mvi, port_id,
761 CONFIG_ID_FRAME0 + i * 4);
762 id_frame[i] = cpu_to_le32(mvs_read_port_cfg_data(mvi, port_id));
763 }
764 memcpy(id, id_frame, 28);
765 }
766
767 static void mvs_94xx_get_att_identify_frame(struct mvs_info *mvi, int port_id,
768 struct sas_identify_frame *id)
769 {
770 int i;
771 u32 id_frame[7];
772
773 /* mvs_hexdump(28, (u8 *)id_frame, 0); */
774 for (i = 0; i < 7; i++) {
775 mvs_write_port_cfg_addr(mvi, port_id,
776 CONFIG_ATT_ID_FRAME0 + i * 4);
777 id_frame[i] = cpu_to_le32(mvs_read_port_cfg_data(mvi, port_id));
778 mv_dprintk("94xx phy %d atta frame %d %x.\n",
779 port_id + mvi->id * mvi->chip->n_phy, i, id_frame[i]);
780 }
781 /* mvs_hexdump(28, (u8 *)id_frame, 0); */
782 memcpy(id, id_frame, 28);
783 }
784
785 static u32 mvs_94xx_make_dev_info(struct sas_identify_frame *id)
786 {
787 u32 att_dev_info = 0;
788
789 att_dev_info |= id->dev_type;
790 if (id->stp_iport)
791 att_dev_info |= PORT_DEV_STP_INIT;
792 if (id->smp_iport)
793 att_dev_info |= PORT_DEV_SMP_INIT;
794 if (id->ssp_iport)
795 att_dev_info |= PORT_DEV_SSP_INIT;
796 if (id->stp_tport)
797 att_dev_info |= PORT_DEV_STP_TRGT;
798 if (id->smp_tport)
799 att_dev_info |= PORT_DEV_SMP_TRGT;
800 if (id->ssp_tport)
801 att_dev_info |= PORT_DEV_SSP_TRGT;
802
803 att_dev_info |= (u32)id->phy_id<<24;
804 return att_dev_info;
805 }
806
807 static u32 mvs_94xx_make_att_info(struct sas_identify_frame *id)
808 {
809 return mvs_94xx_make_dev_info(id);
810 }
811
812 static void mvs_94xx_fix_phy_info(struct mvs_info *mvi, int i,
813 struct sas_identify_frame *id)
814 {
815 struct mvs_phy *phy = &mvi->phy[i];
816 struct asd_sas_phy *sas_phy = &phy->sas_phy;
817 mv_dprintk("get all reg link rate is 0x%x\n", phy->phy_status);
818 sas_phy->linkrate =
819 (phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >>
820 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET;
821 sas_phy->linkrate += 0x8;
822 mv_dprintk("get link rate is %d\n", sas_phy->linkrate);
823 phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
824 phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
825 mvs_94xx_get_dev_identify_frame(mvi, i, id);
826 phy->dev_info = mvs_94xx_make_dev_info(id);
827
828 if (phy->phy_type & PORT_TYPE_SAS) {
829 mvs_94xx_get_att_identify_frame(mvi, i, id);
830 phy->att_dev_info = mvs_94xx_make_att_info(id);
831 phy->att_dev_sas_addr = *(u64 *)id->sas_addr;
832 } else {
833 phy->att_dev_info = PORT_DEV_STP_TRGT | 1;
834 }
835
836 }
837
838 void mvs_94xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
839 struct sas_phy_linkrates *rates)
840 {
841 u32 lrmax = 0;
842 u32 tmp;
843
844 tmp = mvs_read_phy_ctl(mvi, phy_id);
845 lrmax = (rates->maximum_linkrate - SAS_LINK_RATE_1_5_GBPS) << 12;
846
847 if (lrmax) {
848 tmp &= ~(0x3 << 12);
849 tmp |= lrmax;
850 }
851 mvs_write_phy_ctl(mvi, phy_id, tmp);
852 mvs_94xx_phy_reset(mvi, phy_id, PHY_RST_HARD);
853 }
854
855 static void mvs_94xx_clear_active_cmds(struct mvs_info *mvi)
856 {
857 u32 tmp;
858 void __iomem *regs = mvi->regs;
859 tmp = mr32(MVS_STP_REG_SET_0);
860 mw32(MVS_STP_REG_SET_0, 0);
861 mw32(MVS_STP_REG_SET_0, tmp);
862 tmp = mr32(MVS_STP_REG_SET_1);
863 mw32(MVS_STP_REG_SET_1, 0);
864 mw32(MVS_STP_REG_SET_1, tmp);
865 }
866
867
868 u32 mvs_94xx_spi_read_data(struct mvs_info *mvi)
869 {
870 void __iomem *regs = mvi->regs_ex - 0x10200;
871 return mr32(SPI_RD_DATA_REG_94XX);
872 }
873
874 void mvs_94xx_spi_write_data(struct mvs_info *mvi, u32 data)
875 {
876 void __iomem *regs = mvi->regs_ex - 0x10200;
877 mw32(SPI_RD_DATA_REG_94XX, data);
878 }
879
880
881 int mvs_94xx_spi_buildcmd(struct mvs_info *mvi,
882 u32 *dwCmd,
883 u8 cmd,
884 u8 read,
885 u8 length,
886 u32 addr
887 )
888 {
889 void __iomem *regs = mvi->regs_ex - 0x10200;
890 u32 dwTmp;
891
892 dwTmp = ((u32)cmd << 8) | ((u32)length << 4);
893 if (read)
894 dwTmp |= SPI_CTRL_READ_94XX;
895
896 if (addr != MV_MAX_U32) {
897 mw32(SPI_ADDR_REG_94XX, (addr & 0x0003FFFFL));
898 dwTmp |= SPI_ADDR_VLD_94XX;
899 }
900
901 *dwCmd = dwTmp;
902 return 0;
903 }
904
905
906 int mvs_94xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)
907 {
908 void __iomem *regs = mvi->regs_ex - 0x10200;
909 mw32(SPI_CTRL_REG_94XX, cmd | SPI_CTRL_SpiStart_94XX);
910
911 return 0;
912 }
913
914 int mvs_94xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)
915 {
916 void __iomem *regs = mvi->regs_ex - 0x10200;
917 u32 i, dwTmp;
918
919 for (i = 0; i < timeout; i++) {
920 dwTmp = mr32(SPI_CTRL_REG_94XX);
921 if (!(dwTmp & SPI_CTRL_SpiStart_94XX))
922 return 0;
923 msleep(10);
924 }
925
926 return -1;
927 }
928
929 void mvs_94xx_fix_dma(struct mvs_info *mvi, u32 phy_mask,
930 int buf_len, int from, void *prd)
931 {
932 int i;
933 struct mvs_prd *buf_prd = prd;
934 dma_addr_t buf_dma;
935 struct mvs_prd_imt im_len;
936
937 *(u32 *)&im_len = 0;
938 buf_prd += from;
939
940 #define PRD_CHAINED_ENTRY 0x01
941 if ((mvi->pdev->revision == VANIR_A0_REV) ||
942 (mvi->pdev->revision == VANIR_B0_REV))
943 buf_dma = (phy_mask <= 0x08) ?
944 mvi->bulk_buffer_dma : mvi->bulk_buffer_dma1;
945 else
946 return;
947
948 for (i = from; i < MAX_SG_ENTRY; i++, ++buf_prd) {
949 if (i == MAX_SG_ENTRY - 1) {
950 buf_prd->addr = cpu_to_le64(virt_to_phys(buf_prd - 1));
951 im_len.len = 2;
952 im_len.misc_ctl = PRD_CHAINED_ENTRY;
953 } else {
954 buf_prd->addr = cpu_to_le64(buf_dma);
955 im_len.len = buf_len;
956 }
957 buf_prd->im_len = cpu_to_le32(*(u32 *)&im_len);
958 }
959 }
960
961 static void mvs_94xx_tune_interrupt(struct mvs_info *mvi, u32 time)
962 {
963 void __iomem *regs = mvi->regs;
964 u32 tmp = 0;
965 /* interrupt coalescing may cause missing HW interrput in some case,
966 * and the max count is 0x1ff, while our max slot is 0x200,
967 * it will make count 0.
968 */
969 if (time == 0) {
970 mw32(MVS_INT_COAL, 0);
971 mw32(MVS_INT_COAL_TMOUT, 0x10000);
972 } else {
973 if (MVS_CHIP_SLOT_SZ > 0x1ff)
974 mw32(MVS_INT_COAL, 0x1ff|COAL_EN);
975 else
976 mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ|COAL_EN);
977
978 tmp = 0x10000 | time;
979 mw32(MVS_INT_COAL_TMOUT, tmp);
980 }
981
982 }
983
984 const struct mvs_dispatch mvs_94xx_dispatch = {
985 "mv94xx",
986 mvs_94xx_init,
987 NULL,
988 mvs_94xx_ioremap,
989 mvs_94xx_iounmap,
990 mvs_94xx_isr,
991 mvs_94xx_isr_status,
992 mvs_94xx_interrupt_enable,
993 mvs_94xx_interrupt_disable,
994 mvs_read_phy_ctl,
995 mvs_write_phy_ctl,
996 mvs_read_port_cfg_data,
997 mvs_write_port_cfg_data,
998 mvs_write_port_cfg_addr,
999 mvs_read_port_vsr_data,
1000 mvs_write_port_vsr_data,
1001 mvs_write_port_vsr_addr,
1002 mvs_read_port_irq_stat,
1003 mvs_write_port_irq_stat,
1004 mvs_read_port_irq_mask,
1005 mvs_write_port_irq_mask,
1006 mvs_94xx_command_active,
1007 mvs_94xx_clear_srs_irq,
1008 mvs_94xx_issue_stop,
1009 mvs_start_delivery,
1010 mvs_rx_update,
1011 mvs_int_full,
1012 mvs_94xx_assign_reg_set,
1013 mvs_94xx_free_reg_set,
1014 mvs_get_prd_size,
1015 mvs_get_prd_count,
1016 mvs_94xx_make_prd,
1017 mvs_94xx_detect_porttype,
1018 mvs_94xx_oob_done,
1019 mvs_94xx_fix_phy_info,
1020 NULL,
1021 mvs_94xx_phy_set_link_rate,
1022 mvs_hw_max_link_rate,
1023 mvs_94xx_phy_disable,
1024 mvs_94xx_phy_enable,
1025 mvs_94xx_phy_reset,
1026 NULL,
1027 mvs_94xx_clear_active_cmds,
1028 mvs_94xx_spi_read_data,
1029 mvs_94xx_spi_write_data,
1030 mvs_94xx_spi_buildcmd,
1031 mvs_94xx_spi_issuecmd,
1032 mvs_94xx_spi_waitdataready,
1033 mvs_94xx_fix_dma,
1034 mvs_94xx_tune_interrupt,
1035 mvs_94xx_non_spec_ncq_error,
1036 };
1037
Linus' kernel tree