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staging:iio:adc:naming: dev_info to indio_dev for consistency
[linux-2.6.git] / drivers / staging / iio / adc / ad7192.c
blob29258f4a0955e2c129f6f8e0f241afaf8c74a976
1 /*
2 * AD7190 AD7192 AD7195 SPI ADC driver
3 *
4 * Copyright 2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2.
7 */
8
9 #include <linux/interrupt.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/spi/spi.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/err.h>
17 #include <linux/sched.h>
18 #include <linux/delay.h>
19
20 #include "../iio.h"
21 #include "../sysfs.h"
22 #include "../buffer_generic.h"
23 #include "../ring_sw.h"
24 #include "../trigger.h"
25 #include "../trigger_consumer.h"
26
27 #include "ad7192.h"
28
29 /* Registers */
30 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
31 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
32 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
33 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
34 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
35 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
36 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
37 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit
38 * (AD7792)/24-bit (AD7192)) */
39 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register
40 * (RW, 16-bit (AD7792)/24-bit (AD7192)) */
41
42 /* Communications Register Bit Designations (AD7192_REG_COMM) */
43 #define AD7192_COMM_WEN (1 << 7) /* Write Enable */
44 #define AD7192_COMM_WRITE (0 << 6) /* Write Operation */
45 #define AD7192_COMM_READ (1 << 6) /* Read Operation */
46 #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
47 #define AD7192_COMM_CREAD (1 << 2) /* Continuous Read of Data Register */
48
49 /* Status Register Bit Designations (AD7192_REG_STAT) */
50 #define AD7192_STAT_RDY (1 << 7) /* Ready */
51 #define AD7192_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */
52 #define AD7192_STAT_NOREF (1 << 5) /* Error no external reference */
53 #define AD7192_STAT_PARITY (1 << 4) /* Parity */
54 #define AD7192_STAT_CH3 (1 << 2) /* Channel 3 */
55 #define AD7192_STAT_CH2 (1 << 1) /* Channel 2 */
56 #define AD7192_STAT_CH1 (1 << 0) /* Channel 1 */
57
58 /* Mode Register Bit Designations (AD7192_REG_MODE) */
59 #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
60 #define AD7192_MODE_DAT_STA (1 << 20) /* Status Register transmission */
61 #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
62 #define AD7192_MODE_SINC3 (1 << 15) /* SINC3 Filter Select */
63 #define AD7192_MODE_ACX (1 << 14) /* AC excitation enable(AD7195 only)*/
64 #define AD7192_MODE_ENPAR (1 << 13) /* Parity Enable */
65 #define AD7192_MODE_CLKDIV (1 << 12) /* Clock divide by 2 (AD7190/2 only)*/
66 #define AD7192_MODE_SCYCLE (1 << 11) /* Single cycle conversion */
67 #define AD7192_MODE_REJ60 (1 << 10) /* 50/60Hz notch filter */
68 #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
69
70 /* Mode Register: AD7192_MODE_SEL options */
71 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
72 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
73 #define AD7192_MODE_IDLE 2 /* Idle Mode */
74 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
75 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
76 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
77 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
78 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
79
80 /* Mode Register: AD7192_MODE_CLKSRC options */
81 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected
82 * from MCLK1 to MCLK2 */
83 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
84 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not
85 * available at the MCLK2 pin */
86 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available
87 * at the MCLK2 pin */
88
89
90 /* Configuration Register Bit Designations (AD7192_REG_CONF) */
91
92 #define AD7192_CONF_CHOP (1 << 23) /* CHOP enable */
93 #define AD7192_CONF_REFSEL (1 << 20) /* REFIN1/REFIN2 Reference Select */
94 #define AD7192_CONF_CHAN(x) (((x) & 0xFF) << 8) /* Channel select */
95 #define AD7192_CONF_BURN (1 << 7) /* Burnout current enable */
96 #define AD7192_CONF_REFDET (1 << 6) /* Reference detect enable */
97 #define AD7192_CONF_BUF (1 << 4) /* Buffered Mode Enable */
98 #define AD7192_CONF_UNIPOLAR (1 << 3) /* Unipolar/Bipolar Enable */
99 #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
100
101 #define AD7192_CH_AIN1P_AIN2M 0 /* AIN1(+) - AIN2(-) */
102 #define AD7192_CH_AIN3P_AIN4M 1 /* AIN3(+) - AIN4(-) */
103 #define AD7192_CH_TEMP 2 /* Temp Sensor */
104 #define AD7192_CH_AIN2P_AIN2M 3 /* AIN2(+) - AIN2(-) */
105 #define AD7192_CH_AIN1 4 /* AIN1 - AINCOM */
106 #define AD7192_CH_AIN2 5 /* AIN2 - AINCOM */
107 #define AD7192_CH_AIN3 6 /* AIN3 - AINCOM */
108 #define AD7192_CH_AIN4 7 /* AIN4 - AINCOM */
109
110 /* ID Register Bit Designations (AD7192_REG_ID) */
111 #define ID_AD7190 0x4
112 #define ID_AD7192 0x0
113 #define ID_AD7195 0x6
114 #define AD7192_ID_MASK 0x0F
115
116 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
117 #define AD7192_GPOCON_BPDSW (1 << 6) /* Bridge power-down switch enable */
118 #define AD7192_GPOCON_GP32EN (1 << 5) /* Digital Output P3 and P2 enable */
119 #define AD7192_GPOCON_GP10EN (1 << 4) /* Digital Output P1 and P0 enable */
120 #define AD7192_GPOCON_P3DAT (1 << 3) /* P3 state */
121 #define AD7192_GPOCON_P2DAT (1 << 2) /* P2 state */
122 #define AD7192_GPOCON_P1DAT (1 << 1) /* P1 state */
123 #define AD7192_GPOCON_P0DAT (1 << 0) /* P0 state */
124
125 #define AD7192_INT_FREQ_MHz 4915200
126
127 /* NOTE:
128 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
129 * In order to avoid contentions on the SPI bus, it's therefore necessary
130 * to use spi bus locking.
131 *
132 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
133 */
134
135 struct ad7192_state {
136 struct spi_device *spi;
137 struct iio_trigger *trig;
138 struct regulator *reg;
139 struct ad7192_platform_data *pdata;
140 wait_queue_head_t wq_data_avail;
141 bool done;
142 bool irq_dis;
143 u16 int_vref_mv;
144 u32 mclk;
145 u32 f_order;
146 u32 mode;
147 u32 conf;
148 u32 scale_avail[8][2];
149 long available_scan_masks[9];
150 u8 gpocon;
151 u8 devid;
152 /*
153 * DMA (thus cache coherency maintenance) requires the
154 * transfer buffers to live in their own cache lines.
155 */
156 u8 data[4] ____cacheline_aligned;
157 };
158
159 static int __ad7192_write_reg(struct ad7192_state *st, bool locked,
160 bool cs_change, unsigned char reg,
161 unsigned size, unsigned val)
162 {
163 u8 *data = st->data;
164 struct spi_transfer t = {
165 .tx_buf = data,
166 .len = size + 1,
167 .cs_change = cs_change,
168 };
169 struct spi_message m;
170
171 data[0] = AD7192_COMM_WRITE | AD7192_COMM_ADDR(reg);
172
173 switch (size) {
174 case 3:
175 data[1] = val >> 16;
176 data[2] = val >> 8;
177 data[3] = val;
178 break;
179 case 2:
180 data[1] = val >> 8;
181 data[2] = val;
182 break;
183 case 1:
184 data[1] = val;
185 break;
186 default:
187 return -EINVAL;
188 }
189
190 spi_message_init(&m);
191 spi_message_add_tail(&t, &m);
192
193 if (locked)
194 return spi_sync_locked(st->spi, &m);
195 else
196 return spi_sync(st->spi, &m);
197 }
198
199 static int ad7192_write_reg(struct ad7192_state *st,
200 unsigned reg, unsigned size, unsigned val)
201 {
202 return __ad7192_write_reg(st, false, false, reg, size, val);
203 }
204
205 static int __ad7192_read_reg(struct ad7192_state *st, bool locked,
206 bool cs_change, unsigned char reg,
207 int *val, unsigned size)
208 {
209 u8 *data = st->data;
210 int ret;
211 struct spi_transfer t[] = {
212 {
213 .tx_buf = data,
214 .len = 1,
215 }, {
216 .rx_buf = data,
217 .len = size,
218 .cs_change = cs_change,
219 },
220 };
221 struct spi_message m;
222
223 data[0] = AD7192_COMM_READ | AD7192_COMM_ADDR(reg);
224
225 spi_message_init(&m);
226 spi_message_add_tail(&t[0], &m);
227 spi_message_add_tail(&t[1], &m);
228
229 if (locked)
230 ret = spi_sync_locked(st->spi, &m);
231 else
232 ret = spi_sync(st->spi, &m);
233
234 if (ret < 0)
235 return ret;
236
237 switch (size) {
238 case 3:
239 *val = data[0] << 16 | data[1] << 8 | data[2];
240 break;
241 case 2:
242 *val = data[0] << 8 | data[1];
243 break;
244 case 1:
245 *val = data[0];
246 break;
247 default:
248 return -EINVAL;
249 }
250
251 return 0;
252 }
253
254 static int ad7192_read_reg(struct ad7192_state *st,
255 unsigned reg, int *val, unsigned size)
256 {
257 return __ad7192_read_reg(st, 0, 0, reg, val, size);
258 }
259
260 static int ad7192_read(struct ad7192_state *st, unsigned ch,
261 unsigned len, int *val)
262 {
263 int ret;
264 st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) |
265 AD7192_CONF_CHAN(1 << ch);
266 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
267 AD7192_MODE_SEL(AD7192_MODE_SINGLE);
268
269 ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
270
271 spi_bus_lock(st->spi->master);
272 st->done = false;
273
274 ret = __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, st->mode);
275 if (ret < 0)
276 goto out;
277
278 st->irq_dis = false;
279 enable_irq(st->spi->irq);
280 wait_event_interruptible(st->wq_data_avail, st->done);
281
282 ret = __ad7192_read_reg(st, 1, 0, AD7192_REG_DATA, val, len);
283 out:
284 spi_bus_unlock(st->spi->master);
285
286 return ret;
287 }
288
289 static int ad7192_calibrate(struct ad7192_state *st, unsigned mode, unsigned ch)
290 {
291 int ret;
292
293 st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) |
294 AD7192_CONF_CHAN(1 << ch);
295 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | AD7192_MODE_SEL(mode);
296
297 ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
298
299 spi_bus_lock(st->spi->master);
300 st->done = false;
301
302 ret = __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3,
303 (st->devid != ID_AD7195) ?
304 st->mode | AD7192_MODE_CLKDIV :
305 st->mode);
306 if (ret < 0)
307 goto out;
308
309 st->irq_dis = false;
310 enable_irq(st->spi->irq);
311 wait_event_interruptible(st->wq_data_avail, st->done);
312
313 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
314 AD7192_MODE_SEL(AD7192_MODE_IDLE);
315
316 ret = __ad7192_write_reg(st, 1, 0, AD7192_REG_MODE, 3, st->mode);
317 out:
318 spi_bus_unlock(st->spi->master);
319
320 return ret;
321 }
322
323 static const u8 ad7192_calib_arr[8][2] = {
324 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
325 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
326 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
327 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
328 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
329 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
330 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
331 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
332 };
333
334 static int ad7192_calibrate_all(struct ad7192_state *st)
335 {
336 int i, ret;
337
338 for (i = 0; i < ARRAY_SIZE(ad7192_calib_arr); i++) {
339 ret = ad7192_calibrate(st, ad7192_calib_arr[i][0],
340 ad7192_calib_arr[i][1]);
341 if (ret)
342 goto out;
343 }
344
345 return 0;
346 out:
347 dev_err(&st->spi->dev, "Calibration failed\n");
348 return ret;
349 }
350
351 static int ad7192_setup(struct ad7192_state *st)
352 {
353 struct iio_dev *indio_dev = spi_get_drvdata(st->spi);
354 struct ad7192_platform_data *pdata = st->pdata;
355 unsigned long long scale_uv;
356 int i, ret, id;
357 u8 ones[6];
358
359 /* reset the serial interface */
360 memset(&ones, 0xFF, 6);
361 ret = spi_write(st->spi, &ones, 6);
362 if (ret < 0)
363 goto out;
364 msleep(1); /* Wait for at least 500us */
365
366 /* write/read test for device presence */
367 ret = ad7192_read_reg(st, AD7192_REG_ID, &id, 1);
368 if (ret)
369 goto out;
370
371 id &= AD7192_ID_MASK;
372
373 if (id != st->devid)
374 dev_warn(&st->spi->dev, "device ID query failed (0x%X)\n", id);
375
376 switch (pdata->clock_source_sel) {
377 case AD7192_CLK_EXT_MCLK1_2:
378 case AD7192_CLK_EXT_MCLK2:
379 st->mclk = AD7192_INT_FREQ_MHz;
380 break;
381 case AD7192_CLK_INT:
382 case AD7192_CLK_INT_CO:
383 if (pdata->ext_clk_Hz)
384 st->mclk = pdata->ext_clk_Hz;
385 else
386 st->mclk = AD7192_INT_FREQ_MHz;
387 break;
388 default:
389 ret = -EINVAL;
390 goto out;
391 }
392
393 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
394 AD7192_MODE_CLKSRC(pdata->clock_source_sel) |
395 AD7192_MODE_RATE(480);
396
397 st->conf = AD7192_CONF_GAIN(0);
398
399 if (pdata->rej60_en)
400 st->mode |= AD7192_MODE_REJ60;
401
402 if (pdata->sinc3_en)
403 st->mode |= AD7192_MODE_SINC3;
404
405 if (pdata->refin2_en && (st->devid != ID_AD7195))
406 st->conf |= AD7192_CONF_REFSEL;
407
408 if (pdata->chop_en) {
409 st->conf |= AD7192_CONF_CHOP;
410 if (pdata->sinc3_en)
411 st->f_order = 3; /* SINC 3rd order */
412 else
413 st->f_order = 4; /* SINC 4th order */
414 } else {
415 st->f_order = 1;
416 }
417
418 if (pdata->buf_en)
419 st->conf |= AD7192_CONF_BUF;
420
421 if (pdata->unipolar_en)
422 st->conf |= AD7192_CONF_UNIPOLAR;
423
424 if (pdata->burnout_curr_en)
425 st->conf |= AD7192_CONF_BURN;
426
427 ret = ad7192_write_reg(st, AD7192_REG_MODE, 3, st->mode);
428 if (ret)
429 goto out;
430
431 ret = ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
432 if (ret)
433 goto out;
434
435 ret = ad7192_calibrate_all(st);
436 if (ret)
437 goto out;
438
439 /* Populate available ADC input ranges */
440 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
441 scale_uv = ((u64)st->int_vref_mv * 100000000)
442 >> (indio_dev->channels[0].scan_type.realbits -
443 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
444 scale_uv >>= i;
445
446 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
447 st->scale_avail[i][0] = scale_uv;
448 }
449
450 return 0;
451 out:
452 dev_err(&st->spi->dev, "setup failed\n");
453 return ret;
454 }
455
456 static int ad7192_scan_from_ring(struct ad7192_state *st, unsigned ch, int *val)
457 {
458 struct iio_buffer *ring = iio_priv_to_dev(st)->buffer;
459 int ret;
460 s64 dat64[2];
461 u32 *dat32 = (u32 *)dat64;
462
463 if (!(test_bit(ch, ring->scan_mask)))
464 return -EBUSY;
465
466 ret = ring->access->read_last(ring, (u8 *) &dat64);
467 if (ret)
468 return ret;
469
470 *val = *dat32;
471
472 return 0;
473 }
474
475 static int ad7192_ring_preenable(struct iio_dev *indio_dev)
476 {
477 struct ad7192_state *st = iio_priv(indio_dev);
478 struct iio_buffer *ring = indio_dev->buffer;
479 size_t d_size;
480 unsigned channel;
481
482 if (!ring->scan_count)
483 return -EINVAL;
484
485 channel = find_first_bit(ring->scan_mask, indio_dev->masklength);
486
487 d_size = ring->scan_count *
488 indio_dev->channels[0].scan_type.storagebits / 8;
489
490 if (ring->scan_timestamp) {
491 d_size += sizeof(s64);
492
493 if (d_size % sizeof(s64))
494 d_size += sizeof(s64) - (d_size % sizeof(s64));
495 }
496
497 if (indio_dev->buffer->access->set_bytes_per_datum)
498 indio_dev->buffer->access->
499 set_bytes_per_datum(indio_dev->buffer, d_size);
500
501 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
502 AD7192_MODE_SEL(AD7192_MODE_CONT);
503 st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) |
504 AD7192_CONF_CHAN(1 << indio_dev->channels[channel].address);
505
506 ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
507
508 spi_bus_lock(st->spi->master);
509 __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, st->mode);
510
511 st->irq_dis = false;
512 enable_irq(st->spi->irq);
513
514 return 0;
515 }
516
517 static int ad7192_ring_postdisable(struct iio_dev *indio_dev)
518 {
519 struct ad7192_state *st = iio_priv(indio_dev);
520
521 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
522 AD7192_MODE_SEL(AD7192_MODE_IDLE);
523
524 st->done = false;
525 wait_event_interruptible(st->wq_data_avail, st->done);
526
527 if (!st->irq_dis)
528 disable_irq_nosync(st->spi->irq);
529
530 __ad7192_write_reg(st, 1, 0, AD7192_REG_MODE, 3, st->mode);
531
532 return spi_bus_unlock(st->spi->master);
533 }
534
535 /**
536 * ad7192_trigger_handler() bh of trigger launched polling to ring buffer
537 **/
538 static irqreturn_t ad7192_trigger_handler(int irq, void *p)
539 {
540 struct iio_poll_func *pf = p;
541 struct iio_dev *indio_dev = pf->indio_dev;
542 struct iio_buffer *ring = indio_dev->buffer;
543 struct ad7192_state *st = iio_priv(indio_dev);
544 s64 dat64[2];
545 s32 *dat32 = (s32 *)dat64;
546
547 if (ring->scan_count)
548 __ad7192_read_reg(st, 1, 1, AD7192_REG_DATA,
549 dat32,
550 indio_dev->channels[0].scan_type.realbits/8);
551
552 /* Guaranteed to be aligned with 8 byte boundary */
553 if (ring->scan_timestamp)
554 dat64[1] = pf->timestamp;
555
556 ring->access->store_to(ring, (u8 *)dat64, pf->timestamp);
557
558 iio_trigger_notify_done(indio_dev->trig);
559 st->irq_dis = false;
560 enable_irq(st->spi->irq);
561
562 return IRQ_HANDLED;
563 }
564
565 static const struct iio_buffer_setup_ops ad7192_ring_setup_ops = {
566 .preenable = &ad7192_ring_preenable,
567 .postenable = &iio_triggered_buffer_postenable,
568 .predisable = &iio_triggered_buffer_predisable,
569 .postdisable = &ad7192_ring_postdisable,
570 };
571
572 static int ad7192_register_ring_funcs_and_init(struct iio_dev *indio_dev)
573 {
574 int ret;
575
576 indio_dev->buffer = iio_sw_rb_allocate(indio_dev);
577 if (!indio_dev->buffer) {
578 ret = -ENOMEM;
579 goto error_ret;
580 }
581 /* Effectively select the ring buffer implementation */
582 indio_dev->buffer->access = &ring_sw_access_funcs;
583 indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
584 &ad7192_trigger_handler,
585 IRQF_ONESHOT,
586 indio_dev,
587 "ad7192_consumer%d",
588 indio_dev->id);
589 if (indio_dev->pollfunc == NULL) {
590 ret = -ENOMEM;
591 goto error_deallocate_sw_rb;
592 }
593
594 /* Ring buffer functions - here trigger setup related */
595 indio_dev->buffer->setup_ops = &ad7192_ring_setup_ops;
596
597 /* Flag that polled ring buffering is possible */
598 indio_dev->modes |= INDIO_BUFFER_TRIGGERED;
599 return 0;
600
601 error_deallocate_sw_rb:
602 iio_sw_rb_free(indio_dev->buffer);
603 error_ret:
604 return ret;
605 }
606
607 static void ad7192_ring_cleanup(struct iio_dev *indio_dev)
608 {
609 iio_dealloc_pollfunc(indio_dev->pollfunc);
610 iio_sw_rb_free(indio_dev->buffer);
611 }
612
613 /**
614 * ad7192_data_rdy_trig_poll() the event handler for the data rdy trig
615 **/
616 static irqreturn_t ad7192_data_rdy_trig_poll(int irq, void *private)
617 {
618 struct ad7192_state *st = iio_priv(private);
619
620 st->done = true;
621 wake_up_interruptible(&st->wq_data_avail);
622 disable_irq_nosync(irq);
623 st->irq_dis = true;
624 iio_trigger_poll(st->trig, iio_get_time_ns());
625
626 return IRQ_HANDLED;
627 }
628
629 static int ad7192_probe_trigger(struct iio_dev *indio_dev)
630 {
631 struct ad7192_state *st = iio_priv(indio_dev);
632 int ret;
633
634 st->trig = iio_allocate_trigger("%s-dev%d",
635 spi_get_device_id(st->spi)->name,
636 indio_dev->id);
637 if (st->trig == NULL) {
638 ret = -ENOMEM;
639 goto error_ret;
640 }
641
642 ret = request_irq(st->spi->irq,
643 ad7192_data_rdy_trig_poll,
644 IRQF_TRIGGER_LOW,
645 spi_get_device_id(st->spi)->name,
646 indio_dev);
647 if (ret)
648 goto error_free_trig;
649
650 disable_irq_nosync(st->spi->irq);
651 st->irq_dis = true;
652 st->trig->dev.parent = &st->spi->dev;
653 st->trig->owner = THIS_MODULE;
654 st->trig->private_data = indio_dev;
655
656 ret = iio_trigger_register(st->trig);
657
658 /* select default trigger */
659 indio_dev->trig = st->trig;
660 if (ret)
661 goto error_free_irq;
662
663 return 0;
664
665 error_free_irq:
666 free_irq(st->spi->irq, indio_dev);
667 error_free_trig:
668 iio_free_trigger(st->trig);
669 error_ret:
670 return ret;
671 }
672
673 static void ad7192_remove_trigger(struct iio_dev *indio_dev)
674 {
675 struct ad7192_state *st = iio_priv(indio_dev);
676
677 iio_trigger_unregister(st->trig);
678 free_irq(st->spi->irq, indio_dev);
679 iio_free_trigger(st->trig);
680 }
681
682 static ssize_t ad7192_read_frequency(struct device *dev,
683 struct device_attribute *attr,
684 char *buf)
685 {
686 struct iio_dev *indio_dev = dev_get_drvdata(dev);
687 struct ad7192_state *st = iio_priv(indio_dev);
688
689 return sprintf(buf, "%d\n", st->mclk /
690 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode)));
691 }
692
693 static ssize_t ad7192_write_frequency(struct device *dev,
694 struct device_attribute *attr,
695 const char *buf,
696 size_t len)
697 {
698 struct iio_dev *indio_dev = dev_get_drvdata(dev);
699 struct ad7192_state *st = iio_priv(indio_dev);
700 unsigned long lval;
701 int div, ret;
702
703 ret = strict_strtoul(buf, 10, &lval);
704 if (ret)
705 return ret;
706
707 mutex_lock(&indio_dev->mlock);
708 if (iio_buffer_enabled(indio_dev)) {
709 mutex_unlock(&indio_dev->mlock);
710 return -EBUSY;
711 }
712
713 div = st->mclk / (lval * st->f_order * 1024);
714 if (div < 1 || div > 1023) {
715 ret = -EINVAL;
716 goto out;
717 }
718
719 st->mode &= ~AD7192_MODE_RATE(-1);
720 st->mode |= AD7192_MODE_RATE(div);
721 ad7192_write_reg(st, AD7192_REG_MODE, 3, st->mode);
722
723 out:
724 mutex_unlock(&indio_dev->mlock);
725
726 return ret ? ret : len;
727 }
728
729 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
730 ad7192_read_frequency,
731 ad7192_write_frequency);
732
733
734 static ssize_t ad7192_show_scale_available(struct device *dev,
735 struct device_attribute *attr, char *buf)
736 {
737 struct iio_dev *indio_dev = dev_get_drvdata(dev);
738 struct ad7192_state *st = iio_priv(indio_dev);
739 int i, len = 0;
740
741 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
742 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
743 st->scale_avail[i][1]);
744
745 len += sprintf(buf + len, "\n");
746
747 return len;
748 }
749
750 static IIO_DEVICE_ATTR_NAMED(in_v_m_v_scale_available,
751 in_voltage-voltage_scale_available,
752 S_IRUGO, ad7192_show_scale_available, NULL, 0);
753
754 static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO,
755 ad7192_show_scale_available, NULL, 0);
756
757 static ssize_t ad7192_show_ac_excitation(struct device *dev,
758 struct device_attribute *attr,
759 char *buf)
760 {
761 struct iio_dev *indio_dev = dev_get_drvdata(dev);
762 struct ad7192_state *st = iio_priv(indio_dev);
763
764 return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));
765 }
766
767 static ssize_t ad7192_show_bridge_switch(struct device *dev,
768 struct device_attribute *attr,
769 char *buf)
770 {
771 struct iio_dev *indio_dev = dev_get_drvdata(dev);
772 struct ad7192_state *st = iio_priv(indio_dev);
773
774 return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
775 }
776
777 static ssize_t ad7192_set(struct device *dev,
778 struct device_attribute *attr,
779 const char *buf,
780 size_t len)
781 {
782 struct iio_dev *indio_dev = dev_get_drvdata(dev);
783 struct ad7192_state *st = iio_priv(indio_dev);
784 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
785 int ret;
786 bool val;
787
788 ret = strtobool(buf, &val);
789 if (ret < 0)
790 return ret;
791
792 mutex_lock(&indio_dev->mlock);
793 if (iio_buffer_enabled(indio_dev)) {
794 mutex_unlock(&indio_dev->mlock);
795 return -EBUSY;
796 }
797
798 switch (this_attr->address) {
799 case AD7192_REG_GPOCON:
800 if (val)
801 st->gpocon |= AD7192_GPOCON_BPDSW;
802 else
803 st->gpocon &= ~AD7192_GPOCON_BPDSW;
804
805 ad7192_write_reg(st, AD7192_REG_GPOCON, 1, st->gpocon);
806 break;
807 case AD7192_REG_MODE:
808 if (val)
809 st->mode |= AD7192_MODE_ACX;
810 else
811 st->mode &= ~AD7192_MODE_ACX;
812
813 ad7192_write_reg(st, AD7192_REG_GPOCON, 3, st->mode);
814 break;
815 default:
816 ret = -EINVAL;
817 }
818
819 mutex_unlock(&indio_dev->mlock);
820
821 return ret ? ret : len;
822 }
823
824 static IIO_DEVICE_ATTR(bridge_switch_en, S_IRUGO | S_IWUSR,
825 ad7192_show_bridge_switch, ad7192_set,
826 AD7192_REG_GPOCON);
827
828 static IIO_DEVICE_ATTR(ac_excitation_en, S_IRUGO | S_IWUSR,
829 ad7192_show_ac_excitation, ad7192_set,
830 AD7192_REG_MODE);
831
832 static struct attribute *ad7192_attributes[] = {
833 &iio_dev_attr_sampling_frequency.dev_attr.attr,
834 &iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr,
835 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
836 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
837 &iio_dev_attr_ac_excitation_en.dev_attr.attr,
838 NULL
839 };
840
841 static mode_t ad7192_attr_is_visible(struct kobject *kobj,
842 struct attribute *attr, int n)
843 {
844 struct device *dev = container_of(kobj, struct device, kobj);
845 struct iio_dev *indio_dev = dev_get_drvdata(dev);
846 struct ad7192_state *st = iio_priv(indio_dev);
847
848 mode_t mode = attr->mode;
849
850 if ((st->devid != ID_AD7195) &&
851 (attr == &iio_dev_attr_ac_excitation_en.dev_attr.attr))
852 mode = 0;
853
854 return mode;
855 }
856
857 static const struct attribute_group ad7192_attribute_group = {
858 .attrs = ad7192_attributes,
859 .is_visible = ad7192_attr_is_visible,
860 };
861
862 static int ad7192_read_raw(struct iio_dev *indio_dev,
863 struct iio_chan_spec const *chan,
864 int *val,
865 int *val2,
866 long m)
867 {
868 struct ad7192_state *st = iio_priv(indio_dev);
869 int ret, smpl = 0;
870 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
871
872 switch (m) {
873 case 0:
874 mutex_lock(&indio_dev->mlock);
875 if (iio_buffer_enabled(indio_dev))
876 ret = ad7192_scan_from_ring(st,
877 chan->scan_index, &smpl);
878 else
879 ret = ad7192_read(st, chan->address,
880 chan->scan_type.realbits / 8, &smpl);
881 mutex_unlock(&indio_dev->mlock);
882
883 if (ret < 0)
884 return ret;
885
886 *val = (smpl >> chan->scan_type.shift) &
887 ((1 << (chan->scan_type.realbits)) - 1);
888
889 switch (chan->type) {
890 case IIO_VOLTAGE:
891 if (!unipolar)
892 *val -= (1 << (chan->scan_type.realbits - 1));
893 break;
894 case IIO_TEMP:
895 *val -= 0x800000;
896 *val /= 2815; /* temp Kelvin */
897 *val -= 273; /* temp Celsius */
898 break;
899 default:
900 return -EINVAL;
901 }
902 return IIO_VAL_INT;
903
904 case (1 << IIO_CHAN_INFO_SCALE_SHARED):
905 mutex_lock(&indio_dev->mlock);
906 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
907 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
908 mutex_unlock(&indio_dev->mlock);
909
910 return IIO_VAL_INT_PLUS_NANO;
911
912 case (1 << IIO_CHAN_INFO_SCALE_SEPARATE):
913 *val = 1000;
914
915 return IIO_VAL_INT;
916 }
917
918 return -EINVAL;
919 }
920
921 static int ad7192_write_raw(struct iio_dev *indio_dev,
922 struct iio_chan_spec const *chan,
923 int val,
924 int val2,
925 long mask)
926 {
927 struct ad7192_state *st = iio_priv(indio_dev);
928 int ret, i;
929 unsigned int tmp;
930
931 mutex_lock(&indio_dev->mlock);
932 if (iio_buffer_enabled(indio_dev)) {
933 mutex_unlock(&indio_dev->mlock);
934 return -EBUSY;
935 }
936
937 switch (mask) {
938 case (1 << IIO_CHAN_INFO_SCALE_SHARED):
939 ret = -EINVAL;
940 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
941 if (val2 == st->scale_avail[i][1]) {
942 tmp = st->conf;
943 st->conf &= ~AD7192_CONF_GAIN(-1);
944 st->conf |= AD7192_CONF_GAIN(i);
945
946 if (tmp != st->conf) {
947 ad7192_write_reg(st, AD7192_REG_CONF,
948 3, st->conf);
949 ad7192_calibrate_all(st);
950 }
951 ret = 0;
952 }
953
954 default:
955 ret = -EINVAL;
956 }
957
958 mutex_unlock(&indio_dev->mlock);
959
960 return ret;
961 }
962
963 static int ad7192_validate_trigger(struct iio_dev *indio_dev,
964 struct iio_trigger *trig)
965 {
966 if (indio_dev->trig != trig)
967 return -EINVAL;
968
969 return 0;
970 }
971
972 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
973 struct iio_chan_spec const *chan,
974 long mask)
975 {
976 return IIO_VAL_INT_PLUS_NANO;
977 }
978
979 static const struct iio_info ad7192_info = {
980 .read_raw = &ad7192_read_raw,
981 .write_raw = &ad7192_write_raw,
982 .write_raw_get_fmt = &ad7192_write_raw_get_fmt,
983 .attrs = &ad7192_attribute_group,
984 .validate_trigger = ad7192_validate_trigger,
985 .driver_module = THIS_MODULE,
986 };
987
988 #define AD7192_CHAN_DIFF(_chan, _chan2, _name, _address, _si) \
989 { .type = IIO_VOLTAGE, \
990 .differential = 1, \
991 .indexed = 1, \
992 .extend_name = _name, \
993 .channel = _chan, \
994 .channel2 = _chan2, \
995 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED), \
996 .address = _address, \
997 .scan_index = _si, \
998 .scan_type = IIO_ST('s', 24, 32, 0)}
999
1000 #define AD7192_CHAN(_chan, _address, _si) \
1001 { .type = IIO_VOLTAGE, \
1002 .indexed = 1, \
1003 .channel = _chan, \
1004 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED), \
1005 .address = _address, \
1006 .scan_index = _si, \
1007 .scan_type = IIO_ST('s', 24, 32, 0)}
1008
1009 #define AD7192_CHAN_TEMP(_chan, _address, _si) \
1010 { .type = IIO_TEMP, \
1011 .indexed = 1, \
1012 .channel = _chan, \
1013 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SEPARATE), \
1014 .address = _address, \
1015 .scan_index = _si, \
1016 .scan_type = IIO_ST('s', 24, 32, 0)}
1017
1018 static struct iio_chan_spec ad7192_channels[] = {
1019 AD7192_CHAN_DIFF(1, 2, NULL, AD7192_CH_AIN1P_AIN2M, 0),
1020 AD7192_CHAN_DIFF(3, 4, NULL, AD7192_CH_AIN3P_AIN4M, 1),
1021 AD7192_CHAN_TEMP(0, AD7192_CH_TEMP, 2),
1022 AD7192_CHAN_DIFF(2, 2, "shorted", AD7192_CH_AIN2P_AIN2M, 3),
1023 AD7192_CHAN(1, AD7192_CH_AIN1, 4),
1024 AD7192_CHAN(2, AD7192_CH_AIN2, 5),
1025 AD7192_CHAN(3, AD7192_CH_AIN3, 6),
1026 AD7192_CHAN(4, AD7192_CH_AIN4, 7),
1027 IIO_CHAN_SOFT_TIMESTAMP(8),
1028 };
1029
1030 static int __devinit ad7192_probe(struct spi_device *spi)
1031 {
1032 struct ad7192_platform_data *pdata = spi->dev.platform_data;
1033 struct ad7192_state *st;
1034 struct iio_dev *indio_dev;
1035 int ret, i , voltage_uv = 0, regdone = 0;
1036
1037 if (!pdata) {
1038 dev_err(&spi->dev, "no platform data?\n");
1039 return -ENODEV;
1040 }
1041
1042 if (!spi->irq) {
1043 dev_err(&spi->dev, "no IRQ?\n");
1044 return -ENODEV;
1045 }
1046
1047 indio_dev = iio_allocate_device(sizeof(*st));
1048 if (indio_dev == NULL)
1049 return -ENOMEM;
1050
1051 st = iio_priv(indio_dev);
1052
1053 st->reg = regulator_get(&spi->dev, "vcc");
1054 if (!IS_ERR(st->reg)) {
1055 ret = regulator_enable(st->reg);
1056 if (ret)
1057 goto error_put_reg;
1058
1059 voltage_uv = regulator_get_voltage(st->reg);
1060 }
1061
1062 st->pdata = pdata;
1063
1064 if (pdata && pdata->vref_mv)
1065 st->int_vref_mv = pdata->vref_mv;
1066 else if (voltage_uv)
1067 st->int_vref_mv = voltage_uv / 1000;
1068 else
1069 dev_warn(&spi->dev, "reference voltage undefined\n");
1070
1071 spi_set_drvdata(spi, indio_dev);
1072 st->spi = spi;
1073 st->devid = spi_get_device_id(spi)->driver_data;
1074 indio_dev->dev.parent = &spi->dev;
1075 indio_dev->name = spi_get_device_id(spi)->name;
1076 indio_dev->modes = INDIO_DIRECT_MODE;
1077 indio_dev->channels = ad7192_channels;
1078 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
1079 indio_dev->available_scan_masks = st->available_scan_masks;
1080 indio_dev->info = &ad7192_info;
1081
1082 for (i = 0; i < indio_dev->num_channels; i++)
1083 st->available_scan_masks[i] = (1 << i) | (1 <<
1084 indio_dev->channels[indio_dev->num_channels - 1].
1085 scan_index);
1086
1087 init_waitqueue_head(&st->wq_data_avail);
1088
1089 ret = ad7192_register_ring_funcs_and_init(indio_dev);
1090 if (ret)
1091 goto error_disable_reg;
1092
1093 ret = iio_device_register(indio_dev);
1094 if (ret)
1095 goto error_unreg_ring;
1096 regdone = 1;
1097
1098 ret = ad7192_probe_trigger(indio_dev);
1099 if (ret)
1100 goto error_unreg_ring;
1101
1102 ret = iio_buffer_register(indio_dev,
1103 indio_dev->channels,
1104 indio_dev->num_channels);
1105 if (ret)
1106 goto error_remove_trigger;
1107
1108 ret = ad7192_setup(st);
1109 if (ret)
1110 goto error_uninitialize_ring;
1111
1112 return 0;
1113
1114 error_uninitialize_ring:
1115 iio_buffer_unregister(indio_dev);
1116 error_remove_trigger:
1117 ad7192_remove_trigger(indio_dev);
1118 error_unreg_ring:
1119 ad7192_ring_cleanup(indio_dev);
1120 error_disable_reg:
1121 if (!IS_ERR(st->reg))
1122 regulator_disable(st->reg);
1123 error_put_reg:
1124 if (!IS_ERR(st->reg))
1125 regulator_put(st->reg);
1126
1127 if (regdone)
1128 iio_device_unregister(indio_dev);
1129 else
1130 iio_free_device(indio_dev);
1131
1132 return ret;
1133 }
1134
1135 static int ad7192_remove(struct spi_device *spi)
1136 {
1137 struct iio_dev *indio_dev = spi_get_drvdata(spi);
1138 struct ad7192_state *st = iio_priv(indio_dev);
1139
1140 iio_buffer_unregister(indio_dev);
1141 ad7192_remove_trigger(indio_dev);
1142 ad7192_ring_cleanup(indio_dev);
1143
1144 if (!IS_ERR(st->reg)) {
1145 regulator_disable(st->reg);
1146 regulator_put(st->reg);
1147 }
1148
1149 iio_device_unregister(indio_dev);
1150
1151 return 0;
1152 }
1153
1154 static const struct spi_device_id ad7192_id[] = {
1155 {"ad7190", ID_AD7190},
1156 {"ad7192", ID_AD7192},
1157 {"ad7195", ID_AD7195},
1158 {}
1159 };
1160
1161 static struct spi_driver ad7192_driver = {
1162 .driver = {
1163 .name = "ad7192",
1164 .owner = THIS_MODULE,
1165 },
1166 .probe = ad7192_probe,
1167 .remove = __devexit_p(ad7192_remove),
1168 .id_table = ad7192_id,
1169 };
1170
1171 static int __init ad7192_init(void)
1172 {
1173 return spi_register_driver(&ad7192_driver);
1174 }
1175 module_init(ad7192_init);
1176
1177 static void __exit ad7192_exit(void)
1178 {
1179 spi_unregister_driver(&ad7192_driver);
1180 }
1181 module_exit(ad7192_exit);
1182
1183 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
1184 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7195 ADC");
1185 MODULE_LICENSE("GPL v2");
Linus' kernel tree