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musb: proper hookup to transceiver drivers
[linux-2.6.git] / drivers / usb / musb / musb_host.c
blob0d1f15336a9c06652f9e077b686df95b6bfdfbfd
1 /*
2 * MUSB OTG driver host support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/delay.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/errno.h>
42 #include <linux/init.h>
43 #include <linux/list.h>
44
45 #include "musb_core.h"
46 #include "musb_host.h"
47
48
49 /* MUSB HOST status 22-mar-2006
50 *
51 * - There's still lots of partial code duplication for fault paths, so
52 * they aren't handled as consistently as they need to be.
53 *
54 * - PIO mostly behaved when last tested.
55 * + including ep0, with all usbtest cases 9, 10
56 * + usbtest 14 (ep0out) doesn't seem to run at all
57 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
58 * configurations, but otherwise double buffering passes basic tests.
59 * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
60 *
61 * - DMA (CPPI) ... partially behaves, not currently recommended
62 * + about 1/15 the speed of typical EHCI implementations (PCI)
63 * + RX, all too often reqpkt seems to misbehave after tx
64 * + TX, no known issues (other than evident silicon issue)
65 *
66 * - DMA (Mentor/OMAP) ...has at least toggle update problems
67 *
68 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet
69 * starvation ... nothing yet for TX, interrupt, or bulk.
70 *
71 * - Not tested with HNP, but some SRP paths seem to behave.
72 *
73 * NOTE 24-August-2006:
74 *
75 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
76 * extra endpoint for periodic use enabling hub + keybd + mouse. That
77 * mostly works, except that with "usbnet" it's easy to trigger cases
78 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
79 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
80 * although ARP RX wins. (That test was done with a full speed link.)
81 */
82
83
84 /*
85 * NOTE on endpoint usage:
86 *
87 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
88 * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
89 * (Yes, bulk _could_ use more of the endpoints than that, and would even
90 * benefit from it.)
91 *
92 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
93 * So far that scheduling is both dumb and optimistic: the endpoint will be
94 * "claimed" until its software queue is no longer refilled. No multiplexing
95 * of transfers between endpoints, or anything clever.
96 */
97
98
99 static void musb_ep_program(struct musb *musb, u8 epnum,
100 struct urb *urb, int is_out,
101 u8 *buf, u32 offset, u32 len);
102
103 /*
104 * Clear TX fifo. Needed to avoid BABBLE errors.
105 */
106 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
107 {
108 void __iomem *epio = ep->regs;
109 u16 csr;
110 u16 lastcsr = 0;
111 int retries = 1000;
112
113 csr = musb_readw(epio, MUSB_TXCSR);
114 while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
115 if (csr != lastcsr)
116 DBG(3, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
117 lastcsr = csr;
118 csr |= MUSB_TXCSR_FLUSHFIFO;
119 musb_writew(epio, MUSB_TXCSR, csr);
120 csr = musb_readw(epio, MUSB_TXCSR);
121 if (WARN(retries-- < 1,
122 "Could not flush host TX%d fifo: csr: %04x\n",
123 ep->epnum, csr))
124 return;
125 mdelay(1);
126 }
127 }
128
129 static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep)
130 {
131 void __iomem *epio = ep->regs;
132 u16 csr;
133 int retries = 5;
134
135 /* scrub any data left in the fifo */
136 do {
137 csr = musb_readw(epio, MUSB_TXCSR);
138 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY)))
139 break;
140 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO);
141 csr = musb_readw(epio, MUSB_TXCSR);
142 udelay(10);
143 } while (--retries);
144
145 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n",
146 ep->epnum, csr);
147
148 /* and reset for the next transfer */
149 musb_writew(epio, MUSB_TXCSR, 0);
150 }
151
152 /*
153 * Start transmit. Caller is responsible for locking shared resources.
154 * musb must be locked.
155 */
156 static inline void musb_h_tx_start(struct musb_hw_ep *ep)
157 {
158 u16 txcsr;
159
160 /* NOTE: no locks here; caller should lock and select EP */
161 if (ep->epnum) {
162 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
163 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS;
164 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
165 } else {
166 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY;
167 musb_writew(ep->regs, MUSB_CSR0, txcsr);
168 }
169
170 }
171
172 static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
173 {
174 u16 txcsr;
175
176 /* NOTE: no locks here; caller should lock and select EP */
177 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
178 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
179 if (is_cppi_enabled())
180 txcsr |= MUSB_TXCSR_DMAMODE;
181 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
182 }
183
184 static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)
185 {
186 if (is_in != 0 || ep->is_shared_fifo)
187 ep->in_qh = qh;
188 if (is_in == 0 || ep->is_shared_fifo)
189 ep->out_qh = qh;
190 }
191
192 static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)
193 {
194 return is_in ? ep->in_qh : ep->out_qh;
195 }
196
197 /*
198 * Start the URB at the front of an endpoint's queue
199 * end must be claimed from the caller.
200 *
201 * Context: controller locked, irqs blocked
202 */
203 static void
204 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
205 {
206 u16 frame;
207 u32 len;
208 void __iomem *mbase = musb->mregs;
209 struct urb *urb = next_urb(qh);
210 void *buf = urb->transfer_buffer;
211 u32 offset = 0;
212 struct musb_hw_ep *hw_ep = qh->hw_ep;
213 unsigned pipe = urb->pipe;
214 u8 address = usb_pipedevice(pipe);
215 int epnum = hw_ep->epnum;
216
217 /* initialize software qh state */
218 qh->offset = 0;
219 qh->segsize = 0;
220
221 /* gather right source of data */
222 switch (qh->type) {
223 case USB_ENDPOINT_XFER_CONTROL:
224 /* control transfers always start with SETUP */
225 is_in = 0;
226 musb->ep0_stage = MUSB_EP0_START;
227 buf = urb->setup_packet;
228 len = 8;
229 break;
230 case USB_ENDPOINT_XFER_ISOC:
231 qh->iso_idx = 0;
232 qh->frame = 0;
233 offset = urb->iso_frame_desc[0].offset;
234 len = urb->iso_frame_desc[0].length;
235 break;
236 default: /* bulk, interrupt */
237 /* actual_length may be nonzero on retry paths */
238 buf = urb->transfer_buffer + urb->actual_length;
239 len = urb->transfer_buffer_length - urb->actual_length;
240 }
241
242 DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
243 qh, urb, address, qh->epnum,
244 is_in ? "in" : "out",
245 ({char *s; switch (qh->type) {
246 case USB_ENDPOINT_XFER_CONTROL: s = ""; break;
247 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break;
248 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
249 default: s = "-intr"; break;
250 }; s; }),
251 epnum, buf + offset, len);
252
253 /* Configure endpoint */
254 musb_ep_set_qh(hw_ep, is_in, qh);
255 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
256
257 /* transmit may have more work: start it when it is time */
258 if (is_in)
259 return;
260
261 /* determine if the time is right for a periodic transfer */
262 switch (qh->type) {
263 case USB_ENDPOINT_XFER_ISOC:
264 case USB_ENDPOINT_XFER_INT:
265 DBG(3, "check whether there's still time for periodic Tx\n");
266 frame = musb_readw(mbase, MUSB_FRAME);
267 /* FIXME this doesn't implement that scheduling policy ...
268 * or handle framecounter wrapping
269 */
270 if ((urb->transfer_flags & URB_ISO_ASAP)
271 || (frame >= urb->start_frame)) {
272 /* REVISIT the SOF irq handler shouldn't duplicate
273 * this code; and we don't init urb->start_frame...
274 */
275 qh->frame = 0;
276 goto start;
277 } else {
278 qh->frame = urb->start_frame;
279 /* enable SOF interrupt so we can count down */
280 DBG(1, "SOF for %d\n", epnum);
281 #if 1 /* ifndef CONFIG_ARCH_DAVINCI */
282 musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
283 #endif
284 }
285 break;
286 default:
287 start:
288 DBG(4, "Start TX%d %s\n", epnum,
289 hw_ep->tx_channel ? "dma" : "pio");
290
291 if (!hw_ep->tx_channel)
292 musb_h_tx_start(hw_ep);
293 else if (is_cppi_enabled() || tusb_dma_omap())
294 musb_h_tx_dma_start(hw_ep);
295 }
296 }
297
298 /* Context: caller owns controller lock, IRQs are blocked */
299 static void musb_giveback(struct musb *musb, struct urb *urb, int status)
300 __releases(musb->lock)
301 __acquires(musb->lock)
302 {
303 DBG(({ int level; switch (status) {
304 case 0:
305 level = 4;
306 break;
307 /* common/boring faults */
308 case -EREMOTEIO:
309 case -ESHUTDOWN:
310 case -ECONNRESET:
311 case -EPIPE:
312 level = 3;
313 break;
314 default:
315 level = 2;
316 break;
317 }; level; }),
318 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
319 urb, urb->complete, status,
320 usb_pipedevice(urb->pipe),
321 usb_pipeendpoint(urb->pipe),
322 usb_pipein(urb->pipe) ? "in" : "out",
323 urb->actual_length, urb->transfer_buffer_length
324 );
325
326 usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
327 spin_unlock(&musb->lock);
328 usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status);
329 spin_lock(&musb->lock);
330 }
331
332 /* For bulk/interrupt endpoints only */
333 static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
334 struct urb *urb)
335 {
336 void __iomem *epio = qh->hw_ep->regs;
337 u16 csr;
338
339 /*
340 * FIXME: the current Mentor DMA code seems to have
341 * problems getting toggle correct.
342 */
343
344 if (is_in)
345 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
346 else
347 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
348
349 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
350 }
351
352 /*
353 * Advance this hardware endpoint's queue, completing the specified URB and
354 * advancing to either the next URB queued to that qh, or else invalidating
355 * that qh and advancing to the next qh scheduled after the current one.
356 *
357 * Context: caller owns controller lock, IRQs are blocked
358 */
359 static void musb_advance_schedule(struct musb *musb, struct urb *urb,
360 struct musb_hw_ep *hw_ep, int is_in)
361 {
362 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in);
363 struct musb_hw_ep *ep = qh->hw_ep;
364 int ready = qh->is_ready;
365 int status;
366
367 status = (urb->status == -EINPROGRESS) ? 0 : urb->status;
368
369 /* save toggle eagerly, for paranoia */
370 switch (qh->type) {
371 case USB_ENDPOINT_XFER_BULK:
372 case USB_ENDPOINT_XFER_INT:
373 musb_save_toggle(qh, is_in, urb);
374 break;
375 case USB_ENDPOINT_XFER_ISOC:
376 if (urb->error_count)
377 status = -EXDEV;
378 break;
379 }
380
381 qh->is_ready = 0;
382 musb_giveback(musb, urb, status);
383 qh->is_ready = ready;
384
385 /* reclaim resources (and bandwidth) ASAP; deschedule it, and
386 * invalidate qh as soon as list_empty(&hep->urb_list)
387 */
388 if (list_empty(&qh->hep->urb_list)) {
389 struct list_head *head;
390
391 if (is_in)
392 ep->rx_reinit = 1;
393 else
394 ep->tx_reinit = 1;
395
396 /* Clobber old pointers to this qh */
397 musb_ep_set_qh(ep, is_in, NULL);
398 qh->hep->hcpriv = NULL;
399
400 switch (qh->type) {
401
402 case USB_ENDPOINT_XFER_CONTROL:
403 case USB_ENDPOINT_XFER_BULK:
404 /* fifo policy for these lists, except that NAKing
405 * should rotate a qh to the end (for fairness).
406 */
407 if (qh->mux == 1) {
408 head = qh->ring.prev;
409 list_del(&qh->ring);
410 kfree(qh);
411 qh = first_qh(head);
412 break;
413 }
414
415 case USB_ENDPOINT_XFER_ISOC:
416 case USB_ENDPOINT_XFER_INT:
417 /* this is where periodic bandwidth should be
418 * de-allocated if it's tracked and allocated;
419 * and where we'd update the schedule tree...
420 */
421 kfree(qh);
422 qh = NULL;
423 break;
424 }
425 }
426
427 if (qh != NULL && qh->is_ready) {
428 DBG(4, "... next ep%d %cX urb %p\n",
429 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
430 musb_start_urb(musb, is_in, qh);
431 }
432 }
433
434 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
435 {
436 /* we don't want fifo to fill itself again;
437 * ignore dma (various models),
438 * leave toggle alone (may not have been saved yet)
439 */
440 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
441 csr &= ~(MUSB_RXCSR_H_REQPKT
442 | MUSB_RXCSR_H_AUTOREQ
443 | MUSB_RXCSR_AUTOCLEAR);
444
445 /* write 2x to allow double buffering */
446 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
447 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
448
449 /* flush writebuffer */
450 return musb_readw(hw_ep->regs, MUSB_RXCSR);
451 }
452
453 /*
454 * PIO RX for a packet (or part of it).
455 */
456 static bool
457 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
458 {
459 u16 rx_count;
460 u8 *buf;
461 u16 csr;
462 bool done = false;
463 u32 length;
464 int do_flush = 0;
465 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
466 void __iomem *epio = hw_ep->regs;
467 struct musb_qh *qh = hw_ep->in_qh;
468 int pipe = urb->pipe;
469 void *buffer = urb->transfer_buffer;
470
471 /* musb_ep_select(mbase, epnum); */
472 rx_count = musb_readw(epio, MUSB_RXCOUNT);
473 DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
474 urb->transfer_buffer, qh->offset,
475 urb->transfer_buffer_length);
476
477 /* unload FIFO */
478 if (usb_pipeisoc(pipe)) {
479 int status = 0;
480 struct usb_iso_packet_descriptor *d;
481
482 if (iso_err) {
483 status = -EILSEQ;
484 urb->error_count++;
485 }
486
487 d = urb->iso_frame_desc + qh->iso_idx;
488 buf = buffer + d->offset;
489 length = d->length;
490 if (rx_count > length) {
491 if (status == 0) {
492 status = -EOVERFLOW;
493 urb->error_count++;
494 }
495 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
496 do_flush = 1;
497 } else
498 length = rx_count;
499 urb->actual_length += length;
500 d->actual_length = length;
501
502 d->status = status;
503
504 /* see if we are done */
505 done = (++qh->iso_idx >= urb->number_of_packets);
506 } else {
507 /* non-isoch */
508 buf = buffer + qh->offset;
509 length = urb->transfer_buffer_length - qh->offset;
510 if (rx_count > length) {
511 if (urb->status == -EINPROGRESS)
512 urb->status = -EOVERFLOW;
513 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
514 do_flush = 1;
515 } else
516 length = rx_count;
517 urb->actual_length += length;
518 qh->offset += length;
519
520 /* see if we are done */
521 done = (urb->actual_length == urb->transfer_buffer_length)
522 || (rx_count < qh->maxpacket)
523 || (urb->status != -EINPROGRESS);
524 if (done
525 && (urb->status == -EINPROGRESS)
526 && (urb->transfer_flags & URB_SHORT_NOT_OK)
527 && (urb->actual_length
528 < urb->transfer_buffer_length))
529 urb->status = -EREMOTEIO;
530 }
531
532 musb_read_fifo(hw_ep, length, buf);
533
534 csr = musb_readw(epio, MUSB_RXCSR);
535 csr |= MUSB_RXCSR_H_WZC_BITS;
536 if (unlikely(do_flush))
537 musb_h_flush_rxfifo(hw_ep, csr);
538 else {
539 /* REVISIT this assumes AUTOCLEAR is never set */
540 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
541 if (!done)
542 csr |= MUSB_RXCSR_H_REQPKT;
543 musb_writew(epio, MUSB_RXCSR, csr);
544 }
545
546 return done;
547 }
548
549 /* we don't always need to reinit a given side of an endpoint...
550 * when we do, use tx/rx reinit routine and then construct a new CSR
551 * to address data toggle, NYET, and DMA or PIO.
552 *
553 * it's possible that driver bugs (especially for DMA) or aborting a
554 * transfer might have left the endpoint busier than it should be.
555 * the busy/not-empty tests are basically paranoia.
556 */
557 static void
558 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
559 {
560 u16 csr;
561
562 /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
563 * That always uses tx_reinit since ep0 repurposes TX register
564 * offsets; the initial SETUP packet is also a kind of OUT.
565 */
566
567 /* if programmed for Tx, put it in RX mode */
568 if (ep->is_shared_fifo) {
569 csr = musb_readw(ep->regs, MUSB_TXCSR);
570 if (csr & MUSB_TXCSR_MODE) {
571 musb_h_tx_flush_fifo(ep);
572 csr = musb_readw(ep->regs, MUSB_TXCSR);
573 musb_writew(ep->regs, MUSB_TXCSR,
574 csr | MUSB_TXCSR_FRCDATATOG);
575 }
576
577 /*
578 * Clear the MODE bit (and everything else) to enable Rx.
579 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB.
580 */
581 if (csr & MUSB_TXCSR_DMAMODE)
582 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE);
583 musb_writew(ep->regs, MUSB_TXCSR, 0);
584
585 /* scrub all previous state, clearing toggle */
586 } else {
587 csr = musb_readw(ep->regs, MUSB_RXCSR);
588 if (csr & MUSB_RXCSR_RXPKTRDY)
589 WARNING("rx%d, packet/%d ready?\n", ep->epnum,
590 musb_readw(ep->regs, MUSB_RXCOUNT));
591
592 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);
593 }
594
595 /* target addr and (for multipoint) hub addr/port */
596 if (musb->is_multipoint) {
597 musb_write_rxfunaddr(ep->target_regs, qh->addr_reg);
598 musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg);
599 musb_write_rxhubport(ep->target_regs, qh->h_port_reg);
600
601 } else
602 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
603
604 /* protocol/endpoint, interval/NAKlimit, i/o size */
605 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
606 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
607 /* NOTE: bulk combining rewrites high bits of maxpacket */
608 musb_writew(ep->regs, MUSB_RXMAXP, qh->maxpacket);
609
610 ep->rx_reinit = 0;
611 }
612
613 static bool musb_tx_dma_program(struct dma_controller *dma,
614 struct musb_hw_ep *hw_ep, struct musb_qh *qh,
615 struct urb *urb, u32 offset, u32 length)
616 {
617 struct dma_channel *channel = hw_ep->tx_channel;
618 void __iomem *epio = hw_ep->regs;
619 u16 pkt_size = qh->maxpacket;
620 u16 csr;
621 u8 mode;
622
623 #ifdef CONFIG_USB_INVENTRA_DMA
624 if (length > channel->max_len)
625 length = channel->max_len;
626
627 csr = musb_readw(epio, MUSB_TXCSR);
628 if (length > pkt_size) {
629 mode = 1;
630 csr |= MUSB_TXCSR_AUTOSET
631 | MUSB_TXCSR_DMAMODE
632 | MUSB_TXCSR_DMAENAB;
633 } else {
634 mode = 0;
635 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
636 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */
637 }
638 channel->desired_mode = mode;
639 musb_writew(epio, MUSB_TXCSR, csr);
640 #else
641 if (!is_cppi_enabled() && !tusb_dma_omap())
642 return false;
643
644 channel->actual_len = 0;
645
646 /*
647 * TX uses "RNDIS" mode automatically but needs help
648 * to identify the zero-length-final-packet case.
649 */
650 mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
651 #endif
652
653 qh->segsize = length;
654
655 if (!dma->channel_program(channel, pkt_size, mode,
656 urb->transfer_dma + offset, length)) {
657 dma->channel_release(channel);
658 hw_ep->tx_channel = NULL;
659
660 csr = musb_readw(epio, MUSB_TXCSR);
661 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
662 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS);
663 return false;
664 }
665 return true;
666 }
667
668 /*
669 * Program an HDRC endpoint as per the given URB
670 * Context: irqs blocked, controller lock held
671 */
672 static void musb_ep_program(struct musb *musb, u8 epnum,
673 struct urb *urb, int is_out,
674 u8 *buf, u32 offset, u32 len)
675 {
676 struct dma_controller *dma_controller;
677 struct dma_channel *dma_channel;
678 u8 dma_ok;
679 void __iomem *mbase = musb->mregs;
680 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
681 void __iomem *epio = hw_ep->regs;
682 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
683 u16 packet_sz = qh->maxpacket;
684
685 DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s "
686 "h_addr%02x h_port%02x bytes %d\n",
687 is_out ? "-->" : "<--",
688 epnum, urb, urb->dev->speed,
689 qh->addr_reg, qh->epnum, is_out ? "out" : "in",
690 qh->h_addr_reg, qh->h_port_reg,
691 len);
692
693 musb_ep_select(mbase, epnum);
694
695 /* candidate for DMA? */
696 dma_controller = musb->dma_controller;
697 if (is_dma_capable() && epnum && dma_controller) {
698 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
699 if (!dma_channel) {
700 dma_channel = dma_controller->channel_alloc(
701 dma_controller, hw_ep, is_out);
702 if (is_out)
703 hw_ep->tx_channel = dma_channel;
704 else
705 hw_ep->rx_channel = dma_channel;
706 }
707 } else
708 dma_channel = NULL;
709
710 /* make sure we clear DMAEnab, autoSet bits from previous run */
711
712 /* OUT/transmit/EP0 or IN/receive? */
713 if (is_out) {
714 u16 csr;
715 u16 int_txe;
716 u16 load_count;
717
718 csr = musb_readw(epio, MUSB_TXCSR);
719
720 /* disable interrupt in case we flush */
721 int_txe = musb_readw(mbase, MUSB_INTRTXE);
722 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
723
724 /* general endpoint setup */
725 if (epnum) {
726 /* flush all old state, set default */
727 musb_h_tx_flush_fifo(hw_ep);
728
729 /*
730 * We must not clear the DMAMODE bit before or in
731 * the same cycle with the DMAENAB bit, so we clear
732 * the latter first...
733 */
734 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
735 | MUSB_TXCSR_AUTOSET
736 | MUSB_TXCSR_DMAENAB
737 | MUSB_TXCSR_FRCDATATOG
738 | MUSB_TXCSR_H_RXSTALL
739 | MUSB_TXCSR_H_ERROR
740 | MUSB_TXCSR_TXPKTRDY
741 );
742 csr |= MUSB_TXCSR_MODE;
743
744 if (usb_gettoggle(urb->dev, qh->epnum, 1))
745 csr |= MUSB_TXCSR_H_WR_DATATOGGLE
746 | MUSB_TXCSR_H_DATATOGGLE;
747 else
748 csr |= MUSB_TXCSR_CLRDATATOG;
749
750 musb_writew(epio, MUSB_TXCSR, csr);
751 /* REVISIT may need to clear FLUSHFIFO ... */
752 csr &= ~MUSB_TXCSR_DMAMODE;
753 musb_writew(epio, MUSB_TXCSR, csr);
754 csr = musb_readw(epio, MUSB_TXCSR);
755 } else {
756 /* endpoint 0: just flush */
757 musb_h_ep0_flush_fifo(hw_ep);
758 }
759
760 /* target addr and (for multipoint) hub addr/port */
761 if (musb->is_multipoint) {
762 musb_write_txfunaddr(mbase, epnum, qh->addr_reg);
763 musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg);
764 musb_write_txhubport(mbase, epnum, qh->h_port_reg);
765 /* FIXME if !epnum, do the same for RX ... */
766 } else
767 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
768
769 /* protocol/endpoint/interval/NAKlimit */
770 if (epnum) {
771 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
772 if (can_bulk_split(musb, qh->type))
773 musb_writew(epio, MUSB_TXMAXP,
774 packet_sz
775 | ((hw_ep->max_packet_sz_tx /
776 packet_sz) - 1) << 11);
777 else
778 musb_writew(epio, MUSB_TXMAXP,
779 packet_sz);
780 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
781 } else {
782 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
783 if (musb->is_multipoint)
784 musb_writeb(epio, MUSB_TYPE0,
785 qh->type_reg);
786 }
787
788 if (can_bulk_split(musb, qh->type))
789 load_count = min((u32) hw_ep->max_packet_sz_tx,
790 len);
791 else
792 load_count = min((u32) packet_sz, len);
793
794 if (dma_channel && musb_tx_dma_program(dma_controller,
795 hw_ep, qh, urb, offset, len))
796 load_count = 0;
797
798 if (load_count) {
799 /* PIO to load FIFO */
800 qh->segsize = load_count;
801 musb_write_fifo(hw_ep, load_count, buf);
802 }
803
804 /* re-enable interrupt */
805 musb_writew(mbase, MUSB_INTRTXE, int_txe);
806
807 /* IN/receive */
808 } else {
809 u16 csr;
810
811 if (hw_ep->rx_reinit) {
812 musb_rx_reinit(musb, qh, hw_ep);
813
814 /* init new state: toggle and NYET, maybe DMA later */
815 if (usb_gettoggle(urb->dev, qh->epnum, 0))
816 csr = MUSB_RXCSR_H_WR_DATATOGGLE
817 | MUSB_RXCSR_H_DATATOGGLE;
818 else
819 csr = 0;
820 if (qh->type == USB_ENDPOINT_XFER_INT)
821 csr |= MUSB_RXCSR_DISNYET;
822
823 } else {
824 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
825
826 if (csr & (MUSB_RXCSR_RXPKTRDY
827 | MUSB_RXCSR_DMAENAB
828 | MUSB_RXCSR_H_REQPKT))
829 ERR("broken !rx_reinit, ep%d csr %04x\n",
830 hw_ep->epnum, csr);
831
832 /* scrub any stale state, leaving toggle alone */
833 csr &= MUSB_RXCSR_DISNYET;
834 }
835
836 /* kick things off */
837
838 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
839 /* candidate for DMA */
840 if (dma_channel) {
841 dma_channel->actual_len = 0L;
842 qh->segsize = len;
843
844 /* AUTOREQ is in a DMA register */
845 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
846 csr = musb_readw(hw_ep->regs,
847 MUSB_RXCSR);
848
849 /* unless caller treats short rx transfers as
850 * errors, we dare not queue multiple transfers.
851 */
852 dma_ok = dma_controller->channel_program(
853 dma_channel, packet_sz,
854 !(urb->transfer_flags
855 & URB_SHORT_NOT_OK),
856 urb->transfer_dma + offset,
857 qh->segsize);
858 if (!dma_ok) {
859 dma_controller->channel_release(
860 dma_channel);
861 hw_ep->rx_channel = NULL;
862 dma_channel = NULL;
863 } else
864 csr |= MUSB_RXCSR_DMAENAB;
865 }
866 }
867
868 csr |= MUSB_RXCSR_H_REQPKT;
869 DBG(7, "RXCSR%d := %04x\n", epnum, csr);
870 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
871 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
872 }
873 }
874
875
876 /*
877 * Service the default endpoint (ep0) as host.
878 * Return true until it's time to start the status stage.
879 */
880 static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
881 {
882 bool more = false;
883 u8 *fifo_dest = NULL;
884 u16 fifo_count = 0;
885 struct musb_hw_ep *hw_ep = musb->control_ep;
886 struct musb_qh *qh = hw_ep->in_qh;
887 struct usb_ctrlrequest *request;
888
889 switch (musb->ep0_stage) {
890 case MUSB_EP0_IN:
891 fifo_dest = urb->transfer_buffer + urb->actual_length;
892 fifo_count = min_t(size_t, len, urb->transfer_buffer_length -
893 urb->actual_length);
894 if (fifo_count < len)
895 urb->status = -EOVERFLOW;
896
897 musb_read_fifo(hw_ep, fifo_count, fifo_dest);
898
899 urb->actual_length += fifo_count;
900 if (len < qh->maxpacket) {
901 /* always terminate on short read; it's
902 * rarely reported as an error.
903 */
904 } else if (urb->actual_length <
905 urb->transfer_buffer_length)
906 more = true;
907 break;
908 case MUSB_EP0_START:
909 request = (struct usb_ctrlrequest *) urb->setup_packet;
910
911 if (!request->wLength) {
912 DBG(4, "start no-DATA\n");
913 break;
914 } else if (request->bRequestType & USB_DIR_IN) {
915 DBG(4, "start IN-DATA\n");
916 musb->ep0_stage = MUSB_EP0_IN;
917 more = true;
918 break;
919 } else {
920 DBG(4, "start OUT-DATA\n");
921 musb->ep0_stage = MUSB_EP0_OUT;
922 more = true;
923 }
924 /* FALLTHROUGH */
925 case MUSB_EP0_OUT:
926 fifo_count = min_t(size_t, qh->maxpacket,
927 urb->transfer_buffer_length -
928 urb->actual_length);
929 if (fifo_count) {
930 fifo_dest = (u8 *) (urb->transfer_buffer
931 + urb->actual_length);
932 DBG(3, "Sending %d byte%s to ep0 fifo %p\n",
933 fifo_count,
934 (fifo_count == 1) ? "" : "s",
935 fifo_dest);
936 musb_write_fifo(hw_ep, fifo_count, fifo_dest);
937
938 urb->actual_length += fifo_count;
939 more = true;
940 }
941 break;
942 default:
943 ERR("bogus ep0 stage %d\n", musb->ep0_stage);
944 break;
945 }
946
947 return more;
948 }
949
950 /*
951 * Handle default endpoint interrupt as host. Only called in IRQ time
952 * from musb_interrupt().
953 *
954 * called with controller irqlocked
955 */
956 irqreturn_t musb_h_ep0_irq(struct musb *musb)
957 {
958 struct urb *urb;
959 u16 csr, len;
960 int status = 0;
961 void __iomem *mbase = musb->mregs;
962 struct musb_hw_ep *hw_ep = musb->control_ep;
963 void __iomem *epio = hw_ep->regs;
964 struct musb_qh *qh = hw_ep->in_qh;
965 bool complete = false;
966 irqreturn_t retval = IRQ_NONE;
967
968 /* ep0 only has one queue, "in" */
969 urb = next_urb(qh);
970
971 musb_ep_select(mbase, 0);
972 csr = musb_readw(epio, MUSB_CSR0);
973 len = (csr & MUSB_CSR0_RXPKTRDY)
974 ? musb_readb(epio, MUSB_COUNT0)
975 : 0;
976
977 DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
978 csr, qh, len, urb, musb->ep0_stage);
979
980 /* if we just did status stage, we are done */
981 if (MUSB_EP0_STATUS == musb->ep0_stage) {
982 retval = IRQ_HANDLED;
983 complete = true;
984 }
985
986 /* prepare status */
987 if (csr & MUSB_CSR0_H_RXSTALL) {
988 DBG(6, "STALLING ENDPOINT\n");
989 status = -EPIPE;
990
991 } else if (csr & MUSB_CSR0_H_ERROR) {
992 DBG(2, "no response, csr0 %04x\n", csr);
993 status = -EPROTO;
994
995 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
996 DBG(2, "control NAK timeout\n");
997
998 /* NOTE: this code path would be a good place to PAUSE a
999 * control transfer, if another one is queued, so that
1000 * ep0 is more likely to stay busy. That's already done
1001 * for bulk RX transfers.
1002 *
1003 * if (qh->ring.next != &musb->control), then
1004 * we have a candidate... NAKing is *NOT* an error
1005 */
1006 musb_writew(epio, MUSB_CSR0, 0);
1007 retval = IRQ_HANDLED;
1008 }
1009
1010 if (status) {
1011 DBG(6, "aborting\n");
1012 retval = IRQ_HANDLED;
1013 if (urb)
1014 urb->status = status;
1015 complete = true;
1016
1017 /* use the proper sequence to abort the transfer */
1018 if (csr & MUSB_CSR0_H_REQPKT) {
1019 csr &= ~MUSB_CSR0_H_REQPKT;
1020 musb_writew(epio, MUSB_CSR0, csr);
1021 csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
1022 musb_writew(epio, MUSB_CSR0, csr);
1023 } else {
1024 musb_h_ep0_flush_fifo(hw_ep);
1025 }
1026
1027 musb_writeb(epio, MUSB_NAKLIMIT0, 0);
1028
1029 /* clear it */
1030 musb_writew(epio, MUSB_CSR0, 0);
1031 }
1032
1033 if (unlikely(!urb)) {
1034 /* stop endpoint since we have no place for its data, this
1035 * SHOULD NEVER HAPPEN! */
1036 ERR("no URB for end 0\n");
1037
1038 musb_h_ep0_flush_fifo(hw_ep);
1039 goto done;
1040 }
1041
1042 if (!complete) {
1043 /* call common logic and prepare response */
1044 if (musb_h_ep0_continue(musb, len, urb)) {
1045 /* more packets required */
1046 csr = (MUSB_EP0_IN == musb->ep0_stage)
1047 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
1048 } else {
1049 /* data transfer complete; perform status phase */
1050 if (usb_pipeout(urb->pipe)
1051 || !urb->transfer_buffer_length)
1052 csr = MUSB_CSR0_H_STATUSPKT
1053 | MUSB_CSR0_H_REQPKT;
1054 else
1055 csr = MUSB_CSR0_H_STATUSPKT
1056 | MUSB_CSR0_TXPKTRDY;
1057
1058 /* flag status stage */
1059 musb->ep0_stage = MUSB_EP0_STATUS;
1060
1061 DBG(5, "ep0 STATUS, csr %04x\n", csr);
1062
1063 }
1064 musb_writew(epio, MUSB_CSR0, csr);
1065 retval = IRQ_HANDLED;
1066 } else
1067 musb->ep0_stage = MUSB_EP0_IDLE;
1068
1069 /* call completion handler if done */
1070 if (complete)
1071 musb_advance_schedule(musb, urb, hw_ep, 1);
1072 done:
1073 return retval;
1074 }
1075
1076
1077 #ifdef CONFIG_USB_INVENTRA_DMA
1078
1079 /* Host side TX (OUT) using Mentor DMA works as follows:
1080 submit_urb ->
1081 - if queue was empty, Program Endpoint
1082 - ... which starts DMA to fifo in mode 1 or 0
1083
1084 DMA Isr (transfer complete) -> TxAvail()
1085 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1086 only in musb_cleanup_urb)
1087 - TxPktRdy has to be set in mode 0 or for
1088 short packets in mode 1.
1089 */
1090
1091 #endif
1092
1093 /* Service a Tx-Available or dma completion irq for the endpoint */
1094 void musb_host_tx(struct musb *musb, u8 epnum)
1095 {
1096 int pipe;
1097 bool done = false;
1098 u16 tx_csr;
1099 size_t length = 0;
1100 size_t offset = 0;
1101 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1102 void __iomem *epio = hw_ep->regs;
1103 struct musb_qh *qh = hw_ep->out_qh;
1104 struct urb *urb = next_urb(qh);
1105 u32 status = 0;
1106 void __iomem *mbase = musb->mregs;
1107 struct dma_channel *dma;
1108
1109 musb_ep_select(mbase, epnum);
1110 tx_csr = musb_readw(epio, MUSB_TXCSR);
1111
1112 /* with CPPI, DMA sometimes triggers "extra" irqs */
1113 if (!urb) {
1114 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1115 return;
1116 }
1117
1118 pipe = urb->pipe;
1119 dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
1120 DBG(4, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
1121 dma ? ", dma" : "");
1122
1123 /* check for errors */
1124 if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
1125 /* dma was disabled, fifo flushed */
1126 DBG(3, "TX end %d stall\n", epnum);
1127
1128 /* stall; record URB status */
1129 status = -EPIPE;
1130
1131 } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
1132 /* (NON-ISO) dma was disabled, fifo flushed */
1133 DBG(3, "TX 3strikes on ep=%d\n", epnum);
1134
1135 status = -ETIMEDOUT;
1136
1137 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
1138 DBG(6, "TX end=%d device not responding\n", epnum);
1139
1140 /* NOTE: this code path would be a good place to PAUSE a
1141 * transfer, if there's some other (nonperiodic) tx urb
1142 * that could use this fifo. (dma complicates it...)
1143 * That's already done for bulk RX transfers.
1144 *
1145 * if (bulk && qh->ring.next != &musb->out_bulk), then
1146 * we have a candidate... NAKing is *NOT* an error
1147 */
1148 musb_ep_select(mbase, epnum);
1149 musb_writew(epio, MUSB_TXCSR,
1150 MUSB_TXCSR_H_WZC_BITS
1151 | MUSB_TXCSR_TXPKTRDY);
1152 return;
1153 }
1154
1155 if (status) {
1156 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1157 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1158 (void) musb->dma_controller->channel_abort(dma);
1159 }
1160
1161 /* do the proper sequence to abort the transfer in the
1162 * usb core; the dma engine should already be stopped.
1163 */
1164 musb_h_tx_flush_fifo(hw_ep);
1165 tx_csr &= ~(MUSB_TXCSR_AUTOSET
1166 | MUSB_TXCSR_DMAENAB
1167 | MUSB_TXCSR_H_ERROR
1168 | MUSB_TXCSR_H_RXSTALL
1169 | MUSB_TXCSR_H_NAKTIMEOUT
1170 );
1171
1172 musb_ep_select(mbase, epnum);
1173 musb_writew(epio, MUSB_TXCSR, tx_csr);
1174 /* REVISIT may need to clear FLUSHFIFO ... */
1175 musb_writew(epio, MUSB_TXCSR, tx_csr);
1176 musb_writeb(epio, MUSB_TXINTERVAL, 0);
1177
1178 done = true;
1179 }
1180
1181 /* second cppi case */
1182 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1183 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1184 return;
1185 }
1186
1187 if (is_dma_capable() && dma && !status) {
1188 /*
1189 * DMA has completed. But if we're using DMA mode 1 (multi
1190 * packet DMA), we need a terminal TXPKTRDY interrupt before
1191 * we can consider this transfer completed, lest we trash
1192 * its last packet when writing the next URB's data. So we
1193 * switch back to mode 0 to get that interrupt; we'll come
1194 * back here once it happens.
1195 */
1196 if (tx_csr & MUSB_TXCSR_DMAMODE) {
1197 /*
1198 * We shouldn't clear DMAMODE with DMAENAB set; so
1199 * clear them in a safe order. That should be OK
1200 * once TXPKTRDY has been set (and I've never seen
1201 * it being 0 at this moment -- DMA interrupt latency
1202 * is significant) but if it hasn't been then we have
1203 * no choice but to stop being polite and ignore the
1204 * programmer's guide... :-)
1205 *
1206 * Note that we must write TXCSR with TXPKTRDY cleared
1207 * in order not to re-trigger the packet send (this bit
1208 * can't be cleared by CPU), and there's another caveat:
1209 * TXPKTRDY may be set shortly and then cleared in the
1210 * double-buffered FIFO mode, so we do an extra TXCSR
1211 * read for debouncing...
1212 */
1213 tx_csr &= musb_readw(epio, MUSB_TXCSR);
1214 if (tx_csr & MUSB_TXCSR_TXPKTRDY) {
1215 tx_csr &= ~(MUSB_TXCSR_DMAENAB |
1216 MUSB_TXCSR_TXPKTRDY);
1217 musb_writew(epio, MUSB_TXCSR,
1218 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1219 }
1220 tx_csr &= ~(MUSB_TXCSR_DMAMODE |
1221 MUSB_TXCSR_TXPKTRDY);
1222 musb_writew(epio, MUSB_TXCSR,
1223 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1224
1225 /*
1226 * There is no guarantee that we'll get an interrupt
1227 * after clearing DMAMODE as we might have done this
1228 * too late (after TXPKTRDY was cleared by controller).
1229 * Re-read TXCSR as we have spoiled its previous value.
1230 */
1231 tx_csr = musb_readw(epio, MUSB_TXCSR);
1232 }
1233
1234 /*
1235 * We may get here from a DMA completion or TXPKTRDY interrupt.
1236 * In any case, we must check the FIFO status here and bail out
1237 * only if the FIFO still has data -- that should prevent the
1238 * "missed" TXPKTRDY interrupts and deal with double-buffered
1239 * FIFO mode too...
1240 */
1241 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
1242 DBG(2, "DMA complete but packet still in FIFO, "
1243 "CSR %04x\n", tx_csr);
1244 return;
1245 }
1246 }
1247
1248 if (!status || dma || usb_pipeisoc(pipe)) {
1249 if (dma)
1250 length = dma->actual_len;
1251 else
1252 length = qh->segsize;
1253 qh->offset += length;
1254
1255 if (usb_pipeisoc(pipe)) {
1256 struct usb_iso_packet_descriptor *d;
1257
1258 d = urb->iso_frame_desc + qh->iso_idx;
1259 d->actual_length = length;
1260 d->status = status;
1261 if (++qh->iso_idx >= urb->number_of_packets) {
1262 done = true;
1263 } else {
1264 d++;
1265 offset = d->offset;
1266 length = d->length;
1267 }
1268 } else if (dma) {
1269 done = true;
1270 } else {
1271 /* see if we need to send more data, or ZLP */
1272 if (qh->segsize < qh->maxpacket)
1273 done = true;
1274 else if (qh->offset == urb->transfer_buffer_length
1275 && !(urb->transfer_flags
1276 & URB_ZERO_PACKET))
1277 done = true;
1278 if (!done) {
1279 offset = qh->offset;
1280 length = urb->transfer_buffer_length - offset;
1281 }
1282 }
1283 }
1284
1285 /* urb->status != -EINPROGRESS means request has been faulted,
1286 * so we must abort this transfer after cleanup
1287 */
1288 if (urb->status != -EINPROGRESS) {
1289 done = true;
1290 if (status == 0)
1291 status = urb->status;
1292 }
1293
1294 if (done) {
1295 /* set status */
1296 urb->status = status;
1297 urb->actual_length = qh->offset;
1298 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
1299 return;
1300 } else if (usb_pipeisoc(pipe) && dma) {
1301 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
1302 offset, length))
1303 return;
1304 } else if (tx_csr & MUSB_TXCSR_DMAENAB) {
1305 DBG(1, "not complete, but DMA enabled?\n");
1306 return;
1307 }
1308
1309 /*
1310 * PIO: start next packet in this URB.
1311 *
1312 * REVISIT: some docs say that when hw_ep->tx_double_buffered,
1313 * (and presumably, FIFO is not half-full) we should write *two*
1314 * packets before updating TXCSR; other docs disagree...
1315 */
1316 if (length > qh->maxpacket)
1317 length = qh->maxpacket;
1318 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
1319 qh->segsize = length;
1320
1321 musb_ep_select(mbase, epnum);
1322 musb_writew(epio, MUSB_TXCSR,
1323 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
1324 }
1325
1326
1327 #ifdef CONFIG_USB_INVENTRA_DMA
1328
1329 /* Host side RX (IN) using Mentor DMA works as follows:
1330 submit_urb ->
1331 - if queue was empty, ProgramEndpoint
1332 - first IN token is sent out (by setting ReqPkt)
1333 LinuxIsr -> RxReady()
1334 /\ => first packet is received
1335 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1336 | -> DMA Isr (transfer complete) -> RxReady()
1337 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1338 | - if urb not complete, send next IN token (ReqPkt)
1339 | | else complete urb.
1340 | |
1341 ---------------------------
1342 *
1343 * Nuances of mode 1:
1344 * For short packets, no ack (+RxPktRdy) is sent automatically
1345 * (even if AutoClear is ON)
1346 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
1347 * automatically => major problem, as collecting the next packet becomes
1348 * difficult. Hence mode 1 is not used.
1349 *
1350 * REVISIT
1351 * All we care about at this driver level is that
1352 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
1353 * (b) termination conditions are: short RX, or buffer full;
1354 * (c) fault modes include
1355 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1356 * (and that endpoint's dma queue stops immediately)
1357 * - overflow (full, PLUS more bytes in the terminal packet)
1358 *
1359 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1360 * thus be a great candidate for using mode 1 ... for all but the
1361 * last packet of one URB's transfer.
1362 */
1363
1364 #endif
1365
1366 /* Schedule next QH from musb->in_bulk and move the current qh to
1367 * the end; avoids starvation for other endpoints.
1368 */
1369 static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep)
1370 {
1371 struct dma_channel *dma;
1372 struct urb *urb;
1373 void __iomem *mbase = musb->mregs;
1374 void __iomem *epio = ep->regs;
1375 struct musb_qh *cur_qh, *next_qh;
1376 u16 rx_csr;
1377
1378 musb_ep_select(mbase, ep->epnum);
1379 dma = is_dma_capable() ? ep->rx_channel : NULL;
1380
1381 /* clear nak timeout bit */
1382 rx_csr = musb_readw(epio, MUSB_RXCSR);
1383 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1384 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1385 musb_writew(epio, MUSB_RXCSR, rx_csr);
1386
1387 cur_qh = first_qh(&musb->in_bulk);
1388 if (cur_qh) {
1389 urb = next_urb(cur_qh);
1390 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1391 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1392 musb->dma_controller->channel_abort(dma);
1393 urb->actual_length += dma->actual_len;
1394 dma->actual_len = 0L;
1395 }
1396 musb_save_toggle(cur_qh, 1, urb);
1397
1398 /* move cur_qh to end of queue */
1399 list_move_tail(&cur_qh->ring, &musb->in_bulk);
1400
1401 /* get the next qh from musb->in_bulk */
1402 next_qh = first_qh(&musb->in_bulk);
1403
1404 /* set rx_reinit and schedule the next qh */
1405 ep->rx_reinit = 1;
1406 musb_start_urb(musb, 1, next_qh);
1407 }
1408 }
1409
1410 /*
1411 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
1412 * and high-bandwidth IN transfer cases.
1413 */
1414 void musb_host_rx(struct musb *musb, u8 epnum)
1415 {
1416 struct urb *urb;
1417 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1418 void __iomem *epio = hw_ep->regs;
1419 struct musb_qh *qh = hw_ep->in_qh;
1420 size_t xfer_len;
1421 void __iomem *mbase = musb->mregs;
1422 int pipe;
1423 u16 rx_csr, val;
1424 bool iso_err = false;
1425 bool done = false;
1426 u32 status;
1427 struct dma_channel *dma;
1428
1429 musb_ep_select(mbase, epnum);
1430
1431 urb = next_urb(qh);
1432 dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
1433 status = 0;
1434 xfer_len = 0;
1435
1436 rx_csr = musb_readw(epio, MUSB_RXCSR);
1437 val = rx_csr;
1438
1439 if (unlikely(!urb)) {
1440 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
1441 * usbtest #11 (unlinks) triggers it regularly, sometimes
1442 * with fifo full. (Only with DMA??)
1443 */
1444 DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
1445 musb_readw(epio, MUSB_RXCOUNT));
1446 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1447 return;
1448 }
1449
1450 pipe = urb->pipe;
1451
1452 DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
1453 epnum, rx_csr, urb->actual_length,
1454 dma ? dma->actual_len : 0);
1455
1456 /* check for errors, concurrent stall & unlink is not really
1457 * handled yet! */
1458 if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
1459 DBG(3, "RX end %d STALL\n", epnum);
1460
1461 /* stall; record URB status */
1462 status = -EPIPE;
1463
1464 } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
1465 DBG(3, "end %d RX proto error\n", epnum);
1466
1467 status = -EPROTO;
1468 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1469
1470 } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
1471
1472 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1473 DBG(6, "RX end %d NAK timeout\n", epnum);
1474
1475 /* NOTE: NAKing is *NOT* an error, so we want to
1476 * continue. Except ... if there's a request for
1477 * another QH, use that instead of starving it.
1478 *
1479 * Devices like Ethernet and serial adapters keep
1480 * reads posted at all times, which will starve
1481 * other devices without this logic.
1482 */
1483 if (usb_pipebulk(urb->pipe)
1484 && qh->mux == 1
1485 && !list_is_singular(&musb->in_bulk)) {
1486 musb_bulk_rx_nak_timeout(musb, hw_ep);
1487 return;
1488 }
1489 musb_ep_select(mbase, epnum);
1490 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1491 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1492 musb_writew(epio, MUSB_RXCSR, rx_csr);
1493
1494 goto finish;
1495 } else {
1496 DBG(4, "RX end %d ISO data error\n", epnum);
1497 /* packet error reported later */
1498 iso_err = true;
1499 }
1500 }
1501
1502 /* faults abort the transfer */
1503 if (status) {
1504 /* clean up dma and collect transfer count */
1505 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1506 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1507 (void) musb->dma_controller->channel_abort(dma);
1508 xfer_len = dma->actual_len;
1509 }
1510 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1511 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1512 done = true;
1513 goto finish;
1514 }
1515
1516 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) {
1517 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
1518 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);
1519 goto finish;
1520 }
1521
1522 /* thorough shutdown for now ... given more precise fault handling
1523 * and better queueing support, we might keep a DMA pipeline going
1524 * while processing this irq for earlier completions.
1525 */
1526
1527 /* FIXME this is _way_ too much in-line logic for Mentor DMA */
1528
1529 #ifndef CONFIG_USB_INVENTRA_DMA
1530 if (rx_csr & MUSB_RXCSR_H_REQPKT) {
1531 /* REVISIT this happened for a while on some short reads...
1532 * the cleanup still needs investigation... looks bad...
1533 * and also duplicates dma cleanup code above ... plus,
1534 * shouldn't this be the "half full" double buffer case?
1535 */
1536 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1537 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1538 (void) musb->dma_controller->channel_abort(dma);
1539 xfer_len = dma->actual_len;
1540 done = true;
1541 }
1542
1543 DBG(2, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
1544 xfer_len, dma ? ", dma" : "");
1545 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1546
1547 musb_ep_select(mbase, epnum);
1548 musb_writew(epio, MUSB_RXCSR,
1549 MUSB_RXCSR_H_WZC_BITS | rx_csr);
1550 }
1551 #endif
1552 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
1553 xfer_len = dma->actual_len;
1554
1555 val &= ~(MUSB_RXCSR_DMAENAB
1556 | MUSB_RXCSR_H_AUTOREQ
1557 | MUSB_RXCSR_AUTOCLEAR
1558 | MUSB_RXCSR_RXPKTRDY);
1559 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1560
1561 #ifdef CONFIG_USB_INVENTRA_DMA
1562 if (usb_pipeisoc(pipe)) {
1563 struct usb_iso_packet_descriptor *d;
1564
1565 d = urb->iso_frame_desc + qh->iso_idx;
1566 d->actual_length = xfer_len;
1567
1568 /* even if there was an error, we did the dma
1569 * for iso_frame_desc->length
1570 */
1571 if (d->status != EILSEQ && d->status != -EOVERFLOW)
1572 d->status = 0;
1573
1574 if (++qh->iso_idx >= urb->number_of_packets)
1575 done = true;
1576 else
1577 done = false;
1578
1579 } else {
1580 /* done if urb buffer is full or short packet is recd */
1581 done = (urb->actual_length + xfer_len >=
1582 urb->transfer_buffer_length
1583 || dma->actual_len < qh->maxpacket);
1584 }
1585
1586 /* send IN token for next packet, without AUTOREQ */
1587 if (!done) {
1588 val |= MUSB_RXCSR_H_REQPKT;
1589 musb_writew(epio, MUSB_RXCSR,
1590 MUSB_RXCSR_H_WZC_BITS | val);
1591 }
1592
1593 DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
1594 done ? "off" : "reset",
1595 musb_readw(epio, MUSB_RXCSR),
1596 musb_readw(epio, MUSB_RXCOUNT));
1597 #else
1598 done = true;
1599 #endif
1600 } else if (urb->status == -EINPROGRESS) {
1601 /* if no errors, be sure a packet is ready for unloading */
1602 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
1603 status = -EPROTO;
1604 ERR("Rx interrupt with no errors or packet!\n");
1605
1606 /* FIXME this is another "SHOULD NEVER HAPPEN" */
1607
1608 /* SCRUB (RX) */
1609 /* do the proper sequence to abort the transfer */
1610 musb_ep_select(mbase, epnum);
1611 val &= ~MUSB_RXCSR_H_REQPKT;
1612 musb_writew(epio, MUSB_RXCSR, val);
1613 goto finish;
1614 }
1615
1616 /* we are expecting IN packets */
1617 #ifdef CONFIG_USB_INVENTRA_DMA
1618 if (dma) {
1619 struct dma_controller *c;
1620 u16 rx_count;
1621 int ret, length;
1622 dma_addr_t buf;
1623
1624 rx_count = musb_readw(epio, MUSB_RXCOUNT);
1625
1626 DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n",
1627 epnum, rx_count,
1628 urb->transfer_dma
1629 + urb->actual_length,
1630 qh->offset,
1631 urb->transfer_buffer_length);
1632
1633 c = musb->dma_controller;
1634
1635 if (usb_pipeisoc(pipe)) {
1636 int status = 0;
1637 struct usb_iso_packet_descriptor *d;
1638
1639 d = urb->iso_frame_desc + qh->iso_idx;
1640
1641 if (iso_err) {
1642 status = -EILSEQ;
1643 urb->error_count++;
1644 }
1645 if (rx_count > d->length) {
1646 if (status == 0) {
1647 status = -EOVERFLOW;
1648 urb->error_count++;
1649 }
1650 DBG(2, "** OVERFLOW %d into %d\n",\
1651 rx_count, d->length);
1652
1653 length = d->length;
1654 } else
1655 length = rx_count;
1656 d->status = status;
1657 buf = urb->transfer_dma + d->offset;
1658 } else {
1659 length = rx_count;
1660 buf = urb->transfer_dma +
1661 urb->actual_length;
1662 }
1663
1664 dma->desired_mode = 0;
1665 #ifdef USE_MODE1
1666 /* because of the issue below, mode 1 will
1667 * only rarely behave with correct semantics.
1668 */
1669 if ((urb->transfer_flags &
1670 URB_SHORT_NOT_OK)
1671 && (urb->transfer_buffer_length -
1672 urb->actual_length)
1673 > qh->maxpacket)
1674 dma->desired_mode = 1;
1675 if (rx_count < hw_ep->max_packet_sz_rx) {
1676 length = rx_count;
1677 dma->bDesiredMode = 0;
1678 } else {
1679 length = urb->transfer_buffer_length;
1680 }
1681 #endif
1682
1683 /* Disadvantage of using mode 1:
1684 * It's basically usable only for mass storage class; essentially all
1685 * other protocols also terminate transfers on short packets.
1686 *
1687 * Details:
1688 * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1689 * If you try to use mode 1 for (transfer_buffer_length - 512), and try
1690 * to use the extra IN token to grab the last packet using mode 0, then
1691 * the problem is that you cannot be sure when the device will send the
1692 * last packet and RxPktRdy set. Sometimes the packet is recd too soon
1693 * such that it gets lost when RxCSR is re-set at the end of the mode 1
1694 * transfer, while sometimes it is recd just a little late so that if you
1695 * try to configure for mode 0 soon after the mode 1 transfer is
1696 * completed, you will find rxcount 0. Okay, so you might think why not
1697 * wait for an interrupt when the pkt is recd. Well, you won't get any!
1698 */
1699
1700 val = musb_readw(epio, MUSB_RXCSR);
1701 val &= ~MUSB_RXCSR_H_REQPKT;
1702
1703 if (dma->desired_mode == 0)
1704 val &= ~MUSB_RXCSR_H_AUTOREQ;
1705 else
1706 val |= MUSB_RXCSR_H_AUTOREQ;
1707 val |= MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAENAB;
1708
1709 musb_writew(epio, MUSB_RXCSR,
1710 MUSB_RXCSR_H_WZC_BITS | val);
1711
1712 /* REVISIT if when actual_length != 0,
1713 * transfer_buffer_length needs to be
1714 * adjusted first...
1715 */
1716 ret = c->channel_program(
1717 dma, qh->maxpacket,
1718 dma->desired_mode, buf, length);
1719
1720 if (!ret) {
1721 c->channel_release(dma);
1722 hw_ep->rx_channel = NULL;
1723 dma = NULL;
1724 /* REVISIT reset CSR */
1725 }
1726 }
1727 #endif /* Mentor DMA */
1728
1729 if (!dma) {
1730 done = musb_host_packet_rx(musb, urb,
1731 epnum, iso_err);
1732 DBG(6, "read %spacket\n", done ? "last " : "");
1733 }
1734 }
1735
1736 finish:
1737 urb->actual_length += xfer_len;
1738 qh->offset += xfer_len;
1739 if (done) {
1740 if (urb->status == -EINPROGRESS)
1741 urb->status = status;
1742 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
1743 }
1744 }
1745
1746 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
1747 * the software schedule associates multiple such nodes with a given
1748 * host side hardware endpoint + direction; scheduling may activate
1749 * that hardware endpoint.
1750 */
1751 static int musb_schedule(
1752 struct musb *musb,
1753 struct musb_qh *qh,
1754 int is_in)
1755 {
1756 int idle;
1757 int best_diff;
1758 int best_end, epnum;
1759 struct musb_hw_ep *hw_ep = NULL;
1760 struct list_head *head = NULL;
1761
1762 /* use fixed hardware for control and bulk */
1763 if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
1764 head = &musb->control;
1765 hw_ep = musb->control_ep;
1766 goto success;
1767 }
1768
1769 /* else, periodic transfers get muxed to other endpoints */
1770
1771 /*
1772 * We know this qh hasn't been scheduled, so all we need to do
1773 * is choose which hardware endpoint to put it on ...
1774 *
1775 * REVISIT what we really want here is a regular schedule tree
1776 * like e.g. OHCI uses.
1777 */
1778 best_diff = 4096;
1779 best_end = -1;
1780
1781 for (epnum = 1, hw_ep = musb->endpoints + 1;
1782 epnum < musb->nr_endpoints;
1783 epnum++, hw_ep++) {
1784 int diff;
1785
1786 if (musb_ep_get_qh(hw_ep, is_in) != NULL)
1787 continue;
1788
1789 if (hw_ep == musb->bulk_ep)
1790 continue;
1791
1792 if (is_in)
1793 diff = hw_ep->max_packet_sz_rx - qh->maxpacket;
1794 else
1795 diff = hw_ep->max_packet_sz_tx - qh->maxpacket;
1796
1797 if (diff >= 0 && best_diff > diff) {
1798 best_diff = diff;
1799 best_end = epnum;
1800 }
1801 }
1802 /* use bulk reserved ep1 if no other ep is free */
1803 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) {
1804 hw_ep = musb->bulk_ep;
1805 if (is_in)
1806 head = &musb->in_bulk;
1807 else
1808 head = &musb->out_bulk;
1809
1810 /* Enable bulk RX NAK timeout scheme when bulk requests are
1811 * multiplexed. This scheme doen't work in high speed to full
1812 * speed scenario as NAK interrupts are not coming from a
1813 * full speed device connected to a high speed device.
1814 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
1815 * 4 (8 frame or 8ms) for FS device.
1816 */
1817 if (is_in && qh->dev)
1818 qh->intv_reg =
1819 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
1820 goto success;
1821 } else if (best_end < 0) {
1822 return -ENOSPC;
1823 }
1824
1825 idle = 1;
1826 qh->mux = 0;
1827 hw_ep = musb->endpoints + best_end;
1828 DBG(4, "qh %p periodic slot %d\n", qh, best_end);
1829 success:
1830 if (head) {
1831 idle = list_empty(head);
1832 list_add_tail(&qh->ring, head);
1833 qh->mux = 1;
1834 }
1835 qh->hw_ep = hw_ep;
1836 qh->hep->hcpriv = qh;
1837 if (idle)
1838 musb_start_urb(musb, is_in, qh);
1839 return 0;
1840 }
1841
1842 static int musb_urb_enqueue(
1843 struct usb_hcd *hcd,
1844 struct urb *urb,
1845 gfp_t mem_flags)
1846 {
1847 unsigned long flags;
1848 struct musb *musb = hcd_to_musb(hcd);
1849 struct usb_host_endpoint *hep = urb->ep;
1850 struct musb_qh *qh;
1851 struct usb_endpoint_descriptor *epd = &hep->desc;
1852 int ret;
1853 unsigned type_reg;
1854 unsigned interval;
1855
1856 /* host role must be active */
1857 if (!is_host_active(musb) || !musb->is_active)
1858 return -ENODEV;
1859
1860 spin_lock_irqsave(&musb->lock, flags);
1861 ret = usb_hcd_link_urb_to_ep(hcd, urb);
1862 qh = ret ? NULL : hep->hcpriv;
1863 if (qh)
1864 urb->hcpriv = qh;
1865 spin_unlock_irqrestore(&musb->lock, flags);
1866
1867 /* DMA mapping was already done, if needed, and this urb is on
1868 * hep->urb_list now ... so we're done, unless hep wasn't yet
1869 * scheduled onto a live qh.
1870 *
1871 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
1872 * disabled, testing for empty qh->ring and avoiding qh setup costs
1873 * except for the first urb queued after a config change.
1874 */
1875 if (qh || ret)
1876 return ret;
1877
1878 /* Allocate and initialize qh, minimizing the work done each time
1879 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
1880 *
1881 * REVISIT consider a dedicated qh kmem_cache, so it's harder
1882 * for bugs in other kernel code to break this driver...
1883 */
1884 qh = kzalloc(sizeof *qh, mem_flags);
1885 if (!qh) {
1886 spin_lock_irqsave(&musb->lock, flags);
1887 usb_hcd_unlink_urb_from_ep(hcd, urb);
1888 spin_unlock_irqrestore(&musb->lock, flags);
1889 return -ENOMEM;
1890 }
1891
1892 qh->hep = hep;
1893 qh->dev = urb->dev;
1894 INIT_LIST_HEAD(&qh->ring);
1895 qh->is_ready = 1;
1896
1897 qh->maxpacket = le16_to_cpu(epd->wMaxPacketSize);
1898
1899 /* no high bandwidth support yet */
1900 if (qh->maxpacket & ~0x7ff) {
1901 ret = -EMSGSIZE;
1902 goto done;
1903 }
1904
1905 qh->epnum = usb_endpoint_num(epd);
1906 qh->type = usb_endpoint_type(epd);
1907
1908 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
1909 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
1910
1911 /* precompute rxtype/txtype/type0 register */
1912 type_reg = (qh->type << 4) | qh->epnum;
1913 switch (urb->dev->speed) {
1914 case USB_SPEED_LOW:
1915 type_reg |= 0xc0;
1916 break;
1917 case USB_SPEED_FULL:
1918 type_reg |= 0x80;
1919 break;
1920 default:
1921 type_reg |= 0x40;
1922 }
1923 qh->type_reg = type_reg;
1924
1925 /* Precompute RXINTERVAL/TXINTERVAL register */
1926 switch (qh->type) {
1927 case USB_ENDPOINT_XFER_INT:
1928 /*
1929 * Full/low speeds use the linear encoding,
1930 * high speed uses the logarithmic encoding.
1931 */
1932 if (urb->dev->speed <= USB_SPEED_FULL) {
1933 interval = max_t(u8, epd->bInterval, 1);
1934 break;
1935 }
1936 /* FALLTHROUGH */
1937 case USB_ENDPOINT_XFER_ISOC:
1938 /* ISO always uses logarithmic encoding */
1939 interval = min_t(u8, epd->bInterval, 16);
1940 break;
1941 default:
1942 /* REVISIT we actually want to use NAK limits, hinting to the
1943 * transfer scheduling logic to try some other qh, e.g. try
1944 * for 2 msec first:
1945 *
1946 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
1947 *
1948 * The downside of disabling this is that transfer scheduling
1949 * gets VERY unfair for nonperiodic transfers; a misbehaving
1950 * peripheral could make that hurt. That's perfectly normal
1951 * for reads from network or serial adapters ... so we have
1952 * partial NAKlimit support for bulk RX.
1953 *
1954 * The upside of disabling it is simpler transfer scheduling.
1955 */
1956 interval = 0;
1957 }
1958 qh->intv_reg = interval;
1959
1960 /* precompute addressing for external hub/tt ports */
1961 if (musb->is_multipoint) {
1962 struct usb_device *parent = urb->dev->parent;
1963
1964 if (parent != hcd->self.root_hub) {
1965 qh->h_addr_reg = (u8) parent->devnum;
1966
1967 /* set up tt info if needed */
1968 if (urb->dev->tt) {
1969 qh->h_port_reg = (u8) urb->dev->ttport;
1970 if (urb->dev->tt->hub)
1971 qh->h_addr_reg =
1972 (u8) urb->dev->tt->hub->devnum;
1973 if (urb->dev->tt->multi)
1974 qh->h_addr_reg |= 0x80;
1975 }
1976 }
1977 }
1978
1979 /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
1980 * until we get real dma queues (with an entry for each urb/buffer),
1981 * we only have work to do in the former case.
1982 */
1983 spin_lock_irqsave(&musb->lock, flags);
1984 if (hep->hcpriv) {
1985 /* some concurrent activity submitted another urb to hep...
1986 * odd, rare, error prone, but legal.
1987 */
1988 kfree(qh);
1989 ret = 0;
1990 } else
1991 ret = musb_schedule(musb, qh,
1992 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
1993
1994 if (ret == 0) {
1995 urb->hcpriv = qh;
1996 /* FIXME set urb->start_frame for iso/intr, it's tested in
1997 * musb_start_urb(), but otherwise only konicawc cares ...
1998 */
1999 }
2000 spin_unlock_irqrestore(&musb->lock, flags);
2001
2002 done:
2003 if (ret != 0) {
2004 spin_lock_irqsave(&musb->lock, flags);
2005 usb_hcd_unlink_urb_from_ep(hcd, urb);
2006 spin_unlock_irqrestore(&musb->lock, flags);
2007 kfree(qh);
2008 }
2009 return ret;
2010 }
2011
2012
2013 /*
2014 * abort a transfer that's at the head of a hardware queue.
2015 * called with controller locked, irqs blocked
2016 * that hardware queue advances to the next transfer, unless prevented
2017 */
2018 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
2019 {
2020 struct musb_hw_ep *ep = qh->hw_ep;
2021 void __iomem *epio = ep->regs;
2022 unsigned hw_end = ep->epnum;
2023 void __iomem *regs = ep->musb->mregs;
2024 int is_in = usb_pipein(urb->pipe);
2025 int status = 0;
2026 u16 csr;
2027
2028 musb_ep_select(regs, hw_end);
2029
2030 if (is_dma_capable()) {
2031 struct dma_channel *dma;
2032
2033 dma = is_in ? ep->rx_channel : ep->tx_channel;
2034 if (dma) {
2035 status = ep->musb->dma_controller->channel_abort(dma);
2036 DBG(status ? 1 : 3,
2037 "abort %cX%d DMA for urb %p --> %d\n",
2038 is_in ? 'R' : 'T', ep->epnum,
2039 urb, status);
2040 urb->actual_length += dma->actual_len;
2041 }
2042 }
2043
2044 /* turn off DMA requests, discard state, stop polling ... */
2045 if (is_in) {
2046 /* giveback saves bulk toggle */
2047 csr = musb_h_flush_rxfifo(ep, 0);
2048
2049 /* REVISIT we still get an irq; should likely clear the
2050 * endpoint's irq status here to avoid bogus irqs.
2051 * clearing that status is platform-specific...
2052 */
2053 } else if (ep->epnum) {
2054 musb_h_tx_flush_fifo(ep);
2055 csr = musb_readw(epio, MUSB_TXCSR);
2056 csr &= ~(MUSB_TXCSR_AUTOSET
2057 | MUSB_TXCSR_DMAENAB
2058 | MUSB_TXCSR_H_RXSTALL
2059 | MUSB_TXCSR_H_NAKTIMEOUT
2060 | MUSB_TXCSR_H_ERROR
2061 | MUSB_TXCSR_TXPKTRDY);
2062 musb_writew(epio, MUSB_TXCSR, csr);
2063 /* REVISIT may need to clear FLUSHFIFO ... */
2064 musb_writew(epio, MUSB_TXCSR, csr);
2065 /* flush cpu writebuffer */
2066 csr = musb_readw(epio, MUSB_TXCSR);
2067 } else {
2068 musb_h_ep0_flush_fifo(ep);
2069 }
2070 if (status == 0)
2071 musb_advance_schedule(ep->musb, urb, ep, is_in);
2072 return status;
2073 }
2074
2075 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2076 {
2077 struct musb *musb = hcd_to_musb(hcd);
2078 struct musb_qh *qh;
2079 unsigned long flags;
2080 int is_in = usb_pipein(urb->pipe);
2081 int ret;
2082
2083 DBG(4, "urb=%p, dev%d ep%d%s\n", urb,
2084 usb_pipedevice(urb->pipe),
2085 usb_pipeendpoint(urb->pipe),
2086 is_in ? "in" : "out");
2087
2088 spin_lock_irqsave(&musb->lock, flags);
2089 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
2090 if (ret)
2091 goto done;
2092
2093 qh = urb->hcpriv;
2094 if (!qh)
2095 goto done;
2096
2097 /*
2098 * Any URB not actively programmed into endpoint hardware can be
2099 * immediately given back; that's any URB not at the head of an
2100 * endpoint queue, unless someday we get real DMA queues. And even
2101 * if it's at the head, it might not be known to the hardware...
2102 *
2103 * Otherwise abort current transfer, pending DMA, etc.; urb->status
2104 * has already been updated. This is a synchronous abort; it'd be
2105 * OK to hold off until after some IRQ, though.
2106 *
2107 * NOTE: qh is invalid unless !list_empty(&hep->urb_list)
2108 */
2109 if (!qh->is_ready
2110 || urb->urb_list.prev != &qh->hep->urb_list
2111 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
2112 int ready = qh->is_ready;
2113
2114 qh->is_ready = 0;
2115 musb_giveback(musb, urb, 0);
2116 qh->is_ready = ready;
2117
2118 /* If nothing else (usually musb_giveback) is using it
2119 * and its URB list has emptied, recycle this qh.
2120 */
2121 if (ready && list_empty(&qh->hep->urb_list)) {
2122 qh->hep->hcpriv = NULL;
2123 list_del(&qh->ring);
2124 kfree(qh);
2125 }
2126 } else
2127 ret = musb_cleanup_urb(urb, qh);
2128 done:
2129 spin_unlock_irqrestore(&musb->lock, flags);
2130 return ret;
2131 }
2132
2133 /* disable an endpoint */
2134 static void
2135 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2136 {
2137 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
2138 unsigned long flags;
2139 struct musb *musb = hcd_to_musb(hcd);
2140 struct musb_qh *qh;
2141 struct urb *urb;
2142
2143 spin_lock_irqsave(&musb->lock, flags);
2144
2145 qh = hep->hcpriv;
2146 if (qh == NULL)
2147 goto exit;
2148
2149 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2150
2151 /* Kick the first URB off the hardware, if needed */
2152 qh->is_ready = 0;
2153 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
2154 urb = next_urb(qh);
2155
2156 /* make software (then hardware) stop ASAP */
2157 if (!urb->unlinked)
2158 urb->status = -ESHUTDOWN;
2159
2160 /* cleanup */
2161 musb_cleanup_urb(urb, qh);
2162
2163 /* Then nuke all the others ... and advance the
2164 * queue on hw_ep (e.g. bulk ring) when we're done.
2165 */
2166 while (!list_empty(&hep->urb_list)) {
2167 urb = next_urb(qh);
2168 urb->status = -ESHUTDOWN;
2169 musb_advance_schedule(musb, urb, qh->hw_ep, is_in);
2170 }
2171 } else {
2172 /* Just empty the queue; the hardware is busy with
2173 * other transfers, and since !qh->is_ready nothing
2174 * will activate any of these as it advances.
2175 */
2176 while (!list_empty(&hep->urb_list))
2177 musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
2178
2179 hep->hcpriv = NULL;
2180 list_del(&qh->ring);
2181 kfree(qh);
2182 }
2183 exit:
2184 spin_unlock_irqrestore(&musb->lock, flags);
2185 }
2186
2187 static int musb_h_get_frame_number(struct usb_hcd *hcd)
2188 {
2189 struct musb *musb = hcd_to_musb(hcd);
2190
2191 return musb_readw(musb->mregs, MUSB_FRAME);
2192 }
2193
2194 static int musb_h_start(struct usb_hcd *hcd)
2195 {
2196 struct musb *musb = hcd_to_musb(hcd);
2197
2198 /* NOTE: musb_start() is called when the hub driver turns
2199 * on port power, or when (OTG) peripheral starts.
2200 */
2201 hcd->state = HC_STATE_RUNNING;
2202 musb->port1_status = 0;
2203 return 0;
2204 }
2205
2206 static void musb_h_stop(struct usb_hcd *hcd)
2207 {
2208 musb_stop(hcd_to_musb(hcd));
2209 hcd->state = HC_STATE_HALT;
2210 }
2211
2212 static int musb_bus_suspend(struct usb_hcd *hcd)
2213 {
2214 struct musb *musb = hcd_to_musb(hcd);
2215
2216 if (musb->xceiv->state == OTG_STATE_A_SUSPEND)
2217 return 0;
2218
2219 if (is_host_active(musb) && musb->is_active) {
2220 WARNING("trying to suspend as %s is_active=%i\n",
2221 otg_state_string(musb), musb->is_active);
2222 return -EBUSY;
2223 } else
2224 return 0;
2225 }
2226
2227 static int musb_bus_resume(struct usb_hcd *hcd)
2228 {
2229 /* resuming child port does the work */
2230 return 0;
2231 }
2232
2233 const struct hc_driver musb_hc_driver = {
2234 .description = "musb-hcd",
2235 .product_desc = "MUSB HDRC host driver",
2236 .hcd_priv_size = sizeof(struct musb),
2237 .flags = HCD_USB2 | HCD_MEMORY,
2238
2239 /* not using irq handler or reset hooks from usbcore, since
2240 * those must be shared with peripheral code for OTG configs
2241 */
2242
2243 .start = musb_h_start,
2244 .stop = musb_h_stop,
2245
2246 .get_frame_number = musb_h_get_frame_number,
2247
2248 .urb_enqueue = musb_urb_enqueue,
2249 .urb_dequeue = musb_urb_dequeue,
2250 .endpoint_disable = musb_h_disable,
2251
2252 .hub_status_data = musb_hub_status_data,
2253 .hub_control = musb_hub_control,
2254 .bus_suspend = musb_bus_suspend,
2255 .bus_resume = musb_bus_resume,
2256 /* .start_port_reset = NULL, */
2257 /* .hub_irq_enable = NULL, */
2258 };
Linus' kernel tree