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ide: remove a ton of pointless #undef REALLY_SLOW_IO
[linux-2.6.git] / drivers / kvm / svm.c
blob83da4ea150a335c3543315a7adef7855b1f047ce
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16
17 #include <linux/module.h>
18 #include <linux/vmalloc.h>
19 #include <linux/highmem.h>
20 #include <linux/profile.h>
21 #include <asm/desc.h>
22
23 #include "kvm_svm.h"
24 #include "x86_emulate.h"
25
26 MODULE_AUTHOR("Qumranet");
27 MODULE_LICENSE("GPL");
28
29 #define IOPM_ALLOC_ORDER 2
30 #define MSRPM_ALLOC_ORDER 1
31
32 #define DB_VECTOR 1
33 #define UD_VECTOR 6
34 #define GP_VECTOR 13
35
36 #define DR7_GD_MASK (1 << 13)
37 #define DR6_BD_MASK (1 << 13)
38 #define CR4_DE_MASK (1UL << 3)
39
40 #define SEG_TYPE_LDT 2
41 #define SEG_TYPE_BUSY_TSS16 3
42
43 #define KVM_EFER_LMA (1 << 10)
44 #define KVM_EFER_LME (1 << 8)
45
46 unsigned long iopm_base;
47 unsigned long msrpm_base;
48
49 struct kvm_ldttss_desc {
50 u16 limit0;
51 u16 base0;
52 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
53 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
54 u32 base3;
55 u32 zero1;
56 } __attribute__((packed));
57
58 struct svm_cpu_data {
59 int cpu;
60
61 uint64_t asid_generation;
62 uint32_t max_asid;
63 uint32_t next_asid;
64 struct kvm_ldttss_desc *tss_desc;
65
66 struct page *save_area;
67 };
68
69 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
70
71 struct svm_init_data {
72 int cpu;
73 int r;
74 };
75
76 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
77
78 #define NUM_MSR_MAPS (sizeof(msrpm_ranges) / sizeof(*msrpm_ranges))
79 #define MSRS_RANGE_SIZE 2048
80 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
81
82 #define MAX_INST_SIZE 15
83
84 static unsigned get_addr_size(struct kvm_vcpu *vcpu)
85 {
86 struct vmcb_save_area *sa = &vcpu->svm->vmcb->save;
87 u16 cs_attrib;
88
89 if (!(sa->cr0 & CR0_PE_MASK) || (sa->rflags & X86_EFLAGS_VM))
90 return 2;
91
92 cs_attrib = sa->cs.attrib;
93
94 return (cs_attrib & SVM_SELECTOR_L_MASK) ? 8 :
95 (cs_attrib & SVM_SELECTOR_DB_MASK) ? 4 : 2;
96 }
97
98 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
99 {
100 int word_index = __ffs(vcpu->irq_summary);
101 int bit_index = __ffs(vcpu->irq_pending[word_index]);
102 int irq = word_index * BITS_PER_LONG + bit_index;
103
104 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
105 if (!vcpu->irq_pending[word_index])
106 clear_bit(word_index, &vcpu->irq_summary);
107 return irq;
108 }
109
110 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
111 {
112 set_bit(irq, vcpu->irq_pending);
113 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
114 }
115
116 static inline void clgi(void)
117 {
118 asm volatile (SVM_CLGI);
119 }
120
121 static inline void stgi(void)
122 {
123 asm volatile (SVM_STGI);
124 }
125
126 static inline void invlpga(unsigned long addr, u32 asid)
127 {
128 asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
129 }
130
131 static inline unsigned long kvm_read_cr2(void)
132 {
133 unsigned long cr2;
134
135 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
136 return cr2;
137 }
138
139 static inline void kvm_write_cr2(unsigned long val)
140 {
141 asm volatile ("mov %0, %%cr2" :: "r" (val));
142 }
143
144 static inline unsigned long read_dr6(void)
145 {
146 unsigned long dr6;
147
148 asm volatile ("mov %%dr6, %0" : "=r" (dr6));
149 return dr6;
150 }
151
152 static inline void write_dr6(unsigned long val)
153 {
154 asm volatile ("mov %0, %%dr6" :: "r" (val));
155 }
156
157 static inline unsigned long read_dr7(void)
158 {
159 unsigned long dr7;
160
161 asm volatile ("mov %%dr7, %0" : "=r" (dr7));
162 return dr7;
163 }
164
165 static inline void write_dr7(unsigned long val)
166 {
167 asm volatile ("mov %0, %%dr7" :: "r" (val));
168 }
169
170 static inline void force_new_asid(struct kvm_vcpu *vcpu)
171 {
172 vcpu->svm->asid_generation--;
173 }
174
175 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
176 {
177 force_new_asid(vcpu);
178 }
179
180 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
181 {
182 if (!(efer & KVM_EFER_LMA))
183 efer &= ~KVM_EFER_LME;
184
185 vcpu->svm->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
186 vcpu->shadow_efer = efer;
187 }
188
189 static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
190 {
191 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
192 SVM_EVTINJ_VALID_ERR |
193 SVM_EVTINJ_TYPE_EXEPT |
194 GP_VECTOR;
195 vcpu->svm->vmcb->control.event_inj_err = error_code;
196 }
197
198 static void inject_ud(struct kvm_vcpu *vcpu)
199 {
200 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
201 SVM_EVTINJ_TYPE_EXEPT |
202 UD_VECTOR;
203 }
204
205 static void inject_db(struct kvm_vcpu *vcpu)
206 {
207 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
208 SVM_EVTINJ_TYPE_EXEPT |
209 DB_VECTOR;
210 }
211
212 static int is_page_fault(uint32_t info)
213 {
214 info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
215 return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT);
216 }
217
218 static int is_external_interrupt(u32 info)
219 {
220 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
221 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
222 }
223
224 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
225 {
226 if (!vcpu->svm->next_rip) {
227 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
228 return;
229 }
230 if (vcpu->svm->next_rip - vcpu->svm->vmcb->save.rip > 15) {
231 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
232 __FUNCTION__,
233 vcpu->svm->vmcb->save.rip,
234 vcpu->svm->next_rip);
235 }
236
237 vcpu->rip = vcpu->svm->vmcb->save.rip = vcpu->svm->next_rip;
238 vcpu->svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
239
240 vcpu->interrupt_window_open = 1;
241 }
242
243 static int has_svm(void)
244 {
245 uint32_t eax, ebx, ecx, edx;
246
247 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
248 printk(KERN_INFO "has_svm: not amd\n");
249 return 0;
250 }
251
252 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
253 if (eax < SVM_CPUID_FUNC) {
254 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
255 return 0;
256 }
257
258 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
259 if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
260 printk(KERN_DEBUG "has_svm: svm not available\n");
261 return 0;
262 }
263 return 1;
264 }
265
266 static void svm_hardware_disable(void *garbage)
267 {
268 struct svm_cpu_data *svm_data
269 = per_cpu(svm_data, raw_smp_processor_id());
270
271 if (svm_data) {
272 uint64_t efer;
273
274 wrmsrl(MSR_VM_HSAVE_PA, 0);
275 rdmsrl(MSR_EFER, efer);
276 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
277 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
278 __free_page(svm_data->save_area);
279 kfree(svm_data);
280 }
281 }
282
283 static void svm_hardware_enable(void *garbage)
284 {
285
286 struct svm_cpu_data *svm_data;
287 uint64_t efer;
288 #ifdef CONFIG_X86_64
289 struct desc_ptr gdt_descr;
290 #else
291 struct Xgt_desc_struct gdt_descr;
292 #endif
293 struct desc_struct *gdt;
294 int me = raw_smp_processor_id();
295
296 if (!has_svm()) {
297 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
298 return;
299 }
300 svm_data = per_cpu(svm_data, me);
301
302 if (!svm_data) {
303 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
304 me);
305 return;
306 }
307
308 svm_data->asid_generation = 1;
309 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
310 svm_data->next_asid = svm_data->max_asid + 1;
311
312 asm volatile ( "sgdt %0" : "=m"(gdt_descr) );
313 gdt = (struct desc_struct *)gdt_descr.address;
314 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
315
316 rdmsrl(MSR_EFER, efer);
317 wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
318
319 wrmsrl(MSR_VM_HSAVE_PA,
320 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
321 }
322
323 static int svm_cpu_init(int cpu)
324 {
325 struct svm_cpu_data *svm_data;
326 int r;
327
328 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
329 if (!svm_data)
330 return -ENOMEM;
331 svm_data->cpu = cpu;
332 svm_data->save_area = alloc_page(GFP_KERNEL);
333 r = -ENOMEM;
334 if (!svm_data->save_area)
335 goto err_1;
336
337 per_cpu(svm_data, cpu) = svm_data;
338
339 return 0;
340
341 err_1:
342 kfree(svm_data);
343 return r;
344
345 }
346
347 static int set_msr_interception(u32 *msrpm, unsigned msr,
348 int read, int write)
349 {
350 int i;
351
352 for (i = 0; i < NUM_MSR_MAPS; i++) {
353 if (msr >= msrpm_ranges[i] &&
354 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
355 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
356 msrpm_ranges[i]) * 2;
357
358 u32 *base = msrpm + (msr_offset / 32);
359 u32 msr_shift = msr_offset % 32;
360 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
361 *base = (*base & ~(0x3 << msr_shift)) |
362 (mask << msr_shift);
363 return 1;
364 }
365 }
366 printk(KERN_DEBUG "%s: not found 0x%x\n", __FUNCTION__, msr);
367 return 0;
368 }
369
370 static __init int svm_hardware_setup(void)
371 {
372 int cpu;
373 struct page *iopm_pages;
374 struct page *msrpm_pages;
375 void *msrpm_va;
376 int r;
377
378 kvm_emulator_want_group7_invlpg();
379
380 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
381
382 if (!iopm_pages)
383 return -ENOMEM;
384 memset(page_address(iopm_pages), 0xff,
385 PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
386 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
387
388
389 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
390
391 r = -ENOMEM;
392 if (!msrpm_pages)
393 goto err_1;
394
395 msrpm_va = page_address(msrpm_pages);
396 memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
397 msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
398
399 #ifdef CONFIG_X86_64
400 set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
401 set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
402 set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
403 set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
404 set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
405 set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
406 #endif
407 set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
408 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
409 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
410 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
411
412 for_each_online_cpu(cpu) {
413 r = svm_cpu_init(cpu);
414 if (r)
415 goto err_2;
416 }
417 return 0;
418
419 err_2:
420 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
421 msrpm_base = 0;
422 err_1:
423 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
424 iopm_base = 0;
425 return r;
426 }
427
428 static __exit void svm_hardware_unsetup(void)
429 {
430 __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
431 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
432 iopm_base = msrpm_base = 0;
433 }
434
435 static void init_seg(struct vmcb_seg *seg)
436 {
437 seg->selector = 0;
438 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
439 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
440 seg->limit = 0xffff;
441 seg->base = 0;
442 }
443
444 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
445 {
446 seg->selector = 0;
447 seg->attrib = SVM_SELECTOR_P_MASK | type;
448 seg->limit = 0xffff;
449 seg->base = 0;
450 }
451
452 static int svm_vcpu_setup(struct kvm_vcpu *vcpu)
453 {
454 return 0;
455 }
456
457 static void init_vmcb(struct vmcb *vmcb)
458 {
459 struct vmcb_control_area *control = &vmcb->control;
460 struct vmcb_save_area *save = &vmcb->save;
461 u64 tsc;
462
463 control->intercept_cr_read = INTERCEPT_CR0_MASK |
464 INTERCEPT_CR3_MASK |
465 INTERCEPT_CR4_MASK;
466
467 control->intercept_cr_write = INTERCEPT_CR0_MASK |
468 INTERCEPT_CR3_MASK |
469 INTERCEPT_CR4_MASK;
470
471 control->intercept_dr_read = INTERCEPT_DR0_MASK |
472 INTERCEPT_DR1_MASK |
473 INTERCEPT_DR2_MASK |
474 INTERCEPT_DR3_MASK;
475
476 control->intercept_dr_write = INTERCEPT_DR0_MASK |
477 INTERCEPT_DR1_MASK |
478 INTERCEPT_DR2_MASK |
479 INTERCEPT_DR3_MASK |
480 INTERCEPT_DR5_MASK |
481 INTERCEPT_DR7_MASK;
482
483 control->intercept_exceptions = 1 << PF_VECTOR;
484
485
486 control->intercept = (1ULL << INTERCEPT_INTR) |
487 (1ULL << INTERCEPT_NMI) |
488 /*
489 * selective cr0 intercept bug?
490 * 0: 0f 22 d8 mov %eax,%cr3
491 * 3: 0f 20 c0 mov %cr0,%eax
492 * 6: 0d 00 00 00 80 or $0x80000000,%eax
493 * b: 0f 22 c0 mov %eax,%cr0
494 * set cr3 ->interception
495 * get cr0 ->interception
496 * set cr0 -> no interception
497 */
498 /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */
499 (1ULL << INTERCEPT_CPUID) |
500 (1ULL << INTERCEPT_HLT) |
501 (1ULL << INTERCEPT_INVLPGA) |
502 (1ULL << INTERCEPT_IOIO_PROT) |
503 (1ULL << INTERCEPT_MSR_PROT) |
504 (1ULL << INTERCEPT_TASK_SWITCH) |
505 (1ULL << INTERCEPT_SHUTDOWN) |
506 (1ULL << INTERCEPT_VMRUN) |
507 (1ULL << INTERCEPT_VMMCALL) |
508 (1ULL << INTERCEPT_VMLOAD) |
509 (1ULL << INTERCEPT_VMSAVE) |
510 (1ULL << INTERCEPT_STGI) |
511 (1ULL << INTERCEPT_CLGI) |
512 (1ULL << INTERCEPT_SKINIT);
513
514 control->iopm_base_pa = iopm_base;
515 control->msrpm_base_pa = msrpm_base;
516 rdtscll(tsc);
517 control->tsc_offset = -tsc;
518 control->int_ctl = V_INTR_MASKING_MASK;
519
520 init_seg(&save->es);
521 init_seg(&save->ss);
522 init_seg(&save->ds);
523 init_seg(&save->fs);
524 init_seg(&save->gs);
525
526 save->cs.selector = 0xf000;
527 /* Executable/Readable Code Segment */
528 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
529 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
530 save->cs.limit = 0xffff;
531 /*
532 * cs.base should really be 0xffff0000, but vmx can't handle that, so
533 * be consistent with it.
534 *
535 * Replace when we have real mode working for vmx.
536 */
537 save->cs.base = 0xf0000;
538
539 save->gdtr.limit = 0xffff;
540 save->idtr.limit = 0xffff;
541
542 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
543 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
544
545 save->efer = MSR_EFER_SVME_MASK;
546
547 save->dr6 = 0xffff0ff0;
548 save->dr7 = 0x400;
549 save->rflags = 2;
550 save->rip = 0x0000fff0;
551
552 /*
553 * cr0 val on cpu init should be 0x60000010, we enable cpu
554 * cache by default. the orderly way is to enable cache in bios.
555 */
556 save->cr0 = 0x00000010 | CR0_PG_MASK;
557 save->cr4 = CR4_PAE_MASK;
558 /* rdx = ?? */
559 }
560
561 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
562 {
563 struct page *page;
564 int r;
565
566 r = -ENOMEM;
567 vcpu->svm = kzalloc(sizeof *vcpu->svm, GFP_KERNEL);
568 if (!vcpu->svm)
569 goto out1;
570 page = alloc_page(GFP_KERNEL);
571 if (!page)
572 goto out2;
573
574 vcpu->svm->vmcb = page_address(page);
575 memset(vcpu->svm->vmcb, 0, PAGE_SIZE);
576 vcpu->svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
577 vcpu->svm->cr0 = 0x00000010;
578 vcpu->svm->asid_generation = 0;
579 memset(vcpu->svm->db_regs, 0, sizeof(vcpu->svm->db_regs));
580 init_vmcb(vcpu->svm->vmcb);
581
582 fx_init(vcpu);
583
584 return 0;
585
586 out2:
587 kfree(vcpu->svm);
588 out1:
589 return r;
590 }
591
592 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
593 {
594 if (!vcpu->svm)
595 return;
596 if (vcpu->svm->vmcb)
597 __free_page(pfn_to_page(vcpu->svm->vmcb_pa >> PAGE_SHIFT));
598 kfree(vcpu->svm);
599 }
600
601 static struct kvm_vcpu *svm_vcpu_load(struct kvm_vcpu *vcpu)
602 {
603 get_cpu();
604 return vcpu;
605 }
606
607 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
608 {
609 put_cpu();
610 }
611
612 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
613 {
614 }
615
616 static void svm_cache_regs(struct kvm_vcpu *vcpu)
617 {
618 vcpu->regs[VCPU_REGS_RAX] = vcpu->svm->vmcb->save.rax;
619 vcpu->regs[VCPU_REGS_RSP] = vcpu->svm->vmcb->save.rsp;
620 vcpu->rip = vcpu->svm->vmcb->save.rip;
621 }
622
623 static void svm_decache_regs(struct kvm_vcpu *vcpu)
624 {
625 vcpu->svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX];
626 vcpu->svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP];
627 vcpu->svm->vmcb->save.rip = vcpu->rip;
628 }
629
630 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
631 {
632 return vcpu->svm->vmcb->save.rflags;
633 }
634
635 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
636 {
637 vcpu->svm->vmcb->save.rflags = rflags;
638 }
639
640 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
641 {
642 struct vmcb_save_area *save = &vcpu->svm->vmcb->save;
643
644 switch (seg) {
645 case VCPU_SREG_CS: return &save->cs;
646 case VCPU_SREG_DS: return &save->ds;
647 case VCPU_SREG_ES: return &save->es;
648 case VCPU_SREG_FS: return &save->fs;
649 case VCPU_SREG_GS: return &save->gs;
650 case VCPU_SREG_SS: return &save->ss;
651 case VCPU_SREG_TR: return &save->tr;
652 case VCPU_SREG_LDTR: return &save->ldtr;
653 }
654 BUG();
655 return NULL;
656 }
657
658 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
659 {
660 struct vmcb_seg *s = svm_seg(vcpu, seg);
661
662 return s->base;
663 }
664
665 static void svm_get_segment(struct kvm_vcpu *vcpu,
666 struct kvm_segment *var, int seg)
667 {
668 struct vmcb_seg *s = svm_seg(vcpu, seg);
669
670 var->base = s->base;
671 var->limit = s->limit;
672 var->selector = s->selector;
673 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
674 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
675 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
676 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
677 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
678 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
679 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
680 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
681 var->unusable = !var->present;
682 }
683
684 static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
685 {
686 struct vmcb_seg *s = svm_seg(vcpu, VCPU_SREG_CS);
687
688 *db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
689 *l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
690 }
691
692 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
693 {
694 dt->limit = vcpu->svm->vmcb->save.idtr.limit;
695 dt->base = vcpu->svm->vmcb->save.idtr.base;
696 }
697
698 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
699 {
700 vcpu->svm->vmcb->save.idtr.limit = dt->limit;
701 vcpu->svm->vmcb->save.idtr.base = dt->base ;
702 }
703
704 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
705 {
706 dt->limit = vcpu->svm->vmcb->save.gdtr.limit;
707 dt->base = vcpu->svm->vmcb->save.gdtr.base;
708 }
709
710 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
711 {
712 vcpu->svm->vmcb->save.gdtr.limit = dt->limit;
713 vcpu->svm->vmcb->save.gdtr.base = dt->base ;
714 }
715
716 static void svm_decache_cr0_cr4_guest_bits(struct kvm_vcpu *vcpu)
717 {
718 }
719
720 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
721 {
722 #ifdef CONFIG_X86_64
723 if (vcpu->shadow_efer & KVM_EFER_LME) {
724 if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK)) {
725 vcpu->shadow_efer |= KVM_EFER_LMA;
726 vcpu->svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME;
727 }
728
729 if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK) ) {
730 vcpu->shadow_efer &= ~KVM_EFER_LMA;
731 vcpu->svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME);
732 }
733 }
734 #endif
735 vcpu->svm->cr0 = cr0;
736 vcpu->svm->vmcb->save.cr0 = cr0 | CR0_PG_MASK | CR0_WP_MASK;
737 vcpu->cr0 = cr0;
738 }
739
740 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
741 {
742 vcpu->cr4 = cr4;
743 vcpu->svm->vmcb->save.cr4 = cr4 | CR4_PAE_MASK;
744 }
745
746 static void svm_set_segment(struct kvm_vcpu *vcpu,
747 struct kvm_segment *var, int seg)
748 {
749 struct vmcb_seg *s = svm_seg(vcpu, seg);
750
751 s->base = var->base;
752 s->limit = var->limit;
753 s->selector = var->selector;
754 if (var->unusable)
755 s->attrib = 0;
756 else {
757 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
758 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
759 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
760 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
761 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
762 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
763 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
764 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
765 }
766 if (seg == VCPU_SREG_CS)
767 vcpu->svm->vmcb->save.cpl
768 = (vcpu->svm->vmcb->save.cs.attrib
769 >> SVM_SELECTOR_DPL_SHIFT) & 3;
770
771 }
772
773 /* FIXME:
774
775 vcpu->svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
776 vcpu->svm->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
777
778 */
779
780 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
781 {
782 return -EOPNOTSUPP;
783 }
784
785 static void load_host_msrs(struct kvm_vcpu *vcpu)
786 {
787 int i;
788
789 for ( i = 0; i < NR_HOST_SAVE_MSRS; i++)
790 wrmsrl(host_save_msrs[i], vcpu->svm->host_msrs[i]);
791 }
792
793 static void save_host_msrs(struct kvm_vcpu *vcpu)
794 {
795 int i;
796
797 for ( i = 0; i < NR_HOST_SAVE_MSRS; i++)
798 rdmsrl(host_save_msrs[i], vcpu->svm->host_msrs[i]);
799 }
800
801 static void new_asid(struct kvm_vcpu *vcpu, struct svm_cpu_data *svm_data)
802 {
803 if (svm_data->next_asid > svm_data->max_asid) {
804 ++svm_data->asid_generation;
805 svm_data->next_asid = 1;
806 vcpu->svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
807 }
808
809 vcpu->cpu = svm_data->cpu;
810 vcpu->svm->asid_generation = svm_data->asid_generation;
811 vcpu->svm->vmcb->control.asid = svm_data->next_asid++;
812 }
813
814 static void svm_invlpg(struct kvm_vcpu *vcpu, gva_t address)
815 {
816 invlpga(address, vcpu->svm->vmcb->control.asid); // is needed?
817 }
818
819 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
820 {
821 return vcpu->svm->db_regs[dr];
822 }
823
824 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
825 int *exception)
826 {
827 *exception = 0;
828
829 if (vcpu->svm->vmcb->save.dr7 & DR7_GD_MASK) {
830 vcpu->svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
831 vcpu->svm->vmcb->save.dr6 |= DR6_BD_MASK;
832 *exception = DB_VECTOR;
833 return;
834 }
835
836 switch (dr) {
837 case 0 ... 3:
838 vcpu->svm->db_regs[dr] = value;
839 return;
840 case 4 ... 5:
841 if (vcpu->cr4 & CR4_DE_MASK) {
842 *exception = UD_VECTOR;
843 return;
844 }
845 case 7: {
846 if (value & ~((1ULL << 32) - 1)) {
847 *exception = GP_VECTOR;
848 return;
849 }
850 vcpu->svm->vmcb->save.dr7 = value;
851 return;
852 }
853 default:
854 printk(KERN_DEBUG "%s: unexpected dr %u\n",
855 __FUNCTION__, dr);
856 *exception = UD_VECTOR;
857 return;
858 }
859 }
860
861 static int pf_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
862 {
863 u32 exit_int_info = vcpu->svm->vmcb->control.exit_int_info;
864 u64 fault_address;
865 u32 error_code;
866 enum emulation_result er;
867 int r;
868
869 if (is_external_interrupt(exit_int_info))
870 push_irq(vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
871
872 spin_lock(&vcpu->kvm->lock);
873
874 fault_address = vcpu->svm->vmcb->control.exit_info_2;
875 error_code = vcpu->svm->vmcb->control.exit_info_1;
876 r = kvm_mmu_page_fault(vcpu, fault_address, error_code);
877 if (r < 0) {
878 spin_unlock(&vcpu->kvm->lock);
879 return r;
880 }
881 if (!r) {
882 spin_unlock(&vcpu->kvm->lock);
883 return 1;
884 }
885 er = emulate_instruction(vcpu, kvm_run, fault_address, error_code);
886 spin_unlock(&vcpu->kvm->lock);
887
888 switch (er) {
889 case EMULATE_DONE:
890 return 1;
891 case EMULATE_DO_MMIO:
892 ++kvm_stat.mmio_exits;
893 kvm_run->exit_reason = KVM_EXIT_MMIO;
894 return 0;
895 case EMULATE_FAIL:
896 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
897 break;
898 default:
899 BUG();
900 }
901
902 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
903 return 0;
904 }
905
906 static int shutdown_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
907 {
908 /*
909 * VMCB is undefined after a SHUTDOWN intercept
910 * so reinitialize it.
911 */
912 memset(vcpu->svm->vmcb, 0, PAGE_SIZE);
913 init_vmcb(vcpu->svm->vmcb);
914
915 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
916 return 0;
917 }
918
919 static int io_get_override(struct kvm_vcpu *vcpu,
920 struct vmcb_seg **seg,
921 int *addr_override)
922 {
923 u8 inst[MAX_INST_SIZE];
924 unsigned ins_length;
925 gva_t rip;
926 int i;
927
928 rip = vcpu->svm->vmcb->save.rip;
929 ins_length = vcpu->svm->next_rip - rip;
930 rip += vcpu->svm->vmcb->save.cs.base;
931
932 if (ins_length > MAX_INST_SIZE)
933 printk(KERN_DEBUG
934 "%s: inst length err, cs base 0x%llx rip 0x%llx "
935 "next rip 0x%llx ins_length %u\n",
936 __FUNCTION__,
937 vcpu->svm->vmcb->save.cs.base,
938 vcpu->svm->vmcb->save.rip,
939 vcpu->svm->vmcb->control.exit_info_2,
940 ins_length);
941
942 if (kvm_read_guest(vcpu, rip, ins_length, inst) != ins_length)
943 /* #PF */
944 return 0;
945
946 *addr_override = 0;
947 *seg = NULL;
948 for (i = 0; i < ins_length; i++)
949 switch (inst[i]) {
950 case 0xf0:
951 case 0xf2:
952 case 0xf3:
953 case 0x66:
954 continue;
955 case 0x67:
956 *addr_override = 1;
957 continue;
958 case 0x2e:
959 *seg = &vcpu->svm->vmcb->save.cs;
960 continue;
961 case 0x36:
962 *seg = &vcpu->svm->vmcb->save.ss;
963 continue;
964 case 0x3e:
965 *seg = &vcpu->svm->vmcb->save.ds;
966 continue;
967 case 0x26:
968 *seg = &vcpu->svm->vmcb->save.es;
969 continue;
970 case 0x64:
971 *seg = &vcpu->svm->vmcb->save.fs;
972 continue;
973 case 0x65:
974 *seg = &vcpu->svm->vmcb->save.gs;
975 continue;
976 default:
977 return 1;
978 }
979 printk(KERN_DEBUG "%s: unexpected\n", __FUNCTION__);
980 return 0;
981 }
982
983 static unsigned long io_adress(struct kvm_vcpu *vcpu, int ins, u64 *address)
984 {
985 unsigned long addr_mask;
986 unsigned long *reg;
987 struct vmcb_seg *seg;
988 int addr_override;
989 struct vmcb_save_area *save_area = &vcpu->svm->vmcb->save;
990 u16 cs_attrib = save_area->cs.attrib;
991 unsigned addr_size = get_addr_size(vcpu);
992
993 if (!io_get_override(vcpu, &seg, &addr_override))
994 return 0;
995
996 if (addr_override)
997 addr_size = (addr_size == 2) ? 4: (addr_size >> 1);
998
999 if (ins) {
1000 reg = &vcpu->regs[VCPU_REGS_RDI];
1001 seg = &vcpu->svm->vmcb->save.es;
1002 } else {
1003 reg = &vcpu->regs[VCPU_REGS_RSI];
1004 seg = (seg) ? seg : &vcpu->svm->vmcb->save.ds;
1005 }
1006
1007 addr_mask = ~0ULL >> (64 - (addr_size * 8));
1008
1009 if ((cs_attrib & SVM_SELECTOR_L_MASK) &&
1010 !(vcpu->svm->vmcb->save.rflags & X86_EFLAGS_VM)) {
1011 *address = (*reg & addr_mask);
1012 return addr_mask;
1013 }
1014
1015 if (!(seg->attrib & SVM_SELECTOR_P_SHIFT)) {
1016 svm_inject_gp(vcpu, 0);
1017 return 0;
1018 }
1019
1020 *address = (*reg & addr_mask) + seg->base;
1021 return addr_mask;
1022 }
1023
1024 static int io_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1025 {
1026 u32 io_info = vcpu->svm->vmcb->control.exit_info_1; //address size bug?
1027 int _in = io_info & SVM_IOIO_TYPE_MASK;
1028
1029 ++kvm_stat.io_exits;
1030
1031 vcpu->svm->next_rip = vcpu->svm->vmcb->control.exit_info_2;
1032
1033 kvm_run->exit_reason = KVM_EXIT_IO;
1034 kvm_run->io.port = io_info >> 16;
1035 kvm_run->io.direction = (_in) ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
1036 kvm_run->io.size = ((io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT);
1037 kvm_run->io.string = (io_info & SVM_IOIO_STR_MASK) != 0;
1038 kvm_run->io.rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1039
1040 if (kvm_run->io.string) {
1041 unsigned addr_mask;
1042
1043 addr_mask = io_adress(vcpu, _in, &kvm_run->io.address);
1044 if (!addr_mask) {
1045 printk(KERN_DEBUG "%s: get io address failed\n", __FUNCTION__);
1046 return 1;
1047 }
1048
1049 if (kvm_run->io.rep) {
1050 kvm_run->io.count = vcpu->regs[VCPU_REGS_RCX] & addr_mask;
1051 kvm_run->io.string_down = (vcpu->svm->vmcb->save.rflags
1052 & X86_EFLAGS_DF) != 0;
1053 }
1054 } else {
1055 kvm_run->io.value = vcpu->svm->vmcb->save.rax;
1056 }
1057 return 0;
1058 }
1059
1060
1061 static int nop_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1062 {
1063 return 1;
1064 }
1065
1066 static int halt_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1067 {
1068 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 1;
1069 skip_emulated_instruction(vcpu);
1070 if (vcpu->irq_summary)
1071 return 1;
1072
1073 kvm_run->exit_reason = KVM_EXIT_HLT;
1074 ++kvm_stat.halt_exits;
1075 return 0;
1076 }
1077
1078 static int invalid_op_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1079 {
1080 inject_ud(vcpu);
1081 return 1;
1082 }
1083
1084 static int task_switch_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1085 {
1086 printk(KERN_DEBUG "%s: task swiche is unsupported\n", __FUNCTION__);
1087 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1088 return 0;
1089 }
1090
1091 static int cpuid_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1092 {
1093 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
1094 kvm_run->exit_reason = KVM_EXIT_CPUID;
1095 return 0;
1096 }
1097
1098 static int emulate_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1099 {
1100 if (emulate_instruction(vcpu, NULL, 0, 0) != EMULATE_DONE)
1101 printk(KERN_ERR "%s: failed\n", __FUNCTION__);
1102 return 1;
1103 }
1104
1105 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1106 {
1107 switch (ecx) {
1108 case MSR_IA32_TIME_STAMP_COUNTER: {
1109 u64 tsc;
1110
1111 rdtscll(tsc);
1112 *data = vcpu->svm->vmcb->control.tsc_offset + tsc;
1113 break;
1114 }
1115 case MSR_K6_STAR:
1116 *data = vcpu->svm->vmcb->save.star;
1117 break;
1118 #ifdef CONFIG_X86_64
1119 case MSR_LSTAR:
1120 *data = vcpu->svm->vmcb->save.lstar;
1121 break;
1122 case MSR_CSTAR:
1123 *data = vcpu->svm->vmcb->save.cstar;
1124 break;
1125 case MSR_KERNEL_GS_BASE:
1126 *data = vcpu->svm->vmcb->save.kernel_gs_base;
1127 break;
1128 case MSR_SYSCALL_MASK:
1129 *data = vcpu->svm->vmcb->save.sfmask;
1130 break;
1131 #endif
1132 case MSR_IA32_SYSENTER_CS:
1133 *data = vcpu->svm->vmcb->save.sysenter_cs;
1134 break;
1135 case MSR_IA32_SYSENTER_EIP:
1136 *data = vcpu->svm->vmcb->save.sysenter_eip;
1137 break;
1138 case MSR_IA32_SYSENTER_ESP:
1139 *data = vcpu->svm->vmcb->save.sysenter_esp;
1140 break;
1141 default:
1142 return kvm_get_msr_common(vcpu, ecx, data);
1143 }
1144 return 0;
1145 }
1146
1147 static int rdmsr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1148 {
1149 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1150 u64 data;
1151
1152 if (svm_get_msr(vcpu, ecx, &data))
1153 svm_inject_gp(vcpu, 0);
1154 else {
1155 vcpu->svm->vmcb->save.rax = data & 0xffffffff;
1156 vcpu->regs[VCPU_REGS_RDX] = data >> 32;
1157 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
1158 skip_emulated_instruction(vcpu);
1159 }
1160 return 1;
1161 }
1162
1163 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1164 {
1165 switch (ecx) {
1166 case MSR_IA32_TIME_STAMP_COUNTER: {
1167 u64 tsc;
1168
1169 rdtscll(tsc);
1170 vcpu->svm->vmcb->control.tsc_offset = data - tsc;
1171 break;
1172 }
1173 case MSR_K6_STAR:
1174 vcpu->svm->vmcb->save.star = data;
1175 break;
1176 #ifdef CONFIG_X86_64
1177 case MSR_LSTAR:
1178 vcpu->svm->vmcb->save.lstar = data;
1179 break;
1180 case MSR_CSTAR:
1181 vcpu->svm->vmcb->save.cstar = data;
1182 break;
1183 case MSR_KERNEL_GS_BASE:
1184 vcpu->svm->vmcb->save.kernel_gs_base = data;
1185 break;
1186 case MSR_SYSCALL_MASK:
1187 vcpu->svm->vmcb->save.sfmask = data;
1188 break;
1189 #endif
1190 case MSR_IA32_SYSENTER_CS:
1191 vcpu->svm->vmcb->save.sysenter_cs = data;
1192 break;
1193 case MSR_IA32_SYSENTER_EIP:
1194 vcpu->svm->vmcb->save.sysenter_eip = data;
1195 break;
1196 case MSR_IA32_SYSENTER_ESP:
1197 vcpu->svm->vmcb->save.sysenter_esp = data;
1198 break;
1199 default:
1200 return kvm_set_msr_common(vcpu, ecx, data);
1201 }
1202 return 0;
1203 }
1204
1205 static int wrmsr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1206 {
1207 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1208 u64 data = (vcpu->svm->vmcb->save.rax & -1u)
1209 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1210 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
1211 if (svm_set_msr(vcpu, ecx, data))
1212 svm_inject_gp(vcpu, 0);
1213 else
1214 skip_emulated_instruction(vcpu);
1215 return 1;
1216 }
1217
1218 static int msr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1219 {
1220 if (vcpu->svm->vmcb->control.exit_info_1)
1221 return wrmsr_interception(vcpu, kvm_run);
1222 else
1223 return rdmsr_interception(vcpu, kvm_run);
1224 }
1225
1226 static int interrupt_window_interception(struct kvm_vcpu *vcpu,
1227 struct kvm_run *kvm_run)
1228 {
1229 /*
1230 * If the user space waits to inject interrupts, exit as soon as
1231 * possible
1232 */
1233 if (kvm_run->request_interrupt_window &&
1234 !vcpu->irq_summary) {
1235 ++kvm_stat.irq_window_exits;
1236 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1237 return 0;
1238 }
1239
1240 return 1;
1241 }
1242
1243 static int (*svm_exit_handlers[])(struct kvm_vcpu *vcpu,
1244 struct kvm_run *kvm_run) = {
1245 [SVM_EXIT_READ_CR0] = emulate_on_interception,
1246 [SVM_EXIT_READ_CR3] = emulate_on_interception,
1247 [SVM_EXIT_READ_CR4] = emulate_on_interception,
1248 /* for now: */
1249 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
1250 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
1251 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1252 [SVM_EXIT_READ_DR0] = emulate_on_interception,
1253 [SVM_EXIT_READ_DR1] = emulate_on_interception,
1254 [SVM_EXIT_READ_DR2] = emulate_on_interception,
1255 [SVM_EXIT_READ_DR3] = emulate_on_interception,
1256 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
1257 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
1258 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
1259 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
1260 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
1261 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
1262 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
1263 [SVM_EXIT_INTR] = nop_on_interception,
1264 [SVM_EXIT_NMI] = nop_on_interception,
1265 [SVM_EXIT_SMI] = nop_on_interception,
1266 [SVM_EXIT_INIT] = nop_on_interception,
1267 [SVM_EXIT_VINTR] = interrupt_window_interception,
1268 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
1269 [SVM_EXIT_CPUID] = cpuid_interception,
1270 [SVM_EXIT_HLT] = halt_interception,
1271 [SVM_EXIT_INVLPG] = emulate_on_interception,
1272 [SVM_EXIT_INVLPGA] = invalid_op_interception,
1273 [SVM_EXIT_IOIO] = io_interception,
1274 [SVM_EXIT_MSR] = msr_interception,
1275 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
1276 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
1277 [SVM_EXIT_VMRUN] = invalid_op_interception,
1278 [SVM_EXIT_VMMCALL] = invalid_op_interception,
1279 [SVM_EXIT_VMLOAD] = invalid_op_interception,
1280 [SVM_EXIT_VMSAVE] = invalid_op_interception,
1281 [SVM_EXIT_STGI] = invalid_op_interception,
1282 [SVM_EXIT_CLGI] = invalid_op_interception,
1283 [SVM_EXIT_SKINIT] = invalid_op_interception,
1284 };
1285
1286
1287 static int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1288 {
1289 u32 exit_code = vcpu->svm->vmcb->control.exit_code;
1290
1291 kvm_run->exit_type = KVM_EXIT_TYPE_VM_EXIT;
1292
1293 if (is_external_interrupt(vcpu->svm->vmcb->control.exit_int_info) &&
1294 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
1295 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1296 "exit_code 0x%x\n",
1297 __FUNCTION__, vcpu->svm->vmcb->control.exit_int_info,
1298 exit_code);
1299
1300 if (exit_code >= sizeof(svm_exit_handlers) / sizeof(*svm_exit_handlers)
1301 || svm_exit_handlers[exit_code] == 0) {
1302 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1303 printk(KERN_ERR "%s: 0x%x @ 0x%llx cr0 0x%lx rflags 0x%llx\n",
1304 __FUNCTION__,
1305 exit_code,
1306 vcpu->svm->vmcb->save.rip,
1307 vcpu->cr0,
1308 vcpu->svm->vmcb->save.rflags);
1309 return 0;
1310 }
1311
1312 return svm_exit_handlers[exit_code](vcpu, kvm_run);
1313 }
1314
1315 static void reload_tss(struct kvm_vcpu *vcpu)
1316 {
1317 int cpu = raw_smp_processor_id();
1318
1319 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1320 svm_data->tss_desc->type = 9; //available 32/64-bit TSS
1321 load_TR_desc();
1322 }
1323
1324 static void pre_svm_run(struct kvm_vcpu *vcpu)
1325 {
1326 int cpu = raw_smp_processor_id();
1327
1328 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1329
1330 vcpu->svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1331 if (vcpu->cpu != cpu ||
1332 vcpu->svm->asid_generation != svm_data->asid_generation)
1333 new_asid(vcpu, svm_data);
1334 }
1335
1336
1337 static inline void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1338 {
1339 struct vmcb_control_area *control;
1340
1341 control = &vcpu->svm->vmcb->control;
1342 control->int_vector = pop_irq(vcpu);
1343 control->int_ctl &= ~V_INTR_PRIO_MASK;
1344 control->int_ctl |= V_IRQ_MASK |
1345 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1346 }
1347
1348 static void kvm_reput_irq(struct kvm_vcpu *vcpu)
1349 {
1350 struct vmcb_control_area *control = &vcpu->svm->vmcb->control;
1351
1352 if (control->int_ctl & V_IRQ_MASK) {
1353 control->int_ctl &= ~V_IRQ_MASK;
1354 push_irq(vcpu, control->int_vector);
1355 }
1356
1357 vcpu->interrupt_window_open =
1358 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1359 }
1360
1361 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1362 struct kvm_run *kvm_run)
1363 {
1364 struct vmcb_control_area *control = &vcpu->svm->vmcb->control;
1365
1366 vcpu->interrupt_window_open =
1367 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1368 (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF));
1369
1370 if (vcpu->interrupt_window_open && vcpu->irq_summary)
1371 /*
1372 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1373 */
1374 kvm_do_inject_irq(vcpu);
1375
1376 /*
1377 * Interrupts blocked. Wait for unblock.
1378 */
1379 if (!vcpu->interrupt_window_open &&
1380 (vcpu->irq_summary || kvm_run->request_interrupt_window)) {
1381 control->intercept |= 1ULL << INTERCEPT_VINTR;
1382 } else
1383 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1384 }
1385
1386 static void post_kvm_run_save(struct kvm_vcpu *vcpu,
1387 struct kvm_run *kvm_run)
1388 {
1389 kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open &&
1390 vcpu->irq_summary == 0);
1391 kvm_run->if_flag = (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF) != 0;
1392 kvm_run->cr8 = vcpu->cr8;
1393 kvm_run->apic_base = vcpu->apic_base;
1394 }
1395
1396 /*
1397 * Check if userspace requested an interrupt window, and that the
1398 * interrupt window is open.
1399 *
1400 * No need to exit to userspace if we already have an interrupt queued.
1401 */
1402 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
1403 struct kvm_run *kvm_run)
1404 {
1405 return (!vcpu->irq_summary &&
1406 kvm_run->request_interrupt_window &&
1407 vcpu->interrupt_window_open &&
1408 (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF));
1409 }
1410
1411 static void save_db_regs(unsigned long *db_regs)
1412 {
1413 asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1414 asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1415 asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1416 asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1417 }
1418
1419 static void load_db_regs(unsigned long *db_regs)
1420 {
1421 asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1422 asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1423 asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1424 asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1425 }
1426
1427 static int svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1428 {
1429 u16 fs_selector;
1430 u16 gs_selector;
1431 u16 ldt_selector;
1432 int r;
1433
1434 again:
1435 if (!vcpu->mmio_read_completed)
1436 do_interrupt_requests(vcpu, kvm_run);
1437
1438 clgi();
1439
1440 pre_svm_run(vcpu);
1441
1442 save_host_msrs(vcpu);
1443 fs_selector = read_fs();
1444 gs_selector = read_gs();
1445 ldt_selector = read_ldt();
1446 vcpu->svm->host_cr2 = kvm_read_cr2();
1447 vcpu->svm->host_dr6 = read_dr6();
1448 vcpu->svm->host_dr7 = read_dr7();
1449 vcpu->svm->vmcb->save.cr2 = vcpu->cr2;
1450
1451 if (vcpu->svm->vmcb->save.dr7 & 0xff) {
1452 write_dr7(0);
1453 save_db_regs(vcpu->svm->host_db_regs);
1454 load_db_regs(vcpu->svm->db_regs);
1455 }
1456
1457 fx_save(vcpu->host_fx_image);
1458 fx_restore(vcpu->guest_fx_image);
1459
1460 asm volatile (
1461 #ifdef CONFIG_X86_64
1462 "push %%rbx; push %%rcx; push %%rdx;"
1463 "push %%rsi; push %%rdi; push %%rbp;"
1464 "push %%r8; push %%r9; push %%r10; push %%r11;"
1465 "push %%r12; push %%r13; push %%r14; push %%r15;"
1466 #else
1467 "push %%ebx; push %%ecx; push %%edx;"
1468 "push %%esi; push %%edi; push %%ebp;"
1469 #endif
1470
1471 #ifdef CONFIG_X86_64
1472 "mov %c[rbx](%[vcpu]), %%rbx \n\t"
1473 "mov %c[rcx](%[vcpu]), %%rcx \n\t"
1474 "mov %c[rdx](%[vcpu]), %%rdx \n\t"
1475 "mov %c[rsi](%[vcpu]), %%rsi \n\t"
1476 "mov %c[rdi](%[vcpu]), %%rdi \n\t"
1477 "mov %c[rbp](%[vcpu]), %%rbp \n\t"
1478 "mov %c[r8](%[vcpu]), %%r8 \n\t"
1479 "mov %c[r9](%[vcpu]), %%r9 \n\t"
1480 "mov %c[r10](%[vcpu]), %%r10 \n\t"
1481 "mov %c[r11](%[vcpu]), %%r11 \n\t"
1482 "mov %c[r12](%[vcpu]), %%r12 \n\t"
1483 "mov %c[r13](%[vcpu]), %%r13 \n\t"
1484 "mov %c[r14](%[vcpu]), %%r14 \n\t"
1485 "mov %c[r15](%[vcpu]), %%r15 \n\t"
1486 #else
1487 "mov %c[rbx](%[vcpu]), %%ebx \n\t"
1488 "mov %c[rcx](%[vcpu]), %%ecx \n\t"
1489 "mov %c[rdx](%[vcpu]), %%edx \n\t"
1490 "mov %c[rsi](%[vcpu]), %%esi \n\t"
1491 "mov %c[rdi](%[vcpu]), %%edi \n\t"
1492 "mov %c[rbp](%[vcpu]), %%ebp \n\t"
1493 #endif
1494
1495 #ifdef CONFIG_X86_64
1496 /* Enter guest mode */
1497 "push %%rax \n\t"
1498 "mov %c[svm](%[vcpu]), %%rax \n\t"
1499 "mov %c[vmcb](%%rax), %%rax \n\t"
1500 SVM_VMLOAD "\n\t"
1501 SVM_VMRUN "\n\t"
1502 SVM_VMSAVE "\n\t"
1503 "pop %%rax \n\t"
1504 #else
1505 /* Enter guest mode */
1506 "push %%eax \n\t"
1507 "mov %c[svm](%[vcpu]), %%eax \n\t"
1508 "mov %c[vmcb](%%eax), %%eax \n\t"
1509 SVM_VMLOAD "\n\t"
1510 SVM_VMRUN "\n\t"
1511 SVM_VMSAVE "\n\t"
1512 "pop %%eax \n\t"
1513 #endif
1514
1515 /* Save guest registers, load host registers */
1516 #ifdef CONFIG_X86_64
1517 "mov %%rbx, %c[rbx](%[vcpu]) \n\t"
1518 "mov %%rcx, %c[rcx](%[vcpu]) \n\t"
1519 "mov %%rdx, %c[rdx](%[vcpu]) \n\t"
1520 "mov %%rsi, %c[rsi](%[vcpu]) \n\t"
1521 "mov %%rdi, %c[rdi](%[vcpu]) \n\t"
1522 "mov %%rbp, %c[rbp](%[vcpu]) \n\t"
1523 "mov %%r8, %c[r8](%[vcpu]) \n\t"
1524 "mov %%r9, %c[r9](%[vcpu]) \n\t"
1525 "mov %%r10, %c[r10](%[vcpu]) \n\t"
1526 "mov %%r11, %c[r11](%[vcpu]) \n\t"
1527 "mov %%r12, %c[r12](%[vcpu]) \n\t"
1528 "mov %%r13, %c[r13](%[vcpu]) \n\t"
1529 "mov %%r14, %c[r14](%[vcpu]) \n\t"
1530 "mov %%r15, %c[r15](%[vcpu]) \n\t"
1531
1532 "pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1533 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1534 "pop %%rbp; pop %%rdi; pop %%rsi;"
1535 "pop %%rdx; pop %%rcx; pop %%rbx; \n\t"
1536 #else
1537 "mov %%ebx, %c[rbx](%[vcpu]) \n\t"
1538 "mov %%ecx, %c[rcx](%[vcpu]) \n\t"
1539 "mov %%edx, %c[rdx](%[vcpu]) \n\t"
1540 "mov %%esi, %c[rsi](%[vcpu]) \n\t"
1541 "mov %%edi, %c[rdi](%[vcpu]) \n\t"
1542 "mov %%ebp, %c[rbp](%[vcpu]) \n\t"
1543
1544 "pop %%ebp; pop %%edi; pop %%esi;"
1545 "pop %%edx; pop %%ecx; pop %%ebx; \n\t"
1546 #endif
1547 :
1548 : [vcpu]"a"(vcpu),
1549 [svm]"i"(offsetof(struct kvm_vcpu, svm)),
1550 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1551 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
1552 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
1553 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
1554 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
1555 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
1556 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP]))
1557 #ifdef CONFIG_X86_64
1558 ,[r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
1559 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
1560 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
1561 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
1562 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
1563 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
1564 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
1565 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15]))
1566 #endif
1567 : "cc", "memory" );
1568
1569 fx_save(vcpu->guest_fx_image);
1570 fx_restore(vcpu->host_fx_image);
1571
1572 if ((vcpu->svm->vmcb->save.dr7 & 0xff))
1573 load_db_regs(vcpu->svm->host_db_regs);
1574
1575 vcpu->cr2 = vcpu->svm->vmcb->save.cr2;
1576
1577 write_dr6(vcpu->svm->host_dr6);
1578 write_dr7(vcpu->svm->host_dr7);
1579 kvm_write_cr2(vcpu->svm->host_cr2);
1580
1581 load_fs(fs_selector);
1582 load_gs(gs_selector);
1583 load_ldt(ldt_selector);
1584 load_host_msrs(vcpu);
1585
1586 reload_tss(vcpu);
1587
1588 /*
1589 * Profile KVM exit RIPs:
1590 */
1591 if (unlikely(prof_on == KVM_PROFILING))
1592 profile_hit(KVM_PROFILING,
1593 (void *)(unsigned long)vcpu->svm->vmcb->save.rip);
1594
1595 stgi();
1596
1597 kvm_reput_irq(vcpu);
1598
1599 vcpu->svm->next_rip = 0;
1600
1601 if (vcpu->svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1602 kvm_run->exit_type = KVM_EXIT_TYPE_FAIL_ENTRY;
1603 kvm_run->exit_reason = vcpu->svm->vmcb->control.exit_code;
1604 post_kvm_run_save(vcpu, kvm_run);
1605 return 0;
1606 }
1607
1608 r = handle_exit(vcpu, kvm_run);
1609 if (r > 0) {
1610 if (signal_pending(current)) {
1611 ++kvm_stat.signal_exits;
1612 post_kvm_run_save(vcpu, kvm_run);
1613 return -EINTR;
1614 }
1615
1616 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
1617 ++kvm_stat.request_irq_exits;
1618 post_kvm_run_save(vcpu, kvm_run);
1619 return -EINTR;
1620 }
1621 kvm_resched(vcpu);
1622 goto again;
1623 }
1624 post_kvm_run_save(vcpu, kvm_run);
1625 return r;
1626 }
1627
1628 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1629 {
1630 force_new_asid(vcpu);
1631 }
1632
1633 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1634 {
1635 vcpu->svm->vmcb->save.cr3 = root;
1636 force_new_asid(vcpu);
1637 }
1638
1639 static void svm_inject_page_fault(struct kvm_vcpu *vcpu,
1640 unsigned long addr,
1641 uint32_t err_code)
1642 {
1643 uint32_t exit_int_info = vcpu->svm->vmcb->control.exit_int_info;
1644
1645 ++kvm_stat.pf_guest;
1646
1647 if (is_page_fault(exit_int_info)) {
1648
1649 vcpu->svm->vmcb->control.event_inj_err = 0;
1650 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1651 SVM_EVTINJ_VALID_ERR |
1652 SVM_EVTINJ_TYPE_EXEPT |
1653 DF_VECTOR;
1654 return;
1655 }
1656 vcpu->cr2 = addr;
1657 vcpu->svm->vmcb->save.cr2 = addr;
1658 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1659 SVM_EVTINJ_VALID_ERR |
1660 SVM_EVTINJ_TYPE_EXEPT |
1661 PF_VECTOR;
1662 vcpu->svm->vmcb->control.event_inj_err = err_code;
1663 }
1664
1665
1666 static int is_disabled(void)
1667 {
1668 return 0;
1669 }
1670
1671 static struct kvm_arch_ops svm_arch_ops = {
1672 .cpu_has_kvm_support = has_svm,
1673 .disabled_by_bios = is_disabled,
1674 .hardware_setup = svm_hardware_setup,
1675 .hardware_unsetup = svm_hardware_unsetup,
1676 .hardware_enable = svm_hardware_enable,
1677 .hardware_disable = svm_hardware_disable,
1678
1679 .vcpu_create = svm_create_vcpu,
1680 .vcpu_free = svm_free_vcpu,
1681
1682 .vcpu_load = svm_vcpu_load,
1683 .vcpu_put = svm_vcpu_put,
1684 .vcpu_decache = svm_vcpu_decache,
1685
1686 .set_guest_debug = svm_guest_debug,
1687 .get_msr = svm_get_msr,
1688 .set_msr = svm_set_msr,
1689 .get_segment_base = svm_get_segment_base,
1690 .get_segment = svm_get_segment,
1691 .set_segment = svm_set_segment,
1692 .get_cs_db_l_bits = svm_get_cs_db_l_bits,
1693 .decache_cr0_cr4_guest_bits = svm_decache_cr0_cr4_guest_bits,
1694 .set_cr0 = svm_set_cr0,
1695 .set_cr0_no_modeswitch = svm_set_cr0,
1696 .set_cr3 = svm_set_cr3,
1697 .set_cr4 = svm_set_cr4,
1698 .set_efer = svm_set_efer,
1699 .get_idt = svm_get_idt,
1700 .set_idt = svm_set_idt,
1701 .get_gdt = svm_get_gdt,
1702 .set_gdt = svm_set_gdt,
1703 .get_dr = svm_get_dr,
1704 .set_dr = svm_set_dr,
1705 .cache_regs = svm_cache_regs,
1706 .decache_regs = svm_decache_regs,
1707 .get_rflags = svm_get_rflags,
1708 .set_rflags = svm_set_rflags,
1709
1710 .invlpg = svm_invlpg,
1711 .tlb_flush = svm_flush_tlb,
1712 .inject_page_fault = svm_inject_page_fault,
1713
1714 .inject_gp = svm_inject_gp,
1715
1716 .run = svm_vcpu_run,
1717 .skip_emulated_instruction = skip_emulated_instruction,
1718 .vcpu_setup = svm_vcpu_setup,
1719 };
1720
1721 static int __init svm_init(void)
1722 {
1723 return kvm_init_arch(&svm_arch_ops, THIS_MODULE);
1724 }
1725
1726 static void __exit svm_exit(void)
1727 {
1728 kvm_exit_arch();
1729 }
1730
1731 module_init(svm_init)
1732 module_exit(svm_exit)
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