drivers/ide/pci/atiixp.c

   1 /*
   2  *  Copyright (C) 2003 ATI Inc. <hyu@ati.com>
   3  *  Copyright (C) 2004,2007 Bartlomiej Zolnierkiewicz
   4  */
   5
   6 #include <linux/types.h>
   7 #include <linux/module.h>
   8 #include <linux/kernel.h>
   9 #include <linux/pci.h>
  10 #include <linux/hdreg.h>
  11 #include <linux/ide.h>
  12 #include <linux/init.h>
  13
  14 #define DRV_NAME "atiixp"
  15
  16 #define ATIIXP_IDE_PIO_TIMING           0x40
  17 #define ATIIXP_IDE_MDMA_TIMING          0x44
  18 #define ATIIXP_IDE_PIO_CONTROL          0x48
  19 #define ATIIXP_IDE_PIO_MODE             0x4a
  20 #define ATIIXP_IDE_UDMA_CONTROL         0x54
  21 #define ATIIXP_IDE_UDMA_MODE            0x56
  22
  23 typedef struct {
  24         u8 command_width;
  25         u8 recover_width;
  26 } atiixp_ide_timing;
  27
  28 static atiixp_ide_timing pio_timing[] = {
  29         { 0x05, 0x0d },
  30         { 0x04, 0x07 },
  31         { 0x03, 0x04 },
  32         { 0x02, 0x02 },
  33         { 0x02, 0x00 },
  34 };
  35
  36 static atiixp_ide_timing mdma_timing[] = {
  37         { 0x07, 0x07 },
  38         { 0x02, 0x01 },
  39         { 0x02, 0x00 },
  40 };
  41
  42 static DEFINE_SPINLOCK(atiixp_lock);
  43
  44 /**
  45  *      atiixp_set_pio_mode     -       set host controller for PIO mode
  46  *      @drive: drive
  47  *      @pio: PIO mode number
  48  *
  49  *      Set the interface PIO mode.
  50  */
  51
  52 static void atiixp_set_pio_mode(ide_drive_t *drive, const u8 pio)
  53 {
  54         struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  55         unsigned long flags;
  56         int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
  57         u32 pio_timing_data;
  58         u16 pio_mode_data;
  59
  60         spin_lock_irqsave(&atiixp_lock, flags);
  61
  62         pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
  63         pio_mode_data &= ~(0x07 << (drive->dn * 4));
  64         pio_mode_data |= (pio << (drive->dn * 4));
  65         pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
  66
  67         pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
  68         pio_timing_data &= ~(0xff << timing_shift);
  69         pio_timing_data |= (pio_timing[pio].recover_width << timing_shift) |
  70                  (pio_timing[pio].command_width << (timing_shift + 4));
  71         pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
  72
  73         spin_unlock_irqrestore(&atiixp_lock, flags);
  74 }
  75
  76 /**
  77  *      atiixp_set_dma_mode     -       set host controller for DMA mode
  78  *      @drive: drive
  79  *      @speed: DMA mode
  80  *
  81  *      Set a ATIIXP host controller to the desired DMA mode.  This involves
  82  *      programming the right timing data into the PCI configuration space.
  83  */
  84
  85 static void atiixp_set_dma_mode(ide_drive_t *drive, const u8 speed)
  86 {
  87         struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  88         unsigned long flags;
  89         int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
  90         u32 tmp32;
  91         u16 tmp16;
  92         u16 udma_ctl = 0;
  93
  94         spin_lock_irqsave(&atiixp_lock, flags);
  95
  96         pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &udma_ctl);
  97
  98         if (speed >= XFER_UDMA_0) {
  99                 pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16);
 100                 tmp16 &= ~(0x07 << (drive->dn * 4));
 101                 tmp16 |= ((speed & 0x07) << (drive->dn * 4));
 102                 pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16);
 103
 104                 udma_ctl |= (1 << drive->dn);
 105         } else if (speed >= XFER_MW_DMA_0) {
 106                 u8 i = speed & 0x03;
 107
 108                 pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32);
 109                 tmp32 &= ~(0xff << timing_shift);
 110                 tmp32 |= (mdma_timing[i].recover_width << timing_shift) |
 111                          (mdma_timing[i].command_width << (timing_shift + 4));
 112                 pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32);
 113
 114                 udma_ctl &= ~(1 << drive->dn);
 115         }
 116
 117         pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, udma_ctl);
 118
 119         spin_unlock_irqrestore(&atiixp_lock, flags);
 120 }
 121
 122 static u8 __devinit atiixp_cable_detect(ide_hwif_t *hwif)
 123 {
 124         struct pci_dev *pdev = to_pci_dev(hwif->dev);
 125         u8 udma_mode = 0, ch = hwif->channel;
 126
 127         pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);
 128
 129         if ((udma_mode & 0x07) >= 0x04 || (udma_mode & 0x70) >= 0x40)
 130                 return ATA_CBL_PATA80;
 131         else
 132                 return ATA_CBL_PATA40;
 133 }
 134
 135 static const struct ide_port_ops atiixp_port_ops = {
 136         .set_pio_mode           = atiixp_set_pio_mode,
 137         .set_dma_mode           = atiixp_set_dma_mode,
 138         .cable_detect           = atiixp_cable_detect,
 139 };
 140
 141 static const struct ide_port_info atiixp_pci_info[] __devinitdata = {
 142         {       /* 0: IXP200/300/400/700 */
 143                 .name           = DRV_NAME,
 144                 .enablebits     = {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
 145                 .port_ops       = &atiixp_port_ops,
 146                 .host_flags     = IDE_HFLAG_LEGACY_IRQS,
 147                 .pio_mask       = ATA_PIO4,
 148                 .mwdma_mask     = ATA_MWDMA2,
 149                 .udma_mask      = ATA_UDMA5,
 150         },
 151         {       /* 1: IXP600 */
 152                 .name           = DRV_NAME,
 153                 .enablebits     = {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
 154                 .port_ops       = &atiixp_port_ops,
 155                 .host_flags     = IDE_HFLAG_SINGLE | IDE_HFLAG_LEGACY_IRQS,
 156                 .pio_mask       = ATA_PIO4,
 157                 .mwdma_mask     = ATA_MWDMA2,
 158                 .udma_mask      = ATA_UDMA5,
 159         },
 160 };
 161
 162 /**
 163  *      atiixp_init_one -       called when a ATIIXP is found
 164  *      @dev: the atiixp device
 165  *      @id: the matching pci id
 166  *
 167  *      Called when the PCI registration layer (or the IDE initialization)
 168  *      finds a device matching our IDE device tables.
 169  */
 170
 171 static int __devinit atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 172 {
 173         return ide_pci_init_one(dev, &atiixp_pci_info[id->driver_data], NULL);
 174 }
 175
 176 static const struct pci_device_id atiixp_pci_tbl[] = {
 177         { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), 0 },
 178         { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), 0 },
 179         { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), 0 },
 180         { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), 1 },
 181         { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), 0 },
 182         { 0, },
 183 };
 184 MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl);
 185
 186 static struct pci_driver driver = {
 187         .name           = "ATIIXP_IDE",
 188         .id_table       = atiixp_pci_tbl,
 189         .probe          = atiixp_init_one,
 190         .remove         = ide_pci_remove,
 191 };
 192
 193 static int __init atiixp_ide_init(void)
 194 {
 195         return ide_pci_register_driver(&driver);
 196 }
 197
 198 static void __exit atiixp_ide_exit(void)
 199 {
 200         pci_unregister_driver(&driver);
 201 }
 202
 203 module_init(atiixp_ide_init);
 204 module_exit(atiixp_ide_exit);
 205
 206 MODULE_AUTHOR("HUI YU");
 207 MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE");
 208 MODULE_LICENSE("GPL");