2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/config.h>
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/version.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
37 #include <linux/tcp.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.3"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
64 #define RX_LE_SIZE 512
65 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
66 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
67 #define RX_DEF_PENDING RX_MAX_PENDING
68 #define RX_SKB_ALIGN 8
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define ETH_JUMBO_MTU 9000
78 #define TX_WATCHDOG (5 * HZ)
79 #define NAPI_WEIGHT 64
80 #define PHY_RETRIES 1000
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84 static const u32 default_msg
=
85 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
86 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
89 static int debug
= -1; /* defaults above */
90 module_param(debug
, int, 0);
91 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
93 static int copybreak __read_mostly
= 256;
94 module_param(copybreak
, int, 0);
95 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
97 static int disable_msi
= 0;
98 module_param(disable_msi
, int, 0);
99 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
101 static int idle_timeout
= 100;
102 module_param(idle_timeout
, int, 0);
103 MODULE_PARM_DESC(idle_timeout
, "Idle timeout workaround for lost interrupts (ms)");
105 static const struct pci_device_id sky2_id_table
[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) },
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) },
126 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
128 /* Avoid conditionals by using array */
129 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
130 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
131 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
133 /* This driver supports yukon2 chipset only */
134 static const char *yukon2_name
[] = {
136 "EC Ultra", /* 0xb4 */
137 "UNKNOWN", /* 0xb5 */
142 /* Access to external PHY */
143 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
147 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
148 gma_write16(hw
, port
, GM_SMI_CTRL
,
149 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
151 for (i
= 0; i
< PHY_RETRIES
; i
++) {
152 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
157 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
161 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
165 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
166 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
168 for (i
= 0; i
< PHY_RETRIES
; i
++) {
169 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
170 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
180 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
184 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
185 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
189 static int sky2_set_power_state(struct sky2_hw
*hw
, pci_power_t state
)
196 pr_debug("sky2_set_power_state %d\n", state
);
197 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
199 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_PMC
);
200 vaux
= (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
) &&
201 (power_control
& PCI_PM_CAP_PME_D3cold
);
203 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
);
205 power_control
|= PCI_PM_CTRL_PME_STATUS
;
206 power_control
&= ~(PCI_PM_CTRL_STATE_MASK
);
210 /* switch power to VCC (WA for VAUX problem) */
211 sky2_write8(hw
, B0_POWER_CTRL
,
212 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
214 /* disable Core Clock Division, */
215 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
217 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
218 /* enable bits are inverted */
219 sky2_write8(hw
, B2_Y2_CLK_GATE
,
220 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
221 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
222 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
224 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
226 /* Turn off phy power saving */
227 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
228 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
230 /* looks like this XL is back asswards .. */
231 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1) {
232 reg1
|= PCI_Y2_PHY1_COMA
;
234 reg1
|= PCI_Y2_PHY2_COMA
;
237 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
238 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
239 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
240 reg1
&= P_ASPM_CONTROL_MSK
;
241 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg1
);
242 sky2_pci_write32(hw
, PCI_DEV_REG5
, 0);
245 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
251 /* Turn on phy power saving */
252 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
253 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
254 reg1
&= ~(PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
256 reg1
|= (PCI_Y2_PHY1_POWD
| PCI_Y2_PHY2_POWD
);
257 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
259 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
260 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
262 /* enable bits are inverted */
263 sky2_write8(hw
, B2_Y2_CLK_GATE
,
264 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
265 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
266 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
268 /* switch power to VAUX */
269 if (vaux
&& state
!= PCI_D3cold
)
270 sky2_write8(hw
, B0_POWER_CTRL
,
271 (PC_VAUX_ENA
| PC_VCC_ENA
|
272 PC_VAUX_ON
| PC_VCC_OFF
));
275 printk(KERN_ERR PFX
"Unknown power state %d\n", state
);
279 sky2_pci_write16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
, power_control
);
280 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
284 static void sky2_phy_reset(struct sky2_hw
*hw
, unsigned port
)
288 /* disable all GMAC IRQ's */
289 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
290 /* disable PHY IRQs */
291 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
293 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
294 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
295 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
296 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
298 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
299 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
300 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
303 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
305 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
306 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
;
308 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
309 (hw
->chip_id
!= CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)) {
310 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
312 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
314 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
316 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
317 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
319 ectrl
|= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
321 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
324 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
326 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
327 /* enable automatic crossover */
328 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
330 /* disable energy detect */
331 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
333 /* enable automatic crossover */
334 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
336 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
337 (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)) {
338 ctrl
&= ~PHY_M_PC_DSC_MSK
;
339 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
342 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
344 /* workaround for deviation #4.88 (CRC errors) */
345 /* disable Automatic Crossover */
347 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
348 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
350 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
351 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
352 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
353 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
354 ctrl
&= ~PHY_M_MAC_MD_MSK
;
355 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
356 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
358 /* select page 1 to access Fiber registers */
359 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
363 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
364 if (sky2
->autoneg
== AUTONEG_DISABLE
)
369 ctrl
|= PHY_CT_RESET
;
370 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
376 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
378 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
379 ct1000
|= PHY_M_1000C_AFD
;
380 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
381 ct1000
|= PHY_M_1000C_AHD
;
382 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
383 adv
|= PHY_M_AN_100_FD
;
384 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
385 adv
|= PHY_M_AN_100_HD
;
386 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
387 adv
|= PHY_M_AN_10_FD
;
388 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
389 adv
|= PHY_M_AN_10_HD
;
390 } else /* special defines for FIBER (88E1011S only) */
391 adv
|= PHY_M_AN_1000X_AHD
| PHY_M_AN_1000X_AFD
;
393 /* Set Flow-control capabilities */
394 if (sky2
->tx_pause
&& sky2
->rx_pause
)
395 adv
|= PHY_AN_PAUSE_CAP
; /* symmetric */
396 else if (sky2
->rx_pause
&& !sky2
->tx_pause
)
397 adv
|= PHY_AN_PAUSE_ASYM
| PHY_AN_PAUSE_CAP
;
398 else if (!sky2
->rx_pause
&& sky2
->tx_pause
)
399 adv
|= PHY_AN_PAUSE_ASYM
; /* local */
401 /* Restart Auto-negotiation */
402 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
404 /* forced speed/duplex settings */
405 ct1000
= PHY_M_1000C_MSE
;
407 if (sky2
->duplex
== DUPLEX_FULL
)
408 ctrl
|= PHY_CT_DUP_MD
;
410 switch (sky2
->speed
) {
412 ctrl
|= PHY_CT_SP1000
;
415 ctrl
|= PHY_CT_SP100
;
419 ctrl
|= PHY_CT_RESET
;
422 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
423 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
425 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
426 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
428 /* Setup Phy LED's */
429 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
432 switch (hw
->chip_id
) {
433 case CHIP_ID_YUKON_FE
:
434 /* on 88E3082 these bits are at 11..9 (shifted left) */
435 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
437 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
439 /* delete ACT LED control bits */
440 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
441 /* change ACT LED control to blink mode */
442 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
443 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
446 case CHIP_ID_YUKON_XL
:
447 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
449 /* select page 3 to access LED control register */
450 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
452 /* set LED Function Control register */
453 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
454 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
455 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
456 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
457 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
459 /* set Polarity Control register */
460 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
461 (PHY_M_POLC_LS1_P_MIX(4) |
462 PHY_M_POLC_IS0_P_MIX(4) |
463 PHY_M_POLC_LOS_CTRL(2) |
464 PHY_M_POLC_INIT_CTRL(2) |
465 PHY_M_POLC_STA1_CTRL(2) |
466 PHY_M_POLC_STA0_CTRL(2)));
468 /* restore page register */
469 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
471 case CHIP_ID_YUKON_EC_U
:
472 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
474 /* select page 3 to access LED control register */
475 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
477 /* set LED Function Control register */
478 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
479 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
480 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
481 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
482 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
484 /* set Blink Rate in LED Timer Control Register */
485 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
486 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
487 /* restore page register */
488 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
492 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
493 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
494 /* turn off the Rx LED (LED_RX) */
495 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
498 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
499 /* apply fixes in PHY AFE */
500 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
501 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
503 /* increase differential signal amplitude in 10BASE-T */
504 gm_phy_write(hw
, port
, 0x18, 0xaa99);
505 gm_phy_write(hw
, port
, 0x17, 0x2011);
507 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
508 gm_phy_write(hw
, port
, 0x18, 0xa204);
509 gm_phy_write(hw
, port
, 0x17, 0x2002);
511 /* set page register to 0 */
512 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
514 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
516 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
517 /* turn on 100 Mbps LED (LED_LINK100) */
518 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
522 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
525 /* Enable phy interrupt on auto-negotiation complete (or link up) */
526 if (sky2
->autoneg
== AUTONEG_ENABLE
)
527 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
529 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
532 /* Force a renegotiation */
533 static void sky2_phy_reinit(struct sky2_port
*sky2
)
535 spin_lock_bh(&sky2
->phy_lock
);
536 sky2_phy_init(sky2
->hw
, sky2
->port
);
537 spin_unlock_bh(&sky2
->phy_lock
);
540 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
542 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
545 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
547 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
548 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
|GPC_ENA_PAUSE
);
550 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
552 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
553 /* WA DEV_472 -- looks like crossed wires on port 2 */
554 /* clear GMAC 1 Control reset */
555 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
557 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
558 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
559 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
560 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
561 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
564 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
565 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
566 reg
|= GM_GPCR_AU_ALL_DIS
;
567 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
568 gma_read16(hw
, port
, GM_GP_CTRL
);
570 switch (sky2
->speed
) {
572 reg
&= ~GM_GPCR_SPEED_100
;
573 reg
|= GM_GPCR_SPEED_1000
;
576 reg
&= ~GM_GPCR_SPEED_1000
;
577 reg
|= GM_GPCR_SPEED_100
;
580 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
584 if (sky2
->duplex
== DUPLEX_FULL
)
585 reg
|= GM_GPCR_DUP_FULL
;
587 /* turn off pause in 10/100mbps half duplex */
588 else if (sky2
->speed
!= SPEED_1000
&&
589 hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
590 sky2
->tx_pause
= sky2
->rx_pause
= 0;
592 reg
= GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
| GM_GPCR_DUP_FULL
;
594 if (!sky2
->tx_pause
&& !sky2
->rx_pause
) {
595 sky2_write32(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
597 GM_GPCR_FC_TX_DIS
| GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
598 } else if (sky2
->tx_pause
&& !sky2
->rx_pause
) {
599 /* disable Rx flow-control */
600 reg
|= GM_GPCR_FC_RX_DIS
| GM_GPCR_AU_FCT_DIS
;
603 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
605 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
607 spin_lock_bh(&sky2
->phy_lock
);
608 sky2_phy_init(hw
, port
);
609 spin_unlock_bh(&sky2
->phy_lock
);
612 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
613 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
615 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
616 gma_read16(hw
, port
, i
);
617 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
619 /* transmit control */
620 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
622 /* receive control reg: unicast + multicast + no FCS */
623 gma_write16(hw
, port
, GM_RX_CTRL
,
624 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
626 /* transmit flow control */
627 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
629 /* transmit parameter */
630 gma_write16(hw
, port
, GM_TX_PARAM
,
631 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
632 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
633 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
634 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
636 /* serial mode register */
637 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
638 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
640 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
641 reg
|= GM_SMOD_JUMBO_ENA
;
643 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
645 /* virtual address for data */
646 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
648 /* physical address: used for pause frames */
649 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
651 /* ignore counter overflows */
652 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
653 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
654 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
656 /* Configure Rx MAC FIFO */
657 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
658 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
659 GMF_OPER_ON
| GMF_RX_F_FL_ON
);
661 /* Flush Rx MAC FIFO on any flow control or error */
662 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
664 /* Set threshold to 0xa (64 bytes)
665 * ASF disabled so no need to do WA dev #4.30
667 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
);
669 /* Configure Tx MAC FIFO */
670 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
671 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
673 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
674 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
675 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
676 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
677 /* set Tx GMAC FIFO Almost Empty Threshold */
678 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
), 0x180);
679 /* Disable Store & Forward mode for TX */
680 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
686 /* Assign Ram Buffer allocation.
687 * start and end are in units of 4k bytes
688 * ram registers are in units of 64bit words
690 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u8 startk
, u8 endk
)
694 start
= startk
* 4096/8;
695 end
= (endk
* 4096/8) - 1;
697 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
698 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
699 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
700 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
701 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
703 if (q
== Q_R1
|| q
== Q_R2
) {
704 u32 space
= (endk
- startk
) * 4096/8;
705 u32 tp
= space
- space
/4;
707 /* On receive queue's set the thresholds
708 * give receiver priority when > 3/4 full
709 * send pause when down to 2K
711 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
712 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
715 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
716 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
718 /* Enable store & forward on Tx queue's because
719 * Tx FIFO is only 1K on Yukon
721 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
724 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
725 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
728 /* Setup Bus Memory Interface */
729 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
731 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
732 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
733 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
734 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
737 /* Setup prefetch unit registers. This is the interface between
738 * hardware and driver list elements
740 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
743 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
744 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
745 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
746 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
747 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
748 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
750 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
753 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
755 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
757 sky2
->tx_prod
= RING_NEXT(sky2
->tx_prod
, TX_RING_SIZE
);
761 /* Update chip's next pointer */
762 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
765 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
770 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
772 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
773 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
777 /* Return high part of DMA address (could be 32 or 64 bit) */
778 static inline u32
high32(dma_addr_t a
)
780 return sizeof(a
) > sizeof(u32
) ? (a
>> 16) >> 16 : 0;
783 /* Build description to hardware about buffer */
784 static void sky2_rx_add(struct sky2_port
*sky2
, dma_addr_t map
)
786 struct sky2_rx_le
*le
;
787 u32 hi
= high32(map
);
788 u16 len
= sky2
->rx_bufsize
;
790 if (sky2
->rx_addr64
!= hi
) {
791 le
= sky2_next_rx(sky2
);
792 le
->addr
= cpu_to_le32(hi
);
794 le
->opcode
= OP_ADDR64
| HW_OWNER
;
795 sky2
->rx_addr64
= high32(map
+ len
);
798 le
= sky2_next_rx(sky2
);
799 le
->addr
= cpu_to_le32((u32
) map
);
800 le
->length
= cpu_to_le16(len
);
802 le
->opcode
= OP_PACKET
| HW_OWNER
;
806 /* Tell chip where to start receive checksum.
807 * Actually has two checksums, but set both same to avoid possible byte
810 static void rx_set_checksum(struct sky2_port
*sky2
)
812 struct sky2_rx_le
*le
;
814 le
= sky2_next_rx(sky2
);
815 le
->addr
= (ETH_HLEN
<< 16) | ETH_HLEN
;
817 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
819 sky2_write32(sky2
->hw
,
820 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
821 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
826 * The RX Stop command will not work for Yukon-2 if the BMU does not
827 * reach the end of packet and since we can't make sure that we have
828 * incoming data, we must reset the BMU while it is not doing a DMA
829 * transfer. Since it is possible that the RX path is still active,
830 * the RX RAM buffer will be stopped first, so any possible incoming
831 * data will not trigger a DMA. After the RAM buffer is stopped, the
832 * BMU is polled until any DMA in progress is ended and only then it
835 static void sky2_rx_stop(struct sky2_port
*sky2
)
837 struct sky2_hw
*hw
= sky2
->hw
;
838 unsigned rxq
= rxqaddr
[sky2
->port
];
841 /* disable the RAM Buffer receive queue */
842 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
844 for (i
= 0; i
< 0xffff; i
++)
845 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
846 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
849 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
852 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
854 /* reset the Rx prefetch unit */
855 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
858 /* Clean out receive buffer area, assumes receiver hardware stopped */
859 static void sky2_rx_clean(struct sky2_port
*sky2
)
863 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
864 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
865 struct ring_info
*re
= sky2
->rx_ring
+ i
;
868 pci_unmap_single(sky2
->hw
->pdev
,
869 re
->mapaddr
, sky2
->rx_bufsize
,
877 /* Basic MII support */
878 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
880 struct mii_ioctl_data
*data
= if_mii(ifr
);
881 struct sky2_port
*sky2
= netdev_priv(dev
);
882 struct sky2_hw
*hw
= sky2
->hw
;
883 int err
= -EOPNOTSUPP
;
885 if (!netif_running(dev
))
886 return -ENODEV
; /* Phy still in reset */
890 data
->phy_id
= PHY_ADDR_MARV
;
896 spin_lock_bh(&sky2
->phy_lock
);
897 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
898 spin_unlock_bh(&sky2
->phy_lock
);
905 if (!capable(CAP_NET_ADMIN
))
908 spin_lock_bh(&sky2
->phy_lock
);
909 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
911 spin_unlock_bh(&sky2
->phy_lock
);
917 #ifdef SKY2_VLAN_TAG_USED
918 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
920 struct sky2_port
*sky2
= netdev_priv(dev
);
921 struct sky2_hw
*hw
= sky2
->hw
;
922 u16 port
= sky2
->port
;
924 spin_lock_bh(&sky2
->tx_lock
);
926 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_ON
);
927 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_ON
);
930 spin_unlock_bh(&sky2
->tx_lock
);
933 static void sky2_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
935 struct sky2_port
*sky2
= netdev_priv(dev
);
936 struct sky2_hw
*hw
= sky2
->hw
;
937 u16 port
= sky2
->port
;
939 spin_lock_bh(&sky2
->tx_lock
);
941 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_OFF
);
942 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_OFF
);
944 sky2
->vlgrp
->vlan_devices
[vid
] = NULL
;
946 spin_unlock_bh(&sky2
->tx_lock
);
951 * It appears the hardware has a bug in the FIFO logic that
952 * cause it to hang if the FIFO gets overrun and the receive buffer
953 * is not aligned. ALso alloc_skb() won't align properly if slab
954 * debugging is enabled.
956 static inline struct sk_buff
*sky2_alloc_skb(unsigned int size
, gfp_t gfp_mask
)
960 skb
= alloc_skb(size
+ RX_SKB_ALIGN
, gfp_mask
);
962 unsigned long p
= (unsigned long) skb
->data
;
963 skb_reserve(skb
, ALIGN(p
, RX_SKB_ALIGN
) - p
);
970 * Allocate and setup receiver buffer pool.
971 * In case of 64 bit dma, there are 2X as many list elements
972 * available as ring entries
973 * and need to reserve one list element so we don't wrap around.
975 static int sky2_rx_start(struct sky2_port
*sky2
)
977 struct sky2_hw
*hw
= sky2
->hw
;
978 unsigned rxq
= rxqaddr
[sky2
->port
];
981 sky2
->rx_put
= sky2
->rx_next
= 0;
984 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
>= 2) {
985 /* MAC Rx RAM Read is controlled by hardware */
986 sky2_write32(hw
, Q_ADDR(rxq
, Q_F
), F_M_RX_RAM_DIS
);
989 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
991 rx_set_checksum(sky2
);
992 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
993 struct ring_info
*re
= sky2
->rx_ring
+ i
;
995 re
->skb
= sky2_alloc_skb(sky2
->rx_bufsize
, GFP_KERNEL
);
999 re
->mapaddr
= pci_map_single(hw
->pdev
, re
->skb
->data
,
1000 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1001 sky2_rx_add(sky2
, re
->mapaddr
);
1004 /* Truncate oversize frames */
1005 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), sky2
->rx_bufsize
- 8);
1006 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1008 /* Tell chip about available buffers */
1009 sky2_write16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
), sky2
->rx_put
);
1012 sky2_rx_clean(sky2
);
1016 /* Bring up network interface. */
1017 static int sky2_up(struct net_device
*dev
)
1019 struct sky2_port
*sky2
= netdev_priv(dev
);
1020 struct sky2_hw
*hw
= sky2
->hw
;
1021 unsigned port
= sky2
->port
;
1022 u32 ramsize
, rxspace
, imask
;
1024 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1026 /* Block bringing up both ports at the same time on a dual port card.
1027 * There is an unfixed bug where receiver gets confused and picks up
1028 * packets out of order. Until this is fixed, prevent data corruption.
1030 if (otherdev
&& netif_running(otherdev
)) {
1031 printk(KERN_INFO PFX
"dual port support is disabled.\n");
1036 if (netif_msg_ifup(sky2
))
1037 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1039 /* must be power of 2 */
1040 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1042 sizeof(struct sky2_tx_le
),
1047 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1051 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1053 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1057 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1059 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct ring_info
),
1064 sky2_mac_init(hw
, port
);
1066 /* Determine available ram buffer space (in 4K blocks).
1067 * Note: not sure about the FE setting below yet
1069 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1072 ramsize
= sky2_read8(hw
, B2_E_0
);
1074 /* Give transmitter one third (rounded up) */
1075 rxspace
= ramsize
- (ramsize
+ 2) / 3;
1077 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1078 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
);
1080 /* Make sure SyncQ is disabled */
1081 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1084 sky2_qset(hw
, txqaddr
[port
]);
1086 /* Set almost empty threshold */
1087 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
== 1)
1088 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), 0x1a0);
1090 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1093 err
= sky2_rx_start(sky2
);
1097 /* Enable interrupts from phy/mac for port */
1098 imask
= sky2_read32(hw
, B0_IMSK
);
1099 imask
|= portirq_msk
[port
];
1100 sky2_write32(hw
, B0_IMSK
, imask
);
1106 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1107 sky2
->rx_le
, sky2
->rx_le_map
);
1111 pci_free_consistent(hw
->pdev
,
1112 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1113 sky2
->tx_le
, sky2
->tx_le_map
);
1116 kfree(sky2
->tx_ring
);
1117 kfree(sky2
->rx_ring
);
1119 sky2
->tx_ring
= NULL
;
1120 sky2
->rx_ring
= NULL
;
1124 /* Modular subtraction in ring */
1125 static inline int tx_dist(unsigned tail
, unsigned head
)
1127 return (head
- tail
) & (TX_RING_SIZE
- 1);
1130 /* Number of list elements available for next tx */
1131 static inline int tx_avail(const struct sky2_port
*sky2
)
1133 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1136 /* Estimate of number of transmit list elements required */
1137 static unsigned tx_le_req(const struct sk_buff
*skb
)
1141 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1142 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1144 if (skb_shinfo(skb
)->tso_size
)
1147 if (skb
->ip_summed
== CHECKSUM_HW
)
1154 * Put one packet in ring for transmit.
1155 * A single packet can generate multiple list elements, and
1156 * the number of ring elements will probably be less than the number
1157 * of list elements used.
1159 * No BH disabling for tx_lock here (like tg3)
1161 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1163 struct sky2_port
*sky2
= netdev_priv(dev
);
1164 struct sky2_hw
*hw
= sky2
->hw
;
1165 struct sky2_tx_le
*le
= NULL
;
1166 struct tx_ring_info
*re
;
1174 /* No BH disabling for tx_lock here. We are running in BH disabled
1175 * context and TX reclaim runs via poll inside of a software
1176 * interrupt, and no related locks in IRQ processing.
1178 if (!spin_trylock(&sky2
->tx_lock
))
1179 return NETDEV_TX_LOCKED
;
1181 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
))) {
1182 /* There is a known but harmless race with lockless tx
1183 * and netif_stop_queue.
1185 if (!netif_queue_stopped(dev
)) {
1186 netif_stop_queue(dev
);
1187 if (net_ratelimit())
1188 printk(KERN_WARNING PFX
"%s: ring full when queue awake!\n",
1191 spin_unlock(&sky2
->tx_lock
);
1193 return NETDEV_TX_BUSY
;
1196 if (unlikely(netif_msg_tx_queued(sky2
)))
1197 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1198 dev
->name
, sky2
->tx_prod
, skb
->len
);
1200 len
= skb_headlen(skb
);
1201 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1202 addr64
= high32(mapping
);
1204 re
= sky2
->tx_ring
+ sky2
->tx_prod
;
1206 /* Send high bits if changed or crosses boundary */
1207 if (addr64
!= sky2
->tx_addr64
|| high32(mapping
+ len
) != sky2
->tx_addr64
) {
1208 le
= get_tx_le(sky2
);
1209 le
->tx
.addr
= cpu_to_le32(addr64
);
1211 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1212 sky2
->tx_addr64
= high32(mapping
+ len
);
1215 /* Check for TCP Segmentation Offload */
1216 mss
= skb_shinfo(skb
)->tso_size
;
1218 /* just drop the packet if non-linear expansion fails */
1219 if (skb_header_cloned(skb
) &&
1220 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
1225 mss
+= ((skb
->h
.th
->doff
- 5) * 4); /* TCP options */
1226 mss
+= (skb
->nh
.iph
->ihl
* 4) + sizeof(struct tcphdr
);
1230 if (mss
!= sky2
->tx_last_mss
) {
1231 le
= get_tx_le(sky2
);
1232 le
->tx
.tso
.size
= cpu_to_le16(mss
);
1233 le
->tx
.tso
.rsvd
= 0;
1234 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1236 sky2
->tx_last_mss
= mss
;
1240 #ifdef SKY2_VLAN_TAG_USED
1241 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1242 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1244 le
= get_tx_le(sky2
);
1246 le
->opcode
= OP_VLAN
|HW_OWNER
;
1249 le
->opcode
|= OP_VLAN
;
1250 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1255 /* Handle TCP checksum offload */
1256 if (skb
->ip_summed
== CHECKSUM_HW
) {
1257 u16 hdr
= skb
->h
.raw
- skb
->data
;
1258 u16 offset
= hdr
+ skb
->csum
;
1260 ctrl
= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1261 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
)
1264 le
= get_tx_le(sky2
);
1265 le
->tx
.csum
.start
= cpu_to_le16(hdr
);
1266 le
->tx
.csum
.offset
= cpu_to_le16(offset
);
1267 le
->length
= 0; /* initial checksum value */
1268 le
->ctrl
= 1; /* one packet */
1269 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1272 le
= get_tx_le(sky2
);
1273 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1274 le
->length
= cpu_to_le16(len
);
1276 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1278 /* Record the transmit mapping info */
1280 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1282 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1283 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1284 struct tx_ring_info
*fre
;
1286 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1287 frag
->size
, PCI_DMA_TODEVICE
);
1288 addr64
= high32(mapping
);
1289 if (addr64
!= sky2
->tx_addr64
) {
1290 le
= get_tx_le(sky2
);
1291 le
->tx
.addr
= cpu_to_le32(addr64
);
1293 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1294 sky2
->tx_addr64
= addr64
;
1297 le
= get_tx_le(sky2
);
1298 le
->tx
.addr
= cpu_to_le32((u32
) mapping
);
1299 le
->length
= cpu_to_le16(frag
->size
);
1301 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1304 + RING_NEXT((re
- sky2
->tx_ring
) + i
, TX_RING_SIZE
);
1305 pci_unmap_addr_set(fre
, mapaddr
, mapping
);
1308 re
->idx
= sky2
->tx_prod
;
1311 avail
= tx_avail(sky2
);
1312 if (mss
!= 0 || avail
< TX_MIN_PENDING
) {
1313 le
->ctrl
|= FRC_STAT
;
1314 if (avail
<= MAX_SKB_TX_LE
)
1315 netif_stop_queue(dev
);
1318 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1321 spin_unlock(&sky2
->tx_lock
);
1323 dev
->trans_start
= jiffies
;
1324 return NETDEV_TX_OK
;
1328 * Free ring elements from starting at tx_cons until "done"
1330 * NB: the hardware will tell us about partial completion of multi-part
1331 * buffers; these are deferred until completion.
1333 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1335 struct net_device
*dev
= sky2
->netdev
;
1336 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1340 BUG_ON(done
>= TX_RING_SIZE
);
1342 if (unlikely(netif_msg_tx_done(sky2
)))
1343 printk(KERN_DEBUG
"%s: tx done, up to %u\n",
1346 for (put
= sky2
->tx_cons
; put
!= done
; put
= nxt
) {
1347 struct tx_ring_info
*re
= sky2
->tx_ring
+ put
;
1348 struct sk_buff
*skb
= re
->skb
;
1351 BUG_ON(nxt
>= TX_RING_SIZE
);
1352 prefetch(sky2
->tx_ring
+ nxt
);
1354 /* Check for partial status */
1355 if (tx_dist(put
, done
) < tx_dist(put
, nxt
))
1359 pci_unmap_single(pdev
, pci_unmap_addr(re
, mapaddr
),
1360 skb_headlen(skb
), PCI_DMA_TODEVICE
);
1362 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1363 struct tx_ring_info
*fre
;
1364 fre
= sky2
->tx_ring
+ RING_NEXT(put
+ i
, TX_RING_SIZE
);
1365 pci_unmap_page(pdev
, pci_unmap_addr(fre
, mapaddr
),
1366 skb_shinfo(skb
)->frags
[i
].size
,
1373 sky2
->tx_cons
= put
;
1374 if (tx_avail(sky2
) > MAX_SKB_TX_LE
)
1375 netif_wake_queue(dev
);
1378 /* Cleanup all untransmitted buffers, assume transmitter not running */
1379 static void sky2_tx_clean(struct sky2_port
*sky2
)
1381 spin_lock_bh(&sky2
->tx_lock
);
1382 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1383 spin_unlock_bh(&sky2
->tx_lock
);
1386 /* Network shutdown */
1387 static int sky2_down(struct net_device
*dev
)
1389 struct sky2_port
*sky2
= netdev_priv(dev
);
1390 struct sky2_hw
*hw
= sky2
->hw
;
1391 unsigned port
= sky2
->port
;
1395 /* Never really got started! */
1399 if (netif_msg_ifdown(sky2
))
1400 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1402 /* Stop more packets from being queued */
1403 netif_stop_queue(dev
);
1405 sky2_phy_reset(hw
, port
);
1407 /* Stop transmitter */
1408 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1409 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1411 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1412 RB_RST_SET
| RB_DIS_OP_MD
);
1414 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1415 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1416 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1418 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1420 /* Workaround shared GMAC reset */
1421 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1422 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1423 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1425 /* Disable Force Sync bit and Enable Alloc bit */
1426 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1427 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1429 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1430 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1431 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1433 /* Reset the PCI FIFO of the async Tx queue */
1434 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1435 BMU_RST_SET
| BMU_FIFO_RST
);
1437 /* Reset the Tx prefetch units */
1438 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1441 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1445 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1446 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1448 /* Disable port IRQ */
1449 imask
= sky2_read32(hw
, B0_IMSK
);
1450 imask
&= ~portirq_msk
[port
];
1451 sky2_write32(hw
, B0_IMSK
, imask
);
1453 /* turn off LED's */
1454 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1456 synchronize_irq(hw
->pdev
->irq
);
1458 sky2_tx_clean(sky2
);
1459 sky2_rx_clean(sky2
);
1461 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1462 sky2
->rx_le
, sky2
->rx_le_map
);
1463 kfree(sky2
->rx_ring
);
1465 pci_free_consistent(hw
->pdev
,
1466 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1467 sky2
->tx_le
, sky2
->tx_le_map
);
1468 kfree(sky2
->tx_ring
);
1473 sky2
->rx_ring
= NULL
;
1474 sky2
->tx_ring
= NULL
;
1479 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1484 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1485 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1487 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1488 case PHY_M_PS_SPEED_1000
:
1490 case PHY_M_PS_SPEED_100
:
1497 static void sky2_link_up(struct sky2_port
*sky2
)
1499 struct sky2_hw
*hw
= sky2
->hw
;
1500 unsigned port
= sky2
->port
;
1503 /* Enable Transmit FIFO Underrun */
1504 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
1506 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1507 if (sky2
->autoneg
== AUTONEG_DISABLE
) {
1508 reg
|= GM_GPCR_AU_ALL_DIS
;
1510 /* Is write/read necessary? Copied from sky2_mac_init */
1511 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1512 gma_read16(hw
, port
, GM_GP_CTRL
);
1514 switch (sky2
->speed
) {
1516 reg
&= ~GM_GPCR_SPEED_100
;
1517 reg
|= GM_GPCR_SPEED_1000
;
1520 reg
&= ~GM_GPCR_SPEED_1000
;
1521 reg
|= GM_GPCR_SPEED_100
;
1524 reg
&= ~(GM_GPCR_SPEED_1000
| GM_GPCR_SPEED_100
);
1528 reg
&= ~GM_GPCR_AU_ALL_DIS
;
1530 if (sky2
->duplex
== DUPLEX_FULL
|| sky2
->autoneg
== AUTONEG_ENABLE
)
1531 reg
|= GM_GPCR_DUP_FULL
;
1534 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1535 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1536 gma_read16(hw
, port
, GM_GP_CTRL
);
1538 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1540 netif_carrier_on(sky2
->netdev
);
1541 netif_wake_queue(sky2
->netdev
);
1543 /* Turn on link LED */
1544 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1545 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1547 if (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
1548 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1549 u16 led
= PHY_M_LEDC_LOS_CTRL(1); /* link active */
1551 switch(sky2
->speed
) {
1553 led
|= PHY_M_LEDC_INIT_CTRL(7);
1557 led
|= PHY_M_LEDC_STA1_CTRL(7);
1561 led
|= PHY_M_LEDC_STA0_CTRL(7);
1565 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1566 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, led
);
1567 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1570 if (netif_msg_link(sky2
))
1571 printk(KERN_INFO PFX
1572 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1573 sky2
->netdev
->name
, sky2
->speed
,
1574 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1575 (sky2
->tx_pause
&& sky2
->rx_pause
) ? "both" :
1576 sky2
->tx_pause
? "tx" : sky2
->rx_pause
? "rx" : "none");
1579 static void sky2_link_down(struct sky2_port
*sky2
)
1581 struct sky2_hw
*hw
= sky2
->hw
;
1582 unsigned port
= sky2
->port
;
1585 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1587 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1588 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1589 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1590 gma_read16(hw
, port
, GM_GP_CTRL
); /* PCI post */
1592 if (sky2
->rx_pause
&& !sky2
->tx_pause
) {
1593 /* restore Asymmetric Pause bit */
1594 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
,
1595 gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
)
1599 netif_carrier_off(sky2
->netdev
);
1600 netif_stop_queue(sky2
->netdev
);
1602 /* Turn on link LED */
1603 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1605 if (netif_msg_link(sky2
))
1606 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1607 sky2_phy_init(hw
, port
);
1610 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1612 struct sky2_hw
*hw
= sky2
->hw
;
1613 unsigned port
= sky2
->port
;
1616 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1618 if (lpa
& PHY_M_AN_RF
) {
1619 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1623 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
&&
1624 gm_phy_read(hw
, port
, PHY_MARV_1000T_STAT
) & PHY_B_1000S_MSF
) {
1625 printk(KERN_ERR PFX
"%s: master/slave fault",
1626 sky2
->netdev
->name
);
1630 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1631 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1632 sky2
->netdev
->name
);
1636 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1638 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1640 /* Pause bits are offset (9..8) */
1641 if (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
1644 sky2
->rx_pause
= (aux
& PHY_M_PS_RX_P_EN
) != 0;
1645 sky2
->tx_pause
= (aux
& PHY_M_PS_TX_P_EN
) != 0;
1647 if ((sky2
->tx_pause
|| sky2
->rx_pause
)
1648 && !(sky2
->speed
< SPEED_1000
&& sky2
->duplex
== DUPLEX_HALF
))
1649 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1651 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1656 /* Interrupt from PHY */
1657 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1659 struct net_device
*dev
= hw
->dev
[port
];
1660 struct sky2_port
*sky2
= netdev_priv(dev
);
1661 u16 istatus
, phystat
;
1663 spin_lock(&sky2
->phy_lock
);
1664 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1665 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1667 if (!netif_running(dev
))
1670 if (netif_msg_intr(sky2
))
1671 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1672 sky2
->netdev
->name
, istatus
, phystat
);
1674 if (istatus
& PHY_M_IS_AN_COMPL
) {
1675 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1680 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1681 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1683 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1685 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1687 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1688 if (phystat
& PHY_M_PS_LINK_UP
)
1691 sky2_link_down(sky2
);
1694 spin_unlock(&sky2
->phy_lock
);
1698 /* Transmit timeout is only called if we are running, carries is up
1699 * and tx queue is full (stopped).
1701 static void sky2_tx_timeout(struct net_device
*dev
)
1703 struct sky2_port
*sky2
= netdev_priv(dev
);
1704 struct sky2_hw
*hw
= sky2
->hw
;
1705 unsigned txq
= txqaddr
[sky2
->port
];
1708 if (netif_msg_timer(sky2
))
1709 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1711 report
= sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
);
1712 done
= sky2_read16(hw
, Q_ADDR(txq
, Q_DONE
));
1714 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
1716 sky2
->tx_cons
, sky2
->tx_prod
, report
, done
);
1718 if (report
!= done
) {
1719 printk(KERN_INFO PFX
"status burst pending (irq moderation?)\n");
1721 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
1722 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
1723 } else if (report
!= sky2
->tx_cons
) {
1724 printk(KERN_INFO PFX
"status report lost?\n");
1726 spin_lock_bh(&sky2
->tx_lock
);
1727 sky2_tx_complete(sky2
, report
);
1728 spin_unlock_bh(&sky2
->tx_lock
);
1730 printk(KERN_INFO PFX
"hardware hung? flushing\n");
1732 sky2_write32(hw
, Q_ADDR(txq
, Q_CSR
), BMU_STOP
);
1733 sky2_write32(hw
, Y2_QADDR(txq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1735 sky2_tx_clean(sky2
);
1738 sky2_prefetch_init(hw
, txq
, sky2
->tx_le_map
, TX_RING_SIZE
- 1);
1743 /* Want receive buffer size to be multiple of 64 bits
1744 * and incl room for vlan and truncation
1746 static inline unsigned sky2_buf_size(int mtu
)
1748 return ALIGN(mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8) + 8;
1751 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1753 struct sky2_port
*sky2
= netdev_priv(dev
);
1754 struct sky2_hw
*hw
= sky2
->hw
;
1759 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1762 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& new_mtu
> ETH_DATA_LEN
)
1765 if (!netif_running(dev
)) {
1770 imask
= sky2_read32(hw
, B0_IMSK
);
1771 sky2_write32(hw
, B0_IMSK
, 0);
1773 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1774 netif_stop_queue(dev
);
1775 netif_poll_disable(hw
->dev
[0]);
1777 synchronize_irq(hw
->pdev
->irq
);
1779 ctl
= gma_read16(hw
, sky2
->port
, GM_GP_CTRL
);
1780 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1782 sky2_rx_clean(sky2
);
1785 sky2
->rx_bufsize
= sky2_buf_size(new_mtu
);
1786 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1787 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1789 if (dev
->mtu
> ETH_DATA_LEN
)
1790 mode
|= GM_SMOD_JUMBO_ENA
;
1792 gma_write16(hw
, sky2
->port
, GM_SERIAL_MODE
, mode
);
1794 sky2_write8(hw
, RB_ADDR(rxqaddr
[sky2
->port
], RB_CTRL
), RB_ENA_OP_MD
);
1796 err
= sky2_rx_start(sky2
);
1797 sky2_write32(hw
, B0_IMSK
, imask
);
1802 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
);
1804 netif_poll_enable(hw
->dev
[0]);
1805 netif_wake_queue(dev
);
1812 * Receive one packet.
1813 * For small packets or errors, just reuse existing skb.
1814 * For larger packets, get new buffer.
1816 static struct sk_buff
*sky2_receive(struct sky2_port
*sky2
,
1817 u16 length
, u32 status
)
1819 struct ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
1820 struct sk_buff
*skb
= NULL
;
1822 if (unlikely(netif_msg_rx_status(sky2
)))
1823 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
1824 sky2
->netdev
->name
, sky2
->rx_next
, status
, length
);
1826 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
1827 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
1829 if (status
& GMR_FS_ANY_ERR
)
1832 if (!(status
& GMR_FS_RX_OK
))
1835 if (length
> sky2
->netdev
->mtu
+ ETH_HLEN
)
1838 if (length
< copybreak
) {
1839 skb
= alloc_skb(length
+ 2, GFP_ATOMIC
);
1843 skb_reserve(skb
, 2);
1844 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->mapaddr
,
1845 length
, PCI_DMA_FROMDEVICE
);
1846 memcpy(skb
->data
, re
->skb
->data
, length
);
1847 skb
->ip_summed
= re
->skb
->ip_summed
;
1848 skb
->csum
= re
->skb
->csum
;
1849 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->mapaddr
,
1850 length
, PCI_DMA_FROMDEVICE
);
1852 struct sk_buff
*nskb
;
1854 nskb
= sky2_alloc_skb(sky2
->rx_bufsize
, GFP_ATOMIC
);
1860 pci_unmap_single(sky2
->hw
->pdev
, re
->mapaddr
,
1861 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1862 prefetch(skb
->data
);
1864 re
->mapaddr
= pci_map_single(sky2
->hw
->pdev
, nskb
->data
,
1865 sky2
->rx_bufsize
, PCI_DMA_FROMDEVICE
);
1868 skb_put(skb
, length
);
1870 re
->skb
->ip_summed
= CHECKSUM_NONE
;
1871 sky2_rx_add(sky2
, re
->mapaddr
);
1873 /* Tell receiver about new buffers. */
1874 sky2_put_idx(sky2
->hw
, rxqaddr
[sky2
->port
], sky2
->rx_put
);
1879 ++sky2
->net_stats
.rx_over_errors
;
1883 ++sky2
->net_stats
.rx_errors
;
1885 if (netif_msg_rx_err(sky2
) && net_ratelimit())
1886 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
1887 sky2
->netdev
->name
, status
, length
);
1889 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
1890 sky2
->net_stats
.rx_length_errors
++;
1891 if (status
& GMR_FS_FRAGMENT
)
1892 sky2
->net_stats
.rx_frame_errors
++;
1893 if (status
& GMR_FS_CRC_ERR
)
1894 sky2
->net_stats
.rx_crc_errors
++;
1895 if (status
& GMR_FS_RX_FF_OV
)
1896 sky2
->net_stats
.rx_fifo_errors
++;
1901 /* Transmit complete */
1902 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
1904 struct sky2_port
*sky2
= netdev_priv(dev
);
1906 if (netif_running(dev
)) {
1907 spin_lock(&sky2
->tx_lock
);
1908 sky2_tx_complete(sky2
, last
);
1909 spin_unlock(&sky2
->tx_lock
);
1913 /* Process status response ring */
1914 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
)
1917 u16 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
1921 while (hw
->st_idx
!= hwidx
) {
1922 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
1923 struct net_device
*dev
;
1924 struct sky2_port
*sky2
;
1925 struct sk_buff
*skb
;
1929 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
1931 BUG_ON(le
->link
>= 2);
1932 dev
= hw
->dev
[le
->link
];
1934 sky2
= netdev_priv(dev
);
1935 length
= le
->length
;
1936 status
= le
->status
;
1938 switch (le
->opcode
& ~HW_OWNER
) {
1940 skb
= sky2_receive(sky2
, length
, status
);
1945 skb
->protocol
= eth_type_trans(skb
, dev
);
1946 dev
->last_rx
= jiffies
;
1948 #ifdef SKY2_VLAN_TAG_USED
1949 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
1950 vlan_hwaccel_receive_skb(skb
,
1952 be16_to_cpu(sky2
->rx_tag
));
1955 netif_receive_skb(skb
);
1957 if (++work_done
>= to_do
)
1961 #ifdef SKY2_VLAN_TAG_USED
1963 sky2
->rx_tag
= length
;
1967 sky2
->rx_tag
= length
;
1971 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
1972 skb
->ip_summed
= CHECKSUM_HW
;
1973 skb
->csum
= le16_to_cpu(status
);
1977 /* TX index reports status for both ports */
1978 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
1979 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
1981 sky2_tx_done(hw
->dev
[1],
1982 ((status
>> 24) & 0xff)
1983 | (u16
)(length
& 0xf) << 8);
1987 if (net_ratelimit())
1988 printk(KERN_WARNING PFX
1989 "unknown status opcode 0x%x\n", le
->opcode
);
1998 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2000 struct net_device
*dev
= hw
->dev
[port
];
2002 if (net_ratelimit())
2003 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2006 if (status
& Y2_IS_PAR_RD1
) {
2007 if (net_ratelimit())
2008 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2011 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2014 if (status
& Y2_IS_PAR_WR1
) {
2015 if (net_ratelimit())
2016 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2019 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2022 if (status
& Y2_IS_PAR_MAC1
) {
2023 if (net_ratelimit())
2024 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2025 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2028 if (status
& Y2_IS_PAR_RX1
) {
2029 if (net_ratelimit())
2030 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2031 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2034 if (status
& Y2_IS_TCP_TXA1
) {
2035 if (net_ratelimit())
2036 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2038 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2042 static void sky2_hw_intr(struct sky2_hw
*hw
)
2044 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2046 if (status
& Y2_IS_TIST_OV
)
2047 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2049 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2052 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2053 if (net_ratelimit())
2054 printk(KERN_ERR PFX
"%s: pci hw error (0x%x)\n",
2055 pci_name(hw
->pdev
), pci_err
);
2057 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2058 sky2_pci_write16(hw
, PCI_STATUS
,
2059 pci_err
| PCI_STATUS_ERROR_BITS
);
2060 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2063 if (status
& Y2_IS_PCI_EXP
) {
2064 /* PCI-Express uncorrectable Error occurred */
2067 pex_err
= sky2_pci_read32(hw
, PEX_UNC_ERR_STAT
);
2069 if (net_ratelimit())
2070 printk(KERN_ERR PFX
"%s: pci express error (0x%x)\n",
2071 pci_name(hw
->pdev
), pex_err
);
2073 /* clear the interrupt */
2074 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2075 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
,
2077 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2079 if (pex_err
& PEX_FATAL_ERRORS
) {
2080 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2081 hwmsk
&= ~Y2_IS_PCI_EXP
;
2082 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2086 if (status
& Y2_HWE_L1_MASK
)
2087 sky2_hw_error(hw
, 0, status
);
2089 if (status
& Y2_HWE_L1_MASK
)
2090 sky2_hw_error(hw
, 1, status
);
2093 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2095 struct net_device
*dev
= hw
->dev
[port
];
2096 struct sky2_port
*sky2
= netdev_priv(dev
);
2097 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2099 if (netif_msg_intr(sky2
))
2100 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2103 if (status
& GM_IS_RX_FF_OR
) {
2104 ++sky2
->net_stats
.rx_fifo_errors
;
2105 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2108 if (status
& GM_IS_TX_FF_UR
) {
2109 ++sky2
->net_stats
.tx_fifo_errors
;
2110 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2114 /* This should never happen it is a fatal situation */
2115 static void sky2_descriptor_error(struct sky2_hw
*hw
, unsigned port
,
2116 const char *rxtx
, u32 mask
)
2118 struct net_device
*dev
= hw
->dev
[port
];
2119 struct sky2_port
*sky2
= netdev_priv(dev
);
2122 printk(KERN_ERR PFX
"%s: %s descriptor error (hardware problem)\n",
2123 dev
? dev
->name
: "<not registered>", rxtx
);
2125 imask
= sky2_read32(hw
, B0_IMSK
);
2127 sky2_write32(hw
, B0_IMSK
, imask
);
2130 spin_lock(&sky2
->phy_lock
);
2131 sky2_link_down(sky2
);
2132 spin_unlock(&sky2
->phy_lock
);
2136 /* If idle then force a fake soft NAPI poll once a second
2137 * to work around cases where sharing an edge triggered interrupt.
2139 static void sky2_idle(unsigned long arg
)
2141 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2142 struct net_device
*dev
= hw
->dev
[0];
2144 if (__netif_rx_schedule_prep(dev
))
2145 __netif_rx_schedule(dev
);
2147 mod_timer(&hw
->idle_timer
, jiffies
+ msecs_to_jiffies(idle_timeout
));
2151 static int sky2_poll(struct net_device
*dev0
, int *budget
)
2153 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
2154 int work_limit
= min(dev0
->quota
, *budget
);
2156 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2158 if (status
& Y2_IS_HW_ERR
)
2161 if (status
& Y2_IS_IRQ_PHY1
)
2162 sky2_phy_intr(hw
, 0);
2164 if (status
& Y2_IS_IRQ_PHY2
)
2165 sky2_phy_intr(hw
, 1);
2167 if (status
& Y2_IS_IRQ_MAC1
)
2168 sky2_mac_intr(hw
, 0);
2170 if (status
& Y2_IS_IRQ_MAC2
)
2171 sky2_mac_intr(hw
, 1);
2173 if (status
& Y2_IS_CHK_RX1
)
2174 sky2_descriptor_error(hw
, 0, "receive", Y2_IS_CHK_RX1
);
2176 if (status
& Y2_IS_CHK_RX2
)
2177 sky2_descriptor_error(hw
, 1, "receive", Y2_IS_CHK_RX2
);
2179 if (status
& Y2_IS_CHK_TXA1
)
2180 sky2_descriptor_error(hw
, 0, "transmit", Y2_IS_CHK_TXA1
);
2182 if (status
& Y2_IS_CHK_TXA2
)
2183 sky2_descriptor_error(hw
, 1, "transmit", Y2_IS_CHK_TXA2
);
2185 if (status
& Y2_IS_STAT_BMU
)
2186 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2188 work_done
= sky2_status_intr(hw
, work_limit
);
2189 *budget
-= work_done
;
2190 dev0
->quota
-= work_done
;
2192 if (work_done
>= work_limit
)
2195 netif_rx_complete(dev0
);
2197 status
= sky2_read32(hw
, B0_Y2_SP_LISR
);
2201 static irqreturn_t
sky2_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
2203 struct sky2_hw
*hw
= dev_id
;
2204 struct net_device
*dev0
= hw
->dev
[0];
2207 /* Reading this mask interrupts as side effect */
2208 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2209 if (status
== 0 || status
== ~0)
2212 prefetch(&hw
->st_le
[hw
->st_idx
]);
2213 if (likely(__netif_rx_schedule_prep(dev0
)))
2214 __netif_rx_schedule(dev0
);
2219 #ifdef CONFIG_NET_POLL_CONTROLLER
2220 static void sky2_netpoll(struct net_device
*dev
)
2222 struct sky2_port
*sky2
= netdev_priv(dev
);
2224 sky2_intr(sky2
->hw
->pdev
->irq
, sky2
->hw
, NULL
);
2228 /* Chip internal frequency for clock calculations */
2229 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2231 switch (hw
->chip_id
) {
2232 case CHIP_ID_YUKON_EC
:
2233 case CHIP_ID_YUKON_EC_U
:
2234 return 125; /* 125 Mhz */
2235 case CHIP_ID_YUKON_FE
:
2236 return 100; /* 100 Mhz */
2237 default: /* YUKON_XL */
2238 return 156; /* 156 Mhz */
2242 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2244 return sky2_mhz(hw
) * us
;
2247 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2249 return clk
/ sky2_mhz(hw
);
2253 static int __devinit
sky2_reset(struct sky2_hw
*hw
)
2259 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2261 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2262 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2263 printk(KERN_ERR PFX
"%s: unsupported chip type 0x%x\n",
2264 pci_name(hw
->pdev
), hw
->chip_id
);
2268 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2270 /* This rev is really old, and requires untested workarounds */
2271 if (hw
->chip_id
== CHIP_ID_YUKON_EC
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2272 printk(KERN_ERR PFX
"%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2273 pci_name(hw
->pdev
), yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
2274 hw
->chip_id
, hw
->chip_rev
);
2279 if (hw
->chip_id
<= CHIP_ID_YUKON_EC
) {
2280 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2281 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2285 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2286 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2288 /* clear PCI errors, if any */
2289 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2291 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2292 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2295 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2297 /* clear any PEX errors */
2298 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
2299 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
, 0xffffffffUL
);
2302 pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2303 hw
->copper
= !(pmd_type
== 'L' || pmd_type
== 'S');
2306 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2307 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2308 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2312 sky2_set_power_state(hw
, PCI_D0
);
2314 for (i
= 0; i
< hw
->ports
; i
++) {
2315 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2316 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2319 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2321 /* Clear I2C IRQ noise */
2322 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2324 /* turn off hardware timer (unused) */
2325 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2326 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2328 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2330 /* Turn off descriptor polling */
2331 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2333 /* Turn off receive timestamp */
2334 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2335 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2337 /* enable the Tx Arbiters */
2338 for (i
= 0; i
< hw
->ports
; i
++)
2339 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2341 /* Initialize ram interface */
2342 for (i
= 0; i
< hw
->ports
; i
++) {
2343 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2345 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2346 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2347 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2348 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2349 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2350 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2351 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2352 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2353 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2354 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2355 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2356 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2359 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2361 for (i
= 0; i
< hw
->ports
; i
++)
2362 sky2_phy_reset(hw
, i
);
2364 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2367 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2368 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2370 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2371 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2373 /* Set the list last index */
2374 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2376 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2377 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2379 /* set Status-FIFO ISR watermark */
2380 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2381 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2383 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2385 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2386 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2387 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2389 /* enable status unit */
2390 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2392 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2393 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2394 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2399 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2403 modes
= SUPPORTED_10baseT_Half
2404 | SUPPORTED_10baseT_Full
2405 | SUPPORTED_100baseT_Half
2406 | SUPPORTED_100baseT_Full
2407 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2409 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2410 modes
|= SUPPORTED_1000baseT_Half
2411 | SUPPORTED_1000baseT_Full
;
2413 modes
= SUPPORTED_1000baseT_Full
| SUPPORTED_FIBRE
2414 | SUPPORTED_Autoneg
;
2418 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2420 struct sky2_port
*sky2
= netdev_priv(dev
);
2421 struct sky2_hw
*hw
= sky2
->hw
;
2423 ecmd
->transceiver
= XCVR_INTERNAL
;
2424 ecmd
->supported
= sky2_supported_modes(hw
);
2425 ecmd
->phy_address
= PHY_ADDR_MARV
;
2427 ecmd
->supported
= SUPPORTED_10baseT_Half
2428 | SUPPORTED_10baseT_Full
2429 | SUPPORTED_100baseT_Half
2430 | SUPPORTED_100baseT_Full
2431 | SUPPORTED_1000baseT_Half
2432 | SUPPORTED_1000baseT_Full
2433 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2434 ecmd
->port
= PORT_TP
;
2436 ecmd
->port
= PORT_FIBRE
;
2438 ecmd
->advertising
= sky2
->advertising
;
2439 ecmd
->autoneg
= sky2
->autoneg
;
2440 ecmd
->speed
= sky2
->speed
;
2441 ecmd
->duplex
= sky2
->duplex
;
2445 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2447 struct sky2_port
*sky2
= netdev_priv(dev
);
2448 const struct sky2_hw
*hw
= sky2
->hw
;
2449 u32 supported
= sky2_supported_modes(hw
);
2451 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2452 ecmd
->advertising
= supported
;
2458 switch (ecmd
->speed
) {
2460 if (ecmd
->duplex
== DUPLEX_FULL
)
2461 setting
= SUPPORTED_1000baseT_Full
;
2462 else if (ecmd
->duplex
== DUPLEX_HALF
)
2463 setting
= SUPPORTED_1000baseT_Half
;
2468 if (ecmd
->duplex
== DUPLEX_FULL
)
2469 setting
= SUPPORTED_100baseT_Full
;
2470 else if (ecmd
->duplex
== DUPLEX_HALF
)
2471 setting
= SUPPORTED_100baseT_Half
;
2477 if (ecmd
->duplex
== DUPLEX_FULL
)
2478 setting
= SUPPORTED_10baseT_Full
;
2479 else if (ecmd
->duplex
== DUPLEX_HALF
)
2480 setting
= SUPPORTED_10baseT_Half
;
2488 if ((setting
& supported
) == 0)
2491 sky2
->speed
= ecmd
->speed
;
2492 sky2
->duplex
= ecmd
->duplex
;
2495 sky2
->autoneg
= ecmd
->autoneg
;
2496 sky2
->advertising
= ecmd
->advertising
;
2498 if (netif_running(dev
))
2499 sky2_phy_reinit(sky2
);
2504 static void sky2_get_drvinfo(struct net_device
*dev
,
2505 struct ethtool_drvinfo
*info
)
2507 struct sky2_port
*sky2
= netdev_priv(dev
);
2509 strcpy(info
->driver
, DRV_NAME
);
2510 strcpy(info
->version
, DRV_VERSION
);
2511 strcpy(info
->fw_version
, "N/A");
2512 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2515 static const struct sky2_stat
{
2516 char name
[ETH_GSTRING_LEN
];
2519 { "tx_bytes", GM_TXO_OK_HI
},
2520 { "rx_bytes", GM_RXO_OK_HI
},
2521 { "tx_broadcast", GM_TXF_BC_OK
},
2522 { "rx_broadcast", GM_RXF_BC_OK
},
2523 { "tx_multicast", GM_TXF_MC_OK
},
2524 { "rx_multicast", GM_RXF_MC_OK
},
2525 { "tx_unicast", GM_TXF_UC_OK
},
2526 { "rx_unicast", GM_RXF_UC_OK
},
2527 { "tx_mac_pause", GM_TXF_MPAUSE
},
2528 { "rx_mac_pause", GM_RXF_MPAUSE
},
2529 { "collisions", GM_TXF_COL
},
2530 { "late_collision",GM_TXF_LAT_COL
},
2531 { "aborted", GM_TXF_ABO_COL
},
2532 { "single_collisions", GM_TXF_SNG_COL
},
2533 { "multi_collisions", GM_TXF_MUL_COL
},
2535 { "rx_short", GM_RXF_SHT
},
2536 { "rx_runt", GM_RXE_FRAG
},
2537 { "rx_64_byte_packets", GM_RXF_64B
},
2538 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
2539 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
2540 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
2541 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
2542 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
2543 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
2544 { "rx_too_long", GM_RXF_LNG_ERR
},
2545 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
2546 { "rx_jabber", GM_RXF_JAB_PKT
},
2547 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2549 { "tx_64_byte_packets", GM_TXF_64B
},
2550 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
2551 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
2552 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
2553 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
2554 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
2555 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
2556 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
2559 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2561 struct sky2_port
*sky2
= netdev_priv(dev
);
2563 return sky2
->rx_csum
;
2566 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2568 struct sky2_port
*sky2
= netdev_priv(dev
);
2570 sky2
->rx_csum
= data
;
2572 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2573 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2578 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2580 struct sky2_port
*sky2
= netdev_priv(netdev
);
2581 return sky2
->msg_enable
;
2584 static int sky2_nway_reset(struct net_device
*dev
)
2586 struct sky2_port
*sky2
= netdev_priv(dev
);
2588 if (sky2
->autoneg
!= AUTONEG_ENABLE
)
2591 sky2_phy_reinit(sky2
);
2596 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
2598 struct sky2_hw
*hw
= sky2
->hw
;
2599 unsigned port
= sky2
->port
;
2602 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2603 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
2604 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2605 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
2607 for (i
= 2; i
< count
; i
++)
2608 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
2611 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
2613 struct sky2_port
*sky2
= netdev_priv(netdev
);
2614 sky2
->msg_enable
= value
;
2617 static int sky2_get_stats_count(struct net_device
*dev
)
2619 return ARRAY_SIZE(sky2_stats
);
2622 static void sky2_get_ethtool_stats(struct net_device
*dev
,
2623 struct ethtool_stats
*stats
, u64
* data
)
2625 struct sky2_port
*sky2
= netdev_priv(dev
);
2627 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
2630 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
2634 switch (stringset
) {
2636 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
2637 memcpy(data
+ i
* ETH_GSTRING_LEN
,
2638 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
2643 /* Use hardware MIB variables for critical path statistics and
2644 * transmit feedback not reported at interrupt.
2645 * Other errors are accounted for in interrupt handler.
2647 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
2649 struct sky2_port
*sky2
= netdev_priv(dev
);
2652 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(data
));
2654 sky2
->net_stats
.tx_bytes
= data
[0];
2655 sky2
->net_stats
.rx_bytes
= data
[1];
2656 sky2
->net_stats
.tx_packets
= data
[2] + data
[4] + data
[6];
2657 sky2
->net_stats
.rx_packets
= data
[3] + data
[5] + data
[7];
2658 sky2
->net_stats
.multicast
= data
[3] + data
[5];
2659 sky2
->net_stats
.collisions
= data
[10];
2660 sky2
->net_stats
.tx_aborted_errors
= data
[12];
2662 return &sky2
->net_stats
;
2665 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
2667 struct sky2_port
*sky2
= netdev_priv(dev
);
2668 struct sky2_hw
*hw
= sky2
->hw
;
2669 unsigned port
= sky2
->port
;
2670 const struct sockaddr
*addr
= p
;
2672 if (!is_valid_ether_addr(addr
->sa_data
))
2673 return -EADDRNOTAVAIL
;
2675 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
2676 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
2677 dev
->dev_addr
, ETH_ALEN
);
2678 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
2679 dev
->dev_addr
, ETH_ALEN
);
2681 /* virtual address for data */
2682 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
2684 /* physical address: used for pause frames */
2685 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
2690 static void sky2_set_multicast(struct net_device
*dev
)
2692 struct sky2_port
*sky2
= netdev_priv(dev
);
2693 struct sky2_hw
*hw
= sky2
->hw
;
2694 unsigned port
= sky2
->port
;
2695 struct dev_mc_list
*list
= dev
->mc_list
;
2699 memset(filter
, 0, sizeof(filter
));
2701 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2702 reg
|= GM_RXCR_UCF_ENA
;
2704 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
2705 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2706 else if ((dev
->flags
& IFF_ALLMULTI
) || dev
->mc_count
> 16) /* all multicast */
2707 memset(filter
, 0xff, sizeof(filter
));
2708 else if (dev
->mc_count
== 0) /* no multicast */
2709 reg
&= ~GM_RXCR_MCF_ENA
;
2712 reg
|= GM_RXCR_MCF_ENA
;
2714 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
) {
2715 u32 bit
= ether_crc(ETH_ALEN
, list
->dmi_addr
) & 0x3f;
2716 filter
[bit
/ 8] |= 1 << (bit
% 8);
2720 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2721 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
2722 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2723 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
2724 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2725 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
2726 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2727 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
2729 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2732 /* Can have one global because blinking is controlled by
2733 * ethtool and that is always under RTNL mutex
2735 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
2739 switch (hw
->chip_id
) {
2740 case CHIP_ID_YUKON_XL
:
2741 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2742 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2743 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
2744 on
? (PHY_M_LEDC_LOS_CTRL(1) |
2745 PHY_M_LEDC_INIT_CTRL(7) |
2746 PHY_M_LEDC_STA1_CTRL(7) |
2747 PHY_M_LEDC_STA0_CTRL(7))
2750 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2754 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
2755 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
2756 on
? PHY_M_LED_MO_DUP(MO_LED_ON
) |
2757 PHY_M_LED_MO_10(MO_LED_ON
) |
2758 PHY_M_LED_MO_100(MO_LED_ON
) |
2759 PHY_M_LED_MO_1000(MO_LED_ON
) |
2760 PHY_M_LED_MO_RX(MO_LED_ON
)
2761 : PHY_M_LED_MO_DUP(MO_LED_OFF
) |
2762 PHY_M_LED_MO_10(MO_LED_OFF
) |
2763 PHY_M_LED_MO_100(MO_LED_OFF
) |
2764 PHY_M_LED_MO_1000(MO_LED_OFF
) |
2765 PHY_M_LED_MO_RX(MO_LED_OFF
));
2770 /* blink LED's for finding board */
2771 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
2773 struct sky2_port
*sky2
= netdev_priv(dev
);
2774 struct sky2_hw
*hw
= sky2
->hw
;
2775 unsigned port
= sky2
->port
;
2776 u16 ledctrl
, ledover
= 0;
2781 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
2782 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
2786 /* save initial values */
2787 spin_lock_bh(&sky2
->phy_lock
);
2788 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2789 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2790 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2791 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
2792 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2794 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
2795 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
2799 while (!interrupted
&& ms
> 0) {
2800 sky2_led(hw
, port
, onoff
);
2803 spin_unlock_bh(&sky2
->phy_lock
);
2804 interrupted
= msleep_interruptible(250);
2805 spin_lock_bh(&sky2
->phy_lock
);
2810 /* resume regularly scheduled programming */
2811 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2812 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2813 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2814 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
2815 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2817 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
2818 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
2820 spin_unlock_bh(&sky2
->phy_lock
);
2825 static void sky2_get_pauseparam(struct net_device
*dev
,
2826 struct ethtool_pauseparam
*ecmd
)
2828 struct sky2_port
*sky2
= netdev_priv(dev
);
2830 ecmd
->tx_pause
= sky2
->tx_pause
;
2831 ecmd
->rx_pause
= sky2
->rx_pause
;
2832 ecmd
->autoneg
= sky2
->autoneg
;
2835 static int sky2_set_pauseparam(struct net_device
*dev
,
2836 struct ethtool_pauseparam
*ecmd
)
2838 struct sky2_port
*sky2
= netdev_priv(dev
);
2841 sky2
->autoneg
= ecmd
->autoneg
;
2842 sky2
->tx_pause
= ecmd
->tx_pause
!= 0;
2843 sky2
->rx_pause
= ecmd
->rx_pause
!= 0;
2845 sky2_phy_reinit(sky2
);
2850 static int sky2_get_coalesce(struct net_device
*dev
,
2851 struct ethtool_coalesce
*ecmd
)
2853 struct sky2_port
*sky2
= netdev_priv(dev
);
2854 struct sky2_hw
*hw
= sky2
->hw
;
2856 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
2857 ecmd
->tx_coalesce_usecs
= 0;
2859 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
2860 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2862 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
2864 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
2865 ecmd
->rx_coalesce_usecs
= 0;
2867 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
2868 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
2870 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
2872 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
2873 ecmd
->rx_coalesce_usecs_irq
= 0;
2875 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
2876 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
2879 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
2884 /* Note: this affect both ports */
2885 static int sky2_set_coalesce(struct net_device
*dev
,
2886 struct ethtool_coalesce
*ecmd
)
2888 struct sky2_port
*sky2
= netdev_priv(dev
);
2889 struct sky2_hw
*hw
= sky2
->hw
;
2890 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
2892 if (ecmd
->tx_coalesce_usecs
> tmax
||
2893 ecmd
->rx_coalesce_usecs
> tmax
||
2894 ecmd
->rx_coalesce_usecs_irq
> tmax
)
2897 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
2899 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
2901 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
2904 if (ecmd
->tx_coalesce_usecs
== 0)
2905 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
2907 sky2_write32(hw
, STAT_TX_TIMER_INI
,
2908 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
2909 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2911 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
2913 if (ecmd
->rx_coalesce_usecs
== 0)
2914 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
2916 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
2917 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
2918 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2920 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
2922 if (ecmd
->rx_coalesce_usecs_irq
== 0)
2923 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
2925 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
2926 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
2927 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2929 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
2933 static void sky2_get_ringparam(struct net_device
*dev
,
2934 struct ethtool_ringparam
*ering
)
2936 struct sky2_port
*sky2
= netdev_priv(dev
);
2938 ering
->rx_max_pending
= RX_MAX_PENDING
;
2939 ering
->rx_mini_max_pending
= 0;
2940 ering
->rx_jumbo_max_pending
= 0;
2941 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
2943 ering
->rx_pending
= sky2
->rx_pending
;
2944 ering
->rx_mini_pending
= 0;
2945 ering
->rx_jumbo_pending
= 0;
2946 ering
->tx_pending
= sky2
->tx_pending
;
2949 static int sky2_set_ringparam(struct net_device
*dev
,
2950 struct ethtool_ringparam
*ering
)
2952 struct sky2_port
*sky2
= netdev_priv(dev
);
2955 if (ering
->rx_pending
> RX_MAX_PENDING
||
2956 ering
->rx_pending
< 8 ||
2957 ering
->tx_pending
< MAX_SKB_TX_LE
||
2958 ering
->tx_pending
> TX_RING_SIZE
- 1)
2961 if (netif_running(dev
))
2964 sky2
->rx_pending
= ering
->rx_pending
;
2965 sky2
->tx_pending
= ering
->tx_pending
;
2967 if (netif_running(dev
)) {
2972 sky2_set_multicast(dev
);
2978 static int sky2_get_regs_len(struct net_device
*dev
)
2984 * Returns copy of control register region
2985 * Note: access to the RAM address register set will cause timeouts.
2987 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
2990 const struct sky2_port
*sky2
= netdev_priv(dev
);
2991 const void __iomem
*io
= sky2
->hw
->regs
;
2993 BUG_ON(regs
->len
< B3_RI_WTO_R1
);
2995 memset(p
, 0, regs
->len
);
2997 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
2999 memcpy_fromio(p
+ B3_RI_WTO_R1
,
3001 regs
->len
- B3_RI_WTO_R1
);
3004 static struct ethtool_ops sky2_ethtool_ops
= {
3005 .get_settings
= sky2_get_settings
,
3006 .set_settings
= sky2_set_settings
,
3007 .get_drvinfo
= sky2_get_drvinfo
,
3008 .get_msglevel
= sky2_get_msglevel
,
3009 .set_msglevel
= sky2_set_msglevel
,
3010 .nway_reset
= sky2_nway_reset
,
3011 .get_regs_len
= sky2_get_regs_len
,
3012 .get_regs
= sky2_get_regs
,
3013 .get_link
= ethtool_op_get_link
,
3014 .get_sg
= ethtool_op_get_sg
,
3015 .set_sg
= ethtool_op_set_sg
,
3016 .get_tx_csum
= ethtool_op_get_tx_csum
,
3017 .set_tx_csum
= ethtool_op_set_tx_csum
,
3018 .get_tso
= ethtool_op_get_tso
,
3019 .set_tso
= ethtool_op_set_tso
,
3020 .get_rx_csum
= sky2_get_rx_csum
,
3021 .set_rx_csum
= sky2_set_rx_csum
,
3022 .get_strings
= sky2_get_strings
,
3023 .get_coalesce
= sky2_get_coalesce
,
3024 .set_coalesce
= sky2_set_coalesce
,
3025 .get_ringparam
= sky2_get_ringparam
,
3026 .set_ringparam
= sky2_set_ringparam
,
3027 .get_pauseparam
= sky2_get_pauseparam
,
3028 .set_pauseparam
= sky2_set_pauseparam
,
3029 .phys_id
= sky2_phys_id
,
3030 .get_stats_count
= sky2_get_stats_count
,
3031 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3032 .get_perm_addr
= ethtool_op_get_perm_addr
,
3035 /* Initialize network device */
3036 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
3037 unsigned port
, int highmem
)
3039 struct sky2_port
*sky2
;
3040 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3043 printk(KERN_ERR
"sky2 etherdev alloc failed");
3047 SET_MODULE_OWNER(dev
);
3048 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3049 dev
->irq
= hw
->pdev
->irq
;
3050 dev
->open
= sky2_up
;
3051 dev
->stop
= sky2_down
;
3052 dev
->do_ioctl
= sky2_ioctl
;
3053 dev
->hard_start_xmit
= sky2_xmit_frame
;
3054 dev
->get_stats
= sky2_get_stats
;
3055 dev
->set_multicast_list
= sky2_set_multicast
;
3056 dev
->set_mac_address
= sky2_set_mac_address
;
3057 dev
->change_mtu
= sky2_change_mtu
;
3058 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3059 dev
->tx_timeout
= sky2_tx_timeout
;
3060 dev
->watchdog_timeo
= TX_WATCHDOG
;
3062 dev
->poll
= sky2_poll
;
3063 dev
->weight
= NAPI_WEIGHT
;
3064 #ifdef CONFIG_NET_POLL_CONTROLLER
3065 dev
->poll_controller
= sky2_netpoll
;
3068 sky2
= netdev_priv(dev
);
3071 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3073 spin_lock_init(&sky2
->tx_lock
);
3074 /* Auto speed and flow control */
3075 sky2
->autoneg
= AUTONEG_ENABLE
;
3080 sky2
->advertising
= sky2_supported_modes(hw
);
3082 /* Receive checksum disabled for Yukon XL
3083 * because of observed problems with incorrect
3084 * values when multiple packets are received in one interrupt
3086 sky2
->rx_csum
= (hw
->chip_id
!= CHIP_ID_YUKON_XL
);
3088 spin_lock_init(&sky2
->phy_lock
);
3089 sky2
->tx_pending
= TX_DEF_PENDING
;
3090 sky2
->rx_pending
= RX_DEF_PENDING
;
3091 sky2
->rx_bufsize
= sky2_buf_size(ETH_DATA_LEN
);
3093 hw
->dev
[port
] = dev
;
3097 dev
->features
|= NETIF_F_LLTX
;
3098 if (hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
3099 dev
->features
|= NETIF_F_TSO
;
3101 dev
->features
|= NETIF_F_HIGHDMA
;
3102 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
3104 #ifdef SKY2_VLAN_TAG_USED
3105 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3106 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3107 dev
->vlan_rx_kill_vid
= sky2_vlan_rx_kill_vid
;
3110 /* read the mac address */
3111 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3112 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3114 /* device is off until link detection */
3115 netif_carrier_off(dev
);
3116 netif_stop_queue(dev
);
3121 static void __devinit
sky2_show_addr(struct net_device
*dev
)
3123 const struct sky2_port
*sky2
= netdev_priv(dev
);
3125 if (netif_msg_probe(sky2
))
3126 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3128 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3129 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3132 /* Handle software interrupt used during MSI test */
3133 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
,
3134 struct pt_regs
*regs
)
3136 struct sky2_hw
*hw
= dev_id
;
3137 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3142 if (status
& Y2_IS_IRQ_SW
) {
3143 hw
->msi_detected
= 1;
3144 wake_up(&hw
->msi_wait
);
3145 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3147 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3152 /* Test interrupt path by forcing a a software IRQ */
3153 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
3155 struct pci_dev
*pdev
= hw
->pdev
;
3158 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
3160 err
= request_irq(pdev
->irq
, sky2_test_intr
, SA_SHIRQ
, DRV_NAME
, hw
);
3162 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3163 pci_name(pdev
), pdev
->irq
);
3167 init_waitqueue_head (&hw
->msi_wait
);
3169 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
3172 wait_event_timeout(hw
->msi_wait
, hw
->msi_detected
, HZ
/10);
3174 if (!hw
->msi_detected
) {
3175 /* MSI test failed, go back to INTx mode */
3176 printk(KERN_WARNING PFX
"%s: No interrupt was generated using MSI, "
3177 "switching to INTx mode. Please report this failure to "
3178 "the PCI maintainer and include system chipset information.\n",
3182 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3185 sky2_write32(hw
, B0_IMSK
, 0);
3187 free_irq(pdev
->irq
, hw
);
3192 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3193 const struct pci_device_id
*ent
)
3195 struct net_device
*dev
, *dev1
= NULL
;
3197 int err
, pm_cap
, using_dac
= 0;
3199 err
= pci_enable_device(pdev
);
3201 printk(KERN_ERR PFX
"%s cannot enable PCI device\n",
3206 err
= pci_request_regions(pdev
, DRV_NAME
);
3208 printk(KERN_ERR PFX
"%s cannot obtain PCI resources\n",
3213 pci_set_master(pdev
);
3215 /* Find power-management capability. */
3216 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
3218 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
3221 goto err_out_free_regions
;
3224 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3225 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3227 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3229 printk(KERN_ERR PFX
"%s unable to obtain 64 bit DMA "
3230 "for consistent allocations\n", pci_name(pdev
));
3231 goto err_out_free_regions
;
3235 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3237 printk(KERN_ERR PFX
"%s no usable DMA configuration\n",
3239 goto err_out_free_regions
;
3244 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3246 printk(KERN_ERR PFX
"%s: cannot allocate hardware struct\n",
3248 goto err_out_free_regions
;
3253 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3255 printk(KERN_ERR PFX
"%s: cannot map device registers\n",
3257 goto err_out_free_hw
;
3259 hw
->pm_cap
= pm_cap
;
3262 /* byte swap descriptors in hardware */
3266 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
3267 reg
|= PCI_REV_DESC
;
3268 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
3272 /* ring for status responses */
3273 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3276 goto err_out_iounmap
;
3278 err
= sky2_reset(hw
);
3280 goto err_out_iounmap
;
3282 printk(KERN_INFO PFX
"v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3283 DRV_VERSION
, pci_resource_start(pdev
, 0), pdev
->irq
,
3284 yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3285 hw
->chip_id
, hw
->chip_rev
);
3287 dev
= sky2_init_netdev(hw
, 0, using_dac
);
3289 goto err_out_free_pci
;
3291 err
= register_netdev(dev
);
3293 printk(KERN_ERR PFX
"%s: cannot register net device\n",
3295 goto err_out_free_netdev
;
3298 sky2_show_addr(dev
);
3300 if (hw
->ports
> 1 && (dev1
= sky2_init_netdev(hw
, 1, using_dac
))) {
3301 if (register_netdev(dev1
) == 0)
3302 sky2_show_addr(dev1
);
3304 /* Failure to register second port need not be fatal */
3305 printk(KERN_WARNING PFX
3306 "register of second port failed\n");
3312 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
3313 err
= sky2_test_msi(hw
);
3314 if (err
== -EOPNOTSUPP
)
3315 pci_disable_msi(pdev
);
3317 goto err_out_unregister
;
3320 err
= request_irq(pdev
->irq
, sky2_intr
, SA_SHIRQ
, DRV_NAME
, hw
);
3322 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3323 pci_name(pdev
), pdev
->irq
);
3324 goto err_out_unregister
;
3327 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3329 setup_timer(&hw
->idle_timer
, sky2_idle
, (unsigned long) hw
);
3330 if (idle_timeout
> 0)
3331 mod_timer(&hw
->idle_timer
,
3332 jiffies
+ msecs_to_jiffies(idle_timeout
));
3334 pci_set_drvdata(pdev
, hw
);
3339 pci_disable_msi(pdev
);
3341 unregister_netdev(dev1
);
3344 unregister_netdev(dev
);
3345 err_out_free_netdev
:
3348 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3349 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3354 err_out_free_regions
:
3355 pci_release_regions(pdev
);
3356 pci_disable_device(pdev
);
3361 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
3363 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3364 struct net_device
*dev0
, *dev1
;
3369 del_timer_sync(&hw
->idle_timer
);
3371 sky2_write32(hw
, B0_IMSK
, 0);
3372 synchronize_irq(hw
->pdev
->irq
);
3377 unregister_netdev(dev1
);
3378 unregister_netdev(dev0
);
3380 sky2_set_power_state(hw
, PCI_D3hot
);
3381 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
3382 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3383 sky2_read8(hw
, B0_CTST
);
3385 free_irq(pdev
->irq
, hw
);
3386 pci_disable_msi(pdev
);
3387 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3388 pci_release_regions(pdev
);
3389 pci_disable_device(pdev
);
3397 pci_set_drvdata(pdev
, NULL
);
3401 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3403 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3406 for (i
= 0; i
< 2; i
++) {
3407 struct net_device
*dev
= hw
->dev
[i
];
3410 if (!netif_running(dev
))
3414 netif_device_detach(dev
);
3418 return sky2_set_power_state(hw
, pci_choose_state(pdev
, state
));
3421 static int sky2_resume(struct pci_dev
*pdev
)
3423 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3426 pci_restore_state(pdev
);
3427 pci_enable_wake(pdev
, PCI_D0
, 0);
3428 err
= sky2_set_power_state(hw
, PCI_D0
);
3432 err
= sky2_reset(hw
);
3436 for (i
= 0; i
< 2; i
++) {
3437 struct net_device
*dev
= hw
->dev
[i
];
3438 if (dev
&& netif_running(dev
)) {
3439 netif_device_attach(dev
);
3442 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3454 static struct pci_driver sky2_driver
= {
3456 .id_table
= sky2_id_table
,
3457 .probe
= sky2_probe
,
3458 .remove
= __devexit_p(sky2_remove
),
3460 .suspend
= sky2_suspend
,
3461 .resume
= sky2_resume
,
3465 static int __init
sky2_init_module(void)
3467 return pci_register_driver(&sky2_driver
);
3470 static void __exit
sky2_cleanup_module(void)
3472 pci_unregister_driver(&sky2_driver
);
3475 module_init(sky2_init_module
);
3476 module_exit(sky2_cleanup_module
);
3478 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3479 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3480 MODULE_LICENSE("GPL");
3481 MODULE_VERSION(DRV_VERSION
);