include/linux/platform_data/dma-atmel.h

   1 /*
   2  * Header file for the Atmel AHB DMA Controller driver
   3  *
   4  * Copyright (C) 2008 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11 #ifndef AT_HDMAC_H
  12 #define AT_HDMAC_H
  13
  14 #include <linux/dmaengine.h>
  15
  16 /**
  17  * struct at_dma_platform_data - Controller configuration parameters
  18  * @nr_channels: Number of channels supported by hardware (max 8)
  19  * @cap_mask: dma_capability flags supported by the platform
  20  */
  21 struct at_dma_platform_data {
  22         unsigned int    nr_channels;
  23         dma_cap_mask_t  cap_mask;
  24 };
  25
  26 /**
  27  * struct at_dma_slave - Controller-specific information about a slave
  28  * @dma_dev: required DMA master device
  29  * @cfg: Platform-specific initializer for the CFG register
  30  */
  31 struct at_dma_slave {
  32         struct device           *dma_dev;
  33         u32                     cfg;
  34 };
  35
  36
  37 /* Platform-configurable bits in CFG */
  38 #define ATC_PER_MSB(h)  ((0x30U & (h)) >> 4)    /* Extract most significant bits of a handshaking identifier */
  39
  40 #define ATC_SRC_PER(h)          (0xFU & (h))    /* Channel src rq associated with periph handshaking ifc h */
  41 #define ATC_DST_PER(h)          ((0xFU & (h)) <<  4)    /* Channel dst rq associated with periph handshaking ifc h */
  42 #define ATC_SRC_REP             (0x1 <<  8)     /* Source Replay Mod */
  43 #define ATC_SRC_H2SEL           (0x1 <<  9)     /* Source Handshaking Mod */
  44 #define         ATC_SRC_H2SEL_SW        (0x0 <<  9)
  45 #define         ATC_SRC_H2SEL_HW        (0x1 <<  9)
  46 #define ATC_SRC_PER_MSB(h)      (ATC_PER_MSB(h) << 10)  /* Channel src rq (most significant bits) */
  47 #define ATC_DST_REP             (0x1 << 12)     /* Destination Replay Mod */
  48 #define ATC_DST_H2SEL           (0x1 << 13)     /* Destination Handshaking Mod */
  49 #define         ATC_DST_H2SEL_SW        (0x0 << 13)
  50 #define         ATC_DST_H2SEL_HW        (0x1 << 13)
  51 #define ATC_DST_PER_MSB(h)      (ATC_PER_MSB(h) << 14)  /* Channel dst rq (most significant bits) */
  52 #define ATC_SOD                 (0x1 << 16)     /* Stop On Done */
  53 #define ATC_LOCK_IF             (0x1 << 20)     /* Interface Lock */
  54 #define ATC_LOCK_B              (0x1 << 21)     /* AHB Bus Lock */
  55 #define ATC_LOCK_IF_L           (0x1 << 22)     /* Master Interface Arbiter Lock */
  56 #define         ATC_LOCK_IF_L_CHUNK     (0x0 << 22)
  57 #define         ATC_LOCK_IF_L_BUFFER    (0x1 << 22)
  58 #define ATC_AHB_PROT_MASK       (0x7 << 24)     /* AHB Protection */
  59 #define ATC_FIFOCFG_MASK        (0x3 << 28)     /* FIFO Request Configuration */
  60 #define         ATC_FIFOCFG_LARGESTBURST        (0x0 << 28)
  61 #define         ATC_FIFOCFG_HALFFIFO            (0x1 << 28)
  62 #define         ATC_FIFOCFG_ENOUGHSPACE         (0x2 << 28)
  63
  64
  65 #endif /* AT_HDMAC_H */