drivers/scsi/mvsas/mv_defs.h

   1 /*
   2  * Marvell 88SE64xx/88SE94xx const head file
   3  *
   4  * Copyright 2007 Red Hat, Inc.
   5  * Copyright 2008 Marvell. <kewei@marvell.com>
   6  *
   7  * This file is licensed under GPLv2.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; version 2 of the
  12  * License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  22  * USA
  23 */
  24
  25 #ifndef _MV_DEFS_H_
  26 #define _MV_DEFS_H_
  27
  28 #define PCI_DEVICE_ID_ARECA_1300        0x1300
  29 #define PCI_DEVICE_ID_ARECA_1320        0x1320
  30
  31 enum chip_flavors {
  32         chip_6320,
  33         chip_6440,
  34         chip_6485,
  35         chip_9480,
  36         chip_9180,
  37         chip_9445,
  38         chip_9485,
  39         chip_1300,
  40         chip_1320
  41 };
  42
  43 /* driver compile-time configuration */
  44 enum driver_configuration {
  45         MVS_SLOTS               = 512,  /* command slots */
  46         MVS_TX_RING_SZ          = 1024, /* TX ring size (12-bit) */
  47         MVS_RX_RING_SZ          = 1024, /* RX ring size (12-bit) */
  48                                         /* software requires power-of-2
  49                                            ring size */
  50         MVS_SOC_SLOTS           = 64,
  51         MVS_SOC_TX_RING_SZ      = MVS_SOC_SLOTS * 2,
  52         MVS_SOC_RX_RING_SZ      = MVS_SOC_SLOTS * 2,
  53
  54         MVS_SLOT_BUF_SZ         = 8192, /* cmd tbl + IU + status + PRD */
  55         MVS_SSP_CMD_SZ          = 64,   /* SSP command table buffer size */
  56         MVS_ATA_CMD_SZ          = 96,   /* SATA command table buffer size */
  57         MVS_OAF_SZ              = 64,   /* Open address frame buffer size */
  58         MVS_QUEUE_SIZE  = 32,   /* Support Queue depth */
  59         MVS_CAN_QUEUE           = MVS_SLOTS - 2,        /* SCSI Queue depth */
  60         MVS_SOC_CAN_QUEUE       = MVS_SOC_SLOTS - 2,
  61 };
  62
  63 /* unchangeable hardware details */
  64 enum hardware_details {
  65         MVS_MAX_PHYS            = 8,    /* max. possible phys */
  66         MVS_MAX_PORTS           = 8,    /* max. possible ports */
  67         MVS_SOC_PHYS            = 4,    /* soc phys */
  68         MVS_SOC_PORTS           = 4,    /* soc phys */
  69         MVS_MAX_DEVICES = 1024, /* max supported device */
  70 };
  71
  72 /* peripheral registers (BAR2) */
  73 enum peripheral_registers {
  74         SPI_CTL                 = 0x10, /* EEPROM control */
  75         SPI_CMD                 = 0x14, /* EEPROM command */
  76         SPI_DATA                = 0x18, /* EEPROM data */
  77 };
  78
  79 enum peripheral_register_bits {
  80         TWSI_RDY                = (1U << 7),    /* EEPROM interface ready */
  81         TWSI_RD                 = (1U << 4),    /* EEPROM read access */
  82
  83         SPI_ADDR_MASK           = 0x3ffff,      /* bits 17:0 */
  84 };
  85
  86 enum hw_register_bits {
  87         /* MVS_GBL_CTL */
  88         INT_EN                  = (1U << 1),    /* Global int enable */
  89         HBA_RST                 = (1U << 0),    /* HBA reset */
  90
  91         /* MVS_GBL_INT_STAT */
  92         INT_XOR                 = (1U << 4),    /* XOR engine event */
  93         INT_SAS_SATA            = (1U << 0),    /* SAS/SATA event */
  94
  95         /* MVS_GBL_PORT_TYPE */                 /* shl for ports 1-3 */
  96         SATA_TARGET             = (1U << 16),   /* port0 SATA target enable */
  97         MODE_AUTO_DET_PORT7 = (1U << 15),       /* port0 SAS/SATA autodetect */
  98         MODE_AUTO_DET_PORT6 = (1U << 14),
  99         MODE_AUTO_DET_PORT5 = (1U << 13),
 100         MODE_AUTO_DET_PORT4 = (1U << 12),
 101         MODE_AUTO_DET_PORT3 = (1U << 11),
 102         MODE_AUTO_DET_PORT2 = (1U << 10),
 103         MODE_AUTO_DET_PORT1 = (1U << 9),
 104         MODE_AUTO_DET_PORT0 = (1U << 8),
 105         MODE_AUTO_DET_EN    =   MODE_AUTO_DET_PORT0 | MODE_AUTO_DET_PORT1 |
 106                                 MODE_AUTO_DET_PORT2 | MODE_AUTO_DET_PORT3 |
 107                                 MODE_AUTO_DET_PORT4 | MODE_AUTO_DET_PORT5 |
 108                                 MODE_AUTO_DET_PORT6 | MODE_AUTO_DET_PORT7,
 109         MODE_SAS_PORT7_MASK = (1U << 7),  /* port0 SAS(1), SATA(0) mode */
 110         MODE_SAS_PORT6_MASK = (1U << 6),
 111         MODE_SAS_PORT5_MASK = (1U << 5),
 112         MODE_SAS_PORT4_MASK = (1U << 4),
 113         MODE_SAS_PORT3_MASK = (1U << 3),
 114         MODE_SAS_PORT2_MASK = (1U << 2),
 115         MODE_SAS_PORT1_MASK = (1U << 1),
 116         MODE_SAS_PORT0_MASK = (1U << 0),
 117         MODE_SAS_SATA   =       MODE_SAS_PORT0_MASK | MODE_SAS_PORT1_MASK |
 118                                 MODE_SAS_PORT2_MASK | MODE_SAS_PORT3_MASK |
 119                                 MODE_SAS_PORT4_MASK | MODE_SAS_PORT5_MASK |
 120                                 MODE_SAS_PORT6_MASK | MODE_SAS_PORT7_MASK,
 121
 122                                 /* SAS_MODE value may be
 123                                  * dictated (in hw) by values
 124                                  * of SATA_TARGET & AUTO_DET
 125                                  */
 126
 127         /* MVS_TX_CFG */
 128         TX_EN                   = (1U << 16),   /* Enable TX */
 129         TX_RING_SZ_MASK         = 0xfff,        /* TX ring size, bits 11:0 */
 130
 131         /* MVS_RX_CFG */
 132         RX_EN                   = (1U << 16),   /* Enable RX */
 133         RX_RING_SZ_MASK         = 0xfff,        /* RX ring size, bits 11:0 */
 134
 135         /* MVS_INT_COAL */
 136         COAL_EN                 = (1U << 16),   /* Enable int coalescing */
 137
 138         /* MVS_INT_STAT, MVS_INT_MASK */
 139         CINT_I2C                = (1U << 31),   /* I2C event */
 140         CINT_SW0                = (1U << 30),   /* software event 0 */
 141         CINT_SW1                = (1U << 29),   /* software event 1 */
 142         CINT_PRD_BC             = (1U << 28),   /* PRD BC err for read cmd */
 143         CINT_DMA_PCIE           = (1U << 27),   /* DMA to PCIE timeout */
 144         CINT_MEM                = (1U << 26),   /* int mem parity err */
 145         CINT_I2C_SLAVE          = (1U << 25),   /* slave I2C event */
 146         CINT_SRS                = (1U << 3),    /* SRS event */
 147         CINT_CI_STOP            = (1U << 1),    /* cmd issue stopped */
 148         CINT_DONE               = (1U << 0),    /* cmd completion */
 149
 150                                                 /* shl for ports 1-3 */
 151         CINT_PORT_STOPPED       = (1U << 16),   /* port0 stopped */
 152         CINT_PORT               = (1U << 8),    /* port0 event */
 153         CINT_PORT_MASK_OFFSET   = 8,
 154         CINT_PORT_MASK          = (0xFF << CINT_PORT_MASK_OFFSET),
 155         CINT_PHY_MASK_OFFSET    = 4,
 156         CINT_PHY_MASK           = (0x0F << CINT_PHY_MASK_OFFSET),
 157
 158         /* TX (delivery) ring bits */
 159         TXQ_CMD_SHIFT           = 29,
 160         TXQ_CMD_SSP             = 1,            /* SSP protocol */
 161         TXQ_CMD_SMP             = 2,            /* SMP protocol */
 162         TXQ_CMD_STP             = 3,            /* STP/SATA protocol */
 163         TXQ_CMD_SSP_FREE_LIST   = 4,            /* add to SSP targ free list */
 164         TXQ_CMD_SLOT_RESET      = 7,            /* reset command slot */
 165         TXQ_MODE_I              = (1U << 28),   /* mode: 0=target,1=initiator */
 166         TXQ_MODE_TARGET         = 0,
 167         TXQ_MODE_INITIATOR      = 1,
 168         TXQ_PRIO_HI             = (1U << 27),   /* priority: 0=normal, 1=high */
 169         TXQ_PRI_NORMAL          = 0,
 170         TXQ_PRI_HIGH            = 1,
 171         TXQ_SRS_SHIFT           = 20,           /* SATA register set */
 172         TXQ_SRS_MASK            = 0x7f,
 173         TXQ_PHY_SHIFT           = 12,           /* PHY bitmap */
 174         TXQ_PHY_MASK            = 0xff,
 175         TXQ_SLOT_MASK           = 0xfff,        /* slot number */
 176
 177         /* RX (completion) ring bits */
 178         RXQ_GOOD                = (1U << 23),   /* Response good */
 179         RXQ_SLOT_RESET          = (1U << 21),   /* Slot reset complete */
 180         RXQ_CMD_RX              = (1U << 20),   /* target cmd received */
 181         RXQ_ATTN                = (1U << 19),   /* attention */
 182         RXQ_RSP                 = (1U << 18),   /* response frame xfer'd */
 183         RXQ_ERR                 = (1U << 17),   /* err info rec xfer'd */
 184         RXQ_DONE                = (1U << 16),   /* cmd complete */
 185         RXQ_SLOT_MASK           = 0xfff,        /* slot number */
 186
 187         /* mvs_cmd_hdr bits */
 188         MCH_PRD_LEN_SHIFT       = 16,           /* 16-bit PRD table len */
 189         MCH_SSP_FR_TYPE_SHIFT   = 13,           /* SSP frame type */
 190
 191                                                 /* SSP initiator only */
 192         MCH_SSP_FR_CMD          = 0x0,          /* COMMAND frame */
 193
 194                                                 /* SSP initiator or target */
 195         MCH_SSP_FR_TASK         = 0x1,          /* TASK frame */
 196
 197                                                 /* SSP target only */
 198         MCH_SSP_FR_XFER_RDY     = 0x4,          /* XFER_RDY frame */
 199         MCH_SSP_FR_RESP         = 0x5,          /* RESPONSE frame */
 200         MCH_SSP_FR_READ         = 0x6,          /* Read DATA frame(s) */
 201         MCH_SSP_FR_READ_RESP    = 0x7,          /* ditto, plus RESPONSE */
 202
 203         MCH_SSP_MODE_PASSTHRU   = 1,
 204         MCH_SSP_MODE_NORMAL     = 0,
 205         MCH_PASSTHRU            = (1U << 12),   /* pass-through (SSP) */
 206         MCH_FBURST              = (1U << 11),   /* first burst (SSP) */
 207         MCH_CHK_LEN             = (1U << 10),   /* chk xfer len (SSP) */
 208         MCH_RETRY               = (1U << 9),    /* tport layer retry (SSP) */
 209         MCH_PROTECTION          = (1U << 8),    /* protection info rec (SSP) */
 210         MCH_RESET               = (1U << 7),    /* Reset (STP/SATA) */
 211         MCH_FPDMA               = (1U << 6),    /* First party DMA (STP/SATA) */
 212         MCH_ATAPI               = (1U << 5),    /* ATAPI (STP/SATA) */
 213         MCH_BIST                = (1U << 4),    /* BIST activate (STP/SATA) */
 214         MCH_PMP_MASK            = 0xf,          /* PMP from cmd FIS (STP/SATA)*/
 215
 216         CCTL_RST                = (1U << 5),    /* port logic reset */
 217
 218                                                 /* 0(LSB first), 1(MSB first) */
 219         CCTL_ENDIAN_DATA        = (1U << 3),    /* PRD data */
 220         CCTL_ENDIAN_RSP         = (1U << 2),    /* response frame */
 221         CCTL_ENDIAN_OPEN        = (1U << 1),    /* open address frame */
 222         CCTL_ENDIAN_CMD         = (1U << 0),    /* command table */
 223
 224         /* MVS_Px_SER_CTLSTAT (per-phy control) */
 225         PHY_SSP_RST             = (1U << 3),    /* reset SSP link layer */
 226         PHY_BCAST_CHG           = (1U << 2),    /* broadcast(change) notif */
 227         PHY_RST_HARD            = (1U << 1),    /* hard reset + phy reset */
 228         PHY_RST                 = (1U << 0),    /* phy reset */
 229         PHY_READY_MASK          = (1U << 20),
 230
 231         /* MVS_Px_INT_STAT, MVS_Px_INT_MASK (per-phy events) */
 232         PHYEV_DEC_ERR           = (1U << 24),   /* Phy Decoding Error */
 233         PHYEV_DCDR_ERR          = (1U << 23),   /* STP Deocder Error */
 234         PHYEV_CRC_ERR           = (1U << 22),   /* STP CRC Error */
 235         PHYEV_UNASSOC_FIS       = (1U << 19),   /* unassociated FIS rx'd */
 236         PHYEV_AN                = (1U << 18),   /* SATA async notification */
 237         PHYEV_BIST_ACT          = (1U << 17),   /* BIST activate FIS */
 238         PHYEV_SIG_FIS           = (1U << 16),   /* signature FIS */
 239         PHYEV_POOF              = (1U << 12),   /* phy ready from 1 -> 0 */
 240         PHYEV_IU_BIG            = (1U << 11),   /* IU too long err */
 241         PHYEV_IU_SMALL          = (1U << 10),   /* IU too short err */
 242         PHYEV_UNK_TAG           = (1U << 9),    /* unknown tag */
 243         PHYEV_BROAD_CH          = (1U << 8),    /* broadcast(CHANGE) */
 244         PHYEV_COMWAKE           = (1U << 7),    /* COMWAKE rx'd */
 245         PHYEV_PORT_SEL          = (1U << 6),    /* port selector present */
 246         PHYEV_HARD_RST          = (1U << 5),    /* hard reset rx'd */
 247         PHYEV_ID_TMOUT          = (1U << 4),    /* identify timeout */
 248         PHYEV_ID_FAIL           = (1U << 3),    /* identify failed */
 249         PHYEV_ID_DONE           = (1U << 2),    /* identify done */
 250         PHYEV_HARD_RST_DONE     = (1U << 1),    /* hard reset done */
 251         PHYEV_RDY_CH            = (1U << 0),    /* phy ready changed state */
 252
 253         /* MVS_PCS */
 254         PCS_EN_SATA_REG_SHIFT   = (16),         /* Enable SATA Register Set */
 255         PCS_EN_PORT_XMT_SHIFT   = (12),         /* Enable Port Transmit */
 256         PCS_EN_PORT_XMT_SHIFT2  = (8),          /* For 6485 */
 257         PCS_SATA_RETRY          = (1U << 8),    /* retry ctl FIS on R_ERR */
 258         PCS_RSP_RX_EN           = (1U << 7),    /* raw response rx */
 259         PCS_SATA_RETRY_2        = (1U << 6),    /* For 9180 */
 260         PCS_SELF_CLEAR          = (1U << 5),    /* self-clearing int mode */
 261         PCS_FIS_RX_EN           = (1U << 4),    /* FIS rx enable */
 262         PCS_CMD_STOP_ERR        = (1U << 3),    /* cmd stop-on-err enable */
 263         PCS_CMD_RST             = (1U << 1),    /* reset cmd issue */
 264         PCS_CMD_EN              = (1U << 0),    /* enable cmd issue */
 265
 266         /* Port n Attached Device Info */
 267         PORT_DEV_SSP_TRGT       = (1U << 19),
 268         PORT_DEV_SMP_TRGT       = (1U << 18),
 269         PORT_DEV_STP_TRGT       = (1U << 17),
 270         PORT_DEV_SSP_INIT       = (1U << 11),
 271         PORT_DEV_SMP_INIT       = (1U << 10),
 272         PORT_DEV_STP_INIT       = (1U << 9),
 273         PORT_PHY_ID_MASK        = (0xFFU << 24),
 274         PORT_SSP_TRGT_MASK      = (0x1U << 19),
 275         PORT_SSP_INIT_MASK      = (0x1U << 11),
 276         PORT_DEV_TRGT_MASK      = (0x7U << 17),
 277         PORT_DEV_INIT_MASK      = (0x7U << 9),
 278         PORT_DEV_TYPE_MASK      = (0x7U << 0),
 279
 280         /* Port n PHY Status */
 281         PHY_RDY                 = (1U << 2),
 282         PHY_DW_SYNC             = (1U << 1),
 283         PHY_OOB_DTCTD           = (1U << 0),
 284
 285         /* VSR */
 286         /* PHYMODE 6 (CDB) */
 287         PHY_MODE6_LATECLK       = (1U << 29),   /* Lock Clock */
 288         PHY_MODE6_DTL_SPEED     = (1U << 27),   /* Digital Loop Speed */
 289         PHY_MODE6_FC_ORDER      = (1U << 26),   /* Fibre Channel Mode Order*/
 290         PHY_MODE6_MUCNT_EN      = (1U << 24),   /* u Count Enable */
 291         PHY_MODE6_SEL_MUCNT_LEN = (1U << 22),   /* Training Length Select */
 292         PHY_MODE6_SELMUPI       = (1U << 20),   /* Phase Multi Select (init) */
 293         PHY_MODE6_SELMUPF       = (1U << 18),   /* Phase Multi Select (final) */
 294         PHY_MODE6_SELMUFF       = (1U << 16),   /* Freq Loop Multi Sel(final) */
 295         PHY_MODE6_SELMUFI       = (1U << 14),   /* Freq Loop Multi Sel(init) */
 296         PHY_MODE6_FREEZE_LOOP   = (1U << 12),   /* Freeze Rx CDR Loop */
 297         PHY_MODE6_INT_RXFOFFS   = (1U << 3),    /* Rx CDR Freq Loop Enable */
 298         PHY_MODE6_FRC_RXFOFFS   = (1U << 2),    /* Initial Rx CDR Offset */
 299         PHY_MODE6_STAU_0D8      = (1U << 1),    /* Rx CDR Freq Loop Saturate */
 300         PHY_MODE6_RXSAT_DIS     = (1U << 0),    /* Saturate Ctl */
 301 };
 302
 303 /* SAS/SATA configuration port registers, aka phy registers */
 304 enum sas_sata_config_port_regs {
 305         PHYR_IDENTIFY           = 0x00, /* info for IDENTIFY frame */
 306         PHYR_ADDR_LO            = 0x04, /* my SAS address (low) */
 307         PHYR_ADDR_HI            = 0x08, /* my SAS address (high) */
 308         PHYR_ATT_DEV_INFO       = 0x0C, /* attached device info */
 309         PHYR_ATT_ADDR_LO        = 0x10, /* attached dev SAS addr (low) */
 310         PHYR_ATT_ADDR_HI        = 0x14, /* attached dev SAS addr (high) */
 311         PHYR_SATA_CTL           = 0x18, /* SATA control */
 312         PHYR_PHY_STAT           = 0x1C, /* PHY status */
 313         PHYR_SATA_SIG0  = 0x20, /*port SATA signature FIS(Byte 0-3) */
 314         PHYR_SATA_SIG1  = 0x24, /*port SATA signature FIS(Byte 4-7) */
 315         PHYR_SATA_SIG2  = 0x28, /*port SATA signature FIS(Byte 8-11) */
 316         PHYR_SATA_SIG3  = 0x2c, /*port SATA signature FIS(Byte 12-15) */
 317         PHYR_R_ERR_COUNT        = 0x30, /* port R_ERR count register */
 318         PHYR_CRC_ERR_COUNT      = 0x34, /* port CRC error count register */
 319         PHYR_WIDE_PORT  = 0x38, /* wide port participating */
 320         PHYR_CURRENT0           = 0x80, /* current connection info 0 */
 321         PHYR_CURRENT1           = 0x84, /* current connection info 1 */
 322         PHYR_CURRENT2           = 0x88, /* current connection info 2 */
 323         CONFIG_ID_FRAME0       = 0x100, /* Port device ID frame register 0 */
 324         CONFIG_ID_FRAME1       = 0x104, /* Port device ID frame register 1 */
 325         CONFIG_ID_FRAME2       = 0x108, /* Port device ID frame register 2 */
 326         CONFIG_ID_FRAME3       = 0x10c, /* Port device ID frame register 3 */
 327         CONFIG_ID_FRAME4       = 0x110, /* Port device ID frame register 4 */
 328         CONFIG_ID_FRAME5       = 0x114, /* Port device ID frame register 5 */
 329         CONFIG_ID_FRAME6       = 0x118, /* Port device ID frame register 6 */
 330         CONFIG_ATT_ID_FRAME0   = 0x11c, /* attached ID frame register 0 */
 331         CONFIG_ATT_ID_FRAME1   = 0x120, /* attached ID frame register 1 */
 332         CONFIG_ATT_ID_FRAME2   = 0x124, /* attached ID frame register 2 */
 333         CONFIG_ATT_ID_FRAME3   = 0x128, /* attached ID frame register 3 */
 334         CONFIG_ATT_ID_FRAME4   = 0x12c, /* attached ID frame register 4 */
 335         CONFIG_ATT_ID_FRAME5   = 0x130, /* attached ID frame register 5 */
 336         CONFIG_ATT_ID_FRAME6   = 0x134, /* attached ID frame register 6 */
 337 };
 338
 339 enum sas_cmd_port_registers {
 340         CMD_CMRST_OOB_DET       = 0x100, /* COMRESET OOB detect register */
 341         CMD_CMWK_OOB_DET        = 0x104, /* COMWAKE OOB detect register */
 342         CMD_CMSAS_OOB_DET       = 0x108, /* COMSAS OOB detect register */
 343         CMD_BRST_OOB_DET        = 0x10c, /* burst OOB detect register */
 344         CMD_OOB_SPACE   = 0x110, /* OOB space control register */
 345         CMD_OOB_BURST   = 0x114, /* OOB burst control register */
 346         CMD_PHY_TIMER           = 0x118, /* PHY timer control register */
 347         CMD_PHY_CONFIG0 = 0x11c, /* PHY config register 0 */
 348         CMD_PHY_CONFIG1 = 0x120, /* PHY config register 1 */
 349         CMD_SAS_CTL0            = 0x124, /* SAS control register 0 */
 350         CMD_SAS_CTL1            = 0x128, /* SAS control register 1 */
 351         CMD_SAS_CTL2            = 0x12c, /* SAS control register 2 */
 352         CMD_SAS_CTL3            = 0x130, /* SAS control register 3 */
 353         CMD_ID_TEST             = 0x134, /* ID test register */
 354         CMD_PL_TIMER            = 0x138, /* PL timer register */
 355         CMD_WD_TIMER            = 0x13c, /* WD timer register */
 356         CMD_PORT_SEL_COUNT      = 0x140, /* port selector count register */
 357         CMD_APP_MEM_CTL = 0x144, /* Application Memory Control */
 358         CMD_XOR_MEM_CTL = 0x148, /* XOR Block Memory Control */
 359         CMD_DMA_MEM_CTL = 0x14c, /* DMA Block Memory Control */
 360         CMD_PORT_MEM_CTL0       = 0x150, /* Port Memory Control 0 */
 361         CMD_PORT_MEM_CTL1       = 0x154, /* Port Memory Control 1 */
 362         CMD_SATA_PORT_MEM_CTL0  = 0x158, /* SATA Port Memory Control 0 */
 363         CMD_SATA_PORT_MEM_CTL1  = 0x15c, /* SATA Port Memory Control 1 */
 364         CMD_XOR_MEM_BIST_CTL    = 0x160, /* XOR Memory BIST Control */
 365         CMD_XOR_MEM_BIST_STAT   = 0x164, /* XOR Memroy BIST Status */
 366         CMD_DMA_MEM_BIST_CTL    = 0x168, /* DMA Memory BIST Control */
 367         CMD_DMA_MEM_BIST_STAT   = 0x16c, /* DMA Memory BIST Status */
 368         CMD_PORT_MEM_BIST_CTL   = 0x170, /* Port Memory BIST Control */
 369         CMD_PORT_MEM_BIST_STAT0 = 0x174, /* Port Memory BIST Status 0 */
 370         CMD_PORT_MEM_BIST_STAT1 = 0x178, /* Port Memory BIST Status 1 */
 371         CMD_STP_MEM_BIST_CTL    = 0x17c, /* STP Memory BIST Control */
 372         CMD_STP_MEM_BIST_STAT0  = 0x180, /* STP Memory BIST Status 0 */
 373         CMD_STP_MEM_BIST_STAT1  = 0x184, /* STP Memory BIST Status 1 */
 374         CMD_RESET_COUNT         = 0x188, /* Reset Count */
 375         CMD_MONTR_DATA_SEL      = 0x18C, /* Monitor Data/Select */
 376         CMD_PLL_PHY_CONFIG      = 0x190, /* PLL/PHY Configuration */
 377         CMD_PHY_CTL             = 0x194, /* PHY Control and Status */
 378         CMD_PHY_TEST_COUNT0     = 0x198, /* Phy Test Count 0 */
 379         CMD_PHY_TEST_COUNT1     = 0x19C, /* Phy Test Count 1 */
 380         CMD_PHY_TEST_COUNT2     = 0x1A0, /* Phy Test Count 2 */
 381         CMD_APP_ERR_CONFIG      = 0x1A4, /* Application Error Configuration */
 382         CMD_PND_FIFO_CTL0       = 0x1A8, /* Pending FIFO Control 0 */
 383         CMD_HOST_CTL            = 0x1AC, /* Host Control Status */
 384         CMD_HOST_WR_DATA        = 0x1B0, /* Host Write Data */
 385         CMD_HOST_RD_DATA        = 0x1B4, /* Host Read Data */
 386         CMD_PHY_MODE_21         = 0x1B8, /* Phy Mode 21 */
 387         CMD_SL_MODE0            = 0x1BC, /* SL Mode 0 */
 388         CMD_SL_MODE1            = 0x1C0, /* SL Mode 1 */
 389         CMD_PND_FIFO_CTL1       = 0x1C4, /* Pending FIFO Control 1 */
 390 };
 391
 392 enum mvs_info_flags {
 393         MVF_MSI         = (1U << 0),    /* MSI is enabled */
 394         MVF_PHY_PWR_FIX = (1U << 1),    /* bug workaround */
 395         MVF_FLAG_SOC            = (1U << 2),    /* SoC integrated controllers */
 396 };
 397
 398 enum mvs_event_flags {
 399         PHY_PLUG_EVENT  = (3U),
 400         PHY_PLUG_IN             = (1U << 0),    /* phy plug in */
 401         PHY_PLUG_OUT            = (1U << 1),    /* phy plug out */
 402 };
 403
 404 enum mvs_port_type {
 405         PORT_TGT_MASK   =  (1U << 5),
 406         PORT_INIT_PORT  =  (1U << 4),
 407         PORT_TGT_PORT   =  (1U << 3),
 408         PORT_INIT_TGT_PORT = (PORT_INIT_PORT | PORT_TGT_PORT),
 409         PORT_TYPE_SAS   =  (1U << 1),
 410         PORT_TYPE_SATA  =  (1U << 0),
 411 };
 412
 413 /* Command Table Format */
 414 enum ct_format {
 415         /* SSP */
 416         SSP_F_H         =  0x00,
 417         SSP_F_IU        =  0x18,
 418         SSP_F_MAX       =  0x4D,
 419         /* STP */
 420         STP_CMD_FIS     =  0x00,
 421         STP_ATAPI_CMD   =  0x40,
 422         STP_F_MAX       =  0x10,
 423         /* SMP */
 424         SMP_F_T         =  0x00,
 425         SMP_F_DEP       =  0x01,
 426         SMP_F_MAX       =  0x101,
 427 };
 428
 429 enum status_buffer {
 430         SB_EIR_OFF      =  0x00,        /* Error Information Record */
 431         SB_RFB_OFF      =  0x08,        /* Response Frame Buffer */
 432         SB_RFB_MAX      =  0x400,       /* RFB size*/
 433 };
 434
 435 enum error_info_rec {
 436         CMD_ISS_STPD    = (1U << 31),   /* Cmd Issue Stopped */
 437         CMD_PI_ERR      = (1U << 30),   /* Protection info error.  see flags2 */
 438         RSP_OVER        = (1U << 29),   /* rsp buffer overflow */
 439         RETRY_LIM       = (1U << 28),   /* FIS/frame retry limit exceeded */
 440         UNK_FIS         = (1U << 27),   /* unknown FIS */
 441         DMA_TERM        = (1U << 26),   /* DMA terminate primitive rx'd */
 442         SYNC_ERR        = (1U << 25),   /* SYNC rx'd during frame xmit */
 443         TFILE_ERR       = (1U << 24),   /* SATA taskfile Error bit set */
 444         R_ERR           = (1U << 23),   /* SATA returned R_ERR prim */
 445         RD_OFS          = (1U << 20),   /* Read DATA frame invalid offset */
 446         XFER_RDY_OFS    = (1U << 19),   /* XFER_RDY offset error */
 447         UNEXP_XFER_RDY  = (1U << 18),   /* unexpected XFER_RDY error */
 448         DATA_OVER_UNDER = (1U << 16),   /* data overflow/underflow */
 449         INTERLOCK       = (1U << 15),   /* interlock error */
 450         NAK             = (1U << 14),   /* NAK rx'd */
 451         ACK_NAK_TO      = (1U << 13),   /* ACK/NAK timeout */
 452         CXN_CLOSED      = (1U << 12),   /* cxn closed w/out ack/nak */
 453         OPEN_TO         = (1U << 11),   /* I_T nexus lost, open cxn timeout */
 454         PATH_BLOCKED    = (1U << 10),   /* I_T nexus lost, pathway blocked */
 455         NO_DEST         = (1U << 9),    /* I_T nexus lost, no destination */
 456         STP_RES_BSY     = (1U << 8),    /* STP resources busy */
 457         BREAK           = (1U << 7),    /* break received */
 458         BAD_DEST        = (1U << 6),    /* bad destination */
 459         BAD_PROTO       = (1U << 5),    /* protocol not supported */
 460         BAD_RATE        = (1U << 4),    /* cxn rate not supported */
 461         WRONG_DEST      = (1U << 3),    /* wrong destination error */
 462         CREDIT_TO       = (1U << 2),    /* credit timeout */
 463         WDOG_TO         = (1U << 1),    /* watchdog timeout */
 464         BUF_PAR         = (1U << 0),    /* buffer parity error */
 465 };
 466
 467 enum error_info_rec_2 {
 468         SLOT_BSY_ERR    = (1U << 31),   /* Slot Busy Error */
 469         GRD_CHK_ERR     = (1U << 14),   /* Guard Check Error */
 470         APP_CHK_ERR     = (1U << 13),   /* Application Check error */
 471         REF_CHK_ERR     = (1U << 12),   /* Reference Check Error */
 472         USR_BLK_NM      = (1U << 0),    /* User Block Number */
 473 };
 474
 475 enum pci_cfg_register_bits {
 476         PCTL_PWR_OFF    = (0xFU << 24),
 477         PCTL_COM_ON     = (0xFU << 20),
 478         PCTL_LINK_RST   = (0xFU << 16),
 479         PCTL_LINK_OFFS  = (16),
 480         PCTL_PHY_DSBL   = (0xFU << 12),
 481         PCTL_PHY_DSBL_OFFS      = (12),
 482         PRD_REQ_SIZE    = (0x4000),
 483         PRD_REQ_MASK    = (0x00007000),
 484         PLS_NEG_LINK_WD         = (0x3FU << 4),
 485         PLS_NEG_LINK_WD_OFFS    = 4,
 486         PLS_LINK_SPD            = (0x0FU << 0),
 487         PLS_LINK_SPD_OFFS       = 0,
 488 };
 489
 490 enum open_frame_protocol {
 491         PROTOCOL_SMP    = 0x0,
 492         PROTOCOL_SSP    = 0x1,
 493         PROTOCOL_STP    = 0x2,
 494 };
 495
 496 /* define for response frame datapres field */
 497 enum datapres_field {
 498         NO_DATA         = 0,
 499         RESPONSE_DATA   = 1,
 500         SENSE_DATA      = 2,
 501 };
 502
 503 /* define task management IU */
 504 struct mvs_tmf_task{
 505         u8 tmf;
 506         u16 tag_of_task_to_be_managed;
 507 };
 508 #endif