2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
5 * Copyright (C) 2010 Texas Instruments.
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/serial_reg.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/platform_device.h>
37 #include <linux/clk.h>
38 #include <linux/serial_core.h>
39 #include <linux/irq.h>
40 #include <linux/pm_runtime.h>
42 #include <linux/gpio.h>
43 #include <linux/pinctrl/consumer.h>
44 #include <linux/platform_data/serial-omap.h>
46 #define OMAP_MAX_HSUART_PORTS 6
48 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
50 #define OMAP_UART_REV_42 0x0402
51 #define OMAP_UART_REV_46 0x0406
52 #define OMAP_UART_REV_52 0x0502
53 #define OMAP_UART_REV_63 0x0603
55 #define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
56 #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
58 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
60 /* SCR register bitmasks */
61 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
62 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
63 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
65 /* FCR register bitmasks */
66 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
67 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
69 /* MVR register bitmasks */
70 #define OMAP_UART_MVR_SCHEME_SHIFT 30
72 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
73 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
74 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
76 #define OMAP_UART_MVR_MAJ_MASK 0x700
77 #define OMAP_UART_MVR_MAJ_SHIFT 8
78 #define OMAP_UART_MVR_MIN_MASK 0x3f
80 #define OMAP_UART_DMA_CH_FREE -1
82 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
83 #define OMAP_MODE13X_SPEED 230400
86 * Enable module level wakeup in WER reg
88 #define OMAP_UART_WER_MOD_WKUP 0X7F
90 /* Enable XON/XOFF flow control on output */
91 #define OMAP_UART_SW_TX 0x08
93 /* Enable XON/XOFF flow control on input */
94 #define OMAP_UART_SW_RX 0x02
96 #define OMAP_UART_SW_CLR 0xF0
98 #define OMAP_UART_TCR_TRIG 0x0F
100 struct uart_omap_dma
{
105 dma_addr_t rx_buf_dma_phys
;
106 dma_addr_t tx_buf_dma_phys
;
107 unsigned int uart_base
;
109 * Buffer for rx dma.It is not required for tx because the buffer
110 * comes from port structure.
112 unsigned char *rx_buf
;
113 unsigned int prev_rx_dma_pos
;
119 /* timer to poll activity on rx dma */
120 struct timer_list rx_timer
;
121 unsigned int rx_buf_size
;
122 unsigned int rx_poll_rate
;
123 unsigned int rx_timeout
;
126 struct uart_omap_port
{
127 struct uart_port port
;
128 struct uart_omap_dma uart_dma
;
143 * Some bits in registers are cleared on a read, so they must
144 * be saved whenever the register is read but the bits will not
145 * be immediately processed.
147 unsigned int lsr_break_flag
;
148 unsigned char msr_saved_flags
;
150 unsigned long port_activity
;
151 int context_loss_cnt
;
159 struct pm_qos_request pm_qos_request
;
162 struct work_struct qos_work
;
163 struct pinctrl
*pins
;
166 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
168 static struct uart_omap_port
*ui
[OMAP_MAX_HSUART_PORTS
];
170 /* Forward declaration of functions */
171 static void serial_omap_mdr1_errataset(struct uart_omap_port
*up
, u8 mdr1
);
173 static struct workqueue_struct
*serial_omap_uart_wq
;
175 static inline unsigned int serial_in(struct uart_omap_port
*up
, int offset
)
177 offset
<<= up
->port
.regshift
;
178 return readw(up
->port
.membase
+ offset
);
181 static inline void serial_out(struct uart_omap_port
*up
, int offset
, int value
)
183 offset
<<= up
->port
.regshift
;
184 writew(value
, up
->port
.membase
+ offset
);
187 static inline void serial_omap_clear_fifos(struct uart_omap_port
*up
)
189 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
);
190 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
|
191 UART_FCR_CLEAR_RCVR
| UART_FCR_CLEAR_XMIT
);
192 serial_out(up
, UART_FCR
, 0);
195 static int serial_omap_get_context_loss_count(struct uart_omap_port
*up
)
197 struct omap_uart_port_info
*pdata
= up
->dev
->platform_data
;
199 if (!pdata
|| !pdata
->get_context_loss_count
)
202 return pdata
->get_context_loss_count(up
->dev
);
205 static void serial_omap_set_forceidle(struct uart_omap_port
*up
)
207 struct omap_uart_port_info
*pdata
= up
->dev
->platform_data
;
209 if (!pdata
|| !pdata
->set_forceidle
)
212 pdata
->set_forceidle(up
->dev
);
215 static void serial_omap_set_noidle(struct uart_omap_port
*up
)
217 struct omap_uart_port_info
*pdata
= up
->dev
->platform_data
;
219 if (!pdata
|| !pdata
->set_noidle
)
222 pdata
->set_noidle(up
->dev
);
225 static void serial_omap_enable_wakeup(struct uart_omap_port
*up
, bool enable
)
227 struct omap_uart_port_info
*pdata
= up
->dev
->platform_data
;
229 if (!pdata
|| !pdata
->enable_wakeup
)
232 pdata
->enable_wakeup(up
->dev
, enable
);
236 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
237 * @port: uart port info
238 * @baud: baudrate for which mode needs to be determined
240 * Returns true if baud rate is MODE16X and false if MODE13X
241 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
242 * and Error Rates" determines modes not for all common baud rates.
243 * E.g. for 1000000 baud rate mode must be 16x, but according to that
244 * table it's determined as 13x.
247 serial_omap_baud_is_mode16(struct uart_port
*port
, unsigned int baud
)
249 unsigned int n13
= port
->uartclk
/ (13 * baud
);
250 unsigned int n16
= port
->uartclk
/ (16 * baud
);
251 int baudAbsDiff13
= baud
- (port
->uartclk
/ (13 * n13
));
252 int baudAbsDiff16
= baud
- (port
->uartclk
/ (16 * n16
));
253 if(baudAbsDiff13
< 0)
254 baudAbsDiff13
= -baudAbsDiff13
;
255 if(baudAbsDiff16
< 0)
256 baudAbsDiff16
= -baudAbsDiff16
;
258 return (baudAbsDiff13
> baudAbsDiff16
);
262 * serial_omap_get_divisor - calculate divisor value
263 * @port: uart port info
264 * @baud: baudrate for which divisor needs to be calculated.
267 serial_omap_get_divisor(struct uart_port
*port
, unsigned int baud
)
269 unsigned int divisor
;
271 if (!serial_omap_baud_is_mode16(port
, baud
))
275 return port
->uartclk
/(baud
* divisor
);
278 static void serial_omap_enable_ms(struct uart_port
*port
)
280 struct uart_omap_port
*up
= to_uart_omap_port(port
);
282 dev_dbg(up
->port
.dev
, "serial_omap_enable_ms+%d\n", up
->port
.line
);
284 pm_runtime_get_sync(up
->dev
);
285 up
->ier
|= UART_IER_MSI
;
286 serial_out(up
, UART_IER
, up
->ier
);
287 pm_runtime_mark_last_busy(up
->dev
);
288 pm_runtime_put_autosuspend(up
->dev
);
291 static void serial_omap_stop_tx(struct uart_port
*port
)
293 struct uart_omap_port
*up
= to_uart_omap_port(port
);
295 pm_runtime_get_sync(up
->dev
);
296 if (up
->ier
& UART_IER_THRI
) {
297 up
->ier
&= ~UART_IER_THRI
;
298 serial_out(up
, UART_IER
, up
->ier
);
301 serial_omap_set_forceidle(up
);
303 pm_runtime_mark_last_busy(up
->dev
);
304 pm_runtime_put_autosuspend(up
->dev
);
307 static void serial_omap_stop_rx(struct uart_port
*port
)
309 struct uart_omap_port
*up
= to_uart_omap_port(port
);
311 pm_runtime_get_sync(up
->dev
);
312 up
->ier
&= ~UART_IER_RLSI
;
313 up
->port
.read_status_mask
&= ~UART_LSR_DR
;
314 serial_out(up
, UART_IER
, up
->ier
);
315 pm_runtime_mark_last_busy(up
->dev
);
316 pm_runtime_put_autosuspend(up
->dev
);
319 static void transmit_chars(struct uart_omap_port
*up
, unsigned int lsr
)
321 struct circ_buf
*xmit
= &up
->port
.state
->xmit
;
324 if (up
->port
.x_char
) {
325 serial_out(up
, UART_TX
, up
->port
.x_char
);
326 up
->port
.icount
.tx
++;
330 if (uart_circ_empty(xmit
) || uart_tx_stopped(&up
->port
)) {
331 serial_omap_stop_tx(&up
->port
);
334 count
= up
->port
.fifosize
/ 4;
336 serial_out(up
, UART_TX
, xmit
->buf
[xmit
->tail
]);
337 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
338 up
->port
.icount
.tx
++;
339 if (uart_circ_empty(xmit
))
341 } while (--count
> 0);
343 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
) {
344 spin_unlock(&up
->port
.lock
);
345 uart_write_wakeup(&up
->port
);
346 spin_lock(&up
->port
.lock
);
349 if (uart_circ_empty(xmit
))
350 serial_omap_stop_tx(&up
->port
);
353 static inline void serial_omap_enable_ier_thri(struct uart_omap_port
*up
)
355 if (!(up
->ier
& UART_IER_THRI
)) {
356 up
->ier
|= UART_IER_THRI
;
357 serial_out(up
, UART_IER
, up
->ier
);
361 static void serial_omap_start_tx(struct uart_port
*port
)
363 struct uart_omap_port
*up
= to_uart_omap_port(port
);
365 pm_runtime_get_sync(up
->dev
);
366 serial_omap_enable_ier_thri(up
);
367 serial_omap_set_noidle(up
);
368 pm_runtime_mark_last_busy(up
->dev
);
369 pm_runtime_put_autosuspend(up
->dev
);
372 static void serial_omap_throttle(struct uart_port
*port
)
374 struct uart_omap_port
*up
= to_uart_omap_port(port
);
377 pm_runtime_get_sync(up
->dev
);
378 spin_lock_irqsave(&up
->port
.lock
, flags
);
379 up
->ier
&= ~(UART_IER_RLSI
| UART_IER_RDI
);
380 serial_out(up
, UART_IER
, up
->ier
);
381 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
382 pm_runtime_mark_last_busy(up
->dev
);
383 pm_runtime_put_autosuspend(up
->dev
);
386 static void serial_omap_unthrottle(struct uart_port
*port
)
388 struct uart_omap_port
*up
= to_uart_omap_port(port
);
391 pm_runtime_get_sync(up
->dev
);
392 spin_lock_irqsave(&up
->port
.lock
, flags
);
393 up
->ier
|= UART_IER_RLSI
| UART_IER_RDI
;
394 serial_out(up
, UART_IER
, up
->ier
);
395 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
396 pm_runtime_mark_last_busy(up
->dev
);
397 pm_runtime_put_autosuspend(up
->dev
);
400 static unsigned int check_modem_status(struct uart_omap_port
*up
)
404 status
= serial_in(up
, UART_MSR
);
405 status
|= up
->msr_saved_flags
;
406 up
->msr_saved_flags
= 0;
407 if ((status
& UART_MSR_ANY_DELTA
) == 0)
410 if (status
& UART_MSR_ANY_DELTA
&& up
->ier
& UART_IER_MSI
&&
411 up
->port
.state
!= NULL
) {
412 if (status
& UART_MSR_TERI
)
413 up
->port
.icount
.rng
++;
414 if (status
& UART_MSR_DDSR
)
415 up
->port
.icount
.dsr
++;
416 if (status
& UART_MSR_DDCD
)
417 uart_handle_dcd_change
418 (&up
->port
, status
& UART_MSR_DCD
);
419 if (status
& UART_MSR_DCTS
)
420 uart_handle_cts_change
421 (&up
->port
, status
& UART_MSR_CTS
);
422 wake_up_interruptible(&up
->port
.state
->port
.delta_msr_wait
);
428 static void serial_omap_rlsi(struct uart_omap_port
*up
, unsigned int lsr
)
431 unsigned char ch
= 0;
433 if (likely(lsr
& UART_LSR_DR
))
434 ch
= serial_in(up
, UART_RX
);
436 up
->port
.icount
.rx
++;
439 if (lsr
& UART_LSR_BI
) {
441 lsr
&= ~(UART_LSR_FE
| UART_LSR_PE
);
442 up
->port
.icount
.brk
++;
444 * We do the SysRQ and SAK checking
445 * here because otherwise the break
446 * may get masked by ignore_status_mask
447 * or read_status_mask.
449 if (uart_handle_break(&up
->port
))
454 if (lsr
& UART_LSR_PE
) {
456 up
->port
.icount
.parity
++;
459 if (lsr
& UART_LSR_FE
) {
461 up
->port
.icount
.frame
++;
464 if (lsr
& UART_LSR_OE
)
465 up
->port
.icount
.overrun
++;
467 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
468 if (up
->port
.line
== up
->port
.cons
->index
) {
469 /* Recover the break flag from console xmit */
470 lsr
|= up
->lsr_break_flag
;
473 uart_insert_char(&up
->port
, lsr
, UART_LSR_OE
, 0, flag
);
476 static void serial_omap_rdi(struct uart_omap_port
*up
, unsigned int lsr
)
478 unsigned char ch
= 0;
481 if (!(lsr
& UART_LSR_DR
))
484 ch
= serial_in(up
, UART_RX
);
486 up
->port
.icount
.rx
++;
488 if (uart_handle_sysrq_char(&up
->port
, ch
))
491 uart_insert_char(&up
->port
, lsr
, UART_LSR_OE
, ch
, flag
);
495 * serial_omap_irq() - This handles the interrupt from one port
496 * @irq: uart port irq number
497 * @dev_id: uart port info
499 static irqreturn_t
serial_omap_irq(int irq
, void *dev_id
)
501 struct uart_omap_port
*up
= dev_id
;
502 unsigned int iir
, lsr
;
504 irqreturn_t ret
= IRQ_NONE
;
507 spin_lock(&up
->port
.lock
);
508 pm_runtime_get_sync(up
->dev
);
511 iir
= serial_in(up
, UART_IIR
);
512 if (iir
& UART_IIR_NO_INT
)
516 lsr
= serial_in(up
, UART_LSR
);
518 /* extract IRQ type from IIR register */
523 check_modem_status(up
);
526 transmit_chars(up
, lsr
);
528 case UART_IIR_RX_TIMEOUT
:
531 serial_omap_rdi(up
, lsr
);
534 serial_omap_rlsi(up
, lsr
);
536 case UART_IIR_CTS_RTS_DSR
:
537 /* simply try again */
544 } while (!(iir
& UART_IIR_NO_INT
) && max_count
--);
546 spin_unlock(&up
->port
.lock
);
548 tty_flip_buffer_push(&up
->port
.state
->port
);
550 pm_runtime_mark_last_busy(up
->dev
);
551 pm_runtime_put_autosuspend(up
->dev
);
552 up
->port_activity
= jiffies
;
557 static unsigned int serial_omap_tx_empty(struct uart_port
*port
)
559 struct uart_omap_port
*up
= to_uart_omap_port(port
);
560 unsigned long flags
= 0;
561 unsigned int ret
= 0;
563 pm_runtime_get_sync(up
->dev
);
564 dev_dbg(up
->port
.dev
, "serial_omap_tx_empty+%d\n", up
->port
.line
);
565 spin_lock_irqsave(&up
->port
.lock
, flags
);
566 ret
= serial_in(up
, UART_LSR
) & UART_LSR_TEMT
? TIOCSER_TEMT
: 0;
567 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
568 pm_runtime_mark_last_busy(up
->dev
);
569 pm_runtime_put_autosuspend(up
->dev
);
573 static unsigned int serial_omap_get_mctrl(struct uart_port
*port
)
575 struct uart_omap_port
*up
= to_uart_omap_port(port
);
577 unsigned int ret
= 0;
579 pm_runtime_get_sync(up
->dev
);
580 status
= check_modem_status(up
);
581 pm_runtime_mark_last_busy(up
->dev
);
582 pm_runtime_put_autosuspend(up
->dev
);
584 dev_dbg(up
->port
.dev
, "serial_omap_get_mctrl+%d\n", up
->port
.line
);
586 if (status
& UART_MSR_DCD
)
588 if (status
& UART_MSR_RI
)
590 if (status
& UART_MSR_DSR
)
592 if (status
& UART_MSR_CTS
)
597 static void serial_omap_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
599 struct uart_omap_port
*up
= to_uart_omap_port(port
);
600 unsigned char mcr
= 0, old_mcr
;
602 dev_dbg(up
->port
.dev
, "serial_omap_set_mctrl+%d\n", up
->port
.line
);
603 if (mctrl
& TIOCM_RTS
)
605 if (mctrl
& TIOCM_DTR
)
607 if (mctrl
& TIOCM_OUT1
)
608 mcr
|= UART_MCR_OUT1
;
609 if (mctrl
& TIOCM_OUT2
)
610 mcr
|= UART_MCR_OUT2
;
611 if (mctrl
& TIOCM_LOOP
)
612 mcr
|= UART_MCR_LOOP
;
614 pm_runtime_get_sync(up
->dev
);
615 old_mcr
= serial_in(up
, UART_MCR
);
616 old_mcr
&= ~(UART_MCR_LOOP
| UART_MCR_OUT2
| UART_MCR_OUT1
|
617 UART_MCR_DTR
| UART_MCR_RTS
);
618 up
->mcr
= old_mcr
| mcr
;
619 serial_out(up
, UART_MCR
, up
->mcr
);
620 pm_runtime_mark_last_busy(up
->dev
);
621 pm_runtime_put_autosuspend(up
->dev
);
623 if (gpio_is_valid(up
->DTR_gpio
) &&
624 !!(mctrl
& TIOCM_DTR
) != up
->DTR_active
) {
625 up
->DTR_active
= !up
->DTR_active
;
626 if (gpio_cansleep(up
->DTR_gpio
))
627 schedule_work(&up
->qos_work
);
629 gpio_set_value(up
->DTR_gpio
,
630 up
->DTR_active
!= up
->DTR_inverted
);
634 static void serial_omap_break_ctl(struct uart_port
*port
, int break_state
)
636 struct uart_omap_port
*up
= to_uart_omap_port(port
);
637 unsigned long flags
= 0;
639 dev_dbg(up
->port
.dev
, "serial_omap_break_ctl+%d\n", up
->port
.line
);
640 pm_runtime_get_sync(up
->dev
);
641 spin_lock_irqsave(&up
->port
.lock
, flags
);
642 if (break_state
== -1)
643 up
->lcr
|= UART_LCR_SBC
;
645 up
->lcr
&= ~UART_LCR_SBC
;
646 serial_out(up
, UART_LCR
, up
->lcr
);
647 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
648 pm_runtime_mark_last_busy(up
->dev
);
649 pm_runtime_put_autosuspend(up
->dev
);
652 static int serial_omap_startup(struct uart_port
*port
)
654 struct uart_omap_port
*up
= to_uart_omap_port(port
);
655 unsigned long flags
= 0;
661 retval
= request_irq(up
->port
.irq
, serial_omap_irq
, up
->port
.irqflags
,
666 dev_dbg(up
->port
.dev
, "serial_omap_startup+%d\n", up
->port
.line
);
668 pm_runtime_get_sync(up
->dev
);
670 * Clear the FIFO buffers and disable them.
671 * (they will be reenabled in set_termios())
673 serial_omap_clear_fifos(up
);
674 /* For Hardware flow control */
675 serial_out(up
, UART_MCR
, UART_MCR_RTS
);
678 * Clear the interrupt registers.
680 (void) serial_in(up
, UART_LSR
);
681 if (serial_in(up
, UART_LSR
) & UART_LSR_DR
)
682 (void) serial_in(up
, UART_RX
);
683 (void) serial_in(up
, UART_IIR
);
684 (void) serial_in(up
, UART_MSR
);
687 * Now, initialize the UART
689 serial_out(up
, UART_LCR
, UART_LCR_WLEN8
);
690 spin_lock_irqsave(&up
->port
.lock
, flags
);
692 * Most PC uarts need OUT2 raised to enable interrupts.
694 up
->port
.mctrl
|= TIOCM_OUT2
;
695 serial_omap_set_mctrl(&up
->port
, up
->port
.mctrl
);
696 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
698 up
->msr_saved_flags
= 0;
700 * Finally, enable interrupts. Note: Modem status interrupts
701 * are set via set_termios(), which will be occurring imminently
702 * anyway, so we don't enable them here.
704 up
->ier
= UART_IER_RLSI
| UART_IER_RDI
;
705 serial_out(up
, UART_IER
, up
->ier
);
707 /* Enable module level wake up */
708 serial_out(up
, UART_OMAP_WER
, OMAP_UART_WER_MOD_WKUP
);
710 pm_runtime_mark_last_busy(up
->dev
);
711 pm_runtime_put_autosuspend(up
->dev
);
712 up
->port_activity
= jiffies
;
716 static void serial_omap_shutdown(struct uart_port
*port
)
718 struct uart_omap_port
*up
= to_uart_omap_port(port
);
719 unsigned long flags
= 0;
721 dev_dbg(up
->port
.dev
, "serial_omap_shutdown+%d\n", up
->port
.line
);
723 pm_runtime_get_sync(up
->dev
);
725 * Disable interrupts from this port
728 serial_out(up
, UART_IER
, 0);
730 spin_lock_irqsave(&up
->port
.lock
, flags
);
731 up
->port
.mctrl
&= ~TIOCM_OUT2
;
732 serial_omap_set_mctrl(&up
->port
, up
->port
.mctrl
);
733 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
736 * Disable break condition and FIFOs
738 serial_out(up
, UART_LCR
, serial_in(up
, UART_LCR
) & ~UART_LCR_SBC
);
739 serial_omap_clear_fifos(up
);
742 * Read data port to reset things, and then free the irq
744 if (serial_in(up
, UART_LSR
) & UART_LSR_DR
)
745 (void) serial_in(up
, UART_RX
);
747 pm_runtime_mark_last_busy(up
->dev
);
748 pm_runtime_put_autosuspend(up
->dev
);
749 free_irq(up
->port
.irq
, up
);
752 static void serial_omap_uart_qos_work(struct work_struct
*work
)
754 struct uart_omap_port
*up
= container_of(work
, struct uart_omap_port
,
757 pm_qos_update_request(&up
->pm_qos_request
, up
->latency
);
758 if (gpio_is_valid(up
->DTR_gpio
))
759 gpio_set_value_cansleep(up
->DTR_gpio
,
760 up
->DTR_active
!= up
->DTR_inverted
);
764 serial_omap_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
765 struct ktermios
*old
)
767 struct uart_omap_port
*up
= to_uart_omap_port(port
);
768 unsigned char cval
= 0;
769 unsigned long flags
= 0;
770 unsigned int baud
, quot
;
772 switch (termios
->c_cflag
& CSIZE
) {
774 cval
= UART_LCR_WLEN5
;
777 cval
= UART_LCR_WLEN6
;
780 cval
= UART_LCR_WLEN7
;
784 cval
= UART_LCR_WLEN8
;
788 if (termios
->c_cflag
& CSTOPB
)
789 cval
|= UART_LCR_STOP
;
790 if (termios
->c_cflag
& PARENB
)
791 cval
|= UART_LCR_PARITY
;
792 if (!(termios
->c_cflag
& PARODD
))
793 cval
|= UART_LCR_EPAR
;
794 if (termios
->c_cflag
& CMSPAR
)
795 cval
|= UART_LCR_SPAR
;
798 * Ask the core to calculate the divisor for us.
801 baud
= uart_get_baud_rate(port
, termios
, old
, 0, port
->uartclk
/13);
802 quot
= serial_omap_get_divisor(port
, baud
);
804 /* calculate wakeup latency constraint */
805 up
->calc_latency
= (USEC_PER_SEC
* up
->port
.fifosize
) / (baud
/ 8);
806 up
->latency
= up
->calc_latency
;
807 schedule_work(&up
->qos_work
);
809 up
->dll
= quot
& 0xff;
811 up
->mdr1
= UART_OMAP_MDR1_DISABLE
;
813 up
->fcr
= UART_FCR_R_TRIG_01
| UART_FCR_T_TRIG_01
|
814 UART_FCR_ENABLE_FIFO
;
817 * Ok, we're now changing the port state. Do it with
818 * interrupts disabled.
820 pm_runtime_get_sync(up
->dev
);
821 spin_lock_irqsave(&up
->port
.lock
, flags
);
824 * Update the per-port timeout.
826 uart_update_timeout(port
, termios
->c_cflag
, baud
);
828 up
->port
.read_status_mask
= UART_LSR_OE
| UART_LSR_THRE
| UART_LSR_DR
;
829 if (termios
->c_iflag
& INPCK
)
830 up
->port
.read_status_mask
|= UART_LSR_FE
| UART_LSR_PE
;
831 if (termios
->c_iflag
& (BRKINT
| PARMRK
))
832 up
->port
.read_status_mask
|= UART_LSR_BI
;
835 * Characters to ignore
837 up
->port
.ignore_status_mask
= 0;
838 if (termios
->c_iflag
& IGNPAR
)
839 up
->port
.ignore_status_mask
|= UART_LSR_PE
| UART_LSR_FE
;
840 if (termios
->c_iflag
& IGNBRK
) {
841 up
->port
.ignore_status_mask
|= UART_LSR_BI
;
843 * If we're ignoring parity and break indicators,
844 * ignore overruns too (for real raw support).
846 if (termios
->c_iflag
& IGNPAR
)
847 up
->port
.ignore_status_mask
|= UART_LSR_OE
;
851 * ignore all characters if CREAD is not set
853 if ((termios
->c_cflag
& CREAD
) == 0)
854 up
->port
.ignore_status_mask
|= UART_LSR_DR
;
857 * Modem status interrupts
859 up
->ier
&= ~UART_IER_MSI
;
860 if (UART_ENABLE_MS(&up
->port
, termios
->c_cflag
))
861 up
->ier
|= UART_IER_MSI
;
862 serial_out(up
, UART_IER
, up
->ier
);
863 serial_out(up
, UART_LCR
, cval
); /* reset DLAB */
867 /* FIFOs and DMA Settings */
869 /* FCR can be changed only when the
870 * baud clock is not running
871 * DLL_REG and DLH_REG set to 0.
873 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
874 serial_out(up
, UART_DLL
, 0);
875 serial_out(up
, UART_DLM
, 0);
876 serial_out(up
, UART_LCR
, 0);
878 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
880 up
->efr
= serial_in(up
, UART_EFR
) & ~UART_EFR_ECB
;
881 up
->efr
&= ~UART_EFR_SCD
;
882 serial_out(up
, UART_EFR
, up
->efr
| UART_EFR_ECB
);
884 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
885 up
->mcr
= serial_in(up
, UART_MCR
) & ~UART_MCR_TCRTLR
;
886 serial_out(up
, UART_MCR
, up
->mcr
| UART_MCR_TCRTLR
);
887 /* FIFO ENABLE, DMA MODE */
889 up
->scr
|= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
;
891 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
892 * sets Enables the granularity of 1 for TRIGGER RX
893 * level. Along with setting RX FIFO trigger level
894 * to 1 (as noted below, 16 characters) and TLR[3:0]
895 * to zero this will result RX FIFO threshold level
896 * to 1 character, instead of 16 as noted in comment
900 /* Set receive FIFO threshold to 16 characters and
901 * transmit FIFO threshold to 16 spaces
903 up
->fcr
&= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK
;
904 up
->fcr
&= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK
;
905 up
->fcr
|= UART_FCR6_R_TRIGGER_16
| UART_FCR6_T_TRIGGER_24
|
906 UART_FCR_ENABLE_FIFO
;
908 serial_out(up
, UART_FCR
, up
->fcr
);
909 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
911 serial_out(up
, UART_OMAP_SCR
, up
->scr
);
913 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
914 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
915 serial_out(up
, UART_MCR
, up
->mcr
);
916 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
917 serial_out(up
, UART_EFR
, up
->efr
);
918 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
920 /* Protocol, Baud Rate, and Interrupt Settings */
922 if (up
->errata
& UART_ERRATA_i202_MDR1_ACCESS
)
923 serial_omap_mdr1_errataset(up
, up
->mdr1
);
925 serial_out(up
, UART_OMAP_MDR1
, up
->mdr1
);
927 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
928 serial_out(up
, UART_EFR
, up
->efr
| UART_EFR_ECB
);
930 serial_out(up
, UART_LCR
, 0);
931 serial_out(up
, UART_IER
, 0);
932 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
934 serial_out(up
, UART_DLL
, up
->dll
); /* LS of divisor */
935 serial_out(up
, UART_DLM
, up
->dlh
); /* MS of divisor */
937 serial_out(up
, UART_LCR
, 0);
938 serial_out(up
, UART_IER
, up
->ier
);
939 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
941 serial_out(up
, UART_EFR
, up
->efr
);
942 serial_out(up
, UART_LCR
, cval
);
944 if (!serial_omap_baud_is_mode16(port
, baud
))
945 up
->mdr1
= UART_OMAP_MDR1_13X_MODE
;
947 up
->mdr1
= UART_OMAP_MDR1_16X_MODE
;
949 if (up
->errata
& UART_ERRATA_i202_MDR1_ACCESS
)
950 serial_omap_mdr1_errataset(up
, up
->mdr1
);
952 serial_out(up
, UART_OMAP_MDR1
, up
->mdr1
);
954 /* Configure flow control */
955 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
957 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
958 serial_out(up
, UART_XON1
, termios
->c_cc
[VSTART
]);
959 serial_out(up
, UART_XOFF1
, termios
->c_cc
[VSTOP
]);
961 /* Enable access to TCR/TLR */
962 serial_out(up
, UART_EFR
, up
->efr
| UART_EFR_ECB
);
963 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
964 serial_out(up
, UART_MCR
, up
->mcr
| UART_MCR_TCRTLR
);
966 serial_out(up
, UART_TI752_TCR
, OMAP_UART_TCR_TRIG
);
968 if (termios
->c_cflag
& CRTSCTS
&& up
->port
.flags
& UPF_HARD_FLOW
) {
969 /* Enable AUTORTS and AUTOCTS */
970 up
->efr
|= UART_EFR_CTS
| UART_EFR_RTS
;
972 /* Ensure MCR RTS is asserted */
973 up
->mcr
|= UART_MCR_RTS
;
975 /* Disable AUTORTS and AUTOCTS */
976 up
->efr
&= ~(UART_EFR_CTS
| UART_EFR_RTS
);
979 if (up
->port
.flags
& UPF_SOFT_FLOW
) {
980 /* clear SW control mode bits */
981 up
->efr
&= OMAP_UART_SW_CLR
;
985 * Enable XON/XOFF flow control on input.
986 * Receiver compares XON1, XOFF1.
988 if (termios
->c_iflag
& IXON
)
989 up
->efr
|= OMAP_UART_SW_RX
;
993 * Enable XON/XOFF flow control on output.
994 * Transmit XON1, XOFF1
996 if (termios
->c_iflag
& IXOFF
)
997 up
->efr
|= OMAP_UART_SW_TX
;
1001 * Enable any character to restart output.
1002 * Operation resumes after receiving any
1003 * character after recognition of the XOFF character
1005 if (termios
->c_iflag
& IXANY
)
1006 up
->mcr
|= UART_MCR_XONANY
;
1008 up
->mcr
&= ~UART_MCR_XONANY
;
1010 serial_out(up
, UART_MCR
, up
->mcr
);
1011 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
1012 serial_out(up
, UART_EFR
, up
->efr
);
1013 serial_out(up
, UART_LCR
, up
->lcr
);
1015 serial_omap_set_mctrl(&up
->port
, up
->port
.mctrl
);
1017 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
1018 pm_runtime_mark_last_busy(up
->dev
);
1019 pm_runtime_put_autosuspend(up
->dev
);
1020 dev_dbg(up
->port
.dev
, "serial_omap_set_termios+%d\n", up
->port
.line
);
1023 static int serial_omap_set_wake(struct uart_port
*port
, unsigned int state
)
1025 struct uart_omap_port
*up
= to_uart_omap_port(port
);
1027 serial_omap_enable_wakeup(up
, state
);
1033 serial_omap_pm(struct uart_port
*port
, unsigned int state
,
1034 unsigned int oldstate
)
1036 struct uart_omap_port
*up
= to_uart_omap_port(port
);
1039 dev_dbg(up
->port
.dev
, "serial_omap_pm+%d\n", up
->port
.line
);
1041 pm_runtime_get_sync(up
->dev
);
1042 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
1043 efr
= serial_in(up
, UART_EFR
);
1044 serial_out(up
, UART_EFR
, efr
| UART_EFR_ECB
);
1045 serial_out(up
, UART_LCR
, 0);
1047 serial_out(up
, UART_IER
, (state
!= 0) ? UART_IERX_SLEEP
: 0);
1048 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
);
1049 serial_out(up
, UART_EFR
, efr
);
1050 serial_out(up
, UART_LCR
, 0);
1052 if (!device_may_wakeup(up
->dev
)) {
1054 pm_runtime_forbid(up
->dev
);
1056 pm_runtime_allow(up
->dev
);
1059 pm_runtime_mark_last_busy(up
->dev
);
1060 pm_runtime_put_autosuspend(up
->dev
);
1063 static void serial_omap_release_port(struct uart_port
*port
)
1065 dev_dbg(port
->dev
, "serial_omap_release_port+\n");
1068 static int serial_omap_request_port(struct uart_port
*port
)
1070 dev_dbg(port
->dev
, "serial_omap_request_port+\n");
1074 static void serial_omap_config_port(struct uart_port
*port
, int flags
)
1076 struct uart_omap_port
*up
= to_uart_omap_port(port
);
1078 dev_dbg(up
->port
.dev
, "serial_omap_config_port+%d\n",
1080 up
->port
.type
= PORT_OMAP
;
1081 up
->port
.flags
|= UPF_SOFT_FLOW
| UPF_HARD_FLOW
;
1085 serial_omap_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
1087 /* we don't want the core code to modify any port params */
1088 dev_dbg(port
->dev
, "serial_omap_verify_port+\n");
1093 serial_omap_type(struct uart_port
*port
)
1095 struct uart_omap_port
*up
= to_uart_omap_port(port
);
1097 dev_dbg(up
->port
.dev
, "serial_omap_type+%d\n", up
->port
.line
);
1101 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1103 static inline void wait_for_xmitr(struct uart_omap_port
*up
)
1105 unsigned int status
, tmout
= 10000;
1107 /* Wait up to 10ms for the character(s) to be sent. */
1109 status
= serial_in(up
, UART_LSR
);
1111 if (status
& UART_LSR_BI
)
1112 up
->lsr_break_flag
= UART_LSR_BI
;
1117 } while ((status
& BOTH_EMPTY
) != BOTH_EMPTY
);
1119 /* Wait up to 1s for flow control if necessary */
1120 if (up
->port
.flags
& UPF_CONS_FLOW
) {
1122 for (tmout
= 1000000; tmout
; tmout
--) {
1123 unsigned int msr
= serial_in(up
, UART_MSR
);
1125 up
->msr_saved_flags
|= msr
& MSR_SAVE_FLAGS
;
1126 if (msr
& UART_MSR_CTS
)
1134 #ifdef CONFIG_CONSOLE_POLL
1136 static void serial_omap_poll_put_char(struct uart_port
*port
, unsigned char ch
)
1138 struct uart_omap_port
*up
= to_uart_omap_port(port
);
1140 pm_runtime_get_sync(up
->dev
);
1142 serial_out(up
, UART_TX
, ch
);
1143 pm_runtime_mark_last_busy(up
->dev
);
1144 pm_runtime_put_autosuspend(up
->dev
);
1147 static int serial_omap_poll_get_char(struct uart_port
*port
)
1149 struct uart_omap_port
*up
= to_uart_omap_port(port
);
1150 unsigned int status
;
1152 pm_runtime_get_sync(up
->dev
);
1153 status
= serial_in(up
, UART_LSR
);
1154 if (!(status
& UART_LSR_DR
)) {
1155 status
= NO_POLL_CHAR
;
1159 status
= serial_in(up
, UART_RX
);
1162 pm_runtime_mark_last_busy(up
->dev
);
1163 pm_runtime_put_autosuspend(up
->dev
);
1168 #endif /* CONFIG_CONSOLE_POLL */
1170 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1172 static struct uart_omap_port
*serial_omap_console_ports
[OMAP_MAX_HSUART_PORTS
];
1174 static struct uart_driver serial_omap_reg
;
1176 static void serial_omap_console_putchar(struct uart_port
*port
, int ch
)
1178 struct uart_omap_port
*up
= to_uart_omap_port(port
);
1181 serial_out(up
, UART_TX
, ch
);
1185 serial_omap_console_write(struct console
*co
, const char *s
,
1188 struct uart_omap_port
*up
= serial_omap_console_ports
[co
->index
];
1189 unsigned long flags
;
1193 pm_runtime_get_sync(up
->dev
);
1195 local_irq_save(flags
);
1198 else if (oops_in_progress
)
1199 locked
= spin_trylock(&up
->port
.lock
);
1201 spin_lock(&up
->port
.lock
);
1204 * First save the IER then disable the interrupts
1206 ier
= serial_in(up
, UART_IER
);
1207 serial_out(up
, UART_IER
, 0);
1209 uart_console_write(&up
->port
, s
, count
, serial_omap_console_putchar
);
1212 * Finally, wait for transmitter to become empty
1213 * and restore the IER
1216 serial_out(up
, UART_IER
, ier
);
1218 * The receive handling will happen properly because the
1219 * receive ready bit will still be set; it is not cleared
1220 * on read. However, modem control will not, we must
1221 * call it if we have saved something in the saved flags
1222 * while processing with interrupts off.
1224 if (up
->msr_saved_flags
)
1225 check_modem_status(up
);
1227 pm_runtime_mark_last_busy(up
->dev
);
1228 pm_runtime_put_autosuspend(up
->dev
);
1230 spin_unlock(&up
->port
.lock
);
1231 local_irq_restore(flags
);
1235 serial_omap_console_setup(struct console
*co
, char *options
)
1237 struct uart_omap_port
*up
;
1243 if (serial_omap_console_ports
[co
->index
] == NULL
)
1245 up
= serial_omap_console_ports
[co
->index
];
1248 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1250 return uart_set_options(&up
->port
, co
, baud
, parity
, bits
, flow
);
1253 static struct console serial_omap_console
= {
1254 .name
= OMAP_SERIAL_NAME
,
1255 .write
= serial_omap_console_write
,
1256 .device
= uart_console_device
,
1257 .setup
= serial_omap_console_setup
,
1258 .flags
= CON_PRINTBUFFER
,
1260 .data
= &serial_omap_reg
,
1263 static void serial_omap_add_console_port(struct uart_omap_port
*up
)
1265 serial_omap_console_ports
[up
->port
.line
] = up
;
1268 #define OMAP_CONSOLE (&serial_omap_console)
1272 #define OMAP_CONSOLE NULL
1274 static inline void serial_omap_add_console_port(struct uart_omap_port
*up
)
1279 static struct uart_ops serial_omap_pops
= {
1280 .tx_empty
= serial_omap_tx_empty
,
1281 .set_mctrl
= serial_omap_set_mctrl
,
1282 .get_mctrl
= serial_omap_get_mctrl
,
1283 .stop_tx
= serial_omap_stop_tx
,
1284 .start_tx
= serial_omap_start_tx
,
1285 .throttle
= serial_omap_throttle
,
1286 .unthrottle
= serial_omap_unthrottle
,
1287 .stop_rx
= serial_omap_stop_rx
,
1288 .enable_ms
= serial_omap_enable_ms
,
1289 .break_ctl
= serial_omap_break_ctl
,
1290 .startup
= serial_omap_startup
,
1291 .shutdown
= serial_omap_shutdown
,
1292 .set_termios
= serial_omap_set_termios
,
1293 .pm
= serial_omap_pm
,
1294 .set_wake
= serial_omap_set_wake
,
1295 .type
= serial_omap_type
,
1296 .release_port
= serial_omap_release_port
,
1297 .request_port
= serial_omap_request_port
,
1298 .config_port
= serial_omap_config_port
,
1299 .verify_port
= serial_omap_verify_port
,
1300 #ifdef CONFIG_CONSOLE_POLL
1301 .poll_put_char
= serial_omap_poll_put_char
,
1302 .poll_get_char
= serial_omap_poll_get_char
,
1306 static struct uart_driver serial_omap_reg
= {
1307 .owner
= THIS_MODULE
,
1308 .driver_name
= "OMAP-SERIAL",
1309 .dev_name
= OMAP_SERIAL_NAME
,
1310 .nr
= OMAP_MAX_HSUART_PORTS
,
1311 .cons
= OMAP_CONSOLE
,
1314 #ifdef CONFIG_PM_SLEEP
1315 static int serial_omap_suspend(struct device
*dev
)
1317 struct uart_omap_port
*up
= dev_get_drvdata(dev
);
1319 uart_suspend_port(&serial_omap_reg
, &up
->port
);
1320 flush_work(&up
->qos_work
);
1325 static int serial_omap_resume(struct device
*dev
)
1327 struct uart_omap_port
*up
= dev_get_drvdata(dev
);
1329 uart_resume_port(&serial_omap_reg
, &up
->port
);
1335 static void omap_serial_fill_features_erratas(struct uart_omap_port
*up
)
1338 u16 revision
, major
, minor
;
1340 mvr
= serial_in(up
, UART_OMAP_MVER
);
1342 /* Check revision register scheme */
1343 scheme
= mvr
>> OMAP_UART_MVR_SCHEME_SHIFT
;
1346 case 0: /* Legacy Scheme: OMAP2/3 */
1347 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1348 major
= (mvr
& OMAP_UART_LEGACY_MVR_MAJ_MASK
) >>
1349 OMAP_UART_LEGACY_MVR_MAJ_SHIFT
;
1350 minor
= (mvr
& OMAP_UART_LEGACY_MVR_MIN_MASK
);
1353 /* New Scheme: OMAP4+ */
1354 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1355 major
= (mvr
& OMAP_UART_MVR_MAJ_MASK
) >>
1356 OMAP_UART_MVR_MAJ_SHIFT
;
1357 minor
= (mvr
& OMAP_UART_MVR_MIN_MASK
);
1361 "Unknown %s revision, defaulting to highest\n",
1363 /* highest possible revision */
1368 /* normalize revision for the driver */
1369 revision
= UART_BUILD_REVISION(major
, minor
);
1372 case OMAP_UART_REV_46
:
1373 up
->errata
|= (UART_ERRATA_i202_MDR1_ACCESS
|
1374 UART_ERRATA_i291_DMA_FORCEIDLE
);
1376 case OMAP_UART_REV_52
:
1377 up
->errata
|= (UART_ERRATA_i202_MDR1_ACCESS
|
1378 UART_ERRATA_i291_DMA_FORCEIDLE
);
1380 case OMAP_UART_REV_63
:
1381 up
->errata
|= UART_ERRATA_i202_MDR1_ACCESS
;
1388 static struct omap_uart_port_info
*of_get_uart_port_info(struct device
*dev
)
1390 struct omap_uart_port_info
*omap_up_info
;
1392 omap_up_info
= devm_kzalloc(dev
, sizeof(*omap_up_info
), GFP_KERNEL
);
1394 return NULL
; /* out of memory */
1396 of_property_read_u32(dev
->of_node
, "clock-frequency",
1397 &omap_up_info
->uartclk
);
1398 return omap_up_info
;
1401 static int serial_omap_probe(struct platform_device
*pdev
)
1403 struct uart_omap_port
*up
;
1404 struct resource
*mem
, *irq
;
1405 struct omap_uart_port_info
*omap_up_info
= pdev
->dev
.platform_data
;
1408 if (pdev
->dev
.of_node
)
1409 omap_up_info
= of_get_uart_port_info(&pdev
->dev
);
1411 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1413 dev_err(&pdev
->dev
, "no mem resource?\n");
1417 irq
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1419 dev_err(&pdev
->dev
, "no irq resource?\n");
1423 if (!devm_request_mem_region(&pdev
->dev
, mem
->start
, resource_size(mem
),
1424 pdev
->dev
.driver
->name
)) {
1425 dev_err(&pdev
->dev
, "memory region already claimed\n");
1429 if (gpio_is_valid(omap_up_info
->DTR_gpio
) &&
1430 omap_up_info
->DTR_present
) {
1431 ret
= gpio_request(omap_up_info
->DTR_gpio
, "omap-serial");
1434 ret
= gpio_direction_output(omap_up_info
->DTR_gpio
,
1435 omap_up_info
->DTR_inverted
);
1440 up
= devm_kzalloc(&pdev
->dev
, sizeof(*up
), GFP_KERNEL
);
1444 if (gpio_is_valid(omap_up_info
->DTR_gpio
) &&
1445 omap_up_info
->DTR_present
) {
1446 up
->DTR_gpio
= omap_up_info
->DTR_gpio
;
1447 up
->DTR_inverted
= omap_up_info
->DTR_inverted
;
1449 up
->DTR_gpio
= -EINVAL
;
1452 up
->dev
= &pdev
->dev
;
1453 up
->port
.dev
= &pdev
->dev
;
1454 up
->port
.type
= PORT_OMAP
;
1455 up
->port
.iotype
= UPIO_MEM
;
1456 up
->port
.irq
= irq
->start
;
1458 up
->port
.regshift
= 2;
1459 up
->port
.fifosize
= 64;
1460 up
->port
.ops
= &serial_omap_pops
;
1462 if (pdev
->dev
.of_node
)
1463 up
->port
.line
= of_alias_get_id(pdev
->dev
.of_node
, "serial");
1465 up
->port
.line
= pdev
->id
;
1467 if (up
->port
.line
< 0) {
1468 dev_err(&pdev
->dev
, "failed to get alias/pdev id, errno %d\n",
1474 up
->pins
= devm_pinctrl_get_select_default(&pdev
->dev
);
1475 if (IS_ERR(up
->pins
)) {
1476 dev_warn(&pdev
->dev
, "did not get pins for uart%i error: %li\n",
1477 up
->port
.line
, PTR_ERR(up
->pins
));
1481 sprintf(up
->name
, "OMAP UART%d", up
->port
.line
);
1482 up
->port
.mapbase
= mem
->start
;
1483 up
->port
.membase
= devm_ioremap(&pdev
->dev
, mem
->start
,
1484 resource_size(mem
));
1485 if (!up
->port
.membase
) {
1486 dev_err(&pdev
->dev
, "can't ioremap UART\n");
1491 up
->port
.flags
= omap_up_info
->flags
;
1492 up
->port
.uartclk
= omap_up_info
->uartclk
;
1493 if (!up
->port
.uartclk
) {
1494 up
->port
.uartclk
= DEFAULT_CLK_SPEED
;
1495 dev_warn(&pdev
->dev
, "No clock speed specified: using default:"
1496 "%d\n", DEFAULT_CLK_SPEED
);
1499 up
->latency
= PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE
;
1500 up
->calc_latency
= PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE
;
1501 pm_qos_add_request(&up
->pm_qos_request
,
1502 PM_QOS_CPU_DMA_LATENCY
, up
->latency
);
1503 serial_omap_uart_wq
= create_singlethread_workqueue(up
->name
);
1504 INIT_WORK(&up
->qos_work
, serial_omap_uart_qos_work
);
1506 platform_set_drvdata(pdev
, up
);
1507 pm_runtime_enable(&pdev
->dev
);
1508 pm_runtime_use_autosuspend(&pdev
->dev
);
1509 pm_runtime_set_autosuspend_delay(&pdev
->dev
,
1510 omap_up_info
->autosuspend_timeout
);
1512 pm_runtime_irq_safe(&pdev
->dev
);
1513 pm_runtime_get_sync(&pdev
->dev
);
1515 omap_serial_fill_features_erratas(up
);
1517 ui
[up
->port
.line
] = up
;
1518 serial_omap_add_console_port(up
);
1520 ret
= uart_add_one_port(&serial_omap_reg
, &up
->port
);
1524 pm_runtime_mark_last_busy(up
->dev
);
1525 pm_runtime_put_autosuspend(up
->dev
);
1529 pm_runtime_put(&pdev
->dev
);
1530 pm_runtime_disable(&pdev
->dev
);
1533 dev_err(&pdev
->dev
, "[UART%d]: failure [%s]: %d\n",
1534 pdev
->id
, __func__
, ret
);
1538 static int serial_omap_remove(struct platform_device
*dev
)
1540 struct uart_omap_port
*up
= platform_get_drvdata(dev
);
1542 pm_runtime_put_sync(up
->dev
);
1543 pm_runtime_disable(up
->dev
);
1544 uart_remove_one_port(&serial_omap_reg
, &up
->port
);
1545 pm_qos_remove_request(&up
->pm_qos_request
);
1551 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1552 * The access to uart register after MDR1 Access
1553 * causes UART to corrupt data.
1556 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1557 * give 10 times as much
1559 static void serial_omap_mdr1_errataset(struct uart_omap_port
*up
, u8 mdr1
)
1563 serial_out(up
, UART_OMAP_MDR1
, mdr1
);
1565 serial_out(up
, UART_FCR
, up
->fcr
| UART_FCR_CLEAR_XMIT
|
1566 UART_FCR_CLEAR_RCVR
);
1568 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1569 * TX_FIFO_E bit is 1.
1571 while (UART_LSR_THRE
!= (serial_in(up
, UART_LSR
) &
1572 (UART_LSR_THRE
| UART_LSR_DR
))) {
1575 /* Should *never* happen. we warn and carry on */
1576 dev_crit(up
->dev
, "Errata i202: timedout %x\n",
1577 serial_in(up
, UART_LSR
));
1584 #ifdef CONFIG_PM_RUNTIME
1585 static void serial_omap_restore_context(struct uart_omap_port
*up
)
1587 if (up
->errata
& UART_ERRATA_i202_MDR1_ACCESS
)
1588 serial_omap_mdr1_errataset(up
, UART_OMAP_MDR1_DISABLE
);
1590 serial_out(up
, UART_OMAP_MDR1
, UART_OMAP_MDR1_DISABLE
);
1592 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
); /* Config B mode */
1593 serial_out(up
, UART_EFR
, UART_EFR_ECB
);
1594 serial_out(up
, UART_LCR
, 0x0); /* Operational mode */
1595 serial_out(up
, UART_IER
, 0x0);
1596 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
); /* Config B mode */
1597 serial_out(up
, UART_DLL
, up
->dll
);
1598 serial_out(up
, UART_DLM
, up
->dlh
);
1599 serial_out(up
, UART_LCR
, 0x0); /* Operational mode */
1600 serial_out(up
, UART_IER
, up
->ier
);
1601 serial_out(up
, UART_FCR
, up
->fcr
);
1602 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_A
);
1603 serial_out(up
, UART_MCR
, up
->mcr
);
1604 serial_out(up
, UART_LCR
, UART_LCR_CONF_MODE_B
); /* Config B mode */
1605 serial_out(up
, UART_OMAP_SCR
, up
->scr
);
1606 serial_out(up
, UART_EFR
, up
->efr
);
1607 serial_out(up
, UART_LCR
, up
->lcr
);
1608 if (up
->errata
& UART_ERRATA_i202_MDR1_ACCESS
)
1609 serial_omap_mdr1_errataset(up
, up
->mdr1
);
1611 serial_out(up
, UART_OMAP_MDR1
, up
->mdr1
);
1614 static int serial_omap_runtime_suspend(struct device
*dev
)
1616 struct uart_omap_port
*up
= dev_get_drvdata(dev
);
1617 struct omap_uart_port_info
*pdata
= dev
->platform_data
;
1625 up
->context_loss_cnt
= serial_omap_get_context_loss_count(up
);
1627 if (device_may_wakeup(dev
)) {
1628 if (!up
->wakeups_enabled
) {
1629 serial_omap_enable_wakeup(up
, true);
1630 up
->wakeups_enabled
= true;
1633 if (up
->wakeups_enabled
) {
1634 serial_omap_enable_wakeup(up
, false);
1635 up
->wakeups_enabled
= false;
1639 up
->latency
= PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE
;
1640 schedule_work(&up
->qos_work
);
1645 static int serial_omap_runtime_resume(struct device
*dev
)
1647 struct uart_omap_port
*up
= dev_get_drvdata(dev
);
1649 int loss_cnt
= serial_omap_get_context_loss_count(up
);
1652 dev_err(dev
, "serial_omap_get_context_loss_count failed : %d\n",
1654 serial_omap_restore_context(up
);
1655 } else if (up
->context_loss_cnt
!= loss_cnt
) {
1656 serial_omap_restore_context(up
);
1658 up
->latency
= up
->calc_latency
;
1659 schedule_work(&up
->qos_work
);
1665 static const struct dev_pm_ops serial_omap_dev_pm_ops
= {
1666 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend
, serial_omap_resume
)
1667 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend
,
1668 serial_omap_runtime_resume
, NULL
)
1671 #if defined(CONFIG_OF)
1672 static const struct of_device_id omap_serial_of_match
[] = {
1673 { .compatible
= "ti,omap2-uart" },
1674 { .compatible
= "ti,omap3-uart" },
1675 { .compatible
= "ti,omap4-uart" },
1678 MODULE_DEVICE_TABLE(of
, omap_serial_of_match
);
1681 static struct platform_driver serial_omap_driver
= {
1682 .probe
= serial_omap_probe
,
1683 .remove
= serial_omap_remove
,
1685 .name
= DRIVER_NAME
,
1686 .pm
= &serial_omap_dev_pm_ops
,
1687 .of_match_table
= of_match_ptr(omap_serial_of_match
),
1691 static int __init
serial_omap_init(void)
1695 ret
= uart_register_driver(&serial_omap_reg
);
1698 ret
= platform_driver_register(&serial_omap_driver
);
1700 uart_unregister_driver(&serial_omap_reg
);
1704 static void __exit
serial_omap_exit(void)
1706 platform_driver_unregister(&serial_omap_driver
);
1707 uart_unregister_driver(&serial_omap_reg
);
1710 module_init(serial_omap_init
);
1711 module_exit(serial_omap_exit
);
1713 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1714 MODULE_LICENSE("GPL");
1715 MODULE_AUTHOR("Texas Instruments Inc");