2 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
4 * FIXME According to the usermanual the status bits in the status register
5 * are only updated when the peripherals access the FIFO and not when the
6 * CPU access them. So since we use this bits to know when we stop writing
7 * and reading, they may not be updated in-time and a race condition may
8 * exists. But I haven't be able to prove this and I don't care. But if
9 * any problem arises, it might worth checking. The TX/RX FIFO Stats
10 * registers should be used in addition.
11 * Update: Actually, they seem updated ... At least the bits we use.
14 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
16 * Some of the code has been inspired/copied from the 2.4 code written
17 * by Dale Farnsworth <dfarnsworth@mvista.com>.
19 * Copyright (C) 2008 Freescale Semiconductor Inc.
20 * John Rigby <jrigby@gmail.com>
21 * Added support for MPC5121
22 * Copyright (C) 2006 Secret Lab Technologies Ltd.
23 * Grant Likely <grant.likely@secretlab.ca>
24 * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com>
25 * Copyright (C) 2003 MontaVista, Software, Inc.
27 * This file is licensed under the terms of the GNU General Public License
28 * version 2. This program is licensed "as is" without any warranty of any
29 * kind, whether express or implied.
34 #include <linux/device.h>
35 #include <linux/module.h>
36 #include <linux/tty.h>
37 #include <linux/tty_flip.h>
38 #include <linux/serial.h>
39 #include <linux/sysrq.h>
40 #include <linux/console.h>
41 #include <linux/delay.h>
44 #include <linux/of_platform.h>
45 #include <linux/clk.h>
47 #include <asm/mpc52xx.h>
48 #include <asm/mpc52xx_psc.h>
50 #if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
54 #include <linux/serial_core.h>
57 /* We've been assigned a range on the "Low-density serial ports" major */
58 #define SERIAL_PSC_MAJOR 204
59 #define SERIAL_PSC_MINOR 148
62 #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */
65 static struct uart_port mpc52xx_uart_ports
[MPC52xx_PSC_MAXNUM
];
66 /* Rem: - We use the read_status_mask as a shadow of
67 * psc->mpc52xx_psc_imr
68 * - It's important that is array is all zero on start as we
69 * use it to know if it's initialized or not ! If it's not sure
70 * it's cleared, then a memset(...,0,...) should be added to
74 /* lookup table for matching device nodes to index numbers */
75 static struct device_node
*mpc52xx_uart_nodes
[MPC52xx_PSC_MAXNUM
];
77 static void mpc52xx_uart_of_enumerate(void);
80 #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
83 /* Forward declaration of the interruption handling routine */
84 static irqreturn_t
mpc52xx_uart_int(int irq
, void *dev_id
);
85 static irqreturn_t
mpc5xxx_uart_process_int(struct uart_port
*port
);
88 /* Simple macro to test if a port is console or not. This one is taken
89 * for serial_core.c and maybe should be moved to serial_core.h ? */
90 #ifdef CONFIG_SERIAL_CORE_CONSOLE
91 #define uart_console(port) \
92 ((port)->cons && (port)->cons->index == (port)->line)
94 #define uart_console(port) (0)
97 /* ======================================================================== */
98 /* PSC fifo operations for isolating differences between 52xx and 512x */
99 /* ======================================================================== */
102 void (*fifo_init
)(struct uart_port
*port
);
103 int (*raw_rx_rdy
)(struct uart_port
*port
);
104 int (*raw_tx_rdy
)(struct uart_port
*port
);
105 int (*rx_rdy
)(struct uart_port
*port
);
106 int (*tx_rdy
)(struct uart_port
*port
);
107 int (*tx_empty
)(struct uart_port
*port
);
108 void (*stop_rx
)(struct uart_port
*port
);
109 void (*start_tx
)(struct uart_port
*port
);
110 void (*stop_tx
)(struct uart_port
*port
);
111 void (*rx_clr_irq
)(struct uart_port
*port
);
112 void (*tx_clr_irq
)(struct uart_port
*port
);
113 void (*write_char
)(struct uart_port
*port
, unsigned char c
);
114 unsigned char (*read_char
)(struct uart_port
*port
);
115 void (*cw_disable_ints
)(struct uart_port
*port
);
116 void (*cw_restore_ints
)(struct uart_port
*port
);
117 unsigned int (*set_baudrate
)(struct uart_port
*port
,
118 struct ktermios
*new,
119 struct ktermios
*old
);
120 int (*clock
)(struct uart_port
*port
, int enable
);
121 int (*fifoc_init
)(void);
122 void (*fifoc_uninit
)(void);
123 void (*get_irq
)(struct uart_port
*, struct device_node
*);
124 irqreturn_t (*handle_irq
)(struct uart_port
*port
);
127 /* setting the prescaler and divisor reg is common for all chips */
128 static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem
*psc
,
129 u16 prescaler
, unsigned int divisor
)
131 /* select prescaler */
132 out_be16(&psc
->mpc52xx_psc_clock_select
, prescaler
);
133 out_8(&psc
->ctur
, divisor
>> 8);
134 out_8(&psc
->ctlr
, divisor
& 0xff);
137 #ifdef CONFIG_PPC_MPC52xx
138 #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
139 static void mpc52xx_psc_fifo_init(struct uart_port
*port
)
141 struct mpc52xx_psc __iomem
*psc
= PSC(port
);
142 struct mpc52xx_psc_fifo __iomem
*fifo
= FIFO_52xx(port
);
144 out_8(&fifo
->rfcntl
, 0x00);
145 out_be16(&fifo
->rfalarm
, 0x1ff);
146 out_8(&fifo
->tfcntl
, 0x07);
147 out_be16(&fifo
->tfalarm
, 0x80);
149 port
->read_status_mask
|= MPC52xx_PSC_IMR_RXRDY
| MPC52xx_PSC_IMR_TXRDY
;
150 out_be16(&psc
->mpc52xx_psc_imr
, port
->read_status_mask
);
153 static int mpc52xx_psc_raw_rx_rdy(struct uart_port
*port
)
155 return in_be16(&PSC(port
)->mpc52xx_psc_status
)
156 & MPC52xx_PSC_SR_RXRDY
;
159 static int mpc52xx_psc_raw_tx_rdy(struct uart_port
*port
)
161 return in_be16(&PSC(port
)->mpc52xx_psc_status
)
162 & MPC52xx_PSC_SR_TXRDY
;
166 static int mpc52xx_psc_rx_rdy(struct uart_port
*port
)
168 return in_be16(&PSC(port
)->mpc52xx_psc_isr
)
169 & port
->read_status_mask
170 & MPC52xx_PSC_IMR_RXRDY
;
173 static int mpc52xx_psc_tx_rdy(struct uart_port
*port
)
175 return in_be16(&PSC(port
)->mpc52xx_psc_isr
)
176 & port
->read_status_mask
177 & MPC52xx_PSC_IMR_TXRDY
;
180 static int mpc52xx_psc_tx_empty(struct uart_port
*port
)
182 return in_be16(&PSC(port
)->mpc52xx_psc_status
)
183 & MPC52xx_PSC_SR_TXEMP
;
186 static void mpc52xx_psc_start_tx(struct uart_port
*port
)
188 port
->read_status_mask
|= MPC52xx_PSC_IMR_TXRDY
;
189 out_be16(&PSC(port
)->mpc52xx_psc_imr
, port
->read_status_mask
);
192 static void mpc52xx_psc_stop_tx(struct uart_port
*port
)
194 port
->read_status_mask
&= ~MPC52xx_PSC_IMR_TXRDY
;
195 out_be16(&PSC(port
)->mpc52xx_psc_imr
, port
->read_status_mask
);
198 static void mpc52xx_psc_stop_rx(struct uart_port
*port
)
200 port
->read_status_mask
&= ~MPC52xx_PSC_IMR_RXRDY
;
201 out_be16(&PSC(port
)->mpc52xx_psc_imr
, port
->read_status_mask
);
204 static void mpc52xx_psc_rx_clr_irq(struct uart_port
*port
)
208 static void mpc52xx_psc_tx_clr_irq(struct uart_port
*port
)
212 static void mpc52xx_psc_write_char(struct uart_port
*port
, unsigned char c
)
214 out_8(&PSC(port
)->mpc52xx_psc_buffer_8
, c
);
217 static unsigned char mpc52xx_psc_read_char(struct uart_port
*port
)
219 return in_8(&PSC(port
)->mpc52xx_psc_buffer_8
);
222 static void mpc52xx_psc_cw_disable_ints(struct uart_port
*port
)
224 out_be16(&PSC(port
)->mpc52xx_psc_imr
, 0);
227 static void mpc52xx_psc_cw_restore_ints(struct uart_port
*port
)
229 out_be16(&PSC(port
)->mpc52xx_psc_imr
, port
->read_status_mask
);
232 static unsigned int mpc5200_psc_set_baudrate(struct uart_port
*port
,
233 struct ktermios
*new,
234 struct ktermios
*old
)
237 unsigned int divisor
;
239 /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */
240 baud
= uart_get_baud_rate(port
, new, old
,
241 port
->uartclk
/ (32 * 0xffff) + 1,
243 divisor
= (port
->uartclk
+ 16 * baud
) / (32 * baud
);
245 /* enable the /32 prescaler and set the divisor */
246 mpc52xx_set_divisor(PSC(port
), 0xdd00, divisor
);
250 static unsigned int mpc5200b_psc_set_baudrate(struct uart_port
*port
,
251 struct ktermios
*new,
252 struct ktermios
*old
)
255 unsigned int divisor
;
258 /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the
260 baud
= uart_get_baud_rate(port
, new, old
,
261 port
->uartclk
/ (32 * 0xffff) + 1,
263 divisor
= (port
->uartclk
+ 2 * baud
) / (4 * baud
);
265 /* select the proper prescaler and set the divisor
266 * prefer high prescaler for more tolerance on low baudrates */
267 if (divisor
> 0xffff || baud
<= 115200) {
268 divisor
= (divisor
+ 4) / 8;
269 prescaler
= 0xdd00; /* /32 */
271 prescaler
= 0xff00; /* /4 */
272 mpc52xx_set_divisor(PSC(port
), prescaler
, divisor
);
276 static void mpc52xx_psc_get_irq(struct uart_port
*port
, struct device_node
*np
)
279 port
->irq
= irq_of_parse_and_map(np
, 0);
282 /* 52xx specific interrupt handler. The caller holds the port lock */
283 static irqreturn_t
mpc52xx_psc_handle_irq(struct uart_port
*port
)
285 return mpc5xxx_uart_process_int(port
);
288 static struct psc_ops mpc52xx_psc_ops
= {
289 .fifo_init
= mpc52xx_psc_fifo_init
,
290 .raw_rx_rdy
= mpc52xx_psc_raw_rx_rdy
,
291 .raw_tx_rdy
= mpc52xx_psc_raw_tx_rdy
,
292 .rx_rdy
= mpc52xx_psc_rx_rdy
,
293 .tx_rdy
= mpc52xx_psc_tx_rdy
,
294 .tx_empty
= mpc52xx_psc_tx_empty
,
295 .stop_rx
= mpc52xx_psc_stop_rx
,
296 .start_tx
= mpc52xx_psc_start_tx
,
297 .stop_tx
= mpc52xx_psc_stop_tx
,
298 .rx_clr_irq
= mpc52xx_psc_rx_clr_irq
,
299 .tx_clr_irq
= mpc52xx_psc_tx_clr_irq
,
300 .write_char
= mpc52xx_psc_write_char
,
301 .read_char
= mpc52xx_psc_read_char
,
302 .cw_disable_ints
= mpc52xx_psc_cw_disable_ints
,
303 .cw_restore_ints
= mpc52xx_psc_cw_restore_ints
,
304 .set_baudrate
= mpc5200_psc_set_baudrate
,
305 .get_irq
= mpc52xx_psc_get_irq
,
306 .handle_irq
= mpc52xx_psc_handle_irq
,
309 static struct psc_ops mpc5200b_psc_ops
= {
310 .fifo_init
= mpc52xx_psc_fifo_init
,
311 .raw_rx_rdy
= mpc52xx_psc_raw_rx_rdy
,
312 .raw_tx_rdy
= mpc52xx_psc_raw_tx_rdy
,
313 .rx_rdy
= mpc52xx_psc_rx_rdy
,
314 .tx_rdy
= mpc52xx_psc_tx_rdy
,
315 .tx_empty
= mpc52xx_psc_tx_empty
,
316 .stop_rx
= mpc52xx_psc_stop_rx
,
317 .start_tx
= mpc52xx_psc_start_tx
,
318 .stop_tx
= mpc52xx_psc_stop_tx
,
319 .rx_clr_irq
= mpc52xx_psc_rx_clr_irq
,
320 .tx_clr_irq
= mpc52xx_psc_tx_clr_irq
,
321 .write_char
= mpc52xx_psc_write_char
,
322 .read_char
= mpc52xx_psc_read_char
,
323 .cw_disable_ints
= mpc52xx_psc_cw_disable_ints
,
324 .cw_restore_ints
= mpc52xx_psc_cw_restore_ints
,
325 .set_baudrate
= mpc5200b_psc_set_baudrate
,
326 .get_irq
= mpc52xx_psc_get_irq
,
327 .handle_irq
= mpc52xx_psc_handle_irq
,
330 #endif /* CONFIG_MPC52xx */
332 #ifdef CONFIG_PPC_MPC512x
333 #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
335 /* PSC FIFO Controller for mpc512x */
344 static struct psc_fifoc __iomem
*psc_fifoc
;
345 static unsigned int psc_fifoc_irq
;
347 static void mpc512x_psc_fifo_init(struct uart_port
*port
)
350 out_be16(&PSC(port
)->mpc52xx_psc_clock_select
, 0xdd00);
352 out_be32(&FIFO_512x(port
)->txcmd
, MPC512x_PSC_FIFO_RESET_SLICE
);
353 out_be32(&FIFO_512x(port
)->txcmd
, MPC512x_PSC_FIFO_ENABLE_SLICE
);
354 out_be32(&FIFO_512x(port
)->txalarm
, 1);
355 out_be32(&FIFO_512x(port
)->tximr
, 0);
357 out_be32(&FIFO_512x(port
)->rxcmd
, MPC512x_PSC_FIFO_RESET_SLICE
);
358 out_be32(&FIFO_512x(port
)->rxcmd
, MPC512x_PSC_FIFO_ENABLE_SLICE
);
359 out_be32(&FIFO_512x(port
)->rxalarm
, 1);
360 out_be32(&FIFO_512x(port
)->rximr
, 0);
362 out_be32(&FIFO_512x(port
)->tximr
, MPC512x_PSC_FIFO_ALARM
);
363 out_be32(&FIFO_512x(port
)->rximr
, MPC512x_PSC_FIFO_ALARM
);
366 static int mpc512x_psc_raw_rx_rdy(struct uart_port
*port
)
368 return !(in_be32(&FIFO_512x(port
)->rxsr
) & MPC512x_PSC_FIFO_EMPTY
);
371 static int mpc512x_psc_raw_tx_rdy(struct uart_port
*port
)
373 return !(in_be32(&FIFO_512x(port
)->txsr
) & MPC512x_PSC_FIFO_FULL
);
376 static int mpc512x_psc_rx_rdy(struct uart_port
*port
)
378 return in_be32(&FIFO_512x(port
)->rxsr
)
379 & in_be32(&FIFO_512x(port
)->rximr
)
380 & MPC512x_PSC_FIFO_ALARM
;
383 static int mpc512x_psc_tx_rdy(struct uart_port
*port
)
385 return in_be32(&FIFO_512x(port
)->txsr
)
386 & in_be32(&FIFO_512x(port
)->tximr
)
387 & MPC512x_PSC_FIFO_ALARM
;
390 static int mpc512x_psc_tx_empty(struct uart_port
*port
)
392 return in_be32(&FIFO_512x(port
)->txsr
)
393 & MPC512x_PSC_FIFO_EMPTY
;
396 static void mpc512x_psc_stop_rx(struct uart_port
*port
)
398 unsigned long rx_fifo_imr
;
400 rx_fifo_imr
= in_be32(&FIFO_512x(port
)->rximr
);
401 rx_fifo_imr
&= ~MPC512x_PSC_FIFO_ALARM
;
402 out_be32(&FIFO_512x(port
)->rximr
, rx_fifo_imr
);
405 static void mpc512x_psc_start_tx(struct uart_port
*port
)
407 unsigned long tx_fifo_imr
;
409 tx_fifo_imr
= in_be32(&FIFO_512x(port
)->tximr
);
410 tx_fifo_imr
|= MPC512x_PSC_FIFO_ALARM
;
411 out_be32(&FIFO_512x(port
)->tximr
, tx_fifo_imr
);
414 static void mpc512x_psc_stop_tx(struct uart_port
*port
)
416 unsigned long tx_fifo_imr
;
418 tx_fifo_imr
= in_be32(&FIFO_512x(port
)->tximr
);
419 tx_fifo_imr
&= ~MPC512x_PSC_FIFO_ALARM
;
420 out_be32(&FIFO_512x(port
)->tximr
, tx_fifo_imr
);
423 static void mpc512x_psc_rx_clr_irq(struct uart_port
*port
)
425 out_be32(&FIFO_512x(port
)->rxisr
, in_be32(&FIFO_512x(port
)->rxisr
));
428 static void mpc512x_psc_tx_clr_irq(struct uart_port
*port
)
430 out_be32(&FIFO_512x(port
)->txisr
, in_be32(&FIFO_512x(port
)->txisr
));
433 static void mpc512x_psc_write_char(struct uart_port
*port
, unsigned char c
)
435 out_8(&FIFO_512x(port
)->txdata_8
, c
);
438 static unsigned char mpc512x_psc_read_char(struct uart_port
*port
)
440 return in_8(&FIFO_512x(port
)->rxdata_8
);
443 static void mpc512x_psc_cw_disable_ints(struct uart_port
*port
)
445 port
->read_status_mask
=
446 in_be32(&FIFO_512x(port
)->tximr
) << 16 |
447 in_be32(&FIFO_512x(port
)->rximr
);
448 out_be32(&FIFO_512x(port
)->tximr
, 0);
449 out_be32(&FIFO_512x(port
)->rximr
, 0);
452 static void mpc512x_psc_cw_restore_ints(struct uart_port
*port
)
454 out_be32(&FIFO_512x(port
)->tximr
,
455 (port
->read_status_mask
>> 16) & 0x7f);
456 out_be32(&FIFO_512x(port
)->rximr
, port
->read_status_mask
& 0x7f);
459 static unsigned int mpc512x_psc_set_baudrate(struct uart_port
*port
,
460 struct ktermios
*new,
461 struct ktermios
*old
)
464 unsigned int divisor
;
467 * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on
468 * pg. 30-10 that the chip supports a /32 and a /10 prescaler.
469 * Furthermore, it states that "After reset, the prescaler by 10
470 * for the UART mode is selected", but the reset register value is
471 * 0x0000 which means a /32 prescaler. This is wrong.
473 * In reality using /32 prescaler doesn't work, as it is not supported!
474 * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide",
475 * Chapter 4.1 PSC in UART Mode.
476 * Calculate with a /16 prescaler here.
479 /* uartclk contains the ips freq */
480 baud
= uart_get_baud_rate(port
, new, old
,
481 port
->uartclk
/ (16 * 0xffff) + 1,
483 divisor
= (port
->uartclk
+ 8 * baud
) / (16 * baud
);
485 /* enable the /16 prescaler and set the divisor */
486 mpc52xx_set_divisor(PSC(port
), 0xdd00, divisor
);
490 /* Init PSC FIFO Controller */
491 static int __init
mpc512x_psc_fifoc_init(void)
493 struct device_node
*np
;
495 np
= of_find_compatible_node(NULL
, NULL
,
496 "fsl,mpc5121-psc-fifo");
498 pr_err("%s: Can't find FIFOC node\n", __func__
);
502 psc_fifoc
= of_iomap(np
, 0);
504 pr_err("%s: Can't map FIFOC\n", __func__
);
509 psc_fifoc_irq
= irq_of_parse_and_map(np
, 0);
511 if (psc_fifoc_irq
== 0) {
512 pr_err("%s: Can't get FIFOC irq\n", __func__
);
520 static void __exit
mpc512x_psc_fifoc_uninit(void)
525 /* 512x specific interrupt handler. The caller holds the port lock */
526 static irqreturn_t
mpc512x_psc_handle_irq(struct uart_port
*port
)
528 unsigned long fifoc_int
;
531 /* Read pending PSC FIFOC interrupts */
532 fifoc_int
= in_be32(&psc_fifoc
->fifoc_int
);
534 /* Check if it is an interrupt for this port */
535 psc_num
= (port
->mapbase
& 0xf00) >> 8;
536 if (test_bit(psc_num
, &fifoc_int
) ||
537 test_bit(psc_num
+ 16, &fifoc_int
))
538 return mpc5xxx_uart_process_int(port
);
543 static int mpc512x_psc_clock(struct uart_port
*port
, int enable
)
549 if (uart_console(port
))
552 psc_num
= (port
->mapbase
& 0xf00) >> 8;
553 snprintf(clk_name
, sizeof(clk_name
), "psc%d_mclk", psc_num
);
554 psc_clk
= clk_get(port
->dev
, clk_name
);
555 if (IS_ERR(psc_clk
)) {
556 dev_err(port
->dev
, "Failed to get PSC clock entry!\n");
560 dev_dbg(port
->dev
, "%s %sable\n", clk_name
, enable
? "en" : "dis");
565 clk_disable(psc_clk
);
570 static void mpc512x_psc_get_irq(struct uart_port
*port
, struct device_node
*np
)
572 port
->irqflags
= IRQF_SHARED
;
573 port
->irq
= psc_fifoc_irq
;
576 static struct psc_ops mpc512x_psc_ops
= {
577 .fifo_init
= mpc512x_psc_fifo_init
,
578 .raw_rx_rdy
= mpc512x_psc_raw_rx_rdy
,
579 .raw_tx_rdy
= mpc512x_psc_raw_tx_rdy
,
580 .rx_rdy
= mpc512x_psc_rx_rdy
,
581 .tx_rdy
= mpc512x_psc_tx_rdy
,
582 .tx_empty
= mpc512x_psc_tx_empty
,
583 .stop_rx
= mpc512x_psc_stop_rx
,
584 .start_tx
= mpc512x_psc_start_tx
,
585 .stop_tx
= mpc512x_psc_stop_tx
,
586 .rx_clr_irq
= mpc512x_psc_rx_clr_irq
,
587 .tx_clr_irq
= mpc512x_psc_tx_clr_irq
,
588 .write_char
= mpc512x_psc_write_char
,
589 .read_char
= mpc512x_psc_read_char
,
590 .cw_disable_ints
= mpc512x_psc_cw_disable_ints
,
591 .cw_restore_ints
= mpc512x_psc_cw_restore_ints
,
592 .set_baudrate
= mpc512x_psc_set_baudrate
,
593 .clock
= mpc512x_psc_clock
,
594 .fifoc_init
= mpc512x_psc_fifoc_init
,
595 .fifoc_uninit
= mpc512x_psc_fifoc_uninit
,
596 .get_irq
= mpc512x_psc_get_irq
,
597 .handle_irq
= mpc512x_psc_handle_irq
,
601 static const struct psc_ops
*psc_ops
;
603 /* ======================================================================== */
604 /* UART operations */
605 /* ======================================================================== */
608 mpc52xx_uart_tx_empty(struct uart_port
*port
)
610 return psc_ops
->tx_empty(port
) ? TIOCSER_TEMT
: 0;
614 mpc52xx_uart_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
616 if (mctrl
& TIOCM_RTS
)
617 out_8(&PSC(port
)->op1
, MPC52xx_PSC_OP_RTS
);
619 out_8(&PSC(port
)->op0
, MPC52xx_PSC_OP_RTS
);
623 mpc52xx_uart_get_mctrl(struct uart_port
*port
)
625 unsigned int ret
= TIOCM_DSR
;
626 u8 status
= in_8(&PSC(port
)->mpc52xx_psc_ipcr
);
628 if (!(status
& MPC52xx_PSC_CTS
))
630 if (!(status
& MPC52xx_PSC_DCD
))
637 mpc52xx_uart_stop_tx(struct uart_port
*port
)
639 /* port->lock taken by caller */
640 psc_ops
->stop_tx(port
);
644 mpc52xx_uart_start_tx(struct uart_port
*port
)
646 /* port->lock taken by caller */
647 psc_ops
->start_tx(port
);
651 mpc52xx_uart_send_xchar(struct uart_port
*port
, char ch
)
654 spin_lock_irqsave(&port
->lock
, flags
);
658 /* Make sure tx interrupts are on */
659 /* Truly necessary ??? They should be anyway */
660 psc_ops
->start_tx(port
);
663 spin_unlock_irqrestore(&port
->lock
, flags
);
667 mpc52xx_uart_stop_rx(struct uart_port
*port
)
669 /* port->lock taken by caller */
670 psc_ops
->stop_rx(port
);
674 mpc52xx_uart_enable_ms(struct uart_port
*port
)
676 struct mpc52xx_psc __iomem
*psc
= PSC(port
);
678 /* clear D_*-bits by reading them */
679 in_8(&psc
->mpc52xx_psc_ipcr
);
680 /* enable CTS and DCD as IPC interrupts */
681 out_8(&psc
->mpc52xx_psc_acr
, MPC52xx_PSC_IEC_CTS
| MPC52xx_PSC_IEC_DCD
);
683 port
->read_status_mask
|= MPC52xx_PSC_IMR_IPC
;
684 out_be16(&psc
->mpc52xx_psc_imr
, port
->read_status_mask
);
688 mpc52xx_uart_break_ctl(struct uart_port
*port
, int ctl
)
691 spin_lock_irqsave(&port
->lock
, flags
);
694 out_8(&PSC(port
)->command
, MPC52xx_PSC_START_BRK
);
696 out_8(&PSC(port
)->command
, MPC52xx_PSC_STOP_BRK
);
698 spin_unlock_irqrestore(&port
->lock
, flags
);
702 mpc52xx_uart_startup(struct uart_port
*port
)
704 struct mpc52xx_psc __iomem
*psc
= PSC(port
);
707 if (psc_ops
->clock
) {
708 ret
= psc_ops
->clock(port
, 1);
714 ret
= request_irq(port
->irq
, mpc52xx_uart_int
,
715 port
->irqflags
, "mpc52xx_psc_uart", port
);
719 /* Reset/activate the port, clear and enable interrupts */
720 out_8(&psc
->command
, MPC52xx_PSC_RST_RX
);
721 out_8(&psc
->command
, MPC52xx_PSC_RST_TX
);
723 out_be32(&psc
->sicr
, 0); /* UART mode DCD ignored */
725 psc_ops
->fifo_init(port
);
727 out_8(&psc
->command
, MPC52xx_PSC_TX_ENABLE
);
728 out_8(&psc
->command
, MPC52xx_PSC_RX_ENABLE
);
734 mpc52xx_uart_shutdown(struct uart_port
*port
)
736 struct mpc52xx_psc __iomem
*psc
= PSC(port
);
738 /* Shut down the port. Leave TX active if on a console port */
739 out_8(&psc
->command
, MPC52xx_PSC_RST_RX
);
740 if (!uart_console(port
))
741 out_8(&psc
->command
, MPC52xx_PSC_RST_TX
);
743 port
->read_status_mask
= 0;
744 out_be16(&psc
->mpc52xx_psc_imr
, port
->read_status_mask
);
747 psc_ops
->clock(port
, 0);
749 /* Release interrupt */
750 free_irq(port
->irq
, port
);
754 mpc52xx_uart_set_termios(struct uart_port
*port
, struct ktermios
*new,
755 struct ktermios
*old
)
757 struct mpc52xx_psc __iomem
*psc
= PSC(port
);
759 unsigned char mr1
, mr2
;
763 /* Prepare what we're gonna write */
766 switch (new->c_cflag
& CSIZE
) {
767 case CS5
: mr1
|= MPC52xx_PSC_MODE_5_BITS
;
769 case CS6
: mr1
|= MPC52xx_PSC_MODE_6_BITS
;
771 case CS7
: mr1
|= MPC52xx_PSC_MODE_7_BITS
;
774 default: mr1
|= MPC52xx_PSC_MODE_8_BITS
;
777 if (new->c_cflag
& PARENB
) {
778 if (new->c_cflag
& CMSPAR
)
779 mr1
|= MPC52xx_PSC_MODE_PARFORCE
;
781 /* With CMSPAR, PARODD also means high parity (same as termios) */
782 mr1
|= (new->c_cflag
& PARODD
) ?
783 MPC52xx_PSC_MODE_PARODD
: MPC52xx_PSC_MODE_PAREVEN
;
785 mr1
|= MPC52xx_PSC_MODE_PARNONE
;
790 if (new->c_cflag
& CSTOPB
)
791 mr2
|= MPC52xx_PSC_MODE_TWO_STOP
;
793 mr2
|= ((new->c_cflag
& CSIZE
) == CS5
) ?
794 MPC52xx_PSC_MODE_ONE_STOP_5_BITS
:
795 MPC52xx_PSC_MODE_ONE_STOP
;
797 if (new->c_cflag
& CRTSCTS
) {
798 mr1
|= MPC52xx_PSC_MODE_RXRTS
;
799 mr2
|= MPC52xx_PSC_MODE_TXCTS
;
803 spin_lock_irqsave(&port
->lock
, flags
);
805 /* Do our best to flush TX & RX, so we don't lose anything */
806 /* But we don't wait indefinitely ! */
807 j
= 5000000; /* Maximum wait */
808 /* FIXME Can't receive chars since set_termios might be called at early
809 * boot for the console, all stuff is not yet ready to receive at that
810 * time and that just makes the kernel oops */
811 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
812 while (!mpc52xx_uart_tx_empty(port
) && --j
)
816 printk(KERN_ERR
"mpc52xx_uart.c: "
817 "Unable to flush RX & TX fifos in-time in set_termios."
818 "Some chars may have been lost.\n");
820 /* Reset the TX & RX */
821 out_8(&psc
->command
, MPC52xx_PSC_RST_RX
);
822 out_8(&psc
->command
, MPC52xx_PSC_RST_TX
);
824 /* Send new mode settings */
825 out_8(&psc
->command
, MPC52xx_PSC_SEL_MODE_REG_1
);
826 out_8(&psc
->mode
, mr1
);
827 out_8(&psc
->mode
, mr2
);
828 baud
= psc_ops
->set_baudrate(port
, new, old
);
830 /* Update the per-port timeout */
831 uart_update_timeout(port
, new->c_cflag
, baud
);
833 if (UART_ENABLE_MS(port
, new->c_cflag
))
834 mpc52xx_uart_enable_ms(port
);
836 /* Reenable TX & RX */
837 out_8(&psc
->command
, MPC52xx_PSC_TX_ENABLE
);
838 out_8(&psc
->command
, MPC52xx_PSC_RX_ENABLE
);
840 /* We're all set, release the lock */
841 spin_unlock_irqrestore(&port
->lock
, flags
);
845 mpc52xx_uart_type(struct uart_port
*port
)
848 * We keep using PORT_MPC52xx for historic reasons although it applies
849 * for MPC512x, too, but print "MPC5xxx" to not irritate users
851 return port
->type
== PORT_MPC52xx
? "MPC5xxx PSC" : NULL
;
855 mpc52xx_uart_release_port(struct uart_port
*port
)
857 /* remapped by us ? */
858 if (port
->flags
& UPF_IOREMAP
) {
859 iounmap(port
->membase
);
860 port
->membase
= NULL
;
863 release_mem_region(port
->mapbase
, sizeof(struct mpc52xx_psc
));
867 mpc52xx_uart_request_port(struct uart_port
*port
)
871 if (port
->flags
& UPF_IOREMAP
) /* Need to remap ? */
872 port
->membase
= ioremap(port
->mapbase
,
873 sizeof(struct mpc52xx_psc
));
878 err
= request_mem_region(port
->mapbase
, sizeof(struct mpc52xx_psc
),
879 "mpc52xx_psc_uart") != NULL
? 0 : -EBUSY
;
881 if (err
&& (port
->flags
& UPF_IOREMAP
)) {
882 iounmap(port
->membase
);
883 port
->membase
= NULL
;
890 mpc52xx_uart_config_port(struct uart_port
*port
, int flags
)
892 if ((flags
& UART_CONFIG_TYPE
)
893 && (mpc52xx_uart_request_port(port
) == 0))
894 port
->type
= PORT_MPC52xx
;
898 mpc52xx_uart_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
900 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_MPC52xx
)
903 if ((ser
->irq
!= port
->irq
) ||
904 (ser
->io_type
!= UPIO_MEM
) ||
905 (ser
->baud_base
!= port
->uartclk
) ||
906 (ser
->iomem_base
!= (void *)port
->mapbase
) ||
914 static struct uart_ops mpc52xx_uart_ops
= {
915 .tx_empty
= mpc52xx_uart_tx_empty
,
916 .set_mctrl
= mpc52xx_uart_set_mctrl
,
917 .get_mctrl
= mpc52xx_uart_get_mctrl
,
918 .stop_tx
= mpc52xx_uart_stop_tx
,
919 .start_tx
= mpc52xx_uart_start_tx
,
920 .send_xchar
= mpc52xx_uart_send_xchar
,
921 .stop_rx
= mpc52xx_uart_stop_rx
,
922 .enable_ms
= mpc52xx_uart_enable_ms
,
923 .break_ctl
= mpc52xx_uart_break_ctl
,
924 .startup
= mpc52xx_uart_startup
,
925 .shutdown
= mpc52xx_uart_shutdown
,
926 .set_termios
= mpc52xx_uart_set_termios
,
927 /* .pm = mpc52xx_uart_pm, Not supported yet */
928 /* .set_wake = mpc52xx_uart_set_wake, Not supported yet */
929 .type
= mpc52xx_uart_type
,
930 .release_port
= mpc52xx_uart_release_port
,
931 .request_port
= mpc52xx_uart_request_port
,
932 .config_port
= mpc52xx_uart_config_port
,
933 .verify_port
= mpc52xx_uart_verify_port
937 /* ======================================================================== */
938 /* Interrupt handling */
939 /* ======================================================================== */
942 mpc52xx_uart_int_rx_chars(struct uart_port
*port
)
944 struct tty_port
*tport
= &port
->state
->port
;
945 unsigned char ch
, flag
;
946 unsigned short status
;
948 /* While we can read, do so ! */
949 while (psc_ops
->raw_rx_rdy(port
)) {
951 ch
= psc_ops
->read_char(port
);
953 /* Handle sysreq char */
955 if (uart_handle_sysrq_char(port
, ch
)) {
966 status
= in_be16(&PSC(port
)->mpc52xx_psc_status
);
968 if (status
& (MPC52xx_PSC_SR_PE
|
970 MPC52xx_PSC_SR_RB
)) {
972 if (status
& MPC52xx_PSC_SR_RB
) {
974 uart_handle_break(port
);
976 } else if (status
& MPC52xx_PSC_SR_PE
) {
978 port
->icount
.parity
++;
980 else if (status
& MPC52xx_PSC_SR_FE
) {
982 port
->icount
.frame
++;
985 /* Clear error condition */
986 out_8(&PSC(port
)->command
, MPC52xx_PSC_RST_ERR_STAT
);
989 tty_insert_flip_char(tport
, ch
, flag
);
990 if (status
& MPC52xx_PSC_SR_OE
) {
992 * Overrun is special, since it's
993 * reported immediately, and doesn't
994 * affect the current character
996 tty_insert_flip_char(tport
, 0, TTY_OVERRUN
);
997 port
->icount
.overrun
++;
1001 spin_unlock(&port
->lock
);
1002 tty_flip_buffer_push(tport
);
1003 spin_lock(&port
->lock
);
1005 return psc_ops
->raw_rx_rdy(port
);
1009 mpc52xx_uart_int_tx_chars(struct uart_port
*port
)
1011 struct circ_buf
*xmit
= &port
->state
->xmit
;
1013 /* Process out of band chars */
1015 psc_ops
->write_char(port
, port
->x_char
);
1021 /* Nothing to do ? */
1022 if (uart_circ_empty(xmit
) || uart_tx_stopped(port
)) {
1023 mpc52xx_uart_stop_tx(port
);
1028 while (psc_ops
->raw_tx_rdy(port
)) {
1029 psc_ops
->write_char(port
, xmit
->buf
[xmit
->tail
]);
1030 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
1032 if (uart_circ_empty(xmit
))
1037 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
1038 uart_write_wakeup(port
);
1040 /* Maybe we're done after all */
1041 if (uart_circ_empty(xmit
)) {
1042 mpc52xx_uart_stop_tx(port
);
1050 mpc5xxx_uart_process_int(struct uart_port
*port
)
1052 unsigned long pass
= ISR_PASS_LIMIT
;
1053 unsigned int keepgoing
;
1056 /* While we have stuff to do, we continue */
1058 /* If we don't find anything to do, we stop */
1061 psc_ops
->rx_clr_irq(port
);
1062 if (psc_ops
->rx_rdy(port
))
1063 keepgoing
|= mpc52xx_uart_int_rx_chars(port
);
1065 psc_ops
->tx_clr_irq(port
);
1066 if (psc_ops
->tx_rdy(port
))
1067 keepgoing
|= mpc52xx_uart_int_tx_chars(port
);
1069 status
= in_8(&PSC(port
)->mpc52xx_psc_ipcr
);
1070 if (status
& MPC52xx_PSC_D_DCD
)
1071 uart_handle_dcd_change(port
, !(status
& MPC52xx_PSC_DCD
));
1073 if (status
& MPC52xx_PSC_D_CTS
)
1074 uart_handle_cts_change(port
, !(status
& MPC52xx_PSC_CTS
));
1076 /* Limit number of iteration */
1080 } while (keepgoing
);
1086 mpc52xx_uart_int(int irq
, void *dev_id
)
1088 struct uart_port
*port
= dev_id
;
1091 spin_lock(&port
->lock
);
1093 ret
= psc_ops
->handle_irq(port
);
1095 spin_unlock(&port
->lock
);
1100 /* ======================================================================== */
1101 /* Console ( if applicable ) */
1102 /* ======================================================================== */
1104 #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
1107 mpc52xx_console_get_options(struct uart_port
*port
,
1108 int *baud
, int *parity
, int *bits
, int *flow
)
1110 struct mpc52xx_psc __iomem
*psc
= PSC(port
);
1113 pr_debug("mpc52xx_console_get_options(port=%p)\n", port
);
1115 /* Read the mode registers */
1116 out_8(&psc
->command
, MPC52xx_PSC_SEL_MODE_REG_1
);
1117 mr1
= in_8(&psc
->mode
);
1119 /* CT{U,L}R are write-only ! */
1120 *baud
= CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD
;
1123 switch (mr1
& MPC52xx_PSC_MODE_BITS_MASK
) {
1124 case MPC52xx_PSC_MODE_5_BITS
:
1127 case MPC52xx_PSC_MODE_6_BITS
:
1130 case MPC52xx_PSC_MODE_7_BITS
:
1133 case MPC52xx_PSC_MODE_8_BITS
:
1138 if (mr1
& MPC52xx_PSC_MODE_PARNONE
)
1141 *parity
= mr1
& MPC52xx_PSC_MODE_PARODD
? 'o' : 'e';
1145 mpc52xx_console_write(struct console
*co
, const char *s
, unsigned int count
)
1147 struct uart_port
*port
= &mpc52xx_uart_ports
[co
->index
];
1150 /* Disable interrupts */
1151 psc_ops
->cw_disable_ints(port
);
1153 /* Wait the TX buffer to be empty */
1154 j
= 5000000; /* Maximum wait */
1155 while (!mpc52xx_uart_tx_empty(port
) && --j
)
1158 /* Write all the chars */
1159 for (i
= 0; i
< count
; i
++, s
++) {
1160 /* Line return handling */
1162 psc_ops
->write_char(port
, '\r');
1165 psc_ops
->write_char(port
, *s
);
1167 /* Wait the TX buffer to be empty */
1168 j
= 20000; /* Maximum wait */
1169 while (!mpc52xx_uart_tx_empty(port
) && --j
)
1173 /* Restore interrupt state */
1174 psc_ops
->cw_restore_ints(port
);
1179 mpc52xx_console_setup(struct console
*co
, char *options
)
1181 struct uart_port
*port
= &mpc52xx_uart_ports
[co
->index
];
1182 struct device_node
*np
= mpc52xx_uart_nodes
[co
->index
];
1183 unsigned int uartclk
;
1184 struct resource res
;
1187 int baud
= CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD
;
1192 pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n",
1193 co
, co
->index
, options
);
1195 if ((co
->index
< 0) || (co
->index
>= MPC52xx_PSC_MAXNUM
)) {
1196 pr_debug("PSC%x out of range\n", co
->index
);
1201 pr_debug("PSC%x not found in device tree\n", co
->index
);
1205 pr_debug("Console on ttyPSC%x is %s\n",
1206 co
->index
, mpc52xx_uart_nodes
[co
->index
]->full_name
);
1208 /* Fetch register locations */
1209 ret
= of_address_to_resource(np
, 0, &res
);
1211 pr_debug("Could not get resources for PSC%x\n", co
->index
);
1215 uartclk
= mpc5xxx_get_bus_frequency(np
);
1217 pr_debug("Could not find uart clock frequency!\n");
1221 /* Basic port init. Needed since we use some uart_??? func before
1222 * real init for early access */
1223 spin_lock_init(&port
->lock
);
1224 port
->uartclk
= uartclk
;
1225 port
->ops
= &mpc52xx_uart_ops
;
1226 port
->mapbase
= res
.start
;
1227 port
->membase
= ioremap(res
.start
, sizeof(struct mpc52xx_psc
));
1228 port
->irq
= irq_of_parse_and_map(np
, 0);
1230 if (port
->membase
== NULL
)
1233 pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n",
1234 (void *)port
->mapbase
, port
->membase
,
1235 port
->irq
, port
->uartclk
);
1237 /* Setup the port parameters accoding to options */
1239 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1241 mpc52xx_console_get_options(port
, &baud
, &parity
, &bits
, &flow
);
1243 pr_debug("Setting console parameters: %i %i%c1 flow=%c\n",
1244 baud
, bits
, parity
, flow
);
1246 return uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
1250 static struct uart_driver mpc52xx_uart_driver
;
1252 static struct console mpc52xx_console
= {
1254 .write
= mpc52xx_console_write
,
1255 .device
= uart_console_device
,
1256 .setup
= mpc52xx_console_setup
,
1257 .flags
= CON_PRINTBUFFER
,
1258 .index
= -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */
1259 .data
= &mpc52xx_uart_driver
,
1264 mpc52xx_console_init(void)
1266 mpc52xx_uart_of_enumerate();
1267 register_console(&mpc52xx_console
);
1271 console_initcall(mpc52xx_console_init
);
1273 #define MPC52xx_PSC_CONSOLE &mpc52xx_console
1275 #define MPC52xx_PSC_CONSOLE NULL
1279 /* ======================================================================== */
1281 /* ======================================================================== */
1283 static struct uart_driver mpc52xx_uart_driver
= {
1284 .driver_name
= "mpc52xx_psc_uart",
1285 .dev_name
= "ttyPSC",
1286 .major
= SERIAL_PSC_MAJOR
,
1287 .minor
= SERIAL_PSC_MINOR
,
1288 .nr
= MPC52xx_PSC_MAXNUM
,
1289 .cons
= MPC52xx_PSC_CONSOLE
,
1292 /* ======================================================================== */
1293 /* OF Platform Driver */
1294 /* ======================================================================== */
1296 static struct of_device_id mpc52xx_uart_of_match
[] = {
1297 #ifdef CONFIG_PPC_MPC52xx
1298 { .compatible
= "fsl,mpc5200b-psc-uart", .data
= &mpc5200b_psc_ops
, },
1299 { .compatible
= "fsl,mpc5200-psc-uart", .data
= &mpc52xx_psc_ops
, },
1300 /* binding used by old lite5200 device trees: */
1301 { .compatible
= "mpc5200-psc-uart", .data
= &mpc52xx_psc_ops
, },
1302 /* binding used by efika: */
1303 { .compatible
= "mpc5200-serial", .data
= &mpc52xx_psc_ops
, },
1305 #ifdef CONFIG_PPC_MPC512x
1306 { .compatible
= "fsl,mpc5121-psc-uart", .data
= &mpc512x_psc_ops
, },
1311 static int mpc52xx_uart_of_probe(struct platform_device
*op
)
1314 unsigned int uartclk
;
1315 struct uart_port
*port
= NULL
;
1316 struct resource res
;
1319 /* Check validity & presence */
1320 for (idx
= 0; idx
< MPC52xx_PSC_MAXNUM
; idx
++)
1321 if (mpc52xx_uart_nodes
[idx
] == op
->dev
.of_node
)
1323 if (idx
>= MPC52xx_PSC_MAXNUM
)
1325 pr_debug("Found %s assigned to ttyPSC%x\n",
1326 mpc52xx_uart_nodes
[idx
]->full_name
, idx
);
1328 /* set the uart clock to the input clock of the psc, the different
1329 * prescalers are taken into account in the set_baudrate() methods
1330 * of the respective chip */
1331 uartclk
= mpc5xxx_get_bus_frequency(op
->dev
.of_node
);
1333 dev_dbg(&op
->dev
, "Could not find uart clock frequency!\n");
1337 /* Init the port structure */
1338 port
= &mpc52xx_uart_ports
[idx
];
1340 spin_lock_init(&port
->lock
);
1341 port
->uartclk
= uartclk
;
1342 port
->fifosize
= 512;
1343 port
->iotype
= UPIO_MEM
;
1344 port
->flags
= UPF_BOOT_AUTOCONF
|
1345 (uart_console(port
) ? 0 : UPF_IOREMAP
);
1347 port
->ops
= &mpc52xx_uart_ops
;
1348 port
->dev
= &op
->dev
;
1350 /* Search for IRQ and mapbase */
1351 ret
= of_address_to_resource(op
->dev
.of_node
, 0, &res
);
1355 port
->mapbase
= res
.start
;
1356 if (!port
->mapbase
) {
1357 dev_dbg(&op
->dev
, "Could not allocate resources for PSC\n");
1361 psc_ops
->get_irq(port
, op
->dev
.of_node
);
1362 if (port
->irq
== 0) {
1363 dev_dbg(&op
->dev
, "Could not get irq\n");
1367 dev_dbg(&op
->dev
, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n",
1368 (void *)port
->mapbase
, port
->irq
, port
->uartclk
);
1370 /* Add the port to the uart sub-system */
1371 ret
= uart_add_one_port(&mpc52xx_uart_driver
, port
);
1375 dev_set_drvdata(&op
->dev
, (void *)port
);
1380 mpc52xx_uart_of_remove(struct platform_device
*op
)
1382 struct uart_port
*port
= dev_get_drvdata(&op
->dev
);
1383 dev_set_drvdata(&op
->dev
, NULL
);
1386 uart_remove_one_port(&mpc52xx_uart_driver
, port
);
1393 mpc52xx_uart_of_suspend(struct platform_device
*op
, pm_message_t state
)
1395 struct uart_port
*port
= (struct uart_port
*) dev_get_drvdata(&op
->dev
);
1398 uart_suspend_port(&mpc52xx_uart_driver
, port
);
1404 mpc52xx_uart_of_resume(struct platform_device
*op
)
1406 struct uart_port
*port
= (struct uart_port
*) dev_get_drvdata(&op
->dev
);
1409 uart_resume_port(&mpc52xx_uart_driver
, port
);
1416 mpc52xx_uart_of_assign(struct device_node
*np
)
1420 /* Find the first free PSC number */
1421 for (i
= 0; i
< MPC52xx_PSC_MAXNUM
; i
++) {
1422 if (mpc52xx_uart_nodes
[i
] == NULL
) {
1424 mpc52xx_uart_nodes
[i
] = np
;
1431 mpc52xx_uart_of_enumerate(void)
1433 static int enum_done
;
1434 struct device_node
*np
;
1435 const struct of_device_id
*match
;
1441 /* Assign index to each PSC in device tree */
1442 for_each_matching_node(np
, mpc52xx_uart_of_match
) {
1443 match
= of_match_node(mpc52xx_uart_of_match
, np
);
1444 psc_ops
= match
->data
;
1445 mpc52xx_uart_of_assign(np
);
1450 for (i
= 0; i
< MPC52xx_PSC_MAXNUM
; i
++) {
1451 if (mpc52xx_uart_nodes
[i
])
1452 pr_debug("%s assigned to ttyPSC%x\n",
1453 mpc52xx_uart_nodes
[i
]->full_name
, i
);
1457 MODULE_DEVICE_TABLE(of
, mpc52xx_uart_of_match
);
1459 static struct platform_driver mpc52xx_uart_of_driver
= {
1460 .probe
= mpc52xx_uart_of_probe
,
1461 .remove
= mpc52xx_uart_of_remove
,
1463 .suspend
= mpc52xx_uart_of_suspend
,
1464 .resume
= mpc52xx_uart_of_resume
,
1467 .name
= "mpc52xx-psc-uart",
1468 .owner
= THIS_MODULE
,
1469 .of_match_table
= mpc52xx_uart_of_match
,
1474 /* ======================================================================== */
1476 /* ======================================================================== */
1479 mpc52xx_uart_init(void)
1483 printk(KERN_INFO
"Serial: MPC52xx PSC UART driver\n");
1485 ret
= uart_register_driver(&mpc52xx_uart_driver
);
1487 printk(KERN_ERR
"%s: uart_register_driver failed (%i)\n",
1492 mpc52xx_uart_of_enumerate();
1495 * Map the PSC FIFO Controller and init if on MPC512x.
1497 if (psc_ops
&& psc_ops
->fifoc_init
) {
1498 ret
= psc_ops
->fifoc_init();
1503 ret
= platform_driver_register(&mpc52xx_uart_of_driver
);
1505 printk(KERN_ERR
"%s: platform_driver_register failed (%i)\n",
1507 uart_unregister_driver(&mpc52xx_uart_driver
);
1515 mpc52xx_uart_exit(void)
1517 if (psc_ops
->fifoc_uninit
)
1518 psc_ops
->fifoc_uninit();
1520 platform_driver_unregister(&mpc52xx_uart_of_driver
);
1521 uart_unregister_driver(&mpc52xx_uart_driver
);
1525 module_init(mpc52xx_uart_init
);
1526 module_exit(mpc52xx_uart_exit
);
1528 MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
1529 MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
1530 MODULE_LICENSE("GPL");