2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
42 #include <linux/tcp.h>
43 #include <linux/udp.h>
44 #include <linux/etherdevice.h>
45 #include <linux/delay.h>
46 #include <linux/ethtool.h>
47 #include <linux/platform_device.h>
48 #include <linux/module.h>
49 #include <linux/kernel.h>
50 #include <linux/spinlock.h>
51 #include <linux/workqueue.h>
52 #include <linux/phy.h>
53 #include <linux/mv643xx_eth.h>
55 #include <linux/types.h>
56 #include <linux/inet_lro.h>
57 #include <asm/system.h>
59 static char mv643xx_eth_driver_name
[] = "mv643xx_eth";
60 static char mv643xx_eth_driver_version
[] = "1.4";
64 * Registers shared between all ports.
66 #define PHY_ADDR 0x0000
67 #define SMI_REG 0x0004
68 #define SMI_BUSY 0x10000000
69 #define SMI_READ_VALID 0x08000000
70 #define SMI_OPCODE_READ 0x04000000
71 #define SMI_OPCODE_WRITE 0x00000000
72 #define ERR_INT_CAUSE 0x0080
73 #define ERR_INT_SMI_DONE 0x00000010
74 #define ERR_INT_MASK 0x0084
75 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78 #define WINDOW_BAR_ENABLE 0x0290
79 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
82 * Main per-port registers. These live at offset 0x0400 for
83 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
85 #define PORT_CONFIG 0x0000
86 #define UNICAST_PROMISCUOUS_MODE 0x00000001
87 #define PORT_CONFIG_EXT 0x0004
88 #define MAC_ADDR_LOW 0x0014
89 #define MAC_ADDR_HIGH 0x0018
90 #define SDMA_CONFIG 0x001c
91 #define TX_BURST_SIZE_16_64BIT 0x01000000
92 #define TX_BURST_SIZE_4_64BIT 0x00800000
93 #define BLM_TX_NO_SWAP 0x00000020
94 #define BLM_RX_NO_SWAP 0x00000010
95 #define RX_BURST_SIZE_16_64BIT 0x00000008
96 #define RX_BURST_SIZE_4_64BIT 0x00000004
97 #define PORT_SERIAL_CONTROL 0x003c
98 #define SET_MII_SPEED_TO_100 0x01000000
99 #define SET_GMII_SPEED_TO_1000 0x00800000
100 #define SET_FULL_DUPLEX_MODE 0x00200000
101 #define MAX_RX_PACKET_9700BYTE 0x000a0000
102 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
103 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
104 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
105 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
106 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
107 #define FORCE_LINK_PASS 0x00000002
108 #define SERIAL_PORT_ENABLE 0x00000001
109 #define PORT_STATUS 0x0044
110 #define TX_FIFO_EMPTY 0x00000400
111 #define TX_IN_PROGRESS 0x00000080
112 #define PORT_SPEED_MASK 0x00000030
113 #define PORT_SPEED_1000 0x00000010
114 #define PORT_SPEED_100 0x00000020
115 #define PORT_SPEED_10 0x00000000
116 #define FLOW_CONTROL_ENABLED 0x00000008
117 #define FULL_DUPLEX 0x00000004
118 #define LINK_UP 0x00000002
119 #define TXQ_COMMAND 0x0048
120 #define TXQ_FIX_PRIO_CONF 0x004c
121 #define TX_BW_RATE 0x0050
122 #define TX_BW_MTU 0x0058
123 #define TX_BW_BURST 0x005c
124 #define INT_CAUSE 0x0060
125 #define INT_TX_END 0x07f80000
126 #define INT_RX 0x000003fc
127 #define INT_EXT 0x00000002
128 #define INT_CAUSE_EXT 0x0064
129 #define INT_EXT_LINK_PHY 0x00110000
130 #define INT_EXT_TX 0x000000ff
131 #define INT_MASK 0x0068
132 #define INT_MASK_EXT 0x006c
133 #define TX_FIFO_URGENT_THRESHOLD 0x0074
134 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
135 #define TX_BW_RATE_MOVED 0x00e0
136 #define TX_BW_MTU_MOVED 0x00e8
137 #define TX_BW_BURST_MOVED 0x00ec
138 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
139 #define RXQ_COMMAND 0x0280
140 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
141 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
142 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
143 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
146 * Misc per-port registers.
148 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
149 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
150 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
151 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
155 * SDMA configuration register default value.
157 #if defined(__BIG_ENDIAN)
158 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
159 (RX_BURST_SIZE_4_64BIT | \
160 TX_BURST_SIZE_4_64BIT)
161 #elif defined(__LITTLE_ENDIAN)
162 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
163 (RX_BURST_SIZE_4_64BIT | \
166 TX_BURST_SIZE_4_64BIT)
168 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
175 #define DEFAULT_RX_QUEUE_SIZE 128
176 #define DEFAULT_TX_QUEUE_SIZE 256
177 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
183 #if defined(__BIG_ENDIAN)
185 u16 byte_cnt
; /* Descriptor buffer byte count */
186 u16 buf_size
; /* Buffer size */
187 u32 cmd_sts
; /* Descriptor command status */
188 u32 next_desc_ptr
; /* Next descriptor pointer */
189 u32 buf_ptr
; /* Descriptor buffer pointer */
193 u16 byte_cnt
; /* buffer byte count */
194 u16 l4i_chk
; /* CPU provided TCP checksum */
195 u32 cmd_sts
; /* Command/status field */
196 u32 next_desc_ptr
; /* Pointer to next descriptor */
197 u32 buf_ptr
; /* pointer to buffer for this descriptor*/
199 #elif defined(__LITTLE_ENDIAN)
201 u32 cmd_sts
; /* Descriptor command status */
202 u16 buf_size
; /* Buffer size */
203 u16 byte_cnt
; /* Descriptor buffer byte count */
204 u32 buf_ptr
; /* Descriptor buffer pointer */
205 u32 next_desc_ptr
; /* Next descriptor pointer */
209 u32 cmd_sts
; /* Command/status field */
210 u16 l4i_chk
; /* CPU provided TCP checksum */
211 u16 byte_cnt
; /* buffer byte count */
212 u32 buf_ptr
; /* pointer to buffer for this descriptor*/
213 u32 next_desc_ptr
; /* Pointer to next descriptor */
216 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
219 /* RX & TX descriptor command */
220 #define BUFFER_OWNED_BY_DMA 0x80000000
222 /* RX & TX descriptor status */
223 #define ERROR_SUMMARY 0x00000001
225 /* RX descriptor status */
226 #define LAYER_4_CHECKSUM_OK 0x40000000
227 #define RX_ENABLE_INTERRUPT 0x20000000
228 #define RX_FIRST_DESC 0x08000000
229 #define RX_LAST_DESC 0x04000000
230 #define RX_IP_HDR_OK 0x02000000
231 #define RX_PKT_IS_IPV4 0x01000000
232 #define RX_PKT_IS_ETHERNETV2 0x00800000
233 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
234 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
235 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
237 /* TX descriptor command */
238 #define TX_ENABLE_INTERRUPT 0x00800000
239 #define GEN_CRC 0x00400000
240 #define TX_FIRST_DESC 0x00200000
241 #define TX_LAST_DESC 0x00100000
242 #define ZERO_PADDING 0x00080000
243 #define GEN_IP_V4_CHECKSUM 0x00040000
244 #define GEN_TCP_UDP_CHECKSUM 0x00020000
245 #define UDP_FRAME 0x00010000
246 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
247 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
249 #define TX_IHL_SHIFT 11
252 /* global *******************************************************************/
253 struct mv643xx_eth_shared_private
{
255 * Ethernet controller base address.
260 * Points at the right SMI instance to use.
262 struct mv643xx_eth_shared_private
*smi
;
265 * Provides access to local SMI interface.
267 struct mii_bus
*smi_bus
;
270 * If we have access to the error interrupt pin (which is
271 * somewhat misnamed as it not only reflects internal errors
272 * but also reflects SMI completion), use that to wait for
273 * SMI access completion instead of polling the SMI busy bit.
276 wait_queue_head_t smi_busy_wait
;
279 * Per-port MBUS window access register value.
284 * Hardware-specific parameters.
287 int extended_rx_coal_limit
;
291 #define TX_BW_CONTROL_ABSENT 0
292 #define TX_BW_CONTROL_OLD_LAYOUT 1
293 #define TX_BW_CONTROL_NEW_LAYOUT 2
295 static int mv643xx_eth_open(struct net_device
*dev
);
296 static int mv643xx_eth_stop(struct net_device
*dev
);
299 /* per-port *****************************************************************/
300 struct mib_counters
{
301 u64 good_octets_received
;
302 u32 bad_octets_received
;
303 u32 internal_mac_transmit_err
;
304 u32 good_frames_received
;
305 u32 bad_frames_received
;
306 u32 broadcast_frames_received
;
307 u32 multicast_frames_received
;
308 u32 frames_64_octets
;
309 u32 frames_65_to_127_octets
;
310 u32 frames_128_to_255_octets
;
311 u32 frames_256_to_511_octets
;
312 u32 frames_512_to_1023_octets
;
313 u32 frames_1024_to_max_octets
;
314 u64 good_octets_sent
;
315 u32 good_frames_sent
;
316 u32 excessive_collision
;
317 u32 multicast_frames_sent
;
318 u32 broadcast_frames_sent
;
319 u32 unrec_mac_control_received
;
321 u32 good_fc_received
;
323 u32 undersize_received
;
324 u32 fragments_received
;
325 u32 oversize_received
;
327 u32 mac_receive_error
;
333 struct lro_counters
{
348 struct rx_desc
*rx_desc_area
;
349 dma_addr_t rx_desc_dma
;
350 int rx_desc_area_size
;
351 struct sk_buff
**rx_skb
;
353 struct net_lro_mgr lro_mgr
;
354 struct net_lro_desc lro_arr
[8];
366 struct tx_desc
*tx_desc_area
;
367 dma_addr_t tx_desc_dma
;
368 int tx_desc_area_size
;
370 struct sk_buff_head tx_skb
;
372 unsigned long tx_packets
;
373 unsigned long tx_bytes
;
374 unsigned long tx_dropped
;
377 struct mv643xx_eth_private
{
378 struct mv643xx_eth_shared_private
*shared
;
382 struct net_device
*dev
;
384 struct phy_device
*phy
;
386 struct timer_list mib_counters_timer
;
387 spinlock_t mib_counters_lock
;
388 struct mib_counters mib_counters
;
390 struct lro_counters lro_counters
;
392 struct work_struct tx_timeout_task
;
394 struct napi_struct napi
;
403 struct sk_buff_head rx_recycle
;
409 unsigned long rx_desc_sram_addr
;
410 int rx_desc_sram_size
;
412 struct timer_list rx_oom
;
413 struct rx_queue rxq
[8];
419 unsigned long tx_desc_sram_addr
;
420 int tx_desc_sram_size
;
422 struct tx_queue txq
[8];
426 /* port register accessors **************************************************/
427 static inline u32
rdl(struct mv643xx_eth_private
*mp
, int offset
)
429 return readl(mp
->shared
->base
+ offset
);
432 static inline u32
rdlp(struct mv643xx_eth_private
*mp
, int offset
)
434 return readl(mp
->base
+ offset
);
437 static inline void wrl(struct mv643xx_eth_private
*mp
, int offset
, u32 data
)
439 writel(data
, mp
->shared
->base
+ offset
);
442 static inline void wrlp(struct mv643xx_eth_private
*mp
, int offset
, u32 data
)
444 writel(data
, mp
->base
+ offset
);
448 /* rxq/txq helper functions *************************************************/
449 static struct mv643xx_eth_private
*rxq_to_mp(struct rx_queue
*rxq
)
451 return container_of(rxq
, struct mv643xx_eth_private
, rxq
[rxq
->index
]);
454 static struct mv643xx_eth_private
*txq_to_mp(struct tx_queue
*txq
)
456 return container_of(txq
, struct mv643xx_eth_private
, txq
[txq
->index
]);
459 static void rxq_enable(struct rx_queue
*rxq
)
461 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
462 wrlp(mp
, RXQ_COMMAND
, 1 << rxq
->index
);
465 static void rxq_disable(struct rx_queue
*rxq
)
467 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
468 u8 mask
= 1 << rxq
->index
;
470 wrlp(mp
, RXQ_COMMAND
, mask
<< 8);
471 while (rdlp(mp
, RXQ_COMMAND
) & mask
)
475 static void txq_reset_hw_ptr(struct tx_queue
*txq
)
477 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
480 addr
= (u32
)txq
->tx_desc_dma
;
481 addr
+= txq
->tx_curr_desc
* sizeof(struct tx_desc
);
482 wrlp(mp
, TXQ_CURRENT_DESC_PTR(txq
->index
), addr
);
485 static void txq_enable(struct tx_queue
*txq
)
487 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
488 wrlp(mp
, TXQ_COMMAND
, 1 << txq
->index
);
491 static void txq_disable(struct tx_queue
*txq
)
493 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
494 u8 mask
= 1 << txq
->index
;
496 wrlp(mp
, TXQ_COMMAND
, mask
<< 8);
497 while (rdlp(mp
, TXQ_COMMAND
) & mask
)
501 static void txq_maybe_wake(struct tx_queue
*txq
)
503 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
504 struct netdev_queue
*nq
= netdev_get_tx_queue(mp
->dev
, txq
->index
);
506 if (netif_tx_queue_stopped(nq
)) {
507 __netif_tx_lock(nq
, smp_processor_id());
508 if (txq
->tx_ring_size
- txq
->tx_desc_count
>= MAX_SKB_FRAGS
+ 1)
509 netif_tx_wake_queue(nq
);
510 __netif_tx_unlock(nq
);
515 /* rx napi ******************************************************************/
517 mv643xx_get_skb_header(struct sk_buff
*skb
, void **iphdr
, void **tcph
,
518 u64
*hdr_flags
, void *priv
)
520 unsigned long cmd_sts
= (unsigned long)priv
;
523 * Make sure that this packet is Ethernet II, is not VLAN
524 * tagged, is IPv4, has a valid IP header, and is TCP.
526 if ((cmd_sts
& (RX_IP_HDR_OK
| RX_PKT_IS_IPV4
|
527 RX_PKT_IS_ETHERNETV2
| RX_PKT_LAYER4_TYPE_MASK
|
528 RX_PKT_IS_VLAN_TAGGED
)) !=
529 (RX_IP_HDR_OK
| RX_PKT_IS_IPV4
|
530 RX_PKT_IS_ETHERNETV2
| RX_PKT_LAYER4_TYPE_TCP_IPV4
))
533 skb_reset_network_header(skb
);
534 skb_set_transport_header(skb
, ip_hdrlen(skb
));
535 *iphdr
= ip_hdr(skb
);
536 *tcph
= tcp_hdr(skb
);
537 *hdr_flags
= LRO_IPV4
| LRO_TCP
;
542 static int rxq_process(struct rx_queue
*rxq
, int budget
)
544 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
545 struct net_device_stats
*stats
= &mp
->dev
->stats
;
546 int lro_flush_needed
;
549 lro_flush_needed
= 0;
551 while (rx
< budget
&& rxq
->rx_desc_count
) {
552 struct rx_desc
*rx_desc
;
553 unsigned int cmd_sts
;
557 rx_desc
= &rxq
->rx_desc_area
[rxq
->rx_curr_desc
];
559 cmd_sts
= rx_desc
->cmd_sts
;
560 if (cmd_sts
& BUFFER_OWNED_BY_DMA
)
564 skb
= rxq
->rx_skb
[rxq
->rx_curr_desc
];
565 rxq
->rx_skb
[rxq
->rx_curr_desc
] = NULL
;
568 if (rxq
->rx_curr_desc
== rxq
->rx_ring_size
)
569 rxq
->rx_curr_desc
= 0;
571 dma_unmap_single(NULL
, rx_desc
->buf_ptr
,
572 rx_desc
->buf_size
, DMA_FROM_DEVICE
);
573 rxq
->rx_desc_count
--;
576 mp
->work_rx_refill
|= 1 << rxq
->index
;
578 byte_cnt
= rx_desc
->byte_cnt
;
583 * Note that the descriptor byte count includes 2 dummy
584 * bytes automatically inserted by the hardware at the
585 * start of the packet (which we don't count), and a 4
586 * byte CRC at the end of the packet (which we do count).
589 stats
->rx_bytes
+= byte_cnt
- 2;
592 * In case we received a packet without first / last bits
593 * on, or the error summary bit is set, the packet needs
596 if ((cmd_sts
& (RX_FIRST_DESC
| RX_LAST_DESC
| ERROR_SUMMARY
))
597 != (RX_FIRST_DESC
| RX_LAST_DESC
))
601 * The -4 is for the CRC in the trailer of the
604 skb_put(skb
, byte_cnt
- 2 - 4);
606 if (cmd_sts
& LAYER_4_CHECKSUM_OK
)
607 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
608 skb
->protocol
= eth_type_trans(skb
, mp
->dev
);
610 if (skb
->dev
->features
& NETIF_F_LRO
&&
611 skb
->ip_summed
== CHECKSUM_UNNECESSARY
) {
612 lro_receive_skb(&rxq
->lro_mgr
, skb
, (void *)cmd_sts
);
613 lro_flush_needed
= 1;
615 netif_receive_skb(skb
);
622 if ((cmd_sts
& (RX_FIRST_DESC
| RX_LAST_DESC
)) !=
623 (RX_FIRST_DESC
| RX_LAST_DESC
)) {
625 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
626 "received packet spanning "
627 "multiple descriptors\n");
630 if (cmd_sts
& ERROR_SUMMARY
)
636 if (lro_flush_needed
)
637 lro_flush_all(&rxq
->lro_mgr
);
640 mp
->work_rx
&= ~(1 << rxq
->index
);
645 static int rxq_refill(struct rx_queue
*rxq
, int budget
)
647 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
651 while (refilled
< budget
&& rxq
->rx_desc_count
< rxq
->rx_ring_size
) {
654 struct rx_desc
*rx_desc
;
656 skb
= __skb_dequeue(&mp
->rx_recycle
);
658 skb
= dev_alloc_skb(mp
->skb_size
);
666 skb_reserve(skb
, SKB_DMA_REALIGN
);
669 rxq
->rx_desc_count
++;
671 rx
= rxq
->rx_used_desc
++;
672 if (rxq
->rx_used_desc
== rxq
->rx_ring_size
)
673 rxq
->rx_used_desc
= 0;
675 rx_desc
= rxq
->rx_desc_area
+ rx
;
677 rx_desc
->buf_ptr
= dma_map_single(NULL
, skb
->data
,
678 mp
->skb_size
, DMA_FROM_DEVICE
);
679 rx_desc
->buf_size
= mp
->skb_size
;
680 rxq
->rx_skb
[rx
] = skb
;
682 rx_desc
->cmd_sts
= BUFFER_OWNED_BY_DMA
| RX_ENABLE_INTERRUPT
;
686 * The hardware automatically prepends 2 bytes of
687 * dummy data to each received packet, so that the
688 * IP header ends up 16-byte aligned.
693 if (refilled
< budget
)
694 mp
->work_rx_refill
&= ~(1 << rxq
->index
);
701 /* tx ***********************************************************************/
702 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff
*skb
)
706 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
707 skb_frag_t
*fragp
= &skb_shinfo(skb
)->frags
[frag
];
708 if (fragp
->size
<= 8 && fragp
->page_offset
& 7)
715 static void txq_submit_frag_skb(struct tx_queue
*txq
, struct sk_buff
*skb
)
717 int nr_frags
= skb_shinfo(skb
)->nr_frags
;
720 for (frag
= 0; frag
< nr_frags
; frag
++) {
721 skb_frag_t
*this_frag
;
723 struct tx_desc
*desc
;
725 this_frag
= &skb_shinfo(skb
)->frags
[frag
];
726 tx_index
= txq
->tx_curr_desc
++;
727 if (txq
->tx_curr_desc
== txq
->tx_ring_size
)
728 txq
->tx_curr_desc
= 0;
729 desc
= &txq
->tx_desc_area
[tx_index
];
732 * The last fragment will generate an interrupt
733 * which will free the skb on TX completion.
735 if (frag
== nr_frags
- 1) {
736 desc
->cmd_sts
= BUFFER_OWNED_BY_DMA
|
737 ZERO_PADDING
| TX_LAST_DESC
|
740 desc
->cmd_sts
= BUFFER_OWNED_BY_DMA
;
744 desc
->byte_cnt
= this_frag
->size
;
745 desc
->buf_ptr
= dma_map_page(NULL
, this_frag
->page
,
746 this_frag
->page_offset
,
752 static inline __be16
sum16_as_be(__sum16 sum
)
754 return (__force __be16
)sum
;
757 static int txq_submit_skb(struct tx_queue
*txq
, struct sk_buff
*skb
)
759 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
760 int nr_frags
= skb_shinfo(skb
)->nr_frags
;
762 struct tx_desc
*desc
;
767 cmd_sts
= TX_FIRST_DESC
| GEN_CRC
| BUFFER_OWNED_BY_DMA
;
770 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
773 BUG_ON(skb
->protocol
!= htons(ETH_P_IP
) &&
774 skb
->protocol
!= htons(ETH_P_8021Q
));
776 tag_bytes
= (void *)ip_hdr(skb
) - (void *)skb
->data
- ETH_HLEN
;
777 if (unlikely(tag_bytes
& ~12)) {
778 if (skb_checksum_help(skb
) == 0)
785 cmd_sts
|= MAC_HDR_EXTRA_4_BYTES
;
787 cmd_sts
|= MAC_HDR_EXTRA_8_BYTES
;
789 cmd_sts
|= GEN_TCP_UDP_CHECKSUM
|
791 ip_hdr(skb
)->ihl
<< TX_IHL_SHIFT
;
793 switch (ip_hdr(skb
)->protocol
) {
795 cmd_sts
|= UDP_FRAME
;
796 l4i_chk
= ntohs(sum16_as_be(udp_hdr(skb
)->check
));
799 l4i_chk
= ntohs(sum16_as_be(tcp_hdr(skb
)->check
));
806 /* Errata BTS #50, IHL must be 5 if no HW checksum */
807 cmd_sts
|= 5 << TX_IHL_SHIFT
;
810 tx_index
= txq
->tx_curr_desc
++;
811 if (txq
->tx_curr_desc
== txq
->tx_ring_size
)
812 txq
->tx_curr_desc
= 0;
813 desc
= &txq
->tx_desc_area
[tx_index
];
816 txq_submit_frag_skb(txq
, skb
);
817 length
= skb_headlen(skb
);
819 cmd_sts
|= ZERO_PADDING
| TX_LAST_DESC
| TX_ENABLE_INTERRUPT
;
823 desc
->l4i_chk
= l4i_chk
;
824 desc
->byte_cnt
= length
;
825 desc
->buf_ptr
= dma_map_single(NULL
, skb
->data
, length
, DMA_TO_DEVICE
);
827 __skb_queue_tail(&txq
->tx_skb
, skb
);
829 /* ensure all other descriptors are written before first cmd_sts */
831 desc
->cmd_sts
= cmd_sts
;
833 /* clear TX_END status */
834 mp
->work_tx_end
&= ~(1 << txq
->index
);
836 /* ensure all descriptors are written before poking hardware */
840 txq
->tx_desc_count
+= nr_frags
+ 1;
845 static int mv643xx_eth_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
847 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
849 struct tx_queue
*txq
;
850 struct netdev_queue
*nq
;
852 queue
= skb_get_queue_mapping(skb
);
853 txq
= mp
->txq
+ queue
;
854 nq
= netdev_get_tx_queue(dev
, queue
);
856 if (has_tiny_unaligned_frags(skb
) && __skb_linearize(skb
)) {
858 dev_printk(KERN_DEBUG
, &dev
->dev
,
859 "failed to linearize skb with tiny "
860 "unaligned fragment\n");
861 return NETDEV_TX_BUSY
;
864 if (txq
->tx_ring_size
- txq
->tx_desc_count
< MAX_SKB_FRAGS
+ 1) {
866 dev_printk(KERN_ERR
, &dev
->dev
, "tx queue full?!\n");
871 if (!txq_submit_skb(txq
, skb
)) {
874 txq
->tx_bytes
+= skb
->len
;
876 dev
->trans_start
= jiffies
;
878 entries_left
= txq
->tx_ring_size
- txq
->tx_desc_count
;
879 if (entries_left
< MAX_SKB_FRAGS
+ 1)
880 netif_tx_stop_queue(nq
);
887 /* tx napi ******************************************************************/
888 static void txq_kick(struct tx_queue
*txq
)
890 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
891 struct netdev_queue
*nq
= netdev_get_tx_queue(mp
->dev
, txq
->index
);
895 __netif_tx_lock(nq
, smp_processor_id());
897 if (rdlp(mp
, TXQ_COMMAND
) & (1 << txq
->index
))
900 hw_desc_ptr
= rdlp(mp
, TXQ_CURRENT_DESC_PTR(txq
->index
));
901 expected_ptr
= (u32
)txq
->tx_desc_dma
+
902 txq
->tx_curr_desc
* sizeof(struct tx_desc
);
904 if (hw_desc_ptr
!= expected_ptr
)
908 __netif_tx_unlock(nq
);
910 mp
->work_tx_end
&= ~(1 << txq
->index
);
913 static int txq_reclaim(struct tx_queue
*txq
, int budget
, int force
)
915 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
916 struct netdev_queue
*nq
= netdev_get_tx_queue(mp
->dev
, txq
->index
);
919 __netif_tx_lock(nq
, smp_processor_id());
922 while (reclaimed
< budget
&& txq
->tx_desc_count
> 0) {
924 struct tx_desc
*desc
;
928 tx_index
= txq
->tx_used_desc
;
929 desc
= &txq
->tx_desc_area
[tx_index
];
930 cmd_sts
= desc
->cmd_sts
;
932 if (cmd_sts
& BUFFER_OWNED_BY_DMA
) {
935 desc
->cmd_sts
= cmd_sts
& ~BUFFER_OWNED_BY_DMA
;
938 txq
->tx_used_desc
= tx_index
+ 1;
939 if (txq
->tx_used_desc
== txq
->tx_ring_size
)
940 txq
->tx_used_desc
= 0;
943 txq
->tx_desc_count
--;
946 if (cmd_sts
& TX_LAST_DESC
)
947 skb
= __skb_dequeue(&txq
->tx_skb
);
949 if (cmd_sts
& ERROR_SUMMARY
) {
950 dev_printk(KERN_INFO
, &mp
->dev
->dev
, "tx error\n");
951 mp
->dev
->stats
.tx_errors
++;
954 if (cmd_sts
& TX_FIRST_DESC
) {
955 dma_unmap_single(NULL
, desc
->buf_ptr
,
956 desc
->byte_cnt
, DMA_TO_DEVICE
);
958 dma_unmap_page(NULL
, desc
->buf_ptr
,
959 desc
->byte_cnt
, DMA_TO_DEVICE
);
963 if (skb_queue_len(&mp
->rx_recycle
) <
965 skb_recycle_check(skb
, mp
->skb_size
))
966 __skb_queue_head(&mp
->rx_recycle
, skb
);
972 __netif_tx_unlock(nq
);
974 if (reclaimed
< budget
)
975 mp
->work_tx
&= ~(1 << txq
->index
);
981 /* tx rate control **********************************************************/
983 * Set total maximum TX rate (shared by all TX queues for this port)
984 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
986 static void tx_set_rate(struct mv643xx_eth_private
*mp
, int rate
, int burst
)
992 token_rate
= ((rate
/ 1000) * 64) / (mp
->shared
->t_clk
/ 1000);
993 if (token_rate
> 1023)
996 mtu
= (mp
->dev
->mtu
+ 255) >> 8;
1000 bucket_size
= (burst
+ 255) >> 8;
1001 if (bucket_size
> 65535)
1002 bucket_size
= 65535;
1004 switch (mp
->shared
->tx_bw_control
) {
1005 case TX_BW_CONTROL_OLD_LAYOUT
:
1006 wrlp(mp
, TX_BW_RATE
, token_rate
);
1007 wrlp(mp
, TX_BW_MTU
, mtu
);
1008 wrlp(mp
, TX_BW_BURST
, bucket_size
);
1010 case TX_BW_CONTROL_NEW_LAYOUT
:
1011 wrlp(mp
, TX_BW_RATE_MOVED
, token_rate
);
1012 wrlp(mp
, TX_BW_MTU_MOVED
, mtu
);
1013 wrlp(mp
, TX_BW_BURST_MOVED
, bucket_size
);
1018 static void txq_set_rate(struct tx_queue
*txq
, int rate
, int burst
)
1020 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
1024 token_rate
= ((rate
/ 1000) * 64) / (mp
->shared
->t_clk
/ 1000);
1025 if (token_rate
> 1023)
1028 bucket_size
= (burst
+ 255) >> 8;
1029 if (bucket_size
> 65535)
1030 bucket_size
= 65535;
1032 wrlp(mp
, TXQ_BW_TOKENS(txq
->index
), token_rate
<< 14);
1033 wrlp(mp
, TXQ_BW_CONF(txq
->index
), (bucket_size
<< 10) | token_rate
);
1036 static void txq_set_fixed_prio_mode(struct tx_queue
*txq
)
1038 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
1043 * Turn on fixed priority mode.
1046 switch (mp
->shared
->tx_bw_control
) {
1047 case TX_BW_CONTROL_OLD_LAYOUT
:
1048 off
= TXQ_FIX_PRIO_CONF
;
1050 case TX_BW_CONTROL_NEW_LAYOUT
:
1051 off
= TXQ_FIX_PRIO_CONF_MOVED
;
1056 val
= rdlp(mp
, off
);
1057 val
|= 1 << txq
->index
;
1062 static void txq_set_wrr(struct tx_queue
*txq
, int weight
)
1064 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
1069 * Turn off fixed priority mode.
1072 switch (mp
->shared
->tx_bw_control
) {
1073 case TX_BW_CONTROL_OLD_LAYOUT
:
1074 off
= TXQ_FIX_PRIO_CONF
;
1076 case TX_BW_CONTROL_NEW_LAYOUT
:
1077 off
= TXQ_FIX_PRIO_CONF_MOVED
;
1082 val
= rdlp(mp
, off
);
1083 val
&= ~(1 << txq
->index
);
1087 * Configure WRR weight for this queue.
1090 val
= rdlp(mp
, off
);
1091 val
= (val
& ~0xff) | (weight
& 0xff);
1092 wrlp(mp
, TXQ_BW_WRR_CONF(txq
->index
), val
);
1097 /* mii management interface *************************************************/
1098 static irqreturn_t
mv643xx_eth_err_irq(int irq
, void *dev_id
)
1100 struct mv643xx_eth_shared_private
*msp
= dev_id
;
1102 if (readl(msp
->base
+ ERR_INT_CAUSE
) & ERR_INT_SMI_DONE
) {
1103 writel(~ERR_INT_SMI_DONE
, msp
->base
+ ERR_INT_CAUSE
);
1104 wake_up(&msp
->smi_busy_wait
);
1111 static int smi_is_done(struct mv643xx_eth_shared_private
*msp
)
1113 return !(readl(msp
->base
+ SMI_REG
) & SMI_BUSY
);
1116 static int smi_wait_ready(struct mv643xx_eth_shared_private
*msp
)
1118 if (msp
->err_interrupt
== NO_IRQ
) {
1121 for (i
= 0; !smi_is_done(msp
); i
++) {
1130 if (!smi_is_done(msp
)) {
1131 wait_event_timeout(msp
->smi_busy_wait
, smi_is_done(msp
),
1132 msecs_to_jiffies(100));
1133 if (!smi_is_done(msp
))
1140 static int smi_bus_read(struct mii_bus
*bus
, int addr
, int reg
)
1142 struct mv643xx_eth_shared_private
*msp
= bus
->priv
;
1143 void __iomem
*smi_reg
= msp
->base
+ SMI_REG
;
1146 if (smi_wait_ready(msp
)) {
1147 printk(KERN_WARNING
"mv643xx_eth: SMI bus busy timeout\n");
1151 writel(SMI_OPCODE_READ
| (reg
<< 21) | (addr
<< 16), smi_reg
);
1153 if (smi_wait_ready(msp
)) {
1154 printk(KERN_WARNING
"mv643xx_eth: SMI bus busy timeout\n");
1158 ret
= readl(smi_reg
);
1159 if (!(ret
& SMI_READ_VALID
)) {
1160 printk(KERN_WARNING
"mv643xx_eth: SMI bus read not valid\n");
1164 return ret
& 0xffff;
1167 static int smi_bus_write(struct mii_bus
*bus
, int addr
, int reg
, u16 val
)
1169 struct mv643xx_eth_shared_private
*msp
= bus
->priv
;
1170 void __iomem
*smi_reg
= msp
->base
+ SMI_REG
;
1172 if (smi_wait_ready(msp
)) {
1173 printk(KERN_WARNING
"mv643xx_eth: SMI bus busy timeout\n");
1177 writel(SMI_OPCODE_WRITE
| (reg
<< 21) |
1178 (addr
<< 16) | (val
& 0xffff), smi_reg
);
1180 if (smi_wait_ready(msp
)) {
1181 printk(KERN_WARNING
"mv643xx_eth: SMI bus busy timeout\n");
1189 /* statistics ***************************************************************/
1190 static struct net_device_stats
*mv643xx_eth_get_stats(struct net_device
*dev
)
1192 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1193 struct net_device_stats
*stats
= &dev
->stats
;
1194 unsigned long tx_packets
= 0;
1195 unsigned long tx_bytes
= 0;
1196 unsigned long tx_dropped
= 0;
1199 for (i
= 0; i
< mp
->txq_count
; i
++) {
1200 struct tx_queue
*txq
= mp
->txq
+ i
;
1202 tx_packets
+= txq
->tx_packets
;
1203 tx_bytes
+= txq
->tx_bytes
;
1204 tx_dropped
+= txq
->tx_dropped
;
1207 stats
->tx_packets
= tx_packets
;
1208 stats
->tx_bytes
= tx_bytes
;
1209 stats
->tx_dropped
= tx_dropped
;
1214 static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private
*mp
)
1216 u32 lro_aggregated
= 0;
1217 u32 lro_flushed
= 0;
1218 u32 lro_no_desc
= 0;
1221 for (i
= 0; i
< mp
->rxq_count
; i
++) {
1222 struct rx_queue
*rxq
= mp
->rxq
+ i
;
1224 lro_aggregated
+= rxq
->lro_mgr
.stats
.aggregated
;
1225 lro_flushed
+= rxq
->lro_mgr
.stats
.flushed
;
1226 lro_no_desc
+= rxq
->lro_mgr
.stats
.no_desc
;
1229 mp
->lro_counters
.lro_aggregated
= lro_aggregated
;
1230 mp
->lro_counters
.lro_flushed
= lro_flushed
;
1231 mp
->lro_counters
.lro_no_desc
= lro_no_desc
;
1234 static inline u32
mib_read(struct mv643xx_eth_private
*mp
, int offset
)
1236 return rdl(mp
, MIB_COUNTERS(mp
->port_num
) + offset
);
1239 static void mib_counters_clear(struct mv643xx_eth_private
*mp
)
1243 for (i
= 0; i
< 0x80; i
+= 4)
1247 static void mib_counters_update(struct mv643xx_eth_private
*mp
)
1249 struct mib_counters
*p
= &mp
->mib_counters
;
1251 spin_lock_bh(&mp
->mib_counters_lock
);
1252 p
->good_octets_received
+= mib_read(mp
, 0x00);
1253 p
->bad_octets_received
+= mib_read(mp
, 0x08);
1254 p
->internal_mac_transmit_err
+= mib_read(mp
, 0x0c);
1255 p
->good_frames_received
+= mib_read(mp
, 0x10);
1256 p
->bad_frames_received
+= mib_read(mp
, 0x14);
1257 p
->broadcast_frames_received
+= mib_read(mp
, 0x18);
1258 p
->multicast_frames_received
+= mib_read(mp
, 0x1c);
1259 p
->frames_64_octets
+= mib_read(mp
, 0x20);
1260 p
->frames_65_to_127_octets
+= mib_read(mp
, 0x24);
1261 p
->frames_128_to_255_octets
+= mib_read(mp
, 0x28);
1262 p
->frames_256_to_511_octets
+= mib_read(mp
, 0x2c);
1263 p
->frames_512_to_1023_octets
+= mib_read(mp
, 0x30);
1264 p
->frames_1024_to_max_octets
+= mib_read(mp
, 0x34);
1265 p
->good_octets_sent
+= mib_read(mp
, 0x38);
1266 p
->good_frames_sent
+= mib_read(mp
, 0x40);
1267 p
->excessive_collision
+= mib_read(mp
, 0x44);
1268 p
->multicast_frames_sent
+= mib_read(mp
, 0x48);
1269 p
->broadcast_frames_sent
+= mib_read(mp
, 0x4c);
1270 p
->unrec_mac_control_received
+= mib_read(mp
, 0x50);
1271 p
->fc_sent
+= mib_read(mp
, 0x54);
1272 p
->good_fc_received
+= mib_read(mp
, 0x58);
1273 p
->bad_fc_received
+= mib_read(mp
, 0x5c);
1274 p
->undersize_received
+= mib_read(mp
, 0x60);
1275 p
->fragments_received
+= mib_read(mp
, 0x64);
1276 p
->oversize_received
+= mib_read(mp
, 0x68);
1277 p
->jabber_received
+= mib_read(mp
, 0x6c);
1278 p
->mac_receive_error
+= mib_read(mp
, 0x70);
1279 p
->bad_crc_event
+= mib_read(mp
, 0x74);
1280 p
->collision
+= mib_read(mp
, 0x78);
1281 p
->late_collision
+= mib_read(mp
, 0x7c);
1282 spin_unlock_bh(&mp
->mib_counters_lock
);
1284 mod_timer(&mp
->mib_counters_timer
, jiffies
+ 30 * HZ
);
1287 static void mib_counters_timer_wrapper(unsigned long _mp
)
1289 struct mv643xx_eth_private
*mp
= (void *)_mp
;
1291 mib_counters_update(mp
);
1295 /* interrupt coalescing *****************************************************/
1297 * Hardware coalescing parameters are set in units of 64 t_clk
1300 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1302 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1304 * In the ->set*() methods, we round the computed register value
1305 * to the nearest integer.
1307 static unsigned int get_rx_coal(struct mv643xx_eth_private
*mp
)
1309 u32 val
= rdlp(mp
, SDMA_CONFIG
);
1312 if (mp
->shared
->extended_rx_coal_limit
)
1313 temp
= ((val
& 0x02000000) >> 10) | ((val
& 0x003fff80) >> 7);
1315 temp
= (val
& 0x003fff00) >> 8;
1318 do_div(temp
, mp
->shared
->t_clk
);
1320 return (unsigned int)temp
;
1323 static void set_rx_coal(struct mv643xx_eth_private
*mp
, unsigned int usec
)
1328 temp
= (u64
)usec
* mp
->shared
->t_clk
;
1330 do_div(temp
, 64000000);
1332 val
= rdlp(mp
, SDMA_CONFIG
);
1333 if (mp
->shared
->extended_rx_coal_limit
) {
1337 val
|= (temp
& 0x8000) << 10;
1338 val
|= (temp
& 0x7fff) << 7;
1343 val
|= (temp
& 0x3fff) << 8;
1345 wrlp(mp
, SDMA_CONFIG
, val
);
1348 static unsigned int get_tx_coal(struct mv643xx_eth_private
*mp
)
1352 temp
= (rdlp(mp
, TX_FIFO_URGENT_THRESHOLD
) & 0x3fff0) >> 4;
1354 do_div(temp
, mp
->shared
->t_clk
);
1356 return (unsigned int)temp
;
1359 static void set_tx_coal(struct mv643xx_eth_private
*mp
, unsigned int usec
)
1363 temp
= (u64
)usec
* mp
->shared
->t_clk
;
1365 do_div(temp
, 64000000);
1370 wrlp(mp
, TX_FIFO_URGENT_THRESHOLD
, temp
<< 4);
1374 /* ethtool ******************************************************************/
1375 struct mv643xx_eth_stats
{
1376 char stat_string
[ETH_GSTRING_LEN
];
1383 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1384 offsetof(struct net_device, stats.m), -1 }
1386 #define MIBSTAT(m) \
1387 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1388 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1390 #define LROSTAT(m) \
1391 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1392 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1394 static const struct mv643xx_eth_stats mv643xx_eth_stats
[] = {
1403 MIBSTAT(good_octets_received
),
1404 MIBSTAT(bad_octets_received
),
1405 MIBSTAT(internal_mac_transmit_err
),
1406 MIBSTAT(good_frames_received
),
1407 MIBSTAT(bad_frames_received
),
1408 MIBSTAT(broadcast_frames_received
),
1409 MIBSTAT(multicast_frames_received
),
1410 MIBSTAT(frames_64_octets
),
1411 MIBSTAT(frames_65_to_127_octets
),
1412 MIBSTAT(frames_128_to_255_octets
),
1413 MIBSTAT(frames_256_to_511_octets
),
1414 MIBSTAT(frames_512_to_1023_octets
),
1415 MIBSTAT(frames_1024_to_max_octets
),
1416 MIBSTAT(good_octets_sent
),
1417 MIBSTAT(good_frames_sent
),
1418 MIBSTAT(excessive_collision
),
1419 MIBSTAT(multicast_frames_sent
),
1420 MIBSTAT(broadcast_frames_sent
),
1421 MIBSTAT(unrec_mac_control_received
),
1423 MIBSTAT(good_fc_received
),
1424 MIBSTAT(bad_fc_received
),
1425 MIBSTAT(undersize_received
),
1426 MIBSTAT(fragments_received
),
1427 MIBSTAT(oversize_received
),
1428 MIBSTAT(jabber_received
),
1429 MIBSTAT(mac_receive_error
),
1430 MIBSTAT(bad_crc_event
),
1432 MIBSTAT(late_collision
),
1433 LROSTAT(lro_aggregated
),
1434 LROSTAT(lro_flushed
),
1435 LROSTAT(lro_no_desc
),
1439 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private
*mp
,
1440 struct ethtool_cmd
*cmd
)
1444 err
= phy_read_status(mp
->phy
);
1446 err
= phy_ethtool_gset(mp
->phy
, cmd
);
1449 * The MAC does not support 1000baseT_Half.
1451 cmd
->supported
&= ~SUPPORTED_1000baseT_Half
;
1452 cmd
->advertising
&= ~ADVERTISED_1000baseT_Half
;
1458 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private
*mp
,
1459 struct ethtool_cmd
*cmd
)
1463 port_status
= rdlp(mp
, PORT_STATUS
);
1465 cmd
->supported
= SUPPORTED_MII
;
1466 cmd
->advertising
= ADVERTISED_MII
;
1467 switch (port_status
& PORT_SPEED_MASK
) {
1469 cmd
->speed
= SPEED_10
;
1471 case PORT_SPEED_100
:
1472 cmd
->speed
= SPEED_100
;
1474 case PORT_SPEED_1000
:
1475 cmd
->speed
= SPEED_1000
;
1481 cmd
->duplex
= (port_status
& FULL_DUPLEX
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1482 cmd
->port
= PORT_MII
;
1483 cmd
->phy_address
= 0;
1484 cmd
->transceiver
= XCVR_INTERNAL
;
1485 cmd
->autoneg
= AUTONEG_DISABLE
;
1493 mv643xx_eth_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1495 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1497 if (mp
->phy
!= NULL
)
1498 return mv643xx_eth_get_settings_phy(mp
, cmd
);
1500 return mv643xx_eth_get_settings_phyless(mp
, cmd
);
1504 mv643xx_eth_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1506 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1508 if (mp
->phy
== NULL
)
1512 * The MAC does not support 1000baseT_Half.
1514 cmd
->advertising
&= ~ADVERTISED_1000baseT_Half
;
1516 return phy_ethtool_sset(mp
->phy
, cmd
);
1519 static void mv643xx_eth_get_drvinfo(struct net_device
*dev
,
1520 struct ethtool_drvinfo
*drvinfo
)
1522 strncpy(drvinfo
->driver
, mv643xx_eth_driver_name
, 32);
1523 strncpy(drvinfo
->version
, mv643xx_eth_driver_version
, 32);
1524 strncpy(drvinfo
->fw_version
, "N/A", 32);
1525 strncpy(drvinfo
->bus_info
, "platform", 32);
1526 drvinfo
->n_stats
= ARRAY_SIZE(mv643xx_eth_stats
);
1529 static int mv643xx_eth_nway_reset(struct net_device
*dev
)
1531 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1533 if (mp
->phy
== NULL
)
1536 return genphy_restart_aneg(mp
->phy
);
1539 static u32
mv643xx_eth_get_link(struct net_device
*dev
)
1541 return !!netif_carrier_ok(dev
);
1545 mv643xx_eth_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
1547 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1549 ec
->rx_coalesce_usecs
= get_rx_coal(mp
);
1550 ec
->tx_coalesce_usecs
= get_tx_coal(mp
);
1556 mv643xx_eth_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
1558 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1560 set_rx_coal(mp
, ec
->rx_coalesce_usecs
);
1561 set_tx_coal(mp
, ec
->tx_coalesce_usecs
);
1567 mv643xx_eth_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*er
)
1569 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1571 er
->rx_max_pending
= 4096;
1572 er
->tx_max_pending
= 4096;
1573 er
->rx_mini_max_pending
= 0;
1574 er
->rx_jumbo_max_pending
= 0;
1576 er
->rx_pending
= mp
->rx_ring_size
;
1577 er
->tx_pending
= mp
->tx_ring_size
;
1578 er
->rx_mini_pending
= 0;
1579 er
->rx_jumbo_pending
= 0;
1583 mv643xx_eth_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*er
)
1585 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1587 if (er
->rx_mini_pending
|| er
->rx_jumbo_pending
)
1590 mp
->rx_ring_size
= er
->rx_pending
< 4096 ? er
->rx_pending
: 4096;
1591 mp
->tx_ring_size
= er
->tx_pending
< 4096 ? er
->tx_pending
: 4096;
1593 if (netif_running(dev
)) {
1594 mv643xx_eth_stop(dev
);
1595 if (mv643xx_eth_open(dev
)) {
1596 dev_printk(KERN_ERR
, &dev
->dev
,
1597 "fatal error on re-opening device after "
1598 "ring param change\n");
1607 mv643xx_eth_get_rx_csum(struct net_device
*dev
)
1609 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1611 return !!(rdlp(mp
, PORT_CONFIG
) & 0x02000000);
1615 mv643xx_eth_set_rx_csum(struct net_device
*dev
, u32 rx_csum
)
1617 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1619 wrlp(mp
, PORT_CONFIG
, rx_csum
? 0x02000000 : 0x00000000);
1624 static void mv643xx_eth_get_strings(struct net_device
*dev
,
1625 uint32_t stringset
, uint8_t *data
)
1629 if (stringset
== ETH_SS_STATS
) {
1630 for (i
= 0; i
< ARRAY_SIZE(mv643xx_eth_stats
); i
++) {
1631 memcpy(data
+ i
* ETH_GSTRING_LEN
,
1632 mv643xx_eth_stats
[i
].stat_string
,
1638 static void mv643xx_eth_get_ethtool_stats(struct net_device
*dev
,
1639 struct ethtool_stats
*stats
,
1642 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1645 mv643xx_eth_get_stats(dev
);
1646 mib_counters_update(mp
);
1647 mv643xx_eth_grab_lro_stats(mp
);
1649 for (i
= 0; i
< ARRAY_SIZE(mv643xx_eth_stats
); i
++) {
1650 const struct mv643xx_eth_stats
*stat
;
1653 stat
= mv643xx_eth_stats
+ i
;
1655 if (stat
->netdev_off
>= 0)
1656 p
= ((void *)mp
->dev
) + stat
->netdev_off
;
1658 p
= ((void *)mp
) + stat
->mp_off
;
1660 data
[i
] = (stat
->sizeof_stat
== 8) ?
1661 *(uint64_t *)p
: *(uint32_t *)p
;
1665 static int mv643xx_eth_get_sset_count(struct net_device
*dev
, int sset
)
1667 if (sset
== ETH_SS_STATS
)
1668 return ARRAY_SIZE(mv643xx_eth_stats
);
1673 static const struct ethtool_ops mv643xx_eth_ethtool_ops
= {
1674 .get_settings
= mv643xx_eth_get_settings
,
1675 .set_settings
= mv643xx_eth_set_settings
,
1676 .get_drvinfo
= mv643xx_eth_get_drvinfo
,
1677 .nway_reset
= mv643xx_eth_nway_reset
,
1678 .get_link
= mv643xx_eth_get_link
,
1679 .get_coalesce
= mv643xx_eth_get_coalesce
,
1680 .set_coalesce
= mv643xx_eth_set_coalesce
,
1681 .get_ringparam
= mv643xx_eth_get_ringparam
,
1682 .set_ringparam
= mv643xx_eth_set_ringparam
,
1683 .get_rx_csum
= mv643xx_eth_get_rx_csum
,
1684 .set_rx_csum
= mv643xx_eth_set_rx_csum
,
1685 .set_tx_csum
= ethtool_op_set_tx_csum
,
1686 .set_sg
= ethtool_op_set_sg
,
1687 .get_strings
= mv643xx_eth_get_strings
,
1688 .get_ethtool_stats
= mv643xx_eth_get_ethtool_stats
,
1689 .get_flags
= ethtool_op_get_flags
,
1690 .set_flags
= ethtool_op_set_flags
,
1691 .get_sset_count
= mv643xx_eth_get_sset_count
,
1695 /* address handling *********************************************************/
1696 static void uc_addr_get(struct mv643xx_eth_private
*mp
, unsigned char *addr
)
1698 unsigned int mac_h
= rdlp(mp
, MAC_ADDR_HIGH
);
1699 unsigned int mac_l
= rdlp(mp
, MAC_ADDR_LOW
);
1701 addr
[0] = (mac_h
>> 24) & 0xff;
1702 addr
[1] = (mac_h
>> 16) & 0xff;
1703 addr
[2] = (mac_h
>> 8) & 0xff;
1704 addr
[3] = mac_h
& 0xff;
1705 addr
[4] = (mac_l
>> 8) & 0xff;
1706 addr
[5] = mac_l
& 0xff;
1709 static void uc_addr_set(struct mv643xx_eth_private
*mp
, unsigned char *addr
)
1711 wrlp(mp
, MAC_ADDR_HIGH
,
1712 (addr
[0] << 24) | (addr
[1] << 16) | (addr
[2] << 8) | addr
[3]);
1713 wrlp(mp
, MAC_ADDR_LOW
, (addr
[4] << 8) | addr
[5]);
1716 static u32
uc_addr_filter_mask(struct net_device
*dev
)
1718 struct dev_addr_list
*uc_ptr
;
1721 if (dev
->flags
& IFF_PROMISC
)
1724 nibbles
= 1 << (dev
->dev_addr
[5] & 0x0f);
1725 for (uc_ptr
= dev
->uc_list
; uc_ptr
!= NULL
; uc_ptr
= uc_ptr
->next
) {
1726 if (memcmp(dev
->dev_addr
, uc_ptr
->da_addr
, 5))
1728 if ((dev
->dev_addr
[5] ^ uc_ptr
->da_addr
[5]) & 0xf0)
1731 nibbles
|= 1 << (uc_ptr
->da_addr
[5] & 0x0f);
1737 static void mv643xx_eth_program_unicast_filter(struct net_device
*dev
)
1739 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1744 uc_addr_set(mp
, dev
->dev_addr
);
1746 port_config
= rdlp(mp
, PORT_CONFIG
);
1747 nibbles
= uc_addr_filter_mask(dev
);
1749 port_config
|= UNICAST_PROMISCUOUS_MODE
;
1750 wrlp(mp
, PORT_CONFIG
, port_config
);
1754 for (i
= 0; i
< 16; i
+= 4) {
1755 int off
= UNICAST_TABLE(mp
->port_num
) + i
;
1772 port_config
&= ~UNICAST_PROMISCUOUS_MODE
;
1773 wrlp(mp
, PORT_CONFIG
, port_config
);
1776 static int addr_crc(unsigned char *addr
)
1781 for (i
= 0; i
< 6; i
++) {
1784 crc
= (crc
^ addr
[i
]) << 8;
1785 for (j
= 7; j
>= 0; j
--) {
1786 if (crc
& (0x100 << j
))
1794 static void mv643xx_eth_program_multicast_filter(struct net_device
*dev
)
1796 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1799 struct dev_addr_list
*addr
;
1802 if (dev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
)) {
1807 port_num
= mp
->port_num
;
1808 accept
= 0x01010101;
1809 for (i
= 0; i
< 0x100; i
+= 4) {
1810 wrl(mp
, SPECIAL_MCAST_TABLE(port_num
) + i
, accept
);
1811 wrl(mp
, OTHER_MCAST_TABLE(port_num
) + i
, accept
);
1816 mc_spec
= kmalloc(0x200, GFP_ATOMIC
);
1817 if (mc_spec
== NULL
)
1819 mc_other
= mc_spec
+ (0x100 >> 2);
1821 memset(mc_spec
, 0, 0x100);
1822 memset(mc_other
, 0, 0x100);
1824 for (addr
= dev
->mc_list
; addr
!= NULL
; addr
= addr
->next
) {
1825 u8
*a
= addr
->da_addr
;
1829 if (memcmp(a
, "\x01\x00\x5e\x00\x00", 5) == 0) {
1834 entry
= addr_crc(a
);
1837 table
[entry
>> 2] |= 1 << (8 * (entry
& 3));
1840 for (i
= 0; i
< 0x100; i
+= 4) {
1841 wrl(mp
, SPECIAL_MCAST_TABLE(mp
->port_num
) + i
, mc_spec
[i
>> 2]);
1842 wrl(mp
, OTHER_MCAST_TABLE(mp
->port_num
) + i
, mc_other
[i
>> 2]);
1848 static void mv643xx_eth_set_rx_mode(struct net_device
*dev
)
1850 mv643xx_eth_program_unicast_filter(dev
);
1851 mv643xx_eth_program_multicast_filter(dev
);
1854 static int mv643xx_eth_set_mac_address(struct net_device
*dev
, void *addr
)
1856 struct sockaddr
*sa
= addr
;
1858 memcpy(dev
->dev_addr
, sa
->sa_data
, ETH_ALEN
);
1860 netif_addr_lock_bh(dev
);
1861 mv643xx_eth_program_unicast_filter(dev
);
1862 netif_addr_unlock_bh(dev
);
1868 /* rx/tx queue initialisation ***********************************************/
1869 static int rxq_init(struct mv643xx_eth_private
*mp
, int index
)
1871 struct rx_queue
*rxq
= mp
->rxq
+ index
;
1872 struct rx_desc
*rx_desc
;
1878 rxq
->rx_ring_size
= mp
->rx_ring_size
;
1880 rxq
->rx_desc_count
= 0;
1881 rxq
->rx_curr_desc
= 0;
1882 rxq
->rx_used_desc
= 0;
1884 size
= rxq
->rx_ring_size
* sizeof(struct rx_desc
);
1886 if (index
== 0 && size
<= mp
->rx_desc_sram_size
) {
1887 rxq
->rx_desc_area
= ioremap(mp
->rx_desc_sram_addr
,
1888 mp
->rx_desc_sram_size
);
1889 rxq
->rx_desc_dma
= mp
->rx_desc_sram_addr
;
1891 rxq
->rx_desc_area
= dma_alloc_coherent(NULL
, size
,
1896 if (rxq
->rx_desc_area
== NULL
) {
1897 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
1898 "can't allocate rx ring (%d bytes)\n", size
);
1901 memset(rxq
->rx_desc_area
, 0, size
);
1903 rxq
->rx_desc_area_size
= size
;
1904 rxq
->rx_skb
= kmalloc(rxq
->rx_ring_size
* sizeof(*rxq
->rx_skb
),
1906 if (rxq
->rx_skb
== NULL
) {
1907 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
1908 "can't allocate rx skb ring\n");
1912 rx_desc
= (struct rx_desc
*)rxq
->rx_desc_area
;
1913 for (i
= 0; i
< rxq
->rx_ring_size
; i
++) {
1917 if (nexti
== rxq
->rx_ring_size
)
1920 rx_desc
[i
].next_desc_ptr
= rxq
->rx_desc_dma
+
1921 nexti
* sizeof(struct rx_desc
);
1924 rxq
->lro_mgr
.dev
= mp
->dev
;
1925 memset(&rxq
->lro_mgr
.stats
, 0, sizeof(rxq
->lro_mgr
.stats
));
1926 rxq
->lro_mgr
.features
= LRO_F_NAPI
;
1927 rxq
->lro_mgr
.ip_summed
= CHECKSUM_UNNECESSARY
;
1928 rxq
->lro_mgr
.ip_summed_aggr
= CHECKSUM_UNNECESSARY
;
1929 rxq
->lro_mgr
.max_desc
= ARRAY_SIZE(rxq
->lro_arr
);
1930 rxq
->lro_mgr
.max_aggr
= 32;
1931 rxq
->lro_mgr
.frag_align_pad
= 0;
1932 rxq
->lro_mgr
.lro_arr
= rxq
->lro_arr
;
1933 rxq
->lro_mgr
.get_skb_header
= mv643xx_get_skb_header
;
1935 memset(&rxq
->lro_arr
, 0, sizeof(rxq
->lro_arr
));
1941 if (index
== 0 && size
<= mp
->rx_desc_sram_size
)
1942 iounmap(rxq
->rx_desc_area
);
1944 dma_free_coherent(NULL
, size
,
1952 static void rxq_deinit(struct rx_queue
*rxq
)
1954 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
1959 for (i
= 0; i
< rxq
->rx_ring_size
; i
++) {
1960 if (rxq
->rx_skb
[i
]) {
1961 dev_kfree_skb(rxq
->rx_skb
[i
]);
1962 rxq
->rx_desc_count
--;
1966 if (rxq
->rx_desc_count
) {
1967 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
1968 "error freeing rx ring -- %d skbs stuck\n",
1969 rxq
->rx_desc_count
);
1972 if (rxq
->index
== 0 &&
1973 rxq
->rx_desc_area_size
<= mp
->rx_desc_sram_size
)
1974 iounmap(rxq
->rx_desc_area
);
1976 dma_free_coherent(NULL
, rxq
->rx_desc_area_size
,
1977 rxq
->rx_desc_area
, rxq
->rx_desc_dma
);
1982 static int txq_init(struct mv643xx_eth_private
*mp
, int index
)
1984 struct tx_queue
*txq
= mp
->txq
+ index
;
1985 struct tx_desc
*tx_desc
;
1991 txq
->tx_ring_size
= mp
->tx_ring_size
;
1993 txq
->tx_desc_count
= 0;
1994 txq
->tx_curr_desc
= 0;
1995 txq
->tx_used_desc
= 0;
1997 size
= txq
->tx_ring_size
* sizeof(struct tx_desc
);
1999 if (index
== 0 && size
<= mp
->tx_desc_sram_size
) {
2000 txq
->tx_desc_area
= ioremap(mp
->tx_desc_sram_addr
,
2001 mp
->tx_desc_sram_size
);
2002 txq
->tx_desc_dma
= mp
->tx_desc_sram_addr
;
2004 txq
->tx_desc_area
= dma_alloc_coherent(NULL
, size
,
2009 if (txq
->tx_desc_area
== NULL
) {
2010 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
2011 "can't allocate tx ring (%d bytes)\n", size
);
2014 memset(txq
->tx_desc_area
, 0, size
);
2016 txq
->tx_desc_area_size
= size
;
2018 tx_desc
= (struct tx_desc
*)txq
->tx_desc_area
;
2019 for (i
= 0; i
< txq
->tx_ring_size
; i
++) {
2020 struct tx_desc
*txd
= tx_desc
+ i
;
2024 if (nexti
== txq
->tx_ring_size
)
2028 txd
->next_desc_ptr
= txq
->tx_desc_dma
+
2029 nexti
* sizeof(struct tx_desc
);
2032 skb_queue_head_init(&txq
->tx_skb
);
2037 static void txq_deinit(struct tx_queue
*txq
)
2039 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
2042 txq_reclaim(txq
, txq
->tx_ring_size
, 1);
2044 BUG_ON(txq
->tx_used_desc
!= txq
->tx_curr_desc
);
2046 if (txq
->index
== 0 &&
2047 txq
->tx_desc_area_size
<= mp
->tx_desc_sram_size
)
2048 iounmap(txq
->tx_desc_area
);
2050 dma_free_coherent(NULL
, txq
->tx_desc_area_size
,
2051 txq
->tx_desc_area
, txq
->tx_desc_dma
);
2055 /* netdev ops and related ***************************************************/
2056 static int mv643xx_eth_collect_events(struct mv643xx_eth_private
*mp
)
2061 int_cause
= rdlp(mp
, INT_CAUSE
) & (INT_TX_END
| INT_RX
| INT_EXT
);
2066 if (int_cause
& INT_EXT
)
2067 int_cause_ext
= rdlp(mp
, INT_CAUSE_EXT
);
2069 int_cause
&= INT_TX_END
| INT_RX
;
2071 wrlp(mp
, INT_CAUSE
, ~int_cause
);
2072 mp
->work_tx_end
|= ((int_cause
& INT_TX_END
) >> 19) &
2073 ~(rdlp(mp
, TXQ_COMMAND
) & 0xff);
2074 mp
->work_rx
|= (int_cause
& INT_RX
) >> 2;
2077 int_cause_ext
&= INT_EXT_LINK_PHY
| INT_EXT_TX
;
2078 if (int_cause_ext
) {
2079 wrlp(mp
, INT_CAUSE_EXT
, ~int_cause_ext
);
2080 if (int_cause_ext
& INT_EXT_LINK_PHY
)
2082 mp
->work_tx
|= int_cause_ext
& INT_EXT_TX
;
2088 static irqreturn_t
mv643xx_eth_irq(int irq
, void *dev_id
)
2090 struct net_device
*dev
= (struct net_device
*)dev_id
;
2091 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2093 if (unlikely(!mv643xx_eth_collect_events(mp
)))
2096 wrlp(mp
, INT_MASK
, 0);
2097 napi_schedule(&mp
->napi
);
2102 static void handle_link_event(struct mv643xx_eth_private
*mp
)
2104 struct net_device
*dev
= mp
->dev
;
2110 port_status
= rdlp(mp
, PORT_STATUS
);
2111 if (!(port_status
& LINK_UP
)) {
2112 if (netif_carrier_ok(dev
)) {
2115 printk(KERN_INFO
"%s: link down\n", dev
->name
);
2117 netif_carrier_off(dev
);
2119 for (i
= 0; i
< mp
->txq_count
; i
++) {
2120 struct tx_queue
*txq
= mp
->txq
+ i
;
2122 txq_reclaim(txq
, txq
->tx_ring_size
, 1);
2123 txq_reset_hw_ptr(txq
);
2129 switch (port_status
& PORT_SPEED_MASK
) {
2133 case PORT_SPEED_100
:
2136 case PORT_SPEED_1000
:
2143 duplex
= (port_status
& FULL_DUPLEX
) ? 1 : 0;
2144 fc
= (port_status
& FLOW_CONTROL_ENABLED
) ? 1 : 0;
2146 printk(KERN_INFO
"%s: link up, %d Mb/s, %s duplex, "
2147 "flow control %sabled\n", dev
->name
,
2148 speed
, duplex
? "full" : "half",
2151 if (!netif_carrier_ok(dev
))
2152 netif_carrier_on(dev
);
2155 static int mv643xx_eth_poll(struct napi_struct
*napi
, int budget
)
2157 struct mv643xx_eth_private
*mp
;
2160 mp
= container_of(napi
, struct mv643xx_eth_private
, napi
);
2162 if (unlikely(mp
->oom
)) {
2164 del_timer(&mp
->rx_oom
);
2168 while (work_done
< budget
) {
2173 if (mp
->work_link
) {
2175 handle_link_event(mp
);
2180 queue_mask
= mp
->work_tx
| mp
->work_tx_end
| mp
->work_rx
;
2181 if (likely(!mp
->oom
))
2182 queue_mask
|= mp
->work_rx_refill
;
2185 if (mv643xx_eth_collect_events(mp
))
2190 queue
= fls(queue_mask
) - 1;
2191 queue_mask
= 1 << queue
;
2193 work_tbd
= budget
- work_done
;
2197 if (mp
->work_tx_end
& queue_mask
) {
2198 txq_kick(mp
->txq
+ queue
);
2199 } else if (mp
->work_tx
& queue_mask
) {
2200 work_done
+= txq_reclaim(mp
->txq
+ queue
, work_tbd
, 0);
2201 txq_maybe_wake(mp
->txq
+ queue
);
2202 } else if (mp
->work_rx
& queue_mask
) {
2203 work_done
+= rxq_process(mp
->rxq
+ queue
, work_tbd
);
2204 } else if (!mp
->oom
&& (mp
->work_rx_refill
& queue_mask
)) {
2205 work_done
+= rxq_refill(mp
->rxq
+ queue
, work_tbd
);
2211 if (work_done
< budget
) {
2213 mod_timer(&mp
->rx_oom
, jiffies
+ (HZ
/ 10));
2214 napi_complete(napi
);
2215 wrlp(mp
, INT_MASK
, INT_TX_END
| INT_RX
| INT_EXT
);
2221 static inline void oom_timer_wrapper(unsigned long data
)
2223 struct mv643xx_eth_private
*mp
= (void *)data
;
2225 napi_schedule(&mp
->napi
);
2228 static void phy_reset(struct mv643xx_eth_private
*mp
)
2232 data
= phy_read(mp
->phy
, MII_BMCR
);
2237 if (phy_write(mp
->phy
, MII_BMCR
, data
) < 0)
2241 data
= phy_read(mp
->phy
, MII_BMCR
);
2242 } while (data
>= 0 && data
& BMCR_RESET
);
2245 static void port_start(struct mv643xx_eth_private
*mp
)
2251 * Perform PHY reset, if there is a PHY.
2253 if (mp
->phy
!= NULL
) {
2254 struct ethtool_cmd cmd
;
2256 mv643xx_eth_get_settings(mp
->dev
, &cmd
);
2258 mv643xx_eth_set_settings(mp
->dev
, &cmd
);
2262 * Configure basic link parameters.
2264 pscr
= rdlp(mp
, PORT_SERIAL_CONTROL
);
2266 pscr
|= SERIAL_PORT_ENABLE
;
2267 wrlp(mp
, PORT_SERIAL_CONTROL
, pscr
);
2269 pscr
|= DO_NOT_FORCE_LINK_FAIL
;
2270 if (mp
->phy
== NULL
)
2271 pscr
|= FORCE_LINK_PASS
;
2272 wrlp(mp
, PORT_SERIAL_CONTROL
, pscr
);
2275 * Configure TX path and queues.
2277 tx_set_rate(mp
, 1000000000, 16777216);
2278 for (i
= 0; i
< mp
->txq_count
; i
++) {
2279 struct tx_queue
*txq
= mp
->txq
+ i
;
2281 txq_reset_hw_ptr(txq
);
2282 txq_set_rate(txq
, 1000000000, 16777216);
2283 txq_set_fixed_prio_mode(txq
);
2287 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2288 * frames to RX queue #0, and include the pseudo-header when
2289 * calculating receive checksums.
2291 wrlp(mp
, PORT_CONFIG
, 0x02000000);
2294 * Treat BPDUs as normal multicasts, and disable partition mode.
2296 wrlp(mp
, PORT_CONFIG_EXT
, 0x00000000);
2299 * Add configured unicast addresses to address filter table.
2301 mv643xx_eth_program_unicast_filter(mp
->dev
);
2304 * Enable the receive queues.
2306 for (i
= 0; i
< mp
->rxq_count
; i
++) {
2307 struct rx_queue
*rxq
= mp
->rxq
+ i
;
2310 addr
= (u32
)rxq
->rx_desc_dma
;
2311 addr
+= rxq
->rx_curr_desc
* sizeof(struct rx_desc
);
2312 wrlp(mp
, RXQ_CURRENT_DESC_PTR(i
), addr
);
2318 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private
*mp
)
2323 * Reserve 2+14 bytes for an ethernet header (the hardware
2324 * automatically prepends 2 bytes of dummy data to each
2325 * received packet), 16 bytes for up to four VLAN tags, and
2326 * 4 bytes for the trailing FCS -- 36 bytes total.
2328 skb_size
= mp
->dev
->mtu
+ 36;
2331 * Make sure that the skb size is a multiple of 8 bytes, as
2332 * the lower three bits of the receive descriptor's buffer
2333 * size field are ignored by the hardware.
2335 mp
->skb_size
= (skb_size
+ 7) & ~7;
2338 * If NET_SKB_PAD is smaller than a cache line,
2339 * netdev_alloc_skb() will cause skb->data to be misaligned
2340 * to a cache line boundary. If this is the case, include
2341 * some extra space to allow re-aligning the data area.
2343 mp
->skb_size
+= SKB_DMA_REALIGN
;
2346 static int mv643xx_eth_open(struct net_device
*dev
)
2348 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2352 wrlp(mp
, INT_CAUSE
, 0);
2353 wrlp(mp
, INT_CAUSE_EXT
, 0);
2354 rdlp(mp
, INT_CAUSE_EXT
);
2356 err
= request_irq(dev
->irq
, mv643xx_eth_irq
,
2357 IRQF_SHARED
, dev
->name
, dev
);
2359 dev_printk(KERN_ERR
, &dev
->dev
, "can't assign irq\n");
2363 mv643xx_eth_recalc_skb_size(mp
);
2365 napi_enable(&mp
->napi
);
2367 skb_queue_head_init(&mp
->rx_recycle
);
2369 for (i
= 0; i
< mp
->rxq_count
; i
++) {
2370 err
= rxq_init(mp
, i
);
2373 rxq_deinit(mp
->rxq
+ i
);
2377 rxq_refill(mp
->rxq
+ i
, INT_MAX
);
2381 mp
->rx_oom
.expires
= jiffies
+ (HZ
/ 10);
2382 add_timer(&mp
->rx_oom
);
2385 for (i
= 0; i
< mp
->txq_count
; i
++) {
2386 err
= txq_init(mp
, i
);
2389 txq_deinit(mp
->txq
+ i
);
2396 wrlp(mp
, INT_MASK_EXT
, INT_EXT_LINK_PHY
| INT_EXT_TX
);
2397 wrlp(mp
, INT_MASK
, INT_TX_END
| INT_RX
| INT_EXT
);
2403 for (i
= 0; i
< mp
->rxq_count
; i
++)
2404 rxq_deinit(mp
->rxq
+ i
);
2406 free_irq(dev
->irq
, dev
);
2411 static void port_reset(struct mv643xx_eth_private
*mp
)
2416 for (i
= 0; i
< mp
->rxq_count
; i
++)
2417 rxq_disable(mp
->rxq
+ i
);
2418 for (i
= 0; i
< mp
->txq_count
; i
++)
2419 txq_disable(mp
->txq
+ i
);
2422 u32 ps
= rdlp(mp
, PORT_STATUS
);
2424 if ((ps
& (TX_IN_PROGRESS
| TX_FIFO_EMPTY
)) == TX_FIFO_EMPTY
)
2429 /* Reset the Enable bit in the Configuration Register */
2430 data
= rdlp(mp
, PORT_SERIAL_CONTROL
);
2431 data
&= ~(SERIAL_PORT_ENABLE
|
2432 DO_NOT_FORCE_LINK_FAIL
|
2434 wrlp(mp
, PORT_SERIAL_CONTROL
, data
);
2437 static int mv643xx_eth_stop(struct net_device
*dev
)
2439 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2442 wrlp(mp
, INT_MASK_EXT
, 0x00000000);
2443 wrlp(mp
, INT_MASK
, 0x00000000);
2446 napi_disable(&mp
->napi
);
2448 del_timer_sync(&mp
->rx_oom
);
2450 netif_carrier_off(dev
);
2452 free_irq(dev
->irq
, dev
);
2455 mv643xx_eth_get_stats(dev
);
2456 mib_counters_update(mp
);
2457 del_timer_sync(&mp
->mib_counters_timer
);
2459 skb_queue_purge(&mp
->rx_recycle
);
2461 for (i
= 0; i
< mp
->rxq_count
; i
++)
2462 rxq_deinit(mp
->rxq
+ i
);
2463 for (i
= 0; i
< mp
->txq_count
; i
++)
2464 txq_deinit(mp
->txq
+ i
);
2469 static int mv643xx_eth_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2471 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2473 if (mp
->phy
!= NULL
)
2474 return phy_mii_ioctl(mp
->phy
, if_mii(ifr
), cmd
);
2479 static int mv643xx_eth_change_mtu(struct net_device
*dev
, int new_mtu
)
2481 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2483 if (new_mtu
< 64 || new_mtu
> 9500)
2487 mv643xx_eth_recalc_skb_size(mp
);
2488 tx_set_rate(mp
, 1000000000, 16777216);
2490 if (!netif_running(dev
))
2494 * Stop and then re-open the interface. This will allocate RX
2495 * skbs of the new MTU.
2496 * There is a possible danger that the open will not succeed,
2497 * due to memory being full.
2499 mv643xx_eth_stop(dev
);
2500 if (mv643xx_eth_open(dev
)) {
2501 dev_printk(KERN_ERR
, &dev
->dev
,
2502 "fatal error on re-opening device after "
2509 static void tx_timeout_task(struct work_struct
*ugly
)
2511 struct mv643xx_eth_private
*mp
;
2513 mp
= container_of(ugly
, struct mv643xx_eth_private
, tx_timeout_task
);
2514 if (netif_running(mp
->dev
)) {
2515 netif_tx_stop_all_queues(mp
->dev
);
2518 netif_tx_wake_all_queues(mp
->dev
);
2522 static void mv643xx_eth_tx_timeout(struct net_device
*dev
)
2524 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2526 dev_printk(KERN_INFO
, &dev
->dev
, "tx timeout\n");
2528 schedule_work(&mp
->tx_timeout_task
);
2531 #ifdef CONFIG_NET_POLL_CONTROLLER
2532 static void mv643xx_eth_netpoll(struct net_device
*dev
)
2534 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2536 wrlp(mp
, INT_MASK
, 0x00000000);
2539 mv643xx_eth_irq(dev
->irq
, dev
);
2541 wrlp(mp
, INT_MASK
, INT_TX_END
| INT_RX
| INT_EXT
);
2546 /* platform glue ************************************************************/
2548 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private
*msp
,
2549 struct mbus_dram_target_info
*dram
)
2551 void __iomem
*base
= msp
->base
;
2556 for (i
= 0; i
< 6; i
++) {
2557 writel(0, base
+ WINDOW_BASE(i
));
2558 writel(0, base
+ WINDOW_SIZE(i
));
2560 writel(0, base
+ WINDOW_REMAP_HIGH(i
));
2566 for (i
= 0; i
< dram
->num_cs
; i
++) {
2567 struct mbus_dram_window
*cs
= dram
->cs
+ i
;
2569 writel((cs
->base
& 0xffff0000) |
2570 (cs
->mbus_attr
<< 8) |
2571 dram
->mbus_dram_target_id
, base
+ WINDOW_BASE(i
));
2572 writel((cs
->size
- 1) & 0xffff0000, base
+ WINDOW_SIZE(i
));
2574 win_enable
&= ~(1 << i
);
2575 win_protect
|= 3 << (2 * i
);
2578 writel(win_enable
, base
+ WINDOW_BAR_ENABLE
);
2579 msp
->win_protect
= win_protect
;
2582 static void infer_hw_params(struct mv643xx_eth_shared_private
*msp
)
2585 * Check whether we have a 14-bit coal limit field in bits
2586 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2587 * SDMA config register.
2589 writel(0x02000000, msp
->base
+ 0x0400 + SDMA_CONFIG
);
2590 if (readl(msp
->base
+ 0x0400 + SDMA_CONFIG
) & 0x02000000)
2591 msp
->extended_rx_coal_limit
= 1;
2593 msp
->extended_rx_coal_limit
= 0;
2596 * Check whether the MAC supports TX rate control, and if
2597 * yes, whether its associated registers are in the old or
2600 writel(1, msp
->base
+ 0x0400 + TX_BW_MTU_MOVED
);
2601 if (readl(msp
->base
+ 0x0400 + TX_BW_MTU_MOVED
) & 1) {
2602 msp
->tx_bw_control
= TX_BW_CONTROL_NEW_LAYOUT
;
2604 writel(7, msp
->base
+ 0x0400 + TX_BW_RATE
);
2605 if (readl(msp
->base
+ 0x0400 + TX_BW_RATE
) & 7)
2606 msp
->tx_bw_control
= TX_BW_CONTROL_OLD_LAYOUT
;
2608 msp
->tx_bw_control
= TX_BW_CONTROL_ABSENT
;
2612 static int mv643xx_eth_shared_probe(struct platform_device
*pdev
)
2614 static int mv643xx_eth_version_printed
;
2615 struct mv643xx_eth_shared_platform_data
*pd
= pdev
->dev
.platform_data
;
2616 struct mv643xx_eth_shared_private
*msp
;
2617 struct resource
*res
;
2620 if (!mv643xx_eth_version_printed
++)
2621 printk(KERN_NOTICE
"MV-643xx 10/100/1000 ethernet "
2622 "driver version %s\n", mv643xx_eth_driver_version
);
2625 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2630 msp
= kmalloc(sizeof(*msp
), GFP_KERNEL
);
2633 memset(msp
, 0, sizeof(*msp
));
2635 msp
->base
= ioremap(res
->start
, res
->end
- res
->start
+ 1);
2636 if (msp
->base
== NULL
)
2640 * Set up and register SMI bus.
2642 if (pd
== NULL
|| pd
->shared_smi
== NULL
) {
2643 msp
->smi_bus
= mdiobus_alloc();
2644 if (msp
->smi_bus
== NULL
)
2647 msp
->smi_bus
->priv
= msp
;
2648 msp
->smi_bus
->name
= "mv643xx_eth smi";
2649 msp
->smi_bus
->read
= smi_bus_read
;
2650 msp
->smi_bus
->write
= smi_bus_write
,
2651 snprintf(msp
->smi_bus
->id
, MII_BUS_ID_SIZE
, "%d", pdev
->id
);
2652 msp
->smi_bus
->parent
= &pdev
->dev
;
2653 msp
->smi_bus
->phy_mask
= 0xffffffff;
2654 if (mdiobus_register(msp
->smi_bus
) < 0)
2655 goto out_free_mii_bus
;
2658 msp
->smi
= platform_get_drvdata(pd
->shared_smi
);
2661 msp
->err_interrupt
= NO_IRQ
;
2662 init_waitqueue_head(&msp
->smi_busy_wait
);
2665 * Check whether the error interrupt is hooked up.
2667 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
2671 err
= request_irq(res
->start
, mv643xx_eth_err_irq
,
2672 IRQF_SHARED
, "mv643xx_eth", msp
);
2674 writel(ERR_INT_SMI_DONE
, msp
->base
+ ERR_INT_MASK
);
2675 msp
->err_interrupt
= res
->start
;
2680 * (Re-)program MBUS remapping windows if we are asked to.
2682 if (pd
!= NULL
&& pd
->dram
!= NULL
)
2683 mv643xx_eth_conf_mbus_windows(msp
, pd
->dram
);
2686 * Detect hardware parameters.
2688 msp
->t_clk
= (pd
!= NULL
&& pd
->t_clk
!= 0) ? pd
->t_clk
: 133000000;
2689 infer_hw_params(msp
);
2691 platform_set_drvdata(pdev
, msp
);
2696 mdiobus_free(msp
->smi_bus
);
2705 static int mv643xx_eth_shared_remove(struct platform_device
*pdev
)
2707 struct mv643xx_eth_shared_private
*msp
= platform_get_drvdata(pdev
);
2708 struct mv643xx_eth_shared_platform_data
*pd
= pdev
->dev
.platform_data
;
2710 if (pd
== NULL
|| pd
->shared_smi
== NULL
) {
2711 mdiobus_unregister(msp
->smi_bus
);
2712 mdiobus_free(msp
->smi_bus
);
2714 if (msp
->err_interrupt
!= NO_IRQ
)
2715 free_irq(msp
->err_interrupt
, msp
);
2722 static struct platform_driver mv643xx_eth_shared_driver
= {
2723 .probe
= mv643xx_eth_shared_probe
,
2724 .remove
= mv643xx_eth_shared_remove
,
2726 .name
= MV643XX_ETH_SHARED_NAME
,
2727 .owner
= THIS_MODULE
,
2731 static void phy_addr_set(struct mv643xx_eth_private
*mp
, int phy_addr
)
2733 int addr_shift
= 5 * mp
->port_num
;
2736 data
= rdl(mp
, PHY_ADDR
);
2737 data
&= ~(0x1f << addr_shift
);
2738 data
|= (phy_addr
& 0x1f) << addr_shift
;
2739 wrl(mp
, PHY_ADDR
, data
);
2742 static int phy_addr_get(struct mv643xx_eth_private
*mp
)
2746 data
= rdl(mp
, PHY_ADDR
);
2748 return (data
>> (5 * mp
->port_num
)) & 0x1f;
2751 static void set_params(struct mv643xx_eth_private
*mp
,
2752 struct mv643xx_eth_platform_data
*pd
)
2754 struct net_device
*dev
= mp
->dev
;
2756 if (is_valid_ether_addr(pd
->mac_addr
))
2757 memcpy(dev
->dev_addr
, pd
->mac_addr
, 6);
2759 uc_addr_get(mp
, dev
->dev_addr
);
2761 mp
->rx_ring_size
= DEFAULT_RX_QUEUE_SIZE
;
2762 if (pd
->rx_queue_size
)
2763 mp
->rx_ring_size
= pd
->rx_queue_size
;
2764 mp
->rx_desc_sram_addr
= pd
->rx_sram_addr
;
2765 mp
->rx_desc_sram_size
= pd
->rx_sram_size
;
2767 mp
->rxq_count
= pd
->rx_queue_count
? : 1;
2769 mp
->tx_ring_size
= DEFAULT_TX_QUEUE_SIZE
;
2770 if (pd
->tx_queue_size
)
2771 mp
->tx_ring_size
= pd
->tx_queue_size
;
2772 mp
->tx_desc_sram_addr
= pd
->tx_sram_addr
;
2773 mp
->tx_desc_sram_size
= pd
->tx_sram_size
;
2775 mp
->txq_count
= pd
->tx_queue_count
? : 1;
2778 static struct phy_device
*phy_scan(struct mv643xx_eth_private
*mp
,
2781 struct mii_bus
*bus
= mp
->shared
->smi
->smi_bus
;
2782 struct phy_device
*phydev
;
2787 if (phy_addr
== MV643XX_ETH_PHY_ADDR_DEFAULT
) {
2788 start
= phy_addr_get(mp
) & 0x1f;
2791 start
= phy_addr
& 0x1f;
2796 for (i
= 0; i
< num
; i
++) {
2797 int addr
= (start
+ i
) & 0x1f;
2799 if (bus
->phy_map
[addr
] == NULL
)
2800 mdiobus_scan(bus
, addr
);
2802 if (phydev
== NULL
) {
2803 phydev
= bus
->phy_map
[addr
];
2805 phy_addr_set(mp
, addr
);
2812 static void phy_init(struct mv643xx_eth_private
*mp
, int speed
, int duplex
)
2814 struct phy_device
*phy
= mp
->phy
;
2818 phy_attach(mp
->dev
, dev_name(&phy
->dev
), 0, PHY_INTERFACE_MODE_GMII
);
2821 phy
->autoneg
= AUTONEG_ENABLE
;
2824 phy
->advertising
= phy
->supported
| ADVERTISED_Autoneg
;
2826 phy
->autoneg
= AUTONEG_DISABLE
;
2827 phy
->advertising
= 0;
2829 phy
->duplex
= duplex
;
2831 phy_start_aneg(phy
);
2834 static void init_pscr(struct mv643xx_eth_private
*mp
, int speed
, int duplex
)
2838 pscr
= rdlp(mp
, PORT_SERIAL_CONTROL
);
2839 if (pscr
& SERIAL_PORT_ENABLE
) {
2840 pscr
&= ~SERIAL_PORT_ENABLE
;
2841 wrlp(mp
, PORT_SERIAL_CONTROL
, pscr
);
2844 pscr
= MAX_RX_PACKET_9700BYTE
| SERIAL_PORT_CONTROL_RESERVED
;
2845 if (mp
->phy
== NULL
) {
2846 pscr
|= DISABLE_AUTO_NEG_SPEED_GMII
;
2847 if (speed
== SPEED_1000
)
2848 pscr
|= SET_GMII_SPEED_TO_1000
;
2849 else if (speed
== SPEED_100
)
2850 pscr
|= SET_MII_SPEED_TO_100
;
2852 pscr
|= DISABLE_AUTO_NEG_FOR_FLOW_CTRL
;
2854 pscr
|= DISABLE_AUTO_NEG_FOR_DUPLEX
;
2855 if (duplex
== DUPLEX_FULL
)
2856 pscr
|= SET_FULL_DUPLEX_MODE
;
2859 wrlp(mp
, PORT_SERIAL_CONTROL
, pscr
);
2862 static const struct net_device_ops mv643xx_eth_netdev_ops
= {
2863 .ndo_open
= mv643xx_eth_open
,
2864 .ndo_stop
= mv643xx_eth_stop
,
2865 .ndo_start_xmit
= mv643xx_eth_xmit
,
2866 .ndo_set_rx_mode
= mv643xx_eth_set_rx_mode
,
2867 .ndo_set_mac_address
= mv643xx_eth_set_mac_address
,
2868 .ndo_do_ioctl
= mv643xx_eth_ioctl
,
2869 .ndo_change_mtu
= mv643xx_eth_change_mtu
,
2870 .ndo_tx_timeout
= mv643xx_eth_tx_timeout
,
2871 .ndo_get_stats
= mv643xx_eth_get_stats
,
2872 #ifdef CONFIG_NET_POLL_CONTROLLER
2873 .ndo_poll_controller
= mv643xx_eth_netpoll
,
2877 static int mv643xx_eth_probe(struct platform_device
*pdev
)
2879 struct mv643xx_eth_platform_data
*pd
;
2880 struct mv643xx_eth_private
*mp
;
2881 struct net_device
*dev
;
2882 struct resource
*res
;
2885 pd
= pdev
->dev
.platform_data
;
2887 dev_printk(KERN_ERR
, &pdev
->dev
,
2888 "no mv643xx_eth_platform_data\n");
2892 if (pd
->shared
== NULL
) {
2893 dev_printk(KERN_ERR
, &pdev
->dev
,
2894 "no mv643xx_eth_platform_data->shared\n");
2898 dev
= alloc_etherdev_mq(sizeof(struct mv643xx_eth_private
), 8);
2902 mp
= netdev_priv(dev
);
2903 platform_set_drvdata(pdev
, mp
);
2905 mp
->shared
= platform_get_drvdata(pd
->shared
);
2906 mp
->base
= mp
->shared
->base
+ 0x0400 + (pd
->port_number
<< 10);
2907 mp
->port_num
= pd
->port_number
;
2912 dev
->real_num_tx_queues
= mp
->txq_count
;
2914 if (pd
->phy_addr
!= MV643XX_ETH_PHY_NONE
)
2915 mp
->phy
= phy_scan(mp
, pd
->phy_addr
);
2917 if (mp
->phy
!= NULL
)
2918 phy_init(mp
, pd
->speed
, pd
->duplex
);
2920 SET_ETHTOOL_OPS(dev
, &mv643xx_eth_ethtool_ops
);
2922 init_pscr(mp
, pd
->speed
, pd
->duplex
);
2925 mib_counters_clear(mp
);
2927 init_timer(&mp
->mib_counters_timer
);
2928 mp
->mib_counters_timer
.data
= (unsigned long)mp
;
2929 mp
->mib_counters_timer
.function
= mib_counters_timer_wrapper
;
2930 mp
->mib_counters_timer
.expires
= jiffies
+ 30 * HZ
;
2931 add_timer(&mp
->mib_counters_timer
);
2933 spin_lock_init(&mp
->mib_counters_lock
);
2935 INIT_WORK(&mp
->tx_timeout_task
, tx_timeout_task
);
2937 netif_napi_add(dev
, &mp
->napi
, mv643xx_eth_poll
, 128);
2939 init_timer(&mp
->rx_oom
);
2940 mp
->rx_oom
.data
= (unsigned long)mp
;
2941 mp
->rx_oom
.function
= oom_timer_wrapper
;
2944 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
2946 dev
->irq
= res
->start
;
2948 dev
->netdev_ops
= &mv643xx_eth_netdev_ops
;
2950 dev
->watchdog_timeo
= 2 * HZ
;
2953 dev
->features
= NETIF_F_SG
| NETIF_F_IP_CSUM
;
2954 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
;
2956 SET_NETDEV_DEV(dev
, &pdev
->dev
);
2958 if (mp
->shared
->win_protect
)
2959 wrl(mp
, WINDOW_PROTECT(mp
->port_num
), mp
->shared
->win_protect
);
2961 netif_carrier_off(dev
);
2963 wrlp(mp
, SDMA_CONFIG
, PORT_SDMA_CONFIG_DEFAULT_VALUE
);
2965 set_rx_coal(mp
, 250);
2968 err
= register_netdev(dev
);
2972 dev_printk(KERN_NOTICE
, &dev
->dev
, "port %d with MAC address %pM\n",
2973 mp
->port_num
, dev
->dev_addr
);
2975 if (mp
->tx_desc_sram_size
> 0)
2976 dev_printk(KERN_NOTICE
, &dev
->dev
, "configured with sram\n");
2986 static int mv643xx_eth_remove(struct platform_device
*pdev
)
2988 struct mv643xx_eth_private
*mp
= platform_get_drvdata(pdev
);
2990 unregister_netdev(mp
->dev
);
2991 if (mp
->phy
!= NULL
)
2992 phy_detach(mp
->phy
);
2993 flush_scheduled_work();
2994 free_netdev(mp
->dev
);
2996 platform_set_drvdata(pdev
, NULL
);
3001 static void mv643xx_eth_shutdown(struct platform_device
*pdev
)
3003 struct mv643xx_eth_private
*mp
= platform_get_drvdata(pdev
);
3005 /* Mask all interrupts on ethernet port */
3006 wrlp(mp
, INT_MASK
, 0);
3009 if (netif_running(mp
->dev
))
3013 static struct platform_driver mv643xx_eth_driver
= {
3014 .probe
= mv643xx_eth_probe
,
3015 .remove
= mv643xx_eth_remove
,
3016 .shutdown
= mv643xx_eth_shutdown
,
3018 .name
= MV643XX_ETH_NAME
,
3019 .owner
= THIS_MODULE
,
3023 static int __init
mv643xx_eth_init_module(void)
3027 rc
= platform_driver_register(&mv643xx_eth_shared_driver
);
3029 rc
= platform_driver_register(&mv643xx_eth_driver
);
3031 platform_driver_unregister(&mv643xx_eth_shared_driver
);
3036 module_init(mv643xx_eth_init_module
);
3038 static void __exit
mv643xx_eth_cleanup_module(void)
3040 platform_driver_unregister(&mv643xx_eth_driver
);
3041 platform_driver_unregister(&mv643xx_eth_shared_driver
);
3043 module_exit(mv643xx_eth_cleanup_module
);
3045 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3046 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3047 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3048 MODULE_LICENSE("GPL");
3049 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME
);
3050 MODULE_ALIAS("platform:" MV643XX_ETH_NAME
);