drivers/net/sfc/io.h

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2009 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #ifndef EFX_IO_H
  12 #define EFX_IO_H
  13
  14 #include <linux/io.h>
  15 #include <linux/spinlock.h>
  16
  17 /**************************************************************************
  18  *
  19  * NIC register I/O
  20  *
  21  **************************************************************************
  22  *
  23  * Notes on locking strategy:
  24  *
  25  * Most NIC registers require 16-byte (or 8-byte, for SRAM) atomic writes
  26  * which necessitates locking.
  27  * Under normal operation few writes to NIC registers are made and these
  28  * registers (EVQ_RPTR_REG, RX_DESC_UPD_REG and TX_DESC_UPD_REG) are special
  29  * cased to allow 4-byte (hence lockless) accesses.
  30  *
  31  * It *is* safe to write to these 4-byte registers in the middle of an
  32  * access to an 8-byte or 16-byte register.  We therefore use a
  33  * spinlock to protect accesses to the larger registers, but no locks
  34  * for the 4-byte registers.
  35  *
  36  * A write barrier is needed to ensure that DW3 is written after DW0/1/2
  37  * due to the way the 16byte registers are "collected" in the BIU.
  38  *
  39  * We also lock when carrying out reads, to ensure consistency of the
  40  * data (made possible since the BIU reads all 128 bits into a cache).
  41  * Reads are very rare, so this isn't a significant performance
  42  * impact.  (Most data transferred from NIC to host is DMAed directly
  43  * into host memory).
  44  *
  45  * I/O BAR access uses locks for both reads and writes (but is only provided
  46  * for testing purposes).
  47  */
  48
  49 #if BITS_PER_LONG == 64
  50 #define EFX_USE_QWORD_IO 1
  51 #endif
  52
  53 #ifdef EFX_USE_QWORD_IO
  54 static inline void _efx_writeq(struct efx_nic *efx, __le64 value,
  55                                   unsigned int reg)
  56 {
  57         __raw_writeq((__force u64)value, efx->membase + reg);
  58 }
  59 static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg)
  60 {
  61         return (__force __le64)__raw_readq(efx->membase + reg);
  62 }
  63 #endif
  64
  65 static inline void _efx_writed(struct efx_nic *efx, __le32 value,
  66                                   unsigned int reg)
  67 {
  68         __raw_writel((__force u32)value, efx->membase + reg);
  69 }
  70 static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg)
  71 {
  72         return (__force __le32)__raw_readl(efx->membase + reg);
  73 }
  74
  75 /* Writes to a normal 16-byte Efx register, locking as appropriate. */
  76 static inline void efx_writeo(struct efx_nic *efx, efx_oword_t *value,
  77                               unsigned int reg)
  78 {
  79         unsigned long flags __attribute__ ((unused));
  80
  81         EFX_REGDUMP(efx, "writing register %x with " EFX_OWORD_FMT "\n", reg,
  82                     EFX_OWORD_VAL(*value));
  83
  84         spin_lock_irqsave(&efx->biu_lock, flags);
  85 #ifdef EFX_USE_QWORD_IO
  86         _efx_writeq(efx, value->u64[0], reg + 0);
  87         wmb();
  88         _efx_writeq(efx, value->u64[1], reg + 8);
  89 #else
  90         _efx_writed(efx, value->u32[0], reg + 0);
  91         _efx_writed(efx, value->u32[1], reg + 4);
  92         _efx_writed(efx, value->u32[2], reg + 8);
  93         wmb();
  94         _efx_writed(efx, value->u32[3], reg + 12);
  95 #endif
  96         mmiowb();
  97         spin_unlock_irqrestore(&efx->biu_lock, flags);
  98 }
  99
 100 /* Write an 8-byte NIC SRAM entry through the supplied mapping,
 101  * locking as appropriate. */
 102 static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase,
 103                                    efx_qword_t *value, unsigned int index)
 104 {
 105         unsigned int addr = index * sizeof(*value);
 106         unsigned long flags __attribute__ ((unused));
 107
 108         EFX_REGDUMP(efx, "writing SRAM address %x with " EFX_QWORD_FMT "\n",
 109                     addr, EFX_QWORD_VAL(*value));
 110
 111         spin_lock_irqsave(&efx->biu_lock, flags);
 112 #ifdef EFX_USE_QWORD_IO
 113         __raw_writeq((__force u64)value->u64[0], membase + addr);
 114 #else
 115         __raw_writel((__force u32)value->u32[0], membase + addr);
 116         wmb();
 117         __raw_writel((__force u32)value->u32[1], membase + addr + 4);
 118 #endif
 119         mmiowb();
 120         spin_unlock_irqrestore(&efx->biu_lock, flags);
 121 }
 122
 123 /* Write dword to NIC register that allows partial writes
 124  *
 125  * Some registers (EVQ_RPTR_REG, RX_DESC_UPD_REG and
 126  * TX_DESC_UPD_REG) can be written to as a single dword.  This allows
 127  * for lockless writes.
 128  */
 129 static inline void efx_writed(struct efx_nic *efx, efx_dword_t *value,
 130                               unsigned int reg)
 131 {
 132         EFX_REGDUMP(efx, "writing partial register %x with "EFX_DWORD_FMT"\n",
 133                     reg, EFX_DWORD_VAL(*value));
 134
 135         /* No lock required */
 136         _efx_writed(efx, value->u32[0], reg);
 137 }
 138
 139 /* Read from a NIC register
 140  *
 141  * This reads an entire 16-byte register in one go, locking as
 142  * appropriate.  It is essential to read the first dword first, as this
 143  * prompts the NIC to load the current value into the shadow register.
 144  */
 145 static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value,
 146                              unsigned int reg)
 147 {
 148         unsigned long flags __attribute__ ((unused));
 149
 150         spin_lock_irqsave(&efx->biu_lock, flags);
 151         value->u32[0] = _efx_readd(efx, reg + 0);
 152         rmb();
 153         value->u32[1] = _efx_readd(efx, reg + 4);
 154         value->u32[2] = _efx_readd(efx, reg + 8);
 155         value->u32[3] = _efx_readd(efx, reg + 12);
 156         spin_unlock_irqrestore(&efx->biu_lock, flags);
 157
 158         EFX_REGDUMP(efx, "read from register %x, got " EFX_OWORD_FMT "\n", reg,
 159                     EFX_OWORD_VAL(*value));
 160 }
 161
 162 /* Read an 8-byte SRAM entry through supplied mapping,
 163  * locking as appropriate. */
 164 static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase,
 165                                   efx_qword_t *value, unsigned int index)
 166 {
 167         unsigned int addr = index * sizeof(*value);
 168         unsigned long flags __attribute__ ((unused));
 169
 170         spin_lock_irqsave(&efx->biu_lock, flags);
 171 #ifdef EFX_USE_QWORD_IO
 172         value->u64[0] = (__force __le64)__raw_readq(membase + addr);
 173 #else
 174         value->u32[0] = (__force __le32)__raw_readl(membase + addr);
 175         rmb();
 176         value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
 177 #endif
 178         spin_unlock_irqrestore(&efx->biu_lock, flags);
 179
 180         EFX_REGDUMP(efx, "read from SRAM address %x, got "EFX_QWORD_FMT"\n",
 181                     addr, EFX_QWORD_VAL(*value));
 182 }
 183
 184 /* Read dword from register that allows partial writes (sic) */
 185 static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value,
 186                                 unsigned int reg)
 187 {
 188         value->u32[0] = _efx_readd(efx, reg);
 189         EFX_REGDUMP(efx, "read from register %x, got "EFX_DWORD_FMT"\n",
 190                     reg, EFX_DWORD_VAL(*value));
 191 }
 192
 193 /* Write to a register forming part of a table */
 194 static inline void efx_writeo_table(struct efx_nic *efx, efx_oword_t *value,
 195                                       unsigned int reg, unsigned int index)
 196 {
 197         efx_writeo(efx, value, reg + index * sizeof(efx_oword_t));
 198 }
 199
 200 /* Read to a register forming part of a table */
 201 static inline void efx_reado_table(struct efx_nic *efx, efx_oword_t *value,
 202                                      unsigned int reg, unsigned int index)
 203 {
 204         efx_reado(efx, value, reg + index * sizeof(efx_oword_t));
 205 }
 206
 207 /* Write to a dword register forming part of a table */
 208 static inline void efx_writed_table(struct efx_nic *efx, efx_dword_t *value,
 209                                        unsigned int reg, unsigned int index)
 210 {
 211         efx_writed(efx, value, reg + index * sizeof(efx_oword_t));
 212 }
 213
 214 /* Page-mapped register block size */
 215 #define EFX_PAGE_BLOCK_SIZE 0x2000
 216
 217 /* Calculate offset to page-mapped register block */
 218 #define EFX_PAGED_REG(page, reg) \
 219         ((page) * EFX_PAGE_BLOCK_SIZE + (reg))
 220
 221 /* As for efx_writeo(), but for a page-mapped register. */
 222 static inline void efx_writeo_page(struct efx_nic *efx, efx_oword_t *value,
 223                                    unsigned int reg, unsigned int page)
 224 {
 225         efx_writeo(efx, value, EFX_PAGED_REG(page, reg));
 226 }
 227
 228 /* As for efx_writed(), but for a page-mapped register. */
 229 static inline void efx_writed_page(struct efx_nic *efx, efx_dword_t *value,
 230                                    unsigned int reg, unsigned int page)
 231 {
 232         efx_writed(efx, value, EFX_PAGED_REG(page, reg));
 233 }
 234
 235 /* Write dword to page-mapped register with an extra lock.
 236  *
 237  * As for efx_writed_page(), but for a register that suffers from
 238  * SFC bug 3181. Take out a lock so the BIU collector cannot be
 239  * confused. */
 240 static inline void efx_writed_page_locked(struct efx_nic *efx,
 241                                           efx_dword_t *value,
 242                                           unsigned int reg,
 243                                           unsigned int page)
 244 {
 245         unsigned long flags __attribute__ ((unused));
 246
 247         if (page == 0) {
 248                 spin_lock_irqsave(&efx->biu_lock, flags);
 249                 efx_writed(efx, value, EFX_PAGED_REG(page, reg));
 250                 spin_unlock_irqrestore(&efx->biu_lock, flags);
 251         } else {
 252                 efx_writed(efx, value, EFX_PAGED_REG(page, reg));
 253         }
 254 }
 255
 256 #endif /* EFX_IO_H */