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[PATCH] PPC 44x EMAC driver: add 440SPe support
[linux-2.6.git] / include / linux / i2o.h
blob92300325dbcd30254b1bc72c0b65cd39c1b35b2d
1 /*
2 * I2O kernel space accessible structures/APIs
3 *
4 * (c) Copyright 1999, 2000 Red Hat Software
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 *************************************************************************
12 *
13 * This header file defined the I2O APIs/structures for use by
14 * the I2O kernel modules.
15 *
16 */
17
18 #ifndef _I2O_H
19 #define _I2O_H
20
21 #ifdef __KERNEL__ /* This file to be included by kernel only */
22
23 #include <linux/i2o-dev.h>
24
25 /* How many different OSM's are we allowing */
26 #define I2O_MAX_DRIVERS 8
27
28 #include <asm/io.h>
29 #include <asm/semaphore.h> /* Needed for MUTEX init macros */
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32
33 /* message queue empty */
34 #define I2O_QUEUE_EMPTY 0xffffffff
35
36 /*
37 * Message structures
38 */
39 struct i2o_message {
40 union {
41 struct {
42 u8 version_offset;
43 u8 flags;
44 u16 size;
45 u32 target_tid:12;
46 u32 init_tid:12;
47 u32 function:8;
48 u32 icntxt; /* initiator context */
49 u32 tcntxt; /* transaction context */
50 } s;
51 u32 head[4];
52 } u;
53 /* List follows */
54 u32 body[0];
55 };
56
57 /*
58 * Each I2O device entity has one of these. There is one per device.
59 */
60 struct i2o_device {
61 i2o_lct_entry lct_data; /* Device LCT information */
62
63 struct i2o_controller *iop; /* Controlling IOP */
64 struct list_head list; /* node in IOP devices list */
65
66 struct device device;
67
68 struct semaphore lock; /* device lock */
69 };
70
71 /*
72 * Event structure provided to the event handling function
73 */
74 struct i2o_event {
75 struct work_struct work;
76 struct i2o_device *i2o_dev; /* I2O device pointer from which the
77 event reply was initiated */
78 u16 size; /* Size of data in 32-bit words */
79 u32 tcntxt; /* Transaction context used at
80 registration */
81 u32 event_indicator; /* Event indicator from reply */
82 u32 data[0]; /* Event data from reply */
83 };
84
85 /*
86 * I2O classes which could be handled by the OSM
87 */
88 struct i2o_class_id {
89 u16 class_id:12;
90 };
91
92 /*
93 * I2O driver structure for OSMs
94 */
95 struct i2o_driver {
96 char *name; /* OSM name */
97 int context; /* Low 8 bits of the transaction info */
98 struct i2o_class_id *classes; /* I2O classes that this OSM handles */
99
100 /* Message reply handler */
101 int (*reply) (struct i2o_controller *, u32, struct i2o_message *);
102
103 /* Event handler */
104 void (*event) (struct i2o_event *);
105
106 struct workqueue_struct *event_queue; /* Event queue */
107
108 struct device_driver driver;
109
110 /* notification of changes */
111 void (*notify_controller_add) (struct i2o_controller *);
112 void (*notify_controller_remove) (struct i2o_controller *);
113 void (*notify_device_add) (struct i2o_device *);
114 void (*notify_device_remove) (struct i2o_device *);
115
116 struct semaphore lock;
117 };
118
119 /*
120 * Contains DMA mapped address information
121 */
122 struct i2o_dma {
123 void *virt;
124 dma_addr_t phys;
125 size_t len;
126 };
127
128 /*
129 * Contains IO mapped address information
130 */
131 struct i2o_io {
132 void __iomem *virt;
133 unsigned long phys;
134 unsigned long len;
135 };
136
137 /*
138 * Context queue entry, used for 32-bit context on 64-bit systems
139 */
140 struct i2o_context_list_element {
141 struct list_head list;
142 u32 context;
143 void *ptr;
144 unsigned long timestamp;
145 };
146
147 /*
148 * Each I2O controller has one of these objects
149 */
150 struct i2o_controller {
151 char name[16];
152 int unit;
153 int type;
154
155 struct pci_dev *pdev; /* PCI device */
156
157 unsigned int promise:1; /* Promise controller */
158 unsigned int adaptec:1; /* DPT / Adaptec controller */
159 unsigned int raptor:1; /* split bar */
160 unsigned int no_quiesce:1; /* dont quiesce before reset */
161 unsigned int short_req:1; /* use small block sizes */
162 unsigned int limit_sectors:1; /* limit number of sectors / request */
163 unsigned int pae_support:1; /* controller has 64-bit SGL support */
164
165 struct list_head devices; /* list of I2O devices */
166 struct list_head list; /* Controller list */
167
168 void __iomem *in_port; /* Inbout port address */
169 void __iomem *out_port; /* Outbound port address */
170 void __iomem *irq_status; /* Interrupt status register address */
171 void __iomem *irq_mask; /* Interrupt mask register address */
172
173 /* Dynamic LCT related data */
174
175 struct i2o_dma status; /* IOP status block */
176
177 struct i2o_dma hrt; /* HW Resource Table */
178 i2o_lct *lct; /* Logical Config Table */
179 struct i2o_dma dlct; /* Temp LCT */
180 struct semaphore lct_lock; /* Lock for LCT updates */
181 struct i2o_dma status_block; /* IOP status block */
182
183 struct i2o_io base; /* controller messaging unit */
184 struct i2o_io in_queue; /* inbound message queue Host->IOP */
185 struct i2o_dma out_queue; /* outbound message queue IOP->Host */
186
187 unsigned int battery:1; /* Has a battery backup */
188 unsigned int io_alloc:1; /* An I/O resource was allocated */
189 unsigned int mem_alloc:1; /* A memory resource was allocated */
190
191 struct resource io_resource; /* I/O resource allocated to the IOP */
192 struct resource mem_resource; /* Mem resource allocated to the IOP */
193
194 struct device device;
195 struct class_device *classdev; /* I2O controller class device */
196 struct i2o_device *exec; /* Executive */
197 #if BITS_PER_LONG == 64
198 spinlock_t context_list_lock; /* lock for context_list */
199 atomic_t context_list_counter; /* needed for unique contexts */
200 struct list_head context_list; /* list of context id's
201 and pointers */
202 #endif
203 spinlock_t lock; /* lock for controller
204 configuration */
205
206 void *driver_data[I2O_MAX_DRIVERS]; /* storage for drivers */
207 };
208
209 /*
210 * I2O System table entry
211 *
212 * The system table contains information about all the IOPs in the
213 * system. It is sent to all IOPs so that they can create peer2peer
214 * connections between them.
215 */
216 struct i2o_sys_tbl_entry {
217 u16 org_id;
218 u16 reserved1;
219 u32 iop_id:12;
220 u32 reserved2:20;
221 u16 seg_num:12;
222 u16 i2o_version:4;
223 u8 iop_state;
224 u8 msg_type;
225 u16 frame_size;
226 u16 reserved3;
227 u32 last_changed;
228 u32 iop_capabilities;
229 u32 inbound_low;
230 u32 inbound_high;
231 };
232
233 struct i2o_sys_tbl {
234 u8 num_entries;
235 u8 version;
236 u16 reserved1;
237 u32 change_ind;
238 u32 reserved2;
239 u32 reserved3;
240 struct i2o_sys_tbl_entry iops[0];
241 };
242
243 extern struct list_head i2o_controllers;
244
245 /* Message functions */
246 static inline u32 i2o_msg_get(struct i2o_controller *,
247 struct i2o_message __iomem **);
248 extern u32 i2o_msg_get_wait(struct i2o_controller *,
249 struct i2o_message __iomem **, int);
250 static inline void i2o_msg_post(struct i2o_controller *, u32);
251 static inline int i2o_msg_post_wait(struct i2o_controller *, u32,
252 unsigned long);
253 extern int i2o_msg_post_wait_mem(struct i2o_controller *, u32, unsigned long,
254 struct i2o_dma *);
255 extern void i2o_msg_nop(struct i2o_controller *, u32);
256 static inline void i2o_flush_reply(struct i2o_controller *, u32);
257
258 /* IOP functions */
259 extern int i2o_status_get(struct i2o_controller *);
260
261 extern int i2o_event_register(struct i2o_device *, struct i2o_driver *, int,
262 u32);
263 extern struct i2o_device *i2o_iop_find_device(struct i2o_controller *, u16);
264 extern struct i2o_controller *i2o_find_iop(int);
265
266 /* Functions needed for handling 64-bit pointers in 32-bit context */
267 #if BITS_PER_LONG == 64
268 extern u32 i2o_cntxt_list_add(struct i2o_controller *, void *);
269 extern void *i2o_cntxt_list_get(struct i2o_controller *, u32);
270 extern u32 i2o_cntxt_list_remove(struct i2o_controller *, void *);
271 extern u32 i2o_cntxt_list_get_ptr(struct i2o_controller *, void *);
272
273 static inline u32 i2o_ptr_low(void *ptr)
274 {
275 return (u32) (u64) ptr;
276 };
277
278 static inline u32 i2o_ptr_high(void *ptr)
279 {
280 return (u32) ((u64) ptr >> 32);
281 };
282
283 static inline u32 i2o_dma_low(dma_addr_t dma_addr)
284 {
285 return (u32) (u64) dma_addr;
286 };
287
288 static inline u32 i2o_dma_high(dma_addr_t dma_addr)
289 {
290 return (u32) ((u64) dma_addr >> 32);
291 };
292 #else
293 static inline u32 i2o_cntxt_list_add(struct i2o_controller *c, void *ptr)
294 {
295 return (u32) ptr;
296 };
297
298 static inline void *i2o_cntxt_list_get(struct i2o_controller *c, u32 context)
299 {
300 return (void *)context;
301 };
302
303 static inline u32 i2o_cntxt_list_remove(struct i2o_controller *c, void *ptr)
304 {
305 return (u32) ptr;
306 };
307
308 static inline u32 i2o_cntxt_list_get_ptr(struct i2o_controller *c, void *ptr)
309 {
310 return (u32) ptr;
311 };
312
313 static inline u32 i2o_ptr_low(void *ptr)
314 {
315 return (u32) ptr;
316 };
317
318 static inline u32 i2o_ptr_high(void *ptr)
319 {
320 return 0;
321 };
322
323 static inline u32 i2o_dma_low(dma_addr_t dma_addr)
324 {
325 return (u32) dma_addr;
326 };
327
328 static inline u32 i2o_dma_high(dma_addr_t dma_addr)
329 {
330 return 0;
331 };
332 #endif
333
334 /**
335 * i2o_sg_tablesize - Calculate the maximum number of elements in a SGL
336 * @c: I2O controller for which the calculation should be done
337 * @body_size: maximum body size used for message in 32-bit words.
338 *
339 * Return the maximum number of SG elements in a SG list.
340 */
341 static inline u16 i2o_sg_tablesize(struct i2o_controller *c, u16 body_size)
342 {
343 i2o_status_block *sb = c->status_block.virt;
344 u16 sg_count =
345 (sb->inbound_frame_size - sizeof(struct i2o_message) / 4) -
346 body_size;
347
348 if (c->pae_support) {
349 /*
350 * for 64-bit a SG attribute element must be added and each
351 * SG element needs 12 bytes instead of 8.
352 */
353 sg_count -= 2;
354 sg_count /= 3;
355 } else
356 sg_count /= 2;
357
358 if (c->short_req && (sg_count > 8))
359 sg_count = 8;
360
361 return sg_count;
362 };
363
364 /**
365 * i2o_dma_map_single - Map pointer to controller and fill in I2O message.
366 * @c: I2O controller
367 * @ptr: pointer to the data which should be mapped
368 * @size: size of data in bytes
369 * @direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
370 * @sg_ptr: pointer to the SG list inside the I2O message
371 *
372 * This function does all necessary DMA handling and also writes the I2O
373 * SGL elements into the I2O message. For details on DMA handling see also
374 * dma_map_single(). The pointer sg_ptr will only be set to the end of the
375 * SG list if the allocation was successful.
376 *
377 * Returns DMA address which must be checked for failures using
378 * dma_mapping_error().
379 */
380 static inline dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
381 size_t size,
382 enum dma_data_direction direction,
383 u32 __iomem ** sg_ptr)
384 {
385 u32 sg_flags;
386 u32 __iomem *mptr = *sg_ptr;
387 dma_addr_t dma_addr;
388
389 switch (direction) {
390 case DMA_TO_DEVICE:
391 sg_flags = 0xd4000000;
392 break;
393 case DMA_FROM_DEVICE:
394 sg_flags = 0xd0000000;
395 break;
396 default:
397 return 0;
398 }
399
400 dma_addr = dma_map_single(&c->pdev->dev, ptr, size, direction);
401 if (!dma_mapping_error(dma_addr)) {
402 #ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
403 if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
404 writel(0x7C020002, mptr++);
405 writel(PAGE_SIZE, mptr++);
406 }
407 #endif
408
409 writel(sg_flags | size, mptr++);
410 writel(i2o_dma_low(dma_addr), mptr++);
411 #ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
412 if ((sizeof(dma_addr_t) > 4) && c->pae_support)
413 writel(i2o_dma_high(dma_addr), mptr++);
414 #endif
415 *sg_ptr = mptr;
416 }
417 return dma_addr;
418 };
419
420 /**
421 * i2o_dma_map_sg - Map a SG List to controller and fill in I2O message.
422 * @c: I2O controller
423 * @sg: SG list to be mapped
424 * @sg_count: number of elements in the SG list
425 * @direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
426 * @sg_ptr: pointer to the SG list inside the I2O message
427 *
428 * This function does all necessary DMA handling and also writes the I2O
429 * SGL elements into the I2O message. For details on DMA handling see also
430 * dma_map_sg(). The pointer sg_ptr will only be set to the end of the SG
431 * list if the allocation was successful.
432 *
433 * Returns 0 on failure or 1 on success.
434 */
435 static inline int i2o_dma_map_sg(struct i2o_controller *c,
436 struct scatterlist *sg, int sg_count,
437 enum dma_data_direction direction,
438 u32 __iomem ** sg_ptr)
439 {
440 u32 sg_flags;
441 u32 __iomem *mptr = *sg_ptr;
442
443 switch (direction) {
444 case DMA_TO_DEVICE:
445 sg_flags = 0x14000000;
446 break;
447 case DMA_FROM_DEVICE:
448 sg_flags = 0x10000000;
449 break;
450 default:
451 return 0;
452 }
453
454 sg_count = dma_map_sg(&c->pdev->dev, sg, sg_count, direction);
455 if (!sg_count)
456 return 0;
457
458 #ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
459 if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
460 writel(0x7C020002, mptr++);
461 writel(PAGE_SIZE, mptr++);
462 }
463 #endif
464
465 while (sg_count-- > 0) {
466 if (!sg_count)
467 sg_flags |= 0xC0000000;
468 writel(sg_flags | sg_dma_len(sg), mptr++);
469 writel(i2o_dma_low(sg_dma_address(sg)), mptr++);
470 #ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
471 if ((sizeof(dma_addr_t) > 4) && c->pae_support)
472 writel(i2o_dma_high(sg_dma_address(sg)), mptr++);
473 #endif
474 sg++;
475 }
476 *sg_ptr = mptr;
477
478 return 1;
479 };
480
481 /**
482 * i2o_dma_alloc - Allocate DMA memory
483 * @dev: struct device pointer to the PCI device of the I2O controller
484 * @addr: i2o_dma struct which should get the DMA buffer
485 * @len: length of the new DMA memory
486 * @gfp_mask: GFP mask
487 *
488 * Allocate a coherent DMA memory and write the pointers into addr.
489 *
490 * Returns 0 on success or -ENOMEM on failure.
491 */
492 static inline int i2o_dma_alloc(struct device *dev, struct i2o_dma *addr,
493 size_t len, gfp_t gfp_mask)
494 {
495 struct pci_dev *pdev = to_pci_dev(dev);
496 int dma_64 = 0;
497
498 if ((sizeof(dma_addr_t) > 4) && (pdev->dma_mask == DMA_64BIT_MASK)) {
499 dma_64 = 1;
500 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK))
501 return -ENOMEM;
502 }
503
504 addr->virt = dma_alloc_coherent(dev, len, &addr->phys, gfp_mask);
505
506 if ((sizeof(dma_addr_t) > 4) && dma_64)
507 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK))
508 printk(KERN_WARNING "i2o: unable to set 64-bit DMA");
509
510 if (!addr->virt)
511 return -ENOMEM;
512
513 memset(addr->virt, 0, len);
514 addr->len = len;
515
516 return 0;
517 };
518
519 /**
520 * i2o_dma_free - Free DMA memory
521 * @dev: struct device pointer to the PCI device of the I2O controller
522 * @addr: i2o_dma struct which contains the DMA buffer
523 *
524 * Free a coherent DMA memory and set virtual address of addr to NULL.
525 */
526 static inline void i2o_dma_free(struct device *dev, struct i2o_dma *addr)
527 {
528 if (addr->virt) {
529 if (addr->phys)
530 dma_free_coherent(dev, addr->len, addr->virt,
531 addr->phys);
532 else
533 kfree(addr->virt);
534 addr->virt = NULL;
535 }
536 };
537
538 /**
539 * i2o_dma_realloc - Realloc DMA memory
540 * @dev: struct device pointer to the PCI device of the I2O controller
541 * @addr: pointer to a i2o_dma struct DMA buffer
542 * @len: new length of memory
543 * @gfp_mask: GFP mask
544 *
545 * If there was something allocated in the addr, free it first. If len > 0
546 * than try to allocate it and write the addresses back to the addr
547 * structure. If len == 0 set the virtual address to NULL.
548 *
549 * Returns the 0 on success or negative error code on failure.
550 */
551 static inline int i2o_dma_realloc(struct device *dev, struct i2o_dma *addr,
552 size_t len, gfp_t gfp_mask)
553 {
554 i2o_dma_free(dev, addr);
555
556 if (len)
557 return i2o_dma_alloc(dev, addr, len, gfp_mask);
558
559 return 0;
560 };
561
562 /* I2O driver (OSM) functions */
563 extern int i2o_driver_register(struct i2o_driver *);
564 extern void i2o_driver_unregister(struct i2o_driver *);
565
566 /**
567 * i2o_driver_notify_controller_add - Send notification of added controller
568 * to a single I2O driver
569 *
570 * Send notification of added controller to a single registered driver.
571 */
572 static inline void i2o_driver_notify_controller_add(struct i2o_driver *drv,
573 struct i2o_controller *c)
574 {
575 if (drv->notify_controller_add)
576 drv->notify_controller_add(c);
577 };
578
579 /**
580 * i2o_driver_notify_controller_remove - Send notification of removed
581 * controller to a single I2O driver
582 *
583 * Send notification of removed controller to a single registered driver.
584 */
585 static inline void i2o_driver_notify_controller_remove(struct i2o_driver *drv,
586 struct i2o_controller *c)
587 {
588 if (drv->notify_controller_remove)
589 drv->notify_controller_remove(c);
590 };
591
592 /**
593 * i2o_driver_notify_device_add - Send notification of added device to a
594 * single I2O driver
595 *
596 * Send notification of added device to a single registered driver.
597 */
598 static inline void i2o_driver_notify_device_add(struct i2o_driver *drv,
599 struct i2o_device *i2o_dev)
600 {
601 if (drv->notify_device_add)
602 drv->notify_device_add(i2o_dev);
603 };
604
605 /**
606 * i2o_driver_notify_device_remove - Send notification of removed device
607 * to a single I2O driver
608 *
609 * Send notification of removed device to a single registered driver.
610 */
611 static inline void i2o_driver_notify_device_remove(struct i2o_driver *drv,
612 struct i2o_device *i2o_dev)
613 {
614 if (drv->notify_device_remove)
615 drv->notify_device_remove(i2o_dev);
616 };
617
618 extern void i2o_driver_notify_controller_add_all(struct i2o_controller *);
619 extern void i2o_driver_notify_controller_remove_all(struct i2o_controller *);
620 extern void i2o_driver_notify_device_add_all(struct i2o_device *);
621 extern void i2o_driver_notify_device_remove_all(struct i2o_device *);
622
623 /* I2O device functions */
624 extern int i2o_device_claim(struct i2o_device *);
625 extern int i2o_device_claim_release(struct i2o_device *);
626
627 /* Exec OSM functions */
628 extern int i2o_exec_lct_get(struct i2o_controller *);
629
630 /* device / driver / kobject conversion functions */
631 #define to_i2o_driver(drv) container_of(drv,struct i2o_driver, driver)
632 #define to_i2o_device(dev) container_of(dev, struct i2o_device, device)
633 #define to_i2o_controller(dev) container_of(dev, struct i2o_controller, device)
634 #define kobj_to_i2o_device(kobj) to_i2o_device(container_of(kobj, struct device, kobj))
635
636 /**
637 * i2o_msg_get - obtain an I2O message from the IOP
638 * @c: I2O controller
639 * @msg: pointer to a I2O message pointer
640 *
641 * This function tries to get a message slot. If no message slot is
642 * available do not wait until one is availabe (see also i2o_msg_get_wait).
643 *
644 * On a success the message is returned and the pointer to the message is
645 * set in msg. The returned message is the physical page frame offset
646 * address from the read port (see the i2o spec). If no message is
647 * available returns I2O_QUEUE_EMPTY and msg is leaved untouched.
648 */
649 static inline u32 i2o_msg_get(struct i2o_controller *c,
650 struct i2o_message __iomem ** msg)
651 {
652 u32 m = readl(c->in_port);
653
654 if (m != I2O_QUEUE_EMPTY)
655 *msg = c->in_queue.virt + m;
656
657 return m;
658 };
659
660 /**
661 * i2o_msg_post - Post I2O message to I2O controller
662 * @c: I2O controller to which the message should be send
663 * @m: the message identifier
664 *
665 * Post the message to the I2O controller.
666 */
667 static inline void i2o_msg_post(struct i2o_controller *c, u32 m)
668 {
669 writel(m, c->in_port);
670 };
671
672 /**
673 * i2o_msg_post_wait - Post and wait a message and wait until return
674 * @c: controller
675 * @m: message to post
676 * @timeout: time in seconds to wait
677 *
678 * This API allows an OSM to post a message and then be told whether or
679 * not the system received a successful reply. If the message times out
680 * then the value '-ETIMEDOUT' is returned.
681 *
682 * Returns 0 on success or negative error code on failure.
683 */
684 static inline int i2o_msg_post_wait(struct i2o_controller *c, u32 m,
685 unsigned long timeout)
686 {
687 return i2o_msg_post_wait_mem(c, m, timeout, NULL);
688 };
689
690 /**
691 * i2o_flush_reply - Flush reply from I2O controller
692 * @c: I2O controller
693 * @m: the message identifier
694 *
695 * The I2O controller must be informed that the reply message is not needed
696 * anymore. If you forget to flush the reply, the message frame can't be
697 * used by the controller anymore and is therefore lost.
698 */
699 static inline void i2o_flush_reply(struct i2o_controller *c, u32 m)
700 {
701 writel(m, c->out_port);
702 };
703
704 /**
705 * i2o_out_to_virt - Turn an I2O message to a virtual address
706 * @c: controller
707 * @m: message engine value
708 *
709 * Turn a receive message from an I2O controller bus address into
710 * a Linux virtual address. The shared page frame is a linear block
711 * so we simply have to shift the offset. This function does not
712 * work for sender side messages as they are ioremap objects
713 * provided by the I2O controller.
714 */
715 static inline struct i2o_message *i2o_msg_out_to_virt(struct i2o_controller *c,
716 u32 m)
717 {
718 BUG_ON(m < c->out_queue.phys
719 || m >= c->out_queue.phys + c->out_queue.len);
720
721 return c->out_queue.virt + (m - c->out_queue.phys);
722 };
723
724 /**
725 * i2o_msg_in_to_virt - Turn an I2O message to a virtual address
726 * @c: controller
727 * @m: message engine value
728 *
729 * Turn a send message from an I2O controller bus address into
730 * a Linux virtual address. The shared page frame is a linear block
731 * so we simply have to shift the offset. This function does not
732 * work for receive side messages as they are kmalloc objects
733 * in a different pool.
734 */
735 static inline struct i2o_message __iomem *i2o_msg_in_to_virt(struct
736 i2o_controller *c,
737 u32 m)
738 {
739 return c->in_queue.virt + m;
740 };
741
742 /*
743 * Endian handling wrapped into the macro - keeps the core code
744 * cleaner.
745 */
746
747 #define i2o_raw_writel(val, mem) __raw_writel(cpu_to_le32(val), mem)
748
749 extern int i2o_parm_field_get(struct i2o_device *, int, int, void *, int);
750 extern int i2o_parm_table_get(struct i2o_device *, int, int, int, void *, int,
751 void *, int);
752
753 /* debugging and troubleshooting/diagnostic helpers. */
754 #define osm_printk(level, format, arg...) \
755 printk(level "%s: " format, OSM_NAME , ## arg)
756
757 #ifdef DEBUG
758 #define osm_debug(format, arg...) \
759 osm_printk(KERN_DEBUG, format , ## arg)
760 #else
761 #define osm_debug(format, arg...) \
762 do { } while (0)
763 #endif
764
765 #define osm_err(format, arg...) \
766 osm_printk(KERN_ERR, format , ## arg)
767 #define osm_info(format, arg...) \
768 osm_printk(KERN_INFO, format , ## arg)
769 #define osm_warn(format, arg...) \
770 osm_printk(KERN_WARNING, format , ## arg)
771
772 /* debugging functions */
773 extern void i2o_report_status(const char *, const char *, struct i2o_message *);
774 extern void i2o_dump_message(struct i2o_message *);
775 extern void i2o_dump_hrt(struct i2o_controller *c);
776 extern void i2o_debug_state(struct i2o_controller *c);
777
778 /*
779 * Cache strategies
780 */
781
782 /* The NULL strategy leaves everything up to the controller. This tends to be a
783 * pessimal but functional choice.
784 */
785 #define CACHE_NULL 0
786 /* Prefetch data when reading. We continually attempt to load the next 32 sectors
787 * into the controller cache.
788 */
789 #define CACHE_PREFETCH 1
790 /* Prefetch data when reading. We sometimes attempt to load the next 32 sectors
791 * into the controller cache. When an I/O is less <= 8K we assume its probably
792 * not sequential and don't prefetch (default)
793 */
794 #define CACHE_SMARTFETCH 2
795 /* Data is written to the cache and then out on to the disk. The I/O must be
796 * physically on the medium before the write is acknowledged (default without
797 * NVRAM)
798 */
799 #define CACHE_WRITETHROUGH 17
800 /* Data is written to the cache and then out on to the disk. The controller
801 * is permitted to write back the cache any way it wants. (default if battery
802 * backed NVRAM is present). It can be useful to set this for swap regardless of
803 * battery state.
804 */
805 #define CACHE_WRITEBACK 18
806 /* Optimise for under powered controllers, especially on RAID1 and RAID0. We
807 * write large I/O's directly to disk bypassing the cache to avoid the extra
808 * memory copy hits. Small writes are writeback cached
809 */
810 #define CACHE_SMARTBACK 19
811 /* Optimise for under powered controllers, especially on RAID1 and RAID0. We
812 * write large I/O's directly to disk bypassing the cache to avoid the extra
813 * memory copy hits. Small writes are writethrough cached. Suitable for devices
814 * lacking battery backup
815 */
816 #define CACHE_SMARTTHROUGH 20
817
818 /*
819 * Ioctl structures
820 */
821
822 #define BLKI2OGRSTRAT _IOR('2', 1, int)
823 #define BLKI2OGWSTRAT _IOR('2', 2, int)
824 #define BLKI2OSRSTRAT _IOW('2', 3, int)
825 #define BLKI2OSWSTRAT _IOW('2', 4, int)
826
827 /*
828 * I2O Function codes
829 */
830
831 /*
832 * Executive Class
833 */
834 #define I2O_CMD_ADAPTER_ASSIGN 0xB3
835 #define I2O_CMD_ADAPTER_READ 0xB2
836 #define I2O_CMD_ADAPTER_RELEASE 0xB5
837 #define I2O_CMD_BIOS_INFO_SET 0xA5
838 #define I2O_CMD_BOOT_DEVICE_SET 0xA7
839 #define I2O_CMD_CONFIG_VALIDATE 0xBB
840 #define I2O_CMD_CONN_SETUP 0xCA
841 #define I2O_CMD_DDM_DESTROY 0xB1
842 #define I2O_CMD_DDM_ENABLE 0xD5
843 #define I2O_CMD_DDM_QUIESCE 0xC7
844 #define I2O_CMD_DDM_RESET 0xD9
845 #define I2O_CMD_DDM_SUSPEND 0xAF
846 #define I2O_CMD_DEVICE_ASSIGN 0xB7
847 #define I2O_CMD_DEVICE_RELEASE 0xB9
848 #define I2O_CMD_HRT_GET 0xA8
849 #define I2O_CMD_ADAPTER_CLEAR 0xBE
850 #define I2O_CMD_ADAPTER_CONNECT 0xC9
851 #define I2O_CMD_ADAPTER_RESET 0xBD
852 #define I2O_CMD_LCT_NOTIFY 0xA2
853 #define I2O_CMD_OUTBOUND_INIT 0xA1
854 #define I2O_CMD_PATH_ENABLE 0xD3
855 #define I2O_CMD_PATH_QUIESCE 0xC5
856 #define I2O_CMD_PATH_RESET 0xD7
857 #define I2O_CMD_STATIC_MF_CREATE 0xDD
858 #define I2O_CMD_STATIC_MF_RELEASE 0xDF
859 #define I2O_CMD_STATUS_GET 0xA0
860 #define I2O_CMD_SW_DOWNLOAD 0xA9
861 #define I2O_CMD_SW_UPLOAD 0xAB
862 #define I2O_CMD_SW_REMOVE 0xAD
863 #define I2O_CMD_SYS_ENABLE 0xD1
864 #define I2O_CMD_SYS_MODIFY 0xC1
865 #define I2O_CMD_SYS_QUIESCE 0xC3
866 #define I2O_CMD_SYS_TAB_SET 0xA3
867
868 /*
869 * Utility Class
870 */
871 #define I2O_CMD_UTIL_NOP 0x00
872 #define I2O_CMD_UTIL_ABORT 0x01
873 #define I2O_CMD_UTIL_CLAIM 0x09
874 #define I2O_CMD_UTIL_RELEASE 0x0B
875 #define I2O_CMD_UTIL_PARAMS_GET 0x06
876 #define I2O_CMD_UTIL_PARAMS_SET 0x05
877 #define I2O_CMD_UTIL_EVT_REGISTER 0x13
878 #define I2O_CMD_UTIL_EVT_ACK 0x14
879 #define I2O_CMD_UTIL_CONFIG_DIALOG 0x10
880 #define I2O_CMD_UTIL_DEVICE_RESERVE 0x0D
881 #define I2O_CMD_UTIL_DEVICE_RELEASE 0x0F
882 #define I2O_CMD_UTIL_LOCK 0x17
883 #define I2O_CMD_UTIL_LOCK_RELEASE 0x19
884 #define I2O_CMD_UTIL_REPLY_FAULT_NOTIFY 0x15
885
886 /*
887 * SCSI Host Bus Adapter Class
888 */
889 #define I2O_CMD_SCSI_EXEC 0x81
890 #define I2O_CMD_SCSI_ABORT 0x83
891 #define I2O_CMD_SCSI_BUSRESET 0x27
892
893 /*
894 * Bus Adapter Class
895 */
896 #define I2O_CMD_BUS_ADAPTER_RESET 0x85
897 #define I2O_CMD_BUS_RESET 0x87
898 #define I2O_CMD_BUS_SCAN 0x89
899 #define I2O_CMD_BUS_QUIESCE 0x8b
900
901 /*
902 * Random Block Storage Class
903 */
904 #define I2O_CMD_BLOCK_READ 0x30
905 #define I2O_CMD_BLOCK_WRITE 0x31
906 #define I2O_CMD_BLOCK_CFLUSH 0x37
907 #define I2O_CMD_BLOCK_MLOCK 0x49
908 #define I2O_CMD_BLOCK_MUNLOCK 0x4B
909 #define I2O_CMD_BLOCK_MMOUNT 0x41
910 #define I2O_CMD_BLOCK_MEJECT 0x43
911 #define I2O_CMD_BLOCK_POWER 0x70
912
913 #define I2O_CMD_PRIVATE 0xFF
914
915 /* Command status values */
916
917 #define I2O_CMD_IN_PROGRESS 0x01
918 #define I2O_CMD_REJECTED 0x02
919 #define I2O_CMD_FAILED 0x03
920 #define I2O_CMD_COMPLETED 0x04
921
922 /* I2O API function return values */
923
924 #define I2O_RTN_NO_ERROR 0
925 #define I2O_RTN_NOT_INIT 1
926 #define I2O_RTN_FREE_Q_EMPTY 2
927 #define I2O_RTN_TCB_ERROR 3
928 #define I2O_RTN_TRANSACTION_ERROR 4
929 #define I2O_RTN_ADAPTER_ALREADY_INIT 5
930 #define I2O_RTN_MALLOC_ERROR 6
931 #define I2O_RTN_ADPTR_NOT_REGISTERED 7
932 #define I2O_RTN_MSG_REPLY_TIMEOUT 8
933 #define I2O_RTN_NO_STATUS 9
934 #define I2O_RTN_NO_FIRM_VER 10
935 #define I2O_RTN_NO_LINK_SPEED 11
936
937 /* Reply message status defines for all messages */
938
939 #define I2O_REPLY_STATUS_SUCCESS 0x00
940 #define I2O_REPLY_STATUS_ABORT_DIRTY 0x01
941 #define I2O_REPLY_STATUS_ABORT_NO_DATA_TRANSFER 0x02
942 #define I2O_REPLY_STATUS_ABORT_PARTIAL_TRANSFER 0x03
943 #define I2O_REPLY_STATUS_ERROR_DIRTY 0x04
944 #define I2O_REPLY_STATUS_ERROR_NO_DATA_TRANSFER 0x05
945 #define I2O_REPLY_STATUS_ERROR_PARTIAL_TRANSFER 0x06
946 #define I2O_REPLY_STATUS_PROCESS_ABORT_DIRTY 0x08
947 #define I2O_REPLY_STATUS_PROCESS_ABORT_NO_DATA_TRANSFER 0x09
948 #define I2O_REPLY_STATUS_PROCESS_ABORT_PARTIAL_TRANSFER 0x0A
949 #define I2O_REPLY_STATUS_TRANSACTION_ERROR 0x0B
950 #define I2O_REPLY_STATUS_PROGRESS_REPORT 0x80
951
952 /* Status codes and Error Information for Parameter functions */
953
954 #define I2O_PARAMS_STATUS_SUCCESS 0x00
955 #define I2O_PARAMS_STATUS_BAD_KEY_ABORT 0x01
956 #define I2O_PARAMS_STATUS_BAD_KEY_CONTINUE 0x02
957 #define I2O_PARAMS_STATUS_BUFFER_FULL 0x03
958 #define I2O_PARAMS_STATUS_BUFFER_TOO_SMALL 0x04
959 #define I2O_PARAMS_STATUS_FIELD_UNREADABLE 0x05
960 #define I2O_PARAMS_STATUS_FIELD_UNWRITEABLE 0x06
961 #define I2O_PARAMS_STATUS_INSUFFICIENT_FIELDS 0x07
962 #define I2O_PARAMS_STATUS_INVALID_GROUP_ID 0x08
963 #define I2O_PARAMS_STATUS_INVALID_OPERATION 0x09
964 #define I2O_PARAMS_STATUS_NO_KEY_FIELD 0x0A
965 #define I2O_PARAMS_STATUS_NO_SUCH_FIELD 0x0B
966 #define I2O_PARAMS_STATUS_NON_DYNAMIC_GROUP 0x0C
967 #define I2O_PARAMS_STATUS_OPERATION_ERROR 0x0D
968 #define I2O_PARAMS_STATUS_SCALAR_ERROR 0x0E
969 #define I2O_PARAMS_STATUS_TABLE_ERROR 0x0F
970 #define I2O_PARAMS_STATUS_WRONG_GROUP_TYPE 0x10
971
972 /* DetailedStatusCode defines for Executive, DDM, Util and Transaction error
973 * messages: Table 3-2 Detailed Status Codes.*/
974
975 #define I2O_DSC_SUCCESS 0x0000
976 #define I2O_DSC_BAD_KEY 0x0002
977 #define I2O_DSC_TCL_ERROR 0x0003
978 #define I2O_DSC_REPLY_BUFFER_FULL 0x0004
979 #define I2O_DSC_NO_SUCH_PAGE 0x0005
980 #define I2O_DSC_INSUFFICIENT_RESOURCE_SOFT 0x0006
981 #define I2O_DSC_INSUFFICIENT_RESOURCE_HARD 0x0007
982 #define I2O_DSC_CHAIN_BUFFER_TOO_LARGE 0x0009
983 #define I2O_DSC_UNSUPPORTED_FUNCTION 0x000A
984 #define I2O_DSC_DEVICE_LOCKED 0x000B
985 #define I2O_DSC_DEVICE_RESET 0x000C
986 #define I2O_DSC_INAPPROPRIATE_FUNCTION 0x000D
987 #define I2O_DSC_INVALID_INITIATOR_ADDRESS 0x000E
988 #define I2O_DSC_INVALID_MESSAGE_FLAGS 0x000F
989 #define I2O_DSC_INVALID_OFFSET 0x0010
990 #define I2O_DSC_INVALID_PARAMETER 0x0011
991 #define I2O_DSC_INVALID_REQUEST 0x0012
992 #define I2O_DSC_INVALID_TARGET_ADDRESS 0x0013
993 #define I2O_DSC_MESSAGE_TOO_LARGE 0x0014
994 #define I2O_DSC_MESSAGE_TOO_SMALL 0x0015
995 #define I2O_DSC_MISSING_PARAMETER 0x0016
996 #define I2O_DSC_TIMEOUT 0x0017
997 #define I2O_DSC_UNKNOWN_ERROR 0x0018
998 #define I2O_DSC_UNKNOWN_FUNCTION 0x0019
999 #define I2O_DSC_UNSUPPORTED_VERSION 0x001A
1000 #define I2O_DSC_DEVICE_BUSY 0x001B
1001 #define I2O_DSC_DEVICE_NOT_AVAILABLE 0x001C
1002
1003 /* DetailedStatusCode defines for Block Storage Operation: Table 6-7 Detailed
1004 Status Codes.*/
1005
1006 #define I2O_BSA_DSC_SUCCESS 0x0000
1007 #define I2O_BSA_DSC_MEDIA_ERROR 0x0001
1008 #define I2O_BSA_DSC_ACCESS_ERROR 0x0002
1009 #define I2O_BSA_DSC_DEVICE_FAILURE 0x0003
1010 #define I2O_BSA_DSC_DEVICE_NOT_READY 0x0004
1011 #define I2O_BSA_DSC_MEDIA_NOT_PRESENT 0x0005
1012 #define I2O_BSA_DSC_MEDIA_LOCKED 0x0006
1013 #define I2O_BSA_DSC_MEDIA_FAILURE 0x0007
1014 #define I2O_BSA_DSC_PROTOCOL_FAILURE 0x0008
1015 #define I2O_BSA_DSC_BUS_FAILURE 0x0009
1016 #define I2O_BSA_DSC_ACCESS_VIOLATION 0x000A
1017 #define I2O_BSA_DSC_WRITE_PROTECTED 0x000B
1018 #define I2O_BSA_DSC_DEVICE_RESET 0x000C
1019 #define I2O_BSA_DSC_VOLUME_CHANGED 0x000D
1020 #define I2O_BSA_DSC_TIMEOUT 0x000E
1021
1022 /* FailureStatusCodes, Table 3-3 Message Failure Codes */
1023
1024 #define I2O_FSC_TRANSPORT_SERVICE_SUSPENDED 0x81
1025 #define I2O_FSC_TRANSPORT_SERVICE_TERMINATED 0x82
1026 #define I2O_FSC_TRANSPORT_CONGESTION 0x83
1027 #define I2O_FSC_TRANSPORT_FAILURE 0x84
1028 #define I2O_FSC_TRANSPORT_STATE_ERROR 0x85
1029 #define I2O_FSC_TRANSPORT_TIME_OUT 0x86
1030 #define I2O_FSC_TRANSPORT_ROUTING_FAILURE 0x87
1031 #define I2O_FSC_TRANSPORT_INVALID_VERSION 0x88
1032 #define I2O_FSC_TRANSPORT_INVALID_OFFSET 0x89
1033 #define I2O_FSC_TRANSPORT_INVALID_MSG_FLAGS 0x8A
1034 #define I2O_FSC_TRANSPORT_FRAME_TOO_SMALL 0x8B
1035 #define I2O_FSC_TRANSPORT_FRAME_TOO_LARGE 0x8C
1036 #define I2O_FSC_TRANSPORT_INVALID_TARGET_ID 0x8D
1037 #define I2O_FSC_TRANSPORT_INVALID_INITIATOR_ID 0x8E
1038 #define I2O_FSC_TRANSPORT_INVALID_INITIATOR_CONTEXT 0x8F
1039 #define I2O_FSC_TRANSPORT_UNKNOWN_FAILURE 0xFF
1040
1041 /* Device Claim Types */
1042 #define I2O_CLAIM_PRIMARY 0x01000000
1043 #define I2O_CLAIM_MANAGEMENT 0x02000000
1044 #define I2O_CLAIM_AUTHORIZED 0x03000000
1045 #define I2O_CLAIM_SECONDARY 0x04000000
1046
1047 /* Message header defines for VersionOffset */
1048 #define I2OVER15 0x0001
1049 #define I2OVER20 0x0002
1050
1051 /* Default is 1.5 */
1052 #define I2OVERSION I2OVER15
1053
1054 #define SGL_OFFSET_0 I2OVERSION
1055 #define SGL_OFFSET_4 (0x0040 | I2OVERSION)
1056 #define SGL_OFFSET_5 (0x0050 | I2OVERSION)
1057 #define SGL_OFFSET_6 (0x0060 | I2OVERSION)
1058 #define SGL_OFFSET_7 (0x0070 | I2OVERSION)
1059 #define SGL_OFFSET_8 (0x0080 | I2OVERSION)
1060 #define SGL_OFFSET_9 (0x0090 | I2OVERSION)
1061 #define SGL_OFFSET_10 (0x00A0 | I2OVERSION)
1062 #define SGL_OFFSET_11 (0x00B0 | I2OVERSION)
1063 #define SGL_OFFSET_12 (0x00C0 | I2OVERSION)
1064 #define SGL_OFFSET(x) (((x)<<4) | I2OVERSION)
1065
1066 /* Transaction Reply Lists (TRL) Control Word structure */
1067 #define TRL_SINGLE_FIXED_LENGTH 0x00
1068 #define TRL_SINGLE_VARIABLE_LENGTH 0x40
1069 #define TRL_MULTIPLE_FIXED_LENGTH 0x80
1070
1071 /* msg header defines for MsgFlags */
1072 #define MSG_STATIC 0x0100
1073 #define MSG_64BIT_CNTXT 0x0200
1074 #define MSG_MULTI_TRANS 0x1000
1075 #define MSG_FAIL 0x2000
1076 #define MSG_FINAL 0x4000
1077 #define MSG_REPLY 0x8000
1078
1079 /* minimum size msg */
1080 #define THREE_WORD_MSG_SIZE 0x00030000
1081 #define FOUR_WORD_MSG_SIZE 0x00040000
1082 #define FIVE_WORD_MSG_SIZE 0x00050000
1083 #define SIX_WORD_MSG_SIZE 0x00060000
1084 #define SEVEN_WORD_MSG_SIZE 0x00070000
1085 #define EIGHT_WORD_MSG_SIZE 0x00080000
1086 #define NINE_WORD_MSG_SIZE 0x00090000
1087 #define TEN_WORD_MSG_SIZE 0x000A0000
1088 #define ELEVEN_WORD_MSG_SIZE 0x000B0000
1089 #define I2O_MESSAGE_SIZE(x) ((x)<<16)
1090
1091 /* special TID assignments */
1092 #define ADAPTER_TID 0
1093 #define HOST_TID 1
1094
1095 /* outbound queue defines */
1096 #define I2O_MAX_OUTBOUND_MSG_FRAMES 128
1097 #define I2O_OUTBOUND_MSG_FRAME_SIZE 128 /* in 32-bit words */
1098
1099 #define I2O_POST_WAIT_OK 0
1100 #define I2O_POST_WAIT_TIMEOUT -ETIMEDOUT
1101
1102 #define I2O_CONTEXT_LIST_MIN_LENGTH 15
1103 #define I2O_CONTEXT_LIST_USED 0x01
1104 #define I2O_CONTEXT_LIST_DELETED 0x02
1105
1106 /* timeouts */
1107 #define I2O_TIMEOUT_INIT_OUTBOUND_QUEUE 15
1108 #define I2O_TIMEOUT_MESSAGE_GET 5
1109 #define I2O_TIMEOUT_RESET 30
1110 #define I2O_TIMEOUT_STATUS_GET 5
1111 #define I2O_TIMEOUT_LCT_GET 360
1112 #define I2O_TIMEOUT_SCSI_SCB_ABORT 240
1113
1114 /* retries */
1115 #define I2O_HRT_GET_TRIES 3
1116 #define I2O_LCT_GET_TRIES 3
1117
1118 /* defines for max_sectors and max_phys_segments */
1119 #define I2O_MAX_SECTORS 1024
1120 #define I2O_MAX_SECTORS_LIMITED 256
1121 #define I2O_MAX_PHYS_SEGMENTS MAX_PHYS_SEGMENTS
1122
1123 #endif /* __KERNEL__ */
1124 #endif /* _I2O_H */
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