include/asm-m68knommu/mcfuart.h

   1 /****************************************************************************/
   2
   3 /*
   4  *      mcfuart.h -- ColdFire internal UART support defines.
   5  *
   6  *      (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
   7  *      (C) Copyright 2000, Lineo Inc. (www.lineo.com)
   8  */
   9
  10 /****************************************************************************/
  11 #ifndef mcfuart_h
  12 #define mcfuart_h
  13 /****************************************************************************/
  14
  15 #include <linux/config.h>
  16
  17 /*
  18  *      Define the base address of the UARTS within the MBAR address
  19  *      space.
  20  */
  21 #if defined(CONFIG_M5272)
  22 #define MCFUART_BASE1           0x100           /* Base address of UART1 */
  23 #define MCFUART_BASE2           0x140           /* Base address of UART2 */
  24 #elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
  25 #if defined(CONFIG_NETtel)
  26 #define MCFUART_BASE1           0x180           /* Base address of UART1 */
  27 #define MCFUART_BASE2           0x140           /* Base address of UART2 */
  28 #else
  29 #define MCFUART_BASE1           0x140           /* Base address of UART1 */
  30 #define MCFUART_BASE2           0x180           /* Base address of UART2 */
  31 #endif
  32 #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
  33 #define MCFUART_BASE1           0x200           /* Base address of UART1 */
  34 #define MCFUART_BASE2           0x240           /* Base address of UART2 */
  35 #define MCFUART_BASE3           0x280           /* Base address of UART3 */
  36 #elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
  37 #if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3)
  38 #define MCFUART_BASE1           0x200           /* Base address of UART1 */
  39 #define MCFUART_BASE2           0x1c0           /* Base address of UART2 */
  40 #else
  41 #define MCFUART_BASE1           0x1c0           /* Base address of UART1 */
  42 #define MCFUART_BASE2           0x200           /* Base address of UART2 */
  43 #endif
  44 #endif
  45
  46
  47 /*
  48  *      Define the ColdFire UART register set addresses.
  49  */
  50 #define MCFUART_UMR             0x00            /* Mode register (r/w) */
  51 #define MCFUART_USR             0x04            /* Status register (r) */
  52 #define MCFUART_UCSR            0x04            /* Clock Select (w) */
  53 #define MCFUART_UCR             0x08            /* Command register (w) */
  54 #define MCFUART_URB             0x0c            /* Receiver Buffer (r) */
  55 #define MCFUART_UTB             0x0c            /* Transmit Buffer (w) */
  56 #define MCFUART_UIPCR           0x10            /* Input Port Change (r) */
  57 #define MCFUART_UACR            0x10            /* Auxiliary Control (w) */
  58 #define MCFUART_UISR            0x14            /* Interrup Status (r) */
  59 #define MCFUART_UIMR            0x14            /* Interrupt Mask (w) */
  60 #define MCFUART_UBG1            0x18            /* Baud Rate MSB (r/w) */
  61 #define MCFUART_UBG2            0x1c            /* Baud Rate LSB (r/w) */
  62 #ifdef  CONFIG_M5272
  63 #define MCFUART_UTF             0x28            /* Transmitter FIFO (r/w) */
  64 #define MCFUART_URF             0x2c            /* Receiver FIFO (r/w) */
  65 #define MCFUART_UFPD            0x30            /* Frac Prec. Divider (r/w) */
  66 #else
  67 #define MCFUART_UIVR            0x30            /* Interrupt Vector (r/w) */
  68 #endif
  69 #define MCFUART_UIPR            0x34            /* Input Port (r) */
  70 #define MCFUART_UOP1            0x38            /* Output Port Bit Set (w) */
  71 #define MCFUART_UOP0            0x3c            /* Output Port Bit Reset (w) */
  72
  73
  74 /*
  75  *      Define bit flags in Mode Register 1 (MR1).
  76  */
  77 #define MCFUART_MR1_RXRTS       0x80            /* Auto RTS flow control */
  78 #define MCFUART_MR1_RXIRQFULL   0x40            /* RX IRQ type FULL */
  79 #define MCFUART_MR1_RXIRQRDY    0x00            /* RX IRQ type RDY */
  80 #define MCFUART_MR1_RXERRBLOCK  0x20            /* RX block error mode */
  81 #define MCFUART_MR1_RXERRCHAR   0x00            /* RX char error mode */
  82
  83 #define MCFUART_MR1_PARITYNONE  0x10            /* No parity */
  84 #define MCFUART_MR1_PARITYEVEN  0x00            /* Even parity */
  85 #define MCFUART_MR1_PARITYODD   0x04            /* Odd parity */
  86 #define MCFUART_MR1_PARITYSPACE 0x08            /* Space parity */
  87 #define MCFUART_MR1_PARITYMARK  0x0c            /* Mark parity */
  88
  89 #define MCFUART_MR1_CS5         0x00            /* 5 bits per char */
  90 #define MCFUART_MR1_CS6         0x01            /* 6 bits per char */
  91 #define MCFUART_MR1_CS7         0x02            /* 7 bits per char */
  92 #define MCFUART_MR1_CS8         0x03            /* 8 bits per char */
  93
  94 /*
  95  *      Define bit flags in Mode Register 2 (MR2).
  96  */
  97 #define MCFUART_MR2_LOOPBACK    0x80            /* Loopback mode */
  98 #define MCFUART_MR2_REMOTELOOP  0xc0            /* Remote loopback mode */
  99 #define MCFUART_MR2_AUTOECHO    0x40            /* Automatic echo */
 100 #define MCFUART_MR2_TXRTS       0x20            /* Assert RTS on TX */
 101 #define MCFUART_MR2_TXCTS       0x10            /* Auto CTS flow control */
 102
 103 #define MCFUART_MR2_STOP1       0x07            /* 1 stop bit */
 104 #define MCFUART_MR2_STOP15      0x08            /* 1.5 stop bits */
 105 #define MCFUART_MR2_STOP2       0x0f            /* 2 stop bits */
 106
 107 /*
 108  *      Define bit flags in Status Register (USR).
 109  */
 110 #define MCFUART_USR_RXBREAK     0x80            /* Received BREAK */
 111 #define MCFUART_USR_RXFRAMING   0x40            /* Received framing error */
 112 #define MCFUART_USR_RXPARITY    0x20            /* Received parity error */
 113 #define MCFUART_USR_RXOVERRUN   0x10            /* Received overrun error */
 114 #define MCFUART_USR_TXEMPTY     0x08            /* Transmitter empty */
 115 #define MCFUART_USR_TXREADY     0x04            /* Transmitter ready */
 116 #define MCFUART_USR_RXFULL      0x02            /* Receiver full */
 117 #define MCFUART_USR_RXREADY     0x01            /* Receiver ready */
 118
 119 #define MCFUART_USR_RXERR       (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
 120                                 MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
 121
 122 /*
 123  *      Define bit flags in Clock Select Register (UCSR).
 124  */
 125 #define MCFUART_UCSR_RXCLKTIMER 0xd0            /* RX clock is timer */
 126 #define MCFUART_UCSR_RXCLKEXT16 0xe0            /* RX clock is external x16 */
 127 #define MCFUART_UCSR_RXCLKEXT1  0xf0            /* RX clock is external x1 */
 128
 129 #define MCFUART_UCSR_TXCLKTIMER 0x0d            /* TX clock is timer */
 130 #define MCFUART_UCSR_TXCLKEXT16 0x0e            /* TX clock is external x16 */
 131 #define MCFUART_UCSR_TXCLKEXT1  0x0f            /* TX clock is external x1 */
 132
 133 /*
 134  *      Define bit flags in Command Register (UCR).
 135  */
 136 #define MCFUART_UCR_CMDNULL             0x00    /* No command */
 137 #define MCFUART_UCR_CMDRESETMRPTR       0x10    /* Reset MR pointer */
 138 #define MCFUART_UCR_CMDRESETRX          0x20    /* Reset receiver */
 139 #define MCFUART_UCR_CMDRESETTX          0x30    /* Reset transmitter */
 140 #define MCFUART_UCR_CMDRESETERR         0x40    /* Reset error status */
 141 #define MCFUART_UCR_CMDRESETBREAK       0x50    /* Reset BREAK change */
 142 #define MCFUART_UCR_CMDBREAKSTART       0x60    /* Start BREAK */
 143 #define MCFUART_UCR_CMDBREAKSTOP        0x70    /* Stop BREAK */
 144
 145 #define MCFUART_UCR_TXNULL      0x00            /* No TX command */
 146 #define MCFUART_UCR_TXENABLE    0x04            /* Enable TX */
 147 #define MCFUART_UCR_TXDISABLE   0x08            /* Disable TX */
 148 #define MCFUART_UCR_RXNULL      0x00            /* No RX command */
 149 #define MCFUART_UCR_RXENABLE    0x01            /* Enable RX */
 150 #define MCFUART_UCR_RXDISABLE   0x02            /* Disable RX */
 151
 152 /*
 153  *      Define bit flags in Input Port Change Register (UIPCR).
 154  */
 155 #define MCFUART_UIPCR_CTSCOS    0x10            /* CTS change of state */
 156 #define MCFUART_UIPCR_CTS       0x01            /* CTS value */
 157
 158 /*
 159  *      Define bit flags in Input Port Register (UIP).
 160  */
 161 #define MCFUART_UIPR_CTS        0x01            /* CTS value */
 162
 163 /*
 164  *      Define bit flags in Output Port Registers (UOP).
 165  *      Clear bit by writing to UOP0, set by writing to UOP1.
 166  */
 167 #define MCFUART_UOP_RTS         0x01            /* RTS set or clear */
 168
 169 /*
 170  *      Define bit flags in the Auxiliary Control Register (UACR).
 171  */
 172 #define MCFUART_UACR_IEC        0x01            /* Input enable control */
 173
 174 /*
 175  *      Define bit flags in Interrupt Status Register (UISR).
 176  *      These same bits are used for the Interrupt Mask Register (UIMR).
 177  */
 178 #define MCFUART_UIR_COS         0x80            /* Change of state (CTS) */
 179 #define MCFUART_UIR_DELTABREAK  0x04            /* Break start or stop */
 180 #define MCFUART_UIR_RXREADY     0x02            /* Receiver ready */
 181 #define MCFUART_UIR_TXREADY     0x01            /* Transmitter ready */
 182
 183 #ifdef  CONFIG_M5272
 184 /*
 185  *      Define bit flags in the Transmitter FIFO Register (UTF).
 186  */
 187 #define MCFUART_UTF_TXB         0x1f            /* Transmitter data level */
 188 #define MCFUART_UTF_FULL        0x20            /* Transmitter fifo full */
 189 #define MCFUART_UTF_TXS         0xc0            /* Transmitter status */
 190
 191 /*
 192  *      Define bit flags in the Receiver FIFO Register (URF).
 193  */
 194 #define MCFUART_URF_RXB         0x1f            /* Receiver data level */
 195 #define MCFUART_URF_FULL        0x20            /* Receiver fifo full */
 196 #define MCFUART_URF_RXS         0xc0            /* Receiver status */
 197 #endif
 198
 199 /****************************************************************************/
 200 #endif  /* mcfuart_h */