1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
34 //#include "ixgbe_mbx.h"
36 #define IXGBE_X540_MAX_TX_QUEUES 128
37 #define IXGBE_X540_MAX_RX_QUEUES 128
38 #define IXGBE_X540_RAR_ENTRIES 128
39 #define IXGBE_X540_MC_TBL_SIZE 128
40 #define IXGBE_X540_VFT_TBL_SIZE 128
42 static s32
ixgbe_update_flash_X540(struct ixgbe_hw
*hw
);
43 static s32
ixgbe_poll_flash_update_done_X540(struct ixgbe_hw
*hw
);
44 static s32
ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw
*hw
, u16 mask
);
45 static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw
*hw
, u16 mask
);
46 static s32
ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw
*hw
);
47 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw
*hw
);
49 static enum ixgbe_media_type
ixgbe_get_media_type_X540(struct ixgbe_hw
*hw
)
51 return ixgbe_media_type_copper
;
54 static s32
ixgbe_get_invariants_X540(struct ixgbe_hw
*hw
)
56 struct ixgbe_mac_info
*mac
= &hw
->mac
;
58 /* Call PHY identify routine to get the phy type */
59 ixgbe_identify_phy_generic(hw
);
61 mac
->mcft_size
= IXGBE_X540_MC_TBL_SIZE
;
62 mac
->vft_size
= IXGBE_X540_VFT_TBL_SIZE
;
63 mac
->num_rar_entries
= IXGBE_X540_RAR_ENTRIES
;
64 mac
->max_rx_queues
= IXGBE_X540_MAX_RX_QUEUES
;
65 mac
->max_tx_queues
= IXGBE_X540_MAX_TX_QUEUES
;
66 mac
->max_msix_vectors
= ixgbe_get_pcie_msix_count_generic(hw
);
72 * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
73 * @hw: pointer to hardware structure
74 * @speed: new link speed
75 * @autoneg: true if autonegotiation enabled
76 * @autoneg_wait_to_complete: true when waiting for completion is needed
78 static s32
ixgbe_setup_mac_link_X540(struct ixgbe_hw
*hw
,
79 ixgbe_link_speed speed
, bool autoneg
,
80 bool autoneg_wait_to_complete
)
82 return hw
->phy
.ops
.setup_link_speed(hw
, speed
, autoneg
,
83 autoneg_wait_to_complete
);
87 * ixgbe_reset_hw_X540 - Perform hardware reset
88 * @hw: pointer to hardware structure
90 * Resets the hardware by resetting the transmit and receive units, masks
91 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
94 static s32
ixgbe_reset_hw_X540(struct ixgbe_hw
*hw
)
96 ixgbe_link_speed link_speed
;
104 bool link_up
= false;
106 /* Call adapter stop to disable tx/rx and clear interrupts */
107 hw
->mac
.ops
.stop_adapter(hw
);
110 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
111 * access and verify no pending requests before reset
113 ixgbe_disable_pcie_master(hw
);
117 * Issue global reset to the MAC. Needs to be SW reset if link is up.
118 * If link reset is used when link is up, it might reset the PHY when
119 * mng is using it. If link is down or the flag to force full link
120 * reset is set, then perform link reset.
122 if (hw
->force_full_reset
) {
123 reset_bit
= IXGBE_CTRL_LNK_RST
;
125 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
127 reset_bit
= IXGBE_CTRL_LNK_RST
;
129 reset_bit
= IXGBE_CTRL_RST
;
132 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
133 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, (ctrl
| reset_bit
));
134 IXGBE_WRITE_FLUSH(hw
);
136 /* Poll for reset bit to self-clear indicating reset is complete */
137 for (i
= 0; i
< 10; i
++) {
139 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
140 if (!(ctrl
& reset_bit
))
143 if (ctrl
& reset_bit
) {
144 status
= IXGBE_ERR_RESET_FAILED
;
145 hw_dbg(hw
, "Reset polling failed to complete.\n");
149 * Double resets are required for recovery from certain error
150 * conditions. Between resets, it is necessary to stall to allow time
151 * for any pending HW events to complete. We use 1usec since that is
152 * what is needed for ixgbe_disable_pcie_master(). The second reset
153 * then clears out any effects of those events.
155 if (hw
->mac
.flags
& IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
) {
156 hw
->mac
.flags
&= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
;
161 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
162 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
163 ctrl_ext
|= IXGBE_CTRL_EXT_PFRSTD
;
164 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
168 /* Set the Rx packet buffer size. */
169 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT
);
171 /* Store the permanent mac address */
172 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.perm_addr
);
175 * Store the original AUTOC/AUTOC2 values if they have not been
176 * stored off yet. Otherwise restore the stored original
177 * values since the reset operation sets back to defaults.
179 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
180 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
181 if (hw
->mac
.orig_link_settings_stored
== false) {
182 hw
->mac
.orig_autoc
= autoc
;
183 hw
->mac
.orig_autoc2
= autoc2
;
184 hw
->mac
.orig_link_settings_stored
= true;
186 if (autoc
!= hw
->mac
.orig_autoc
)
187 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, (hw
->mac
.orig_autoc
|
188 IXGBE_AUTOC_AN_RESTART
));
190 if ((autoc2
& IXGBE_AUTOC2_UPPER_MASK
) !=
191 (hw
->mac
.orig_autoc2
& IXGBE_AUTOC2_UPPER_MASK
)) {
192 autoc2
&= ~IXGBE_AUTOC2_UPPER_MASK
;
193 autoc2
|= (hw
->mac
.orig_autoc2
&
194 IXGBE_AUTOC2_UPPER_MASK
);
195 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC2
, autoc2
);
200 * Store MAC address from RAR0, clear receive address registers, and
201 * clear the multicast table. Also reset num_rar_entries to 128,
202 * since we modify this value when programming the SAN MAC address.
204 hw
->mac
.num_rar_entries
= 128;
205 hw
->mac
.ops
.init_rx_addrs(hw
);
207 /* Store the permanent mac address */
208 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.perm_addr
);
210 /* Store the permanent SAN mac address */
211 hw
->mac
.ops
.get_san_mac_addr(hw
, hw
->mac
.san_addr
);
213 /* Add the SAN MAC address to the RAR only if it's a valid address */
214 if (ixgbe_validate_mac_addr(hw
->mac
.san_addr
) == 0) {
215 hw
->mac
.ops
.set_rar(hw
, hw
->mac
.num_rar_entries
- 1,
216 hw
->mac
.san_addr
, 0, IXGBE_RAH_AV
);
218 /* Reserve the last RAR for the SAN MAC address */
219 hw
->mac
.num_rar_entries
--;
222 /* Store the alternative WWNN/WWPN prefix */
223 hw
->mac
.ops
.get_wwn_prefix(hw
, &hw
->mac
.wwnn_prefix
,
224 &hw
->mac
.wwpn_prefix
);
230 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
231 * @hw: pointer to hardware structure
233 * Determines physical layer capabilities of the current configuration.
235 static u32
ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw
*hw
)
237 u32 physical_layer
= IXGBE_PHYSICAL_LAYER_UNKNOWN
;
240 hw
->phy
.ops
.identify(hw
);
242 hw
->phy
.ops
.read_reg(hw
, MDIO_PMA_EXTABLE
, MDIO_MMD_PMAPMD
,
244 if (ext_ability
& MDIO_PMA_EXTABLE_10GBT
)
245 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_T
;
246 if (ext_ability
& MDIO_PMA_EXTABLE_1000BT
)
247 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_T
;
248 if (ext_ability
& MDIO_PMA_EXTABLE_100BTX
)
249 physical_layer
|= IXGBE_PHYSICAL_LAYER_100BASE_TX
;
251 return physical_layer
;
255 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
256 * @hw: pointer to hardware structure
258 static s32
ixgbe_init_eeprom_params_X540(struct ixgbe_hw
*hw
)
260 struct ixgbe_eeprom_info
*eeprom
= &hw
->eeprom
;
264 if (eeprom
->type
== ixgbe_eeprom_uninitialized
) {
265 eeprom
->semaphore_delay
= 10;
266 eeprom
->type
= ixgbe_flash
;
268 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
269 eeprom_size
= (u16
)((eec
& IXGBE_EEC_SIZE
) >>
270 IXGBE_EEC_SIZE_SHIFT
);
271 eeprom
->word_size
= 1 << (eeprom_size
+
272 IXGBE_EEPROM_WORD_SIZE_SHIFT
);
274 hw_dbg(hw
, "Eeprom params: type = %d, size = %d\n",
275 eeprom
->type
, eeprom
->word_size
);
282 * ixgbe_read_eerd_X540 - Read EEPROM word using EERD
283 * @hw: pointer to hardware structure
284 * @offset: offset of word in the EEPROM to read
285 * @data: word read from the EERPOM
287 static s32
ixgbe_read_eerd_X540(struct ixgbe_hw
*hw
, u16 offset
, u16
*data
)
291 if (ixgbe_acquire_swfw_sync_X540(hw
, IXGBE_GSSR_EEP_SM
) == 0)
292 status
= ixgbe_read_eerd_generic(hw
, offset
, data
);
294 status
= IXGBE_ERR_SWFW_SYNC
;
296 ixgbe_release_swfw_sync_X540(hw
, IXGBE_GSSR_EEP_SM
);
301 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
302 * @hw: pointer to hardware structure
303 * @offset: offset of word in the EEPROM to write
304 * @data: word write to the EEPROM
306 * Write a 16 bit word to the EEPROM using the EEWR register.
308 static s32
ixgbe_write_eewr_X540(struct ixgbe_hw
*hw
, u16 offset
, u16 data
)
313 hw
->eeprom
.ops
.init_params(hw
);
315 if (offset
>= hw
->eeprom
.word_size
) {
316 status
= IXGBE_ERR_EEPROM
;
320 eewr
= (offset
<< IXGBE_EEPROM_RW_ADDR_SHIFT
) |
321 (data
<< IXGBE_EEPROM_RW_REG_DATA
) |
322 IXGBE_EEPROM_RW_REG_START
;
324 if (ixgbe_acquire_swfw_sync_X540(hw
, IXGBE_GSSR_EEP_SM
) == 0) {
325 status
= ixgbe_poll_eerd_eewr_done(hw
, IXGBE_NVM_POLL_WRITE
);
327 hw_dbg(hw
, "Eeprom write EEWR timed out\n");
331 IXGBE_WRITE_REG(hw
, IXGBE_EEWR
, eewr
);
333 status
= ixgbe_poll_eerd_eewr_done(hw
, IXGBE_NVM_POLL_WRITE
);
335 hw_dbg(hw
, "Eeprom write EEWR timed out\n");
339 status
= IXGBE_ERR_SWFW_SYNC
;
343 ixgbe_release_swfw_sync_X540(hw
, IXGBE_GSSR_EEP_SM
);
348 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
349 * @hw: pointer to hardware structure
351 static u16
ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw
*hw
)
360 /* Include 0x0-0x3F in the checksum */
361 for (i
= 0; i
< IXGBE_EEPROM_CHECKSUM
; i
++) {
362 if (hw
->eeprom
.ops
.read(hw
, i
, &word
) != 0) {
363 hw_dbg(hw
, "EEPROM read failed\n");
370 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
371 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
373 for (i
= IXGBE_PCIE_ANALOG_PTR
; i
< IXGBE_FW_PTR
; i
++) {
374 if (i
== IXGBE_PHY_PTR
|| i
== IXGBE_OPTION_ROM_PTR
)
377 if (hw
->eeprom
.ops
.read(hw
, i
, &pointer
) != 0) {
378 hw_dbg(hw
, "EEPROM read failed\n");
382 /* Skip pointer section if the pointer is invalid. */
383 if (pointer
== 0xFFFF || pointer
== 0 ||
384 pointer
>= hw
->eeprom
.word_size
)
387 if (hw
->eeprom
.ops
.read(hw
, pointer
, &length
) != 0) {
388 hw_dbg(hw
, "EEPROM read failed\n");
392 /* Skip pointer section if length is invalid. */
393 if (length
== 0xFFFF || length
== 0 ||
394 (pointer
+ length
) >= hw
->eeprom
.word_size
)
397 for (j
= pointer
+1; j
<= pointer
+length
; j
++) {
398 if (hw
->eeprom
.ops
.read(hw
, j
, &word
) != 0) {
399 hw_dbg(hw
, "EEPROM read failed\n");
406 checksum
= (u16
)IXGBE_EEPROM_SUM
- checksum
;
412 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
413 * @hw: pointer to hardware structure
415 * After writing EEPROM to shadow RAM using EEWR register, software calculates
416 * checksum and updates the EEPROM and instructs the hardware to update
419 static s32
ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw
*hw
)
423 status
= ixgbe_update_eeprom_checksum_generic(hw
);
426 status
= ixgbe_update_flash_X540(hw
);
432 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
433 * @hw: pointer to hardware structure
435 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
436 * EEPROM from shadow RAM to the flash device.
438 static s32
ixgbe_update_flash_X540(struct ixgbe_hw
*hw
)
441 s32 status
= IXGBE_ERR_EEPROM
;
443 status
= ixgbe_poll_flash_update_done_X540(hw
);
444 if (status
== IXGBE_ERR_EEPROM
) {
445 hw_dbg(hw
, "Flash update time out\n");
449 flup
= IXGBE_READ_REG(hw
, IXGBE_EEC
) | IXGBE_EEC_FLUP
;
450 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, flup
);
452 status
= ixgbe_poll_flash_update_done_X540(hw
);
454 hw_dbg(hw
, "Flash update complete\n");
456 hw_dbg(hw
, "Flash update time out\n");
458 if (hw
->revision_id
== 0) {
459 flup
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
461 if (flup
& IXGBE_EEC_SEC1VAL
) {
462 flup
|= IXGBE_EEC_FLUP
;
463 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, flup
);
466 status
= ixgbe_poll_flash_update_done_X540(hw
);
468 hw_dbg(hw
, "Flash update complete\n");
470 hw_dbg(hw
, "Flash update time out\n");
478 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
479 * @hw: pointer to hardware structure
481 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
482 * flash update is done.
484 static s32
ixgbe_poll_flash_update_done_X540(struct ixgbe_hw
*hw
)
488 s32 status
= IXGBE_ERR_EEPROM
;
490 for (i
= 0; i
< IXGBE_FLUDONE_ATTEMPTS
; i
++) {
491 reg
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
492 if (reg
& IXGBE_EEC_FLUDONE
) {
502 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
503 * @hw: pointer to hardware structure
504 * @mask: Mask to specify which semaphore to acquire
506 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
507 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
509 static s32
ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw
*hw
, u16 mask
)
513 u32 fwmask
= mask
<< 5;
518 if (swmask
== IXGBE_GSSR_EEP_SM
)
519 hwmask
= IXGBE_GSSR_FLASH_SM
;
521 for (i
= 0; i
< timeout
; i
++) {
523 * SW NVM semaphore bit is used for access to all
524 * SW_FW_SYNC bits (not just NVM)
526 if (ixgbe_get_swfw_sync_semaphore(hw
))
527 return IXGBE_ERR_SWFW_SYNC
;
529 swfw_sync
= IXGBE_READ_REG(hw
, IXGBE_SWFW_SYNC
);
530 if (!(swfw_sync
& (fwmask
| swmask
| hwmask
))) {
532 IXGBE_WRITE_REG(hw
, IXGBE_SWFW_SYNC
, swfw_sync
);
533 ixgbe_release_swfw_sync_semaphore(hw
);
537 * Firmware currently using resource (fwmask),
538 * hardware currently using resource (hwmask),
539 * or other software thread currently using
542 ixgbe_release_swfw_sync_semaphore(hw
);
548 * If the resource is not released by the FW/HW the SW can assume that
549 * the FW/HW malfunctions. In that case the SW should sets the
550 * SW bit(s) of the requested resource(s) while ignoring the
551 * corresponding FW/HW bits in the SW_FW_SYNC register.
554 swfw_sync
= IXGBE_READ_REG(hw
, IXGBE_SWFW_SYNC
);
555 if (swfw_sync
& (fwmask
| hwmask
)) {
556 if (ixgbe_get_swfw_sync_semaphore(hw
))
557 return IXGBE_ERR_SWFW_SYNC
;
560 IXGBE_WRITE_REG(hw
, IXGBE_SWFW_SYNC
, swfw_sync
);
561 ixgbe_release_swfw_sync_semaphore(hw
);
570 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
571 * @hw: pointer to hardware structure
572 * @mask: Mask to specify which semaphore to release
574 * Releases the SWFW semaphore throught the SW_FW_SYNC register
575 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
577 static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw
*hw
, u16 mask
)
582 ixgbe_get_swfw_sync_semaphore(hw
);
584 swfw_sync
= IXGBE_READ_REG(hw
, IXGBE_SWFW_SYNC
);
585 swfw_sync
&= ~swmask
;
586 IXGBE_WRITE_REG(hw
, IXGBE_SWFW_SYNC
, swfw_sync
);
588 ixgbe_release_swfw_sync_semaphore(hw
);
593 * ixgbe_get_nvm_semaphore - Get hardware semaphore
594 * @hw: pointer to hardware structure
596 * Sets the hardware semaphores so SW/FW can gain control of shared resources
598 static s32
ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw
*hw
)
600 s32 status
= IXGBE_ERR_EEPROM
;
605 /* Get SMBI software semaphore between device drivers first */
606 for (i
= 0; i
< timeout
; i
++) {
608 * If the SMBI bit is 0 when we read it, then the bit will be
609 * set and we have the semaphore
611 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
612 if (!(swsm
& IXGBE_SWSM_SMBI
)) {
619 /* Now get the semaphore between SW/FW through the REGSMP bit */
621 for (i
= 0; i
< timeout
; i
++) {
622 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWFW_SYNC
);
623 if (!(swsm
& IXGBE_SWFW_REGSMP
))
629 hw_dbg(hw
, "Software semaphore SMBI between device drivers "
637 * ixgbe_release_nvm_semaphore - Release hardware semaphore
638 * @hw: pointer to hardware structure
640 * This function clears hardware semaphore bits.
642 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw
*hw
)
646 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
648 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
649 swsm
&= ~IXGBE_SWSM_SMBI
;
650 IXGBE_WRITE_REG(hw
, IXGBE_SWSM
, swsm
);
652 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWFW_SYNC
);
653 swsm
&= ~IXGBE_SWFW_REGSMP
;
654 IXGBE_WRITE_REG(hw
, IXGBE_SWFW_SYNC
, swsm
);
656 IXGBE_WRITE_FLUSH(hw
);
659 static struct ixgbe_mac_operations mac_ops_X540
= {
660 .init_hw
= &ixgbe_init_hw_generic
,
661 .reset_hw
= &ixgbe_reset_hw_X540
,
662 .start_hw
= &ixgbe_start_hw_generic
,
663 .clear_hw_cntrs
= &ixgbe_clear_hw_cntrs_generic
,
664 .get_media_type
= &ixgbe_get_media_type_X540
,
665 .get_supported_physical_layer
=
666 &ixgbe_get_supported_physical_layer_X540
,
667 .enable_rx_dma
= &ixgbe_enable_rx_dma_generic
,
668 .get_mac_addr
= &ixgbe_get_mac_addr_generic
,
669 .get_san_mac_addr
= &ixgbe_get_san_mac_addr_generic
,
670 .get_device_caps
= NULL
,
671 .get_wwn_prefix
= &ixgbe_get_wwn_prefix_generic
,
672 .stop_adapter
= &ixgbe_stop_adapter_generic
,
673 .get_bus_info
= &ixgbe_get_bus_info_generic
,
674 .set_lan_id
= &ixgbe_set_lan_id_multi_port_pcie
,
675 .read_analog_reg8
= NULL
,
676 .write_analog_reg8
= NULL
,
677 .setup_link
= &ixgbe_setup_mac_link_X540
,
678 .check_link
= &ixgbe_check_mac_link_generic
,
679 .get_link_capabilities
= &ixgbe_get_copper_link_capabilities_generic
,
680 .led_on
= &ixgbe_led_on_generic
,
681 .led_off
= &ixgbe_led_off_generic
,
682 .blink_led_start
= &ixgbe_blink_led_start_generic
,
683 .blink_led_stop
= &ixgbe_blink_led_stop_generic
,
684 .set_rar
= &ixgbe_set_rar_generic
,
685 .clear_rar
= &ixgbe_clear_rar_generic
,
686 .set_vmdq
= &ixgbe_set_vmdq_generic
,
687 .clear_vmdq
= &ixgbe_clear_vmdq_generic
,
688 .init_rx_addrs
= &ixgbe_init_rx_addrs_generic
,
689 .update_mc_addr_list
= &ixgbe_update_mc_addr_list_generic
,
690 .enable_mc
= &ixgbe_enable_mc_generic
,
691 .disable_mc
= &ixgbe_disable_mc_generic
,
692 .clear_vfta
= &ixgbe_clear_vfta_generic
,
693 .set_vfta
= &ixgbe_set_vfta_generic
,
694 .fc_enable
= &ixgbe_fc_enable_generic
,
695 .init_uta_tables
= &ixgbe_init_uta_tables_generic
,
697 .set_mac_anti_spoofing
= &ixgbe_set_mac_anti_spoofing
,
698 .set_vlan_anti_spoofing
= &ixgbe_set_vlan_anti_spoofing
,
701 static struct ixgbe_eeprom_operations eeprom_ops_X540
= {
702 .init_params
= &ixgbe_init_eeprom_params_X540
,
703 .read
= &ixgbe_read_eerd_X540
,
704 .write
= &ixgbe_write_eewr_X540
,
705 .calc_checksum
= &ixgbe_calc_eeprom_checksum_X540
,
706 .validate_checksum
= &ixgbe_validate_eeprom_checksum_generic
,
707 .update_checksum
= &ixgbe_update_eeprom_checksum_X540
,
710 static struct ixgbe_phy_operations phy_ops_X540
= {
711 .identify
= &ixgbe_identify_phy_generic
,
712 .identify_sfp
= &ixgbe_identify_sfp_module_generic
,
715 .read_reg
= &ixgbe_read_phy_reg_generic
,
716 .write_reg
= &ixgbe_write_phy_reg_generic
,
717 .setup_link
= &ixgbe_setup_phy_link_generic
,
718 .setup_link_speed
= &ixgbe_setup_phy_link_speed_generic
,
719 .read_i2c_byte
= &ixgbe_read_i2c_byte_generic
,
720 .write_i2c_byte
= &ixgbe_write_i2c_byte_generic
,
721 .read_i2c_eeprom
= &ixgbe_read_i2c_eeprom_generic
,
722 .write_i2c_eeprom
= &ixgbe_write_i2c_eeprom_generic
,
723 .check_overtemp
= &ixgbe_tn_check_overtemp
,
726 struct ixgbe_info ixgbe_X540_info
= {
727 .mac
= ixgbe_mac_X540
,
728 .get_invariants
= &ixgbe_get_invariants_X540
,
729 .mac_ops
= &mac_ops_X540
,
730 .eeprom_ops
= &eeprom_ops_X540
,
731 .phy_ops
= &phy_ops_X540
,
732 .mbx_ops
= &mbx_ops_generic
,